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Merge branch 'for-linville' of git://github.com/lucacoelho/wl12xx
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <asm/unaligned.h>
31 #include <defs.h>
32 #include <brcmu_wifi.h>
33 #include <brcmu_utils.h>
34 #include <brcm_hw_ids.h>
35 #include <soc.h>
36 #include "sdio_host.h"
37
38 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
39
40 #ifdef BCMDBG
41
42 #define BRCMF_TRAP_INFO_SIZE 80
43
44 #define CBUF_LEN (128)
45
46 struct rte_log_le {
47 __le32 buf; /* Can't be pointer on (64-bit) hosts */
48 __le32 buf_size;
49 __le32 idx;
50 char *_buf_compat; /* Redundant pointer for backward compat. */
51 };
52
53 struct rte_console {
54 /* Virtual UART
55 * When there is no UART (e.g. Quickturn),
56 * the host should write a complete
57 * input line directly into cbuf and then write
58 * the length into vcons_in.
59 * This may also be used when there is a real UART
60 * (at risk of conflicting with
61 * the real UART). vcons_out is currently unused.
62 */
63 uint vcons_in;
64 uint vcons_out;
65
66 /* Output (logging) buffer
67 * Console output is written to a ring buffer log_buf at index log_idx.
68 * The host may read the output when it sees log_idx advance.
69 * Output will be lost if the output wraps around faster than the host
70 * polls.
71 */
72 struct rte_log_le log_le;
73
74 /* Console input line buffer
75 * Characters are read one at a time into cbuf
76 * until <CR> is received, then
77 * the buffer is processed as a command line.
78 * Also used for virtual UART.
79 */
80 uint cbuf_idx;
81 char cbuf[CBUF_LEN];
82 };
83
84 #endif /* BCMDBG */
85 #include <chipcommon.h>
86
87 #include "dhd.h"
88 #include "dhd_bus.h"
89 #include "dhd_proto.h"
90 #include "dhd_dbg.h"
91 #include <bcmchip.h>
92
93 #define TXQLEN 2048 /* bulk tx queue length */
94 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
95 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
96 #define PRIOMASK 7
97
98 #define TXRETRIES 2 /* # of retries for tx frames */
99
100 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
101 one scheduling */
102
103 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
104 one scheduling */
105
106 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
107
108 #define MEMBLOCK 2048 /* Block size used for downloading
109 of dongle image */
110 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
111 biggest possible glom */
112
113 #define BRCMF_FIRSTREAD (1 << 6)
114
115
116 /* SBSDIO_DEVICE_CTL */
117
118 /* 1: device will assert busy signal when receiving CMD53 */
119 #define SBSDIO_DEVCTL_SETBUSY 0x01
120 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
121 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
122 /* 1: mask all interrupts to host except the chipActive (rev 8) */
123 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
124 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
125 * sdio bus power cycle to clear (rev 9) */
126 #define SBSDIO_DEVCTL_PADS_ISO 0x08
127 /* Force SD->SB reset mapping (rev 11) */
128 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
129 /* Determined by CoreControl bit */
130 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
131 /* Force backplane reset */
132 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
133 /* Force no backplane reset */
134 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
135
136 /* SBSDIO_FUNC1_CHIPCLKCSR */
137
138 /* Force ALP request to backplane */
139 #define SBSDIO_FORCE_ALP 0x01
140 /* Force HT request to backplane */
141 #define SBSDIO_FORCE_HT 0x02
142 /* Force ILP request to backplane */
143 #define SBSDIO_FORCE_ILP 0x04
144 /* Make ALP ready (power up xtal) */
145 #define SBSDIO_ALP_AVAIL_REQ 0x08
146 /* Make HT ready (power up PLL) */
147 #define SBSDIO_HT_AVAIL_REQ 0x10
148 /* Squelch clock requests from HW */
149 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
150 /* Status: ALP is ready */
151 #define SBSDIO_ALP_AVAIL 0x40
152 /* Status: HT is ready */
153 #define SBSDIO_HT_AVAIL 0x80
154
155 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
156 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
157 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
158 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
159
160 #define SBSDIO_CLKAV(regval, alponly) \
161 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
162
163 /* direct(mapped) cis space */
164
165 /* MAPPED common CIS address */
166 #define SBSDIO_CIS_BASE_COMMON 0x1000
167 /* maximum bytes in one CIS */
168 #define SBSDIO_CIS_SIZE_LIMIT 0x200
169 /* cis offset addr is < 17 bits */
170 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
171
172 /* manfid tuple length, include tuple, link bytes */
173 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
174
175 /* intstatus */
176 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
177 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
178 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
179 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
180 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
181 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
182 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
183 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
184 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
185 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
186 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
187 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
188 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
189 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
190 #define I_PC (1 << 10) /* descriptor error */
191 #define I_PD (1 << 11) /* data error */
192 #define I_DE (1 << 12) /* Descriptor protocol Error */
193 #define I_RU (1 << 13) /* Receive descriptor Underflow */
194 #define I_RO (1 << 14) /* Receive fifo Overflow */
195 #define I_XU (1 << 15) /* Transmit fifo Underflow */
196 #define I_RI (1 << 16) /* Receive Interrupt */
197 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
198 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
199 #define I_XI (1 << 24) /* Transmit Interrupt */
200 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
201 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
202 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
203 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
204 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
205 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
206 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
207 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
208 #define I_DMA (I_RI | I_XI | I_ERRORS)
209
210 /* corecontrol */
211 #define CC_CISRDY (1 << 0) /* CIS Ready */
212 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
213 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
214 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
215 #define CC_XMTDATAAVAIL_MODE (1 << 4)
216 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
217
218 /* SDA_FRAMECTRL */
219 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
220 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
221 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
222 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
223
224 /* HW frame tag */
225 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
226
227 /* Total length of frame header for dongle protocol */
228 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
229 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
230
231 /*
232 * Software allocation of To SB Mailbox resources
233 */
234
235 /* tosbmailbox bits corresponding to intstatus bits */
236 #define SMB_NAK (1 << 0) /* Frame NAK */
237 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
238 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
239 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
240
241 /* tosbmailboxdata */
242 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
243
244 /*
245 * Software allocation of To Host Mailbox resources
246 */
247
248 /* intstatus bits */
249 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
250 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
251 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
252 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
253
254 /* tohostmailboxdata */
255 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
256 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
257 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
258 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
259
260 #define HMB_DATA_FCDATA_MASK 0xff000000
261 #define HMB_DATA_FCDATA_SHIFT 24
262
263 #define HMB_DATA_VERSION_MASK 0x00ff0000
264 #define HMB_DATA_VERSION_SHIFT 16
265
266 /*
267 * Software-defined protocol header
268 */
269
270 /* Current protocol version */
271 #define SDPCM_PROT_VERSION 4
272
273 /* SW frame header */
274 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
275
276 #define SDPCM_CHANNEL_MASK 0x00000f00
277 #define SDPCM_CHANNEL_SHIFT 8
278 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
279
280 #define SDPCM_NEXTLEN_OFFSET 2
281
282 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
283 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
284 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
285 #define SDPCM_DOFFSET_MASK 0xff000000
286 #define SDPCM_DOFFSET_SHIFT 24
287 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
288 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
289 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
290 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
291
292 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
293
294 /* logical channel numbers */
295 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
296 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
297 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
298 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
299 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
300
301 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
302
303 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
304
305 /*
306 * Shared structure between dongle and the host.
307 * The structure contains pointers to trap or assert information.
308 */
309 #define SDPCM_SHARED_VERSION 0x0002
310 #define SDPCM_SHARED_VERSION_MASK 0x00FF
311 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
312 #define SDPCM_SHARED_ASSERT 0x0200
313 #define SDPCM_SHARED_TRAP 0x0400
314
315 /* Space for header read, limit for data packets */
316 #define MAX_HDR_READ (1 << 6)
317 #define MAX_RX_DATASZ 2048
318
319 /* Maximum milliseconds to wait for F2 to come up */
320 #define BRCMF_WAIT_F2RDY 3000
321
322 /* Bump up limit on waiting for HT to account for first startup;
323 * if the image is doing a CRC calculation before programming the PMU
324 * for HT availability, it could take a couple hundred ms more, so
325 * max out at a 1 second (1000000us).
326 */
327 #undef PMU_MAX_TRANSITION_DLY
328 #define PMU_MAX_TRANSITION_DLY 1000000
329
330 /* Value for ChipClockCSR during initial setup */
331 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
332 SBSDIO_ALP_AVAIL_REQ)
333
334 /* Flags for SDH calls */
335 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
336
337 /* sbimstate */
338 #define SBIM_IBE 0x20000 /* inbanderror */
339 #define SBIM_TO 0x40000 /* timeout */
340 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
341 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
342
343 /* sbtmstatelow */
344
345 /* reset */
346 #define SBTML_RESET 0x0001
347 /* reject field */
348 #define SBTML_REJ_MASK 0x0006
349 /* reject */
350 #define SBTML_REJ 0x0002
351 /* temporary reject, for error recovery */
352 #define SBTML_TMPREJ 0x0004
353
354 /* Shift to locate the SI control flags in sbtml */
355 #define SBTML_SICF_SHIFT 16
356
357 /* sbtmstatehigh */
358 #define SBTMH_SERR 0x0001 /* serror */
359 #define SBTMH_INT 0x0002 /* interrupt */
360 #define SBTMH_BUSY 0x0004 /* busy */
361 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
362
363 /* Shift to locate the SI status flags in sbtmh */
364 #define SBTMH_SISF_SHIFT 16
365
366 /* sbidlow */
367 #define SBIDL_INIT 0x80 /* initiator */
368
369 /* sbidhigh */
370 #define SBIDH_RC_MASK 0x000f /* revision code */
371 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
372 #define SBIDH_RCE_SHIFT 8
373 #define SBCOREREV(sbidh) \
374 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
375 ((sbidh) & SBIDH_RC_MASK))
376 #define SBIDH_CC_MASK 0x8ff0 /* core code */
377 #define SBIDH_CC_SHIFT 4
378 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
379 #define SBIDH_VC_SHIFT 16
380
381 /*
382 * Conversion of 802.1D priority to precedence level
383 */
384 static uint prio2prec(u32 prio)
385 {
386 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
387 (prio^2) : prio;
388 }
389
390 /*
391 * Core reg address translation.
392 * Both macro's returns a 32 bits byte address on the backplane bus.
393 */
394 #define CORE_CC_REG(base, field) \
395 (base + offsetof(struct chipcregs, field))
396 #define CORE_BUS_REG(base, field) \
397 (base + offsetof(struct sdpcmd_regs, field))
398 #define CORE_SB(base, field) \
399 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
400
401 /* core registers */
402 struct sdpcmd_regs {
403 u32 corecontrol; /* 0x00, rev8 */
404 u32 corestatus; /* rev8 */
405 u32 PAD[1];
406 u32 biststatus; /* rev8 */
407
408 /* PCMCIA access */
409 u16 pcmciamesportaladdr; /* 0x010, rev8 */
410 u16 PAD[1];
411 u16 pcmciamesportalmask; /* rev8 */
412 u16 PAD[1];
413 u16 pcmciawrframebc; /* rev8 */
414 u16 PAD[1];
415 u16 pcmciaunderflowtimer; /* rev8 */
416 u16 PAD[1];
417
418 /* interrupt */
419 u32 intstatus; /* 0x020, rev8 */
420 u32 hostintmask; /* rev8 */
421 u32 intmask; /* rev8 */
422 u32 sbintstatus; /* rev8 */
423 u32 sbintmask; /* rev8 */
424 u32 funcintmask; /* rev4 */
425 u32 PAD[2];
426 u32 tosbmailbox; /* 0x040, rev8 */
427 u32 tohostmailbox; /* rev8 */
428 u32 tosbmailboxdata; /* rev8 */
429 u32 tohostmailboxdata; /* rev8 */
430
431 /* synchronized access to registers in SDIO clock domain */
432 u32 sdioaccess; /* 0x050, rev8 */
433 u32 PAD[3];
434
435 /* PCMCIA frame control */
436 u8 pcmciaframectrl; /* 0x060, rev8 */
437 u8 PAD[3];
438 u8 pcmciawatermark; /* rev8 */
439 u8 PAD[155];
440
441 /* interrupt batching control */
442 u32 intrcvlazy; /* 0x100, rev8 */
443 u32 PAD[3];
444
445 /* counters */
446 u32 cmd52rd; /* 0x110, rev8 */
447 u32 cmd52wr; /* rev8 */
448 u32 cmd53rd; /* rev8 */
449 u32 cmd53wr; /* rev8 */
450 u32 abort; /* rev8 */
451 u32 datacrcerror; /* rev8 */
452 u32 rdoutofsync; /* rev8 */
453 u32 wroutofsync; /* rev8 */
454 u32 writebusy; /* rev8 */
455 u32 readwait; /* rev8 */
456 u32 readterm; /* rev8 */
457 u32 writeterm; /* rev8 */
458 u32 PAD[40];
459 u32 clockctlstatus; /* rev8 */
460 u32 PAD[7];
461
462 u32 PAD[128]; /* DMA engines */
463
464 /* SDIO/PCMCIA CIS region */
465 char cis[512]; /* 0x400-0x5ff, rev6 */
466
467 /* PCMCIA function control registers */
468 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
469 u16 PAD[55];
470
471 /* PCMCIA backplane access */
472 u16 backplanecsr; /* 0x76E, rev6 */
473 u16 backplaneaddr0; /* rev6 */
474 u16 backplaneaddr1; /* rev6 */
475 u16 backplaneaddr2; /* rev6 */
476 u16 backplaneaddr3; /* rev6 */
477 u16 backplanedata0; /* rev6 */
478 u16 backplanedata1; /* rev6 */
479 u16 backplanedata2; /* rev6 */
480 u16 backplanedata3; /* rev6 */
481 u16 PAD[31];
482
483 /* sprom "size" & "blank" info */
484 u16 spromstatus; /* 0x7BE, rev2 */
485 u32 PAD[464];
486
487 u16 PAD[0x80];
488 };
489
490 #ifdef BCMDBG
491 /* Device console log buffer state */
492 struct brcmf_console {
493 uint count; /* Poll interval msec counter */
494 uint log_addr; /* Log struct address (fixed) */
495 struct rte_log_le log_le; /* Log struct (host copy) */
496 uint bufsize; /* Size of log buffer */
497 u8 *buf; /* Log buffer (host copy) */
498 uint last; /* Last buffer read index */
499 };
500 #endif /* BCMDBG */
501
502 struct sdpcm_shared {
503 u32 flags;
504 u32 trap_addr;
505 u32 assert_exp_addr;
506 u32 assert_file_addr;
507 u32 assert_line;
508 u32 console_addr; /* Address of struct rte_console */
509 u32 msgtrace_addr;
510 u8 tag[32];
511 };
512
513 struct sdpcm_shared_le {
514 __le32 flags;
515 __le32 trap_addr;
516 __le32 assert_exp_addr;
517 __le32 assert_file_addr;
518 __le32 assert_line;
519 __le32 console_addr; /* Address of struct rte_console */
520 __le32 msgtrace_addr;
521 u8 tag[32];
522 };
523
524
525 /* misc chip info needed by some of the routines */
526 struct chip_info {
527 u32 chip;
528 u32 chiprev;
529 u32 cccorebase;
530 u32 ccrev;
531 u32 cccaps;
532 u32 buscorebase; /* 32 bits backplane bus address */
533 u32 buscorerev;
534 u32 buscoretype;
535 u32 ramcorebase;
536 u32 armcorebase;
537 u32 pmurev;
538 u32 ramsize;
539 };
540
541 /* Private data for SDIO bus interaction */
542 struct brcmf_bus {
543 struct brcmf_pub *drvr;
544
545 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
546 struct chip_info *ci; /* Chip info struct */
547 char *vars; /* Variables (from CIS and/or other) */
548 uint varsz; /* Size of variables buffer */
549
550 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
551
552 u32 hostintmask; /* Copy of Host Interrupt Mask */
553 u32 intstatus; /* Intstatus bits (events) pending */
554 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
555 bool fcstate; /* State of dongle flow-control */
556
557 uint blocksize; /* Block size of SDIO transfers */
558 uint roundup; /* Max roundup limit */
559
560 struct pktq txq; /* Queue length used for flow-control */
561 u8 flowcontrol; /* per prio flow control bitmask */
562 u8 tx_seq; /* Transmit sequence number (next) */
563 u8 tx_max; /* Maximum transmit sequence allowed */
564
565 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
566 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
567 u16 nextlen; /* Next Read Len from last header */
568 u8 rx_seq; /* Receive sequence number (expected) */
569 bool rxskip; /* Skip receive (awaiting NAK ACK) */
570
571 uint rxbound; /* Rx frames to read before resched */
572 uint txbound; /* Tx frames to send before resched */
573 uint txminmax;
574
575 struct sk_buff *glomd; /* Packet containing glomming descriptor */
576 struct sk_buff *glom; /* Packet chain for glommed superframe */
577 uint glomerr; /* Glom packet read errors */
578
579 u8 *rxbuf; /* Buffer for receiving control packets */
580 uint rxblen; /* Allocated length of rxbuf */
581 u8 *rxctl; /* Aligned pointer into rxbuf */
582 u8 *databuf; /* Buffer for receiving big glom packet */
583 u8 *dataptr; /* Aligned pointer into databuf */
584 uint rxlen; /* Length of valid data in buffer */
585
586 u8 sdpcm_ver; /* Bus protocol reported by dongle */
587
588 bool intr; /* Use interrupts */
589 bool poll; /* Use polling */
590 bool ipend; /* Device interrupt is pending */
591 uint intrcount; /* Count of device interrupt callbacks */
592 uint lastintrs; /* Count as of last watchdog timer */
593 uint spurious; /* Count of spurious interrupts */
594 uint pollrate; /* Ticks between device polls */
595 uint polltick; /* Tick counter */
596 uint pollcnt; /* Count of active polls */
597
598 #ifdef BCMDBG
599 uint console_interval;
600 struct brcmf_console console; /* Console output polling support */
601 uint console_addr; /* Console address from shared struct */
602 #endif /* BCMDBG */
603
604 uint regfails; /* Count of R_REG failures */
605
606 uint clkstate; /* State of sd and backplane clock(s) */
607 bool activity; /* Activity flag for clock down */
608 s32 idletime; /* Control for activity timeout */
609 s32 idlecount; /* Activity timeout counter */
610 s32 idleclock; /* How to set bus driver when idle */
611 s32 sd_rxchain;
612 bool use_rxchain; /* If brcmf should use PKT chains */
613 bool sleeping; /* Is SDIO bus sleeping? */
614 bool rxflow_mode; /* Rx flow control mode */
615 bool rxflow; /* Is rx flow control on */
616 bool alp_only; /* Don't use HT clock (ALP only) */
617 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
618 bool usebufpool;
619
620 /* Some additional counters */
621 uint tx_sderrs; /* Count of tx attempts with sd errors */
622 uint fcqueued; /* Tx packets that got queued */
623 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
624 uint rx_toolong; /* Receive frames too long to receive */
625 uint rxc_errors; /* SDIO errors when reading control frames */
626 uint rx_hdrfail; /* SDIO errors on header reads */
627 uint rx_badhdr; /* Bad received headers (roosync?) */
628 uint rx_badseq; /* Mismatched rx sequence number */
629 uint fc_rcvd; /* Number of flow-control events received */
630 uint fc_xoff; /* Number which turned on flow-control */
631 uint fc_xon; /* Number which turned off flow-control */
632 uint rxglomfail; /* Failed deglom attempts */
633 uint rxglomframes; /* Number of glom frames (superframes) */
634 uint rxglompkts; /* Number of packets from glom frames */
635 uint f2rxhdrs; /* Number of header reads */
636 uint f2rxdata; /* Number of frame data reads */
637 uint f2txdata; /* Number of f2 frame writes */
638 uint f1regdata; /* Number of f1 register accesses */
639
640 u8 *ctrl_frame_buf;
641 u32 ctrl_frame_len;
642 bool ctrl_frame_stat;
643
644 spinlock_t txqlock;
645 wait_queue_head_t ctrl_wait;
646 wait_queue_head_t dcmd_resp_wait;
647
648 struct timer_list timer;
649 struct completion watchdog_wait;
650 struct task_struct *watchdog_tsk;
651 bool wd_timer_valid;
652 uint save_ms;
653
654 struct task_struct *dpc_tsk;
655 struct completion dpc_wait;
656
657 struct semaphore sdsem;
658
659 const char *fw_name;
660 const struct firmware *firmware;
661 const char *nv_name;
662 u32 fw_ptr;
663 };
664
665 struct sbconfig {
666 u32 PAD[2];
667 u32 sbipsflag; /* initiator port ocp slave flag */
668 u32 PAD[3];
669 u32 sbtpsflag; /* target port ocp slave flag */
670 u32 PAD[11];
671 u32 sbtmerrloga; /* (sonics >= 2.3) */
672 u32 PAD;
673 u32 sbtmerrlog; /* (sonics >= 2.3) */
674 u32 PAD[3];
675 u32 sbadmatch3; /* address match3 */
676 u32 PAD;
677 u32 sbadmatch2; /* address match2 */
678 u32 PAD;
679 u32 sbadmatch1; /* address match1 */
680 u32 PAD[7];
681 u32 sbimstate; /* initiator agent state */
682 u32 sbintvec; /* interrupt mask */
683 u32 sbtmstatelow; /* target state */
684 u32 sbtmstatehigh; /* target state */
685 u32 sbbwa0; /* bandwidth allocation table0 */
686 u32 PAD;
687 u32 sbimconfiglow; /* initiator configuration */
688 u32 sbimconfighigh; /* initiator configuration */
689 u32 sbadmatch0; /* address match0 */
690 u32 PAD;
691 u32 sbtmconfiglow; /* target configuration */
692 u32 sbtmconfighigh; /* target configuration */
693 u32 sbbconfig; /* broadcast configuration */
694 u32 PAD;
695 u32 sbbstate; /* broadcast state */
696 u32 PAD[3];
697 u32 sbactcnfg; /* activate configuration */
698 u32 PAD[3];
699 u32 sbflagst; /* current sbflags */
700 u32 PAD[3];
701 u32 sbidlow; /* identification */
702 u32 sbidhigh; /* identification */
703 };
704
705 /* clkstate */
706 #define CLK_NONE 0
707 #define CLK_SDONLY 1
708 #define CLK_PENDING 2 /* Not used yet */
709 #define CLK_AVAIL 3
710
711 #ifdef BCMDBG
712 static int qcount[NUMPRIO];
713 static int tx_packets[NUMPRIO];
714 #endif /* BCMDBG */
715
716 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
717
718 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
719
720 /* Retry count for register access failures */
721 static const uint retry_limit = 2;
722
723 /* Limit on rounding up frames */
724 static const uint max_roundup = 512;
725
726 #define ALIGNMENT 4
727
728 static void pkt_align(struct sk_buff *p, int len, int align)
729 {
730 uint datalign;
731 datalign = (unsigned long)(p->data);
732 datalign = roundup(datalign, (align)) - datalign;
733 if (datalign)
734 skb_pull(p, datalign);
735 __skb_trim(p, len);
736 }
737
738 /* To check if there's window offered */
739 static bool data_ok(struct brcmf_bus *bus)
740 {
741 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
742 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
743 }
744
745 /*
746 * Reads a register in the SDIO hardware block. This block occupies a series of
747 * adresses on the 32 bit backplane bus.
748 */
749 static void
750 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
751 {
752 *retryvar = 0;
753 do {
754 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
755 bus->ci->buscorebase + reg_offset, sizeof(u32));
756 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
757 (++(*retryvar) <= retry_limit));
758 if (*retryvar) {
759 bus->regfails += (*retryvar-1);
760 if (*retryvar > retry_limit) {
761 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
762 *regvar = 0;
763 }
764 }
765 }
766
767 static void
768 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
769 {
770 *retryvar = 0;
771 do {
772 brcmf_sdcard_reg_write(bus->sdiodev,
773 bus->ci->buscorebase + reg_offset,
774 sizeof(u32), regval);
775 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
776 (++(*retryvar) <= retry_limit));
777 if (*retryvar) {
778 bus->regfails += (*retryvar-1);
779 if (*retryvar > retry_limit)
780 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
781 reg_offset);
782 }
783 }
784
785 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
786
787 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
788
789 /* Packet free applicable unconditionally for sdio and sdspi.
790 * Conditional if bufpool was present for gspi bus.
791 */
792 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
793 {
794 if (bus->usebufpool)
795 brcmu_pkt_buf_free_skb(pkt);
796 }
797
798 /* Turn backplane clock on or off */
799 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
800 {
801 int err;
802 u8 clkctl, clkreq, devctl;
803 unsigned long timeout;
804
805 brcmf_dbg(TRACE, "Enter\n");
806
807 clkctl = 0;
808
809 if (on) {
810 /* Request HT Avail */
811 clkreq =
812 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
813
814 if ((bus->ci->chip == BCM4329_CHIP_ID)
815 && (bus->ci->chiprev == 0))
816 clkreq |= SBSDIO_FORCE_ALP;
817
818 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
819 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
820 if (err) {
821 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
822 return -EBADE;
823 }
824
825 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
826 && (bus->ci->buscorerev == 9))) {
827 u32 dummy, retries;
828 r_sdreg32(bus, &dummy,
829 offsetof(struct sdpcmd_regs, clockctlstatus),
830 &retries);
831 }
832
833 /* Check current status */
834 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
835 SBSDIO_FUNC1_CHIPCLKCSR, &err);
836 if (err) {
837 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
838 return -EBADE;
839 }
840
841 /* Go to pending and await interrupt if appropriate */
842 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
843 /* Allow only clock-available interrupt */
844 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
845 SDIO_FUNC_1,
846 SBSDIO_DEVICE_CTL, &err);
847 if (err) {
848 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
849 err);
850 return -EBADE;
851 }
852
853 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
854 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
855 SBSDIO_DEVICE_CTL, devctl, &err);
856 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
857 bus->clkstate = CLK_PENDING;
858
859 return 0;
860 } else if (bus->clkstate == CLK_PENDING) {
861 /* Cancel CA-only interrupt filter */
862 devctl =
863 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
864 SBSDIO_DEVICE_CTL, &err);
865 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
866 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
867 SBSDIO_DEVICE_CTL, devctl, &err);
868 }
869
870 /* Otherwise, wait here (polling) for HT Avail */
871 timeout = jiffies +
872 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
873 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
874 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
875 SDIO_FUNC_1,
876 SBSDIO_FUNC1_CHIPCLKCSR,
877 &err);
878 if (time_after(jiffies, timeout))
879 break;
880 else
881 usleep_range(5000, 10000);
882 }
883 if (err) {
884 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
885 return -EBADE;
886 }
887 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
888 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
889 PMU_MAX_TRANSITION_DLY, clkctl);
890 return -EBADE;
891 }
892
893 /* Mark clock available */
894 bus->clkstate = CLK_AVAIL;
895 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
896
897 #if defined(BCMDBG)
898 if (bus->alp_only != true) {
899 if (SBSDIO_ALPONLY(clkctl))
900 brcmf_dbg(ERROR, "HT Clock should be on\n");
901 }
902 #endif /* defined (BCMDBG) */
903
904 bus->activity = true;
905 } else {
906 clkreq = 0;
907
908 if (bus->clkstate == CLK_PENDING) {
909 /* Cancel CA-only interrupt filter */
910 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
911 SDIO_FUNC_1,
912 SBSDIO_DEVICE_CTL, &err);
913 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
915 SBSDIO_DEVICE_CTL, devctl, &err);
916 }
917
918 bus->clkstate = CLK_SDONLY;
919 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
920 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
921 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
922 if (err) {
923 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
924 err);
925 return -EBADE;
926 }
927 }
928 return 0;
929 }
930
931 /* Change idle/active SD state */
932 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
933 {
934 brcmf_dbg(TRACE, "Enter\n");
935
936 if (on)
937 bus->clkstate = CLK_SDONLY;
938 else
939 bus->clkstate = CLK_NONE;
940
941 return 0;
942 }
943
944 /* Transition SD and backplane clock readiness */
945 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
946 {
947 #ifdef BCMDBG
948 uint oldstate = bus->clkstate;
949 #endif /* BCMDBG */
950
951 brcmf_dbg(TRACE, "Enter\n");
952
953 /* Early exit if we're already there */
954 if (bus->clkstate == target) {
955 if (target == CLK_AVAIL) {
956 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
957 bus->activity = true;
958 }
959 return 0;
960 }
961
962 switch (target) {
963 case CLK_AVAIL:
964 /* Make sure SD clock is available */
965 if (bus->clkstate == CLK_NONE)
966 brcmf_sdbrcm_sdclk(bus, true);
967 /* Now request HT Avail on the backplane */
968 brcmf_sdbrcm_htclk(bus, true, pendok);
969 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
970 bus->activity = true;
971 break;
972
973 case CLK_SDONLY:
974 /* Remove HT request, or bring up SD clock */
975 if (bus->clkstate == CLK_NONE)
976 brcmf_sdbrcm_sdclk(bus, true);
977 else if (bus->clkstate == CLK_AVAIL)
978 brcmf_sdbrcm_htclk(bus, false, false);
979 else
980 brcmf_dbg(ERROR, "request for %d -> %d\n",
981 bus->clkstate, target);
982 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
983 break;
984
985 case CLK_NONE:
986 /* Make sure to remove HT request */
987 if (bus->clkstate == CLK_AVAIL)
988 brcmf_sdbrcm_htclk(bus, false, false);
989 /* Now remove the SD clock */
990 brcmf_sdbrcm_sdclk(bus, false);
991 brcmf_sdbrcm_wd_timer(bus, 0);
992 break;
993 }
994 #ifdef BCMDBG
995 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
996 #endif /* BCMDBG */
997
998 return 0;
999 }
1000
1001 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1002 {
1003 uint retries = 0;
1004
1005 brcmf_dbg(INFO, "request %s (currently %s)\n",
1006 sleep ? "SLEEP" : "WAKE",
1007 bus->sleeping ? "SLEEP" : "WAKE");
1008
1009 /* Done if we're already in the requested state */
1010 if (sleep == bus->sleeping)
1011 return 0;
1012
1013 /* Going to sleep: set the alarm and turn off the lights... */
1014 if (sleep) {
1015 /* Don't sleep if something is pending */
1016 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1017 return -EBUSY;
1018
1019 /* Make sure the controller has the bus up */
1020 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1021
1022 /* Tell device to start using OOB wakeup */
1023 w_sdreg32(bus, SMB_USE_OOB,
1024 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1025 if (retries > retry_limit)
1026 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1027
1028 /* Turn off our contribution to the HT clock request */
1029 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1030
1031 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1032 SBSDIO_FUNC1_CHIPCLKCSR,
1033 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1034
1035 /* Isolate the bus */
1036 if (bus->ci->chip != BCM4329_CHIP_ID) {
1037 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1038 SBSDIO_DEVICE_CTL,
1039 SBSDIO_DEVCTL_PADS_ISO, NULL);
1040 }
1041
1042 /* Change state */
1043 bus->sleeping = true;
1044
1045 } else {
1046 /* Waking up: bus power up is ok, set local state */
1047
1048 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1049 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1050
1051 /* Force pad isolation off if possible
1052 (in case power never toggled) */
1053 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1054 && (bus->ci->buscorerev >= 10))
1055 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1056 SBSDIO_DEVICE_CTL, 0, NULL);
1057
1058 /* Make sure the controller has the bus up */
1059 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1060
1061 /* Send misc interrupt to indicate OOB not needed */
1062 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1063 &retries);
1064 if (retries <= retry_limit)
1065 w_sdreg32(bus, SMB_DEV_INT,
1066 offsetof(struct sdpcmd_regs, tosbmailbox),
1067 &retries);
1068
1069 if (retries > retry_limit)
1070 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1071
1072 /* Make sure we have SD bus access */
1073 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1074
1075 /* Change state */
1076 bus->sleeping = false;
1077 }
1078
1079 return 0;
1080 }
1081
1082 static void bus_wake(struct brcmf_bus *bus)
1083 {
1084 if (bus->sleeping)
1085 brcmf_sdbrcm_bussleep(bus, false);
1086 }
1087
1088 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1089 {
1090 u32 intstatus = 0;
1091 u32 hmb_data;
1092 u8 fcbits;
1093 uint retries = 0;
1094
1095 brcmf_dbg(TRACE, "Enter\n");
1096
1097 /* Read mailbox data and ack that we did so */
1098 r_sdreg32(bus, &hmb_data,
1099 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1100
1101 if (retries <= retry_limit)
1102 w_sdreg32(bus, SMB_INT_ACK,
1103 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1104 bus->f1regdata += 2;
1105
1106 /* Dongle recomposed rx frames, accept them again */
1107 if (hmb_data & HMB_DATA_NAKHANDLED) {
1108 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1109 bus->rx_seq);
1110 if (!bus->rxskip)
1111 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1112
1113 bus->rxskip = false;
1114 intstatus |= I_HMB_FRAME_IND;
1115 }
1116
1117 /*
1118 * DEVREADY does not occur with gSPI.
1119 */
1120 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1121 bus->sdpcm_ver =
1122 (hmb_data & HMB_DATA_VERSION_MASK) >>
1123 HMB_DATA_VERSION_SHIFT;
1124 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1125 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1126 "expecting %d\n",
1127 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1128 else
1129 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1130 bus->sdpcm_ver);
1131 }
1132
1133 /*
1134 * Flow Control has been moved into the RX headers and this out of band
1135 * method isn't used any more.
1136 * remaining backward compatible with older dongles.
1137 */
1138 if (hmb_data & HMB_DATA_FC) {
1139 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1140 HMB_DATA_FCDATA_SHIFT;
1141
1142 if (fcbits & ~bus->flowcontrol)
1143 bus->fc_xoff++;
1144
1145 if (bus->flowcontrol & ~fcbits)
1146 bus->fc_xon++;
1147
1148 bus->fc_rcvd++;
1149 bus->flowcontrol = fcbits;
1150 }
1151
1152 /* Shouldn't be any others */
1153 if (hmb_data & ~(HMB_DATA_DEVREADY |
1154 HMB_DATA_NAKHANDLED |
1155 HMB_DATA_FC |
1156 HMB_DATA_FWREADY |
1157 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1158 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1159 hmb_data);
1160
1161 return intstatus;
1162 }
1163
1164 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1165 {
1166 uint retries = 0;
1167 u16 lastrbc;
1168 u8 hi, lo;
1169 int err;
1170
1171 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1172 abort ? "abort command, " : "",
1173 rtx ? ", send NAK" : "");
1174
1175 if (abort)
1176 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1177
1178 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1179 SBSDIO_FUNC1_FRAMECTRL,
1180 SFC_RF_TERM, &err);
1181 bus->f1regdata++;
1182
1183 /* Wait until the packet has been flushed (device/FIFO stable) */
1184 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1185 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1186 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1187 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1188 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1189 bus->f1regdata += 2;
1190
1191 if ((hi == 0) && (lo == 0))
1192 break;
1193
1194 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1195 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1196 lastrbc, (hi << 8) + lo);
1197 }
1198 lastrbc = (hi << 8) + lo;
1199 }
1200
1201 if (!retries)
1202 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1203 else
1204 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1205
1206 if (rtx) {
1207 bus->rxrtx++;
1208 w_sdreg32(bus, SMB_NAK,
1209 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1210
1211 bus->f1regdata++;
1212 if (retries <= retry_limit)
1213 bus->rxskip = true;
1214 }
1215
1216 /* Clear partial in any case */
1217 bus->nextlen = 0;
1218
1219 /* If we can't reach the device, signal failure */
1220 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1221 bus->drvr->busstate = BRCMF_BUS_DOWN;
1222 }
1223
1224 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1225 {
1226 u16 dlen, totlen;
1227 u8 *dptr, num = 0;
1228
1229 u16 sublen, check;
1230 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1231
1232 int errcode;
1233 u8 chan, seq, doff, sfdoff;
1234 u8 txmax;
1235
1236 int ifidx = 0;
1237 bool usechain = bus->use_rxchain;
1238
1239 /* If packets, issue read(s) and send up packet chain */
1240 /* Return sequence numbers consumed? */
1241
1242 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
1243
1244 /* If there's a descriptor, generate the packet chain */
1245 if (bus->glomd) {
1246 pfirst = plast = pnext = NULL;
1247 dlen = (u16) (bus->glomd->len);
1248 dptr = bus->glomd->data;
1249 if (!dlen || (dlen & 1)) {
1250 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1251 dlen);
1252 dlen = 0;
1253 }
1254
1255 for (totlen = num = 0; dlen; num++) {
1256 /* Get (and move past) next length */
1257 sublen = get_unaligned_le16(dptr);
1258 dlen -= sizeof(u16);
1259 dptr += sizeof(u16);
1260 if ((sublen < SDPCM_HDRLEN) ||
1261 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1262 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1263 num, sublen);
1264 pnext = NULL;
1265 break;
1266 }
1267 if (sublen % BRCMF_SDALIGN) {
1268 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1269 sublen, BRCMF_SDALIGN);
1270 usechain = false;
1271 }
1272 totlen += sublen;
1273
1274 /* For last frame, adjust read len so total
1275 is a block multiple */
1276 if (!dlen) {
1277 sublen +=
1278 (roundup(totlen, bus->blocksize) - totlen);
1279 totlen = roundup(totlen, bus->blocksize);
1280 }
1281
1282 /* Allocate/chain packet for next subframe */
1283 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1284 if (pnext == NULL) {
1285 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1286 num, sublen);
1287 break;
1288 }
1289 if (!pfirst) {
1290 pfirst = plast = pnext;
1291 } else {
1292 plast->next = pnext;
1293 plast = pnext;
1294 }
1295
1296 /* Adhere to start alignment requirements */
1297 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1298 }
1299
1300 /* If all allocations succeeded, save packet chain
1301 in bus structure */
1302 if (pnext) {
1303 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1304 totlen, num);
1305 if (BRCMF_GLOM_ON() && bus->nextlen &&
1306 totlen != bus->nextlen) {
1307 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1308 bus->nextlen, totlen, rxseq);
1309 }
1310 bus->glom = pfirst;
1311 pfirst = pnext = NULL;
1312 } else {
1313 if (pfirst)
1314 brcmu_pkt_buf_free_skb(pfirst);
1315 bus->glom = NULL;
1316 num = 0;
1317 }
1318
1319 /* Done with descriptor packet */
1320 brcmu_pkt_buf_free_skb(bus->glomd);
1321 bus->glomd = NULL;
1322 bus->nextlen = 0;
1323 }
1324
1325 /* Ok -- either we just generated a packet chain,
1326 or had one from before */
1327 if (bus->glom) {
1328 if (BRCMF_GLOM_ON()) {
1329 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1330 for (pnext = bus->glom; pnext; pnext = pnext->next) {
1331 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1332 pnext, (u8 *) (pnext->data),
1333 pnext->len, pnext->len);
1334 }
1335 }
1336
1337 pfirst = bus->glom;
1338 dlen = (u16) brcmu_pkttotlen(pfirst);
1339
1340 /* Do an SDIO read for the superframe. Configurable iovar to
1341 * read directly into the chained packet, or allocate a large
1342 * packet and and copy into the chain.
1343 */
1344 if (usechain) {
1345 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1346 bus->sdiodev->sbwad,
1347 SDIO_FUNC_2,
1348 F2SYNC, (u8 *) pfirst->data, dlen,
1349 pfirst);
1350 } else if (bus->dataptr) {
1351 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1352 bus->sdiodev->sbwad,
1353 SDIO_FUNC_2,
1354 F2SYNC, bus->dataptr, dlen,
1355 NULL);
1356 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
1357 bus->dataptr);
1358 if (sublen != dlen) {
1359 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1360 dlen, sublen);
1361 errcode = -1;
1362 }
1363 pnext = NULL;
1364 } else {
1365 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1366 dlen);
1367 errcode = -1;
1368 }
1369 bus->f2rxdata++;
1370
1371 /* On failure, kill the superframe, allow a couple retries */
1372 if (errcode < 0) {
1373 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1374 dlen, errcode);
1375 bus->drvr->rx_errors++;
1376
1377 if (bus->glomerr++ < 3) {
1378 brcmf_sdbrcm_rxfail(bus, true, true);
1379 } else {
1380 bus->glomerr = 0;
1381 brcmf_sdbrcm_rxfail(bus, true, false);
1382 brcmu_pkt_buf_free_skb(bus->glom);
1383 bus->rxglomfail++;
1384 bus->glom = NULL;
1385 }
1386 return 0;
1387 }
1388 #ifdef BCMDBG
1389 if (BRCMF_GLOM_ON()) {
1390 printk(KERN_DEBUG "SUPERFRAME:\n");
1391 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1392 pfirst->data, min_t(int, pfirst->len, 48));
1393 }
1394 #endif
1395
1396 /* Validate the superframe header */
1397 dptr = (u8 *) (pfirst->data);
1398 sublen = get_unaligned_le16(dptr);
1399 check = get_unaligned_le16(dptr + sizeof(u16));
1400
1401 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1402 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1403 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1404 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1405 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1406 bus->nextlen, seq);
1407 bus->nextlen = 0;
1408 }
1409 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1410 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1411
1412 errcode = 0;
1413 if ((u16)~(sublen ^ check)) {
1414 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1415 sublen, check);
1416 errcode = -1;
1417 } else if (roundup(sublen, bus->blocksize) != dlen) {
1418 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1419 sublen, roundup(sublen, bus->blocksize),
1420 dlen);
1421 errcode = -1;
1422 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1423 SDPCM_GLOM_CHANNEL) {
1424 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1425 SDPCM_PACKET_CHANNEL(
1426 &dptr[SDPCM_FRAMETAG_LEN]));
1427 errcode = -1;
1428 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1429 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1430 errcode = -1;
1431 } else if ((doff < SDPCM_HDRLEN) ||
1432 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1433 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1434 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1435 errcode = -1;
1436 }
1437
1438 /* Check sequence number of superframe SW header */
1439 if (rxseq != seq) {
1440 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1441 seq, rxseq);
1442 bus->rx_badseq++;
1443 rxseq = seq;
1444 }
1445
1446 /* Check window for sanity */
1447 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1448 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1449 txmax, bus->tx_seq);
1450 txmax = bus->tx_seq + 2;
1451 }
1452 bus->tx_max = txmax;
1453
1454 /* Remove superframe header, remember offset */
1455 skb_pull(pfirst, doff);
1456 sfdoff = doff;
1457
1458 /* Validate all the subframe headers */
1459 for (num = 0, pnext = pfirst; pnext && !errcode;
1460 num++, pnext = pnext->next) {
1461 dptr = (u8 *) (pnext->data);
1462 dlen = (u16) (pnext->len);
1463 sublen = get_unaligned_le16(dptr);
1464 check = get_unaligned_le16(dptr + sizeof(u16));
1465 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1466 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1467 #ifdef BCMDBG
1468 if (BRCMF_GLOM_ON()) {
1469 printk(KERN_DEBUG "subframe:\n");
1470 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1471 dptr, 32);
1472 }
1473 #endif
1474
1475 if ((u16)~(sublen ^ check)) {
1476 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1477 num, sublen, check);
1478 errcode = -1;
1479 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1480 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1481 num, sublen, dlen);
1482 errcode = -1;
1483 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1484 (chan != SDPCM_EVENT_CHANNEL)) {
1485 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1486 num, chan);
1487 errcode = -1;
1488 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1489 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1490 num, doff, sublen, SDPCM_HDRLEN);
1491 errcode = -1;
1492 }
1493 }
1494
1495 if (errcode) {
1496 /* Terminate frame on error, request
1497 a couple retries */
1498 if (bus->glomerr++ < 3) {
1499 /* Restore superframe header space */
1500 skb_push(pfirst, sfdoff);
1501 brcmf_sdbrcm_rxfail(bus, true, true);
1502 } else {
1503 bus->glomerr = 0;
1504 brcmf_sdbrcm_rxfail(bus, true, false);
1505 brcmu_pkt_buf_free_skb(bus->glom);
1506 bus->rxglomfail++;
1507 bus->glom = NULL;
1508 }
1509 bus->nextlen = 0;
1510 return 0;
1511 }
1512
1513 /* Basic SD framing looks ok - process each packet (header) */
1514 save_pfirst = pfirst;
1515 bus->glom = NULL;
1516 plast = NULL;
1517
1518 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1519 pnext = pfirst->next;
1520 pfirst->next = NULL;
1521
1522 dptr = (u8 *) (pfirst->data);
1523 sublen = get_unaligned_le16(dptr);
1524 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1525 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1526 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1527
1528 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1529 num, pfirst, pfirst->data,
1530 pfirst->len, sublen, chan, seq);
1531
1532 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1533 chan == SDPCM_EVENT_CHANNEL */
1534
1535 if (rxseq != seq) {
1536 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1537 seq, rxseq);
1538 bus->rx_badseq++;
1539 rxseq = seq;
1540 }
1541 #ifdef BCMDBG
1542 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1543 printk(KERN_DEBUG "Rx Subframe Data:\n");
1544 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1545 dptr, dlen);
1546 }
1547 #endif
1548
1549 __skb_trim(pfirst, sublen);
1550 skb_pull(pfirst, doff);
1551
1552 if (pfirst->len == 0) {
1553 brcmu_pkt_buf_free_skb(pfirst);
1554 if (plast)
1555 plast->next = pnext;
1556 else
1557 save_pfirst = pnext;
1558
1559 continue;
1560 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1561 pfirst) != 0) {
1562 brcmf_dbg(ERROR, "rx protocol error\n");
1563 bus->drvr->rx_errors++;
1564 brcmu_pkt_buf_free_skb(pfirst);
1565 if (plast)
1566 plast->next = pnext;
1567 else
1568 save_pfirst = pnext;
1569
1570 continue;
1571 }
1572
1573 /* this packet will go up, link back into
1574 chain and count it */
1575 pfirst->next = pnext;
1576 plast = pfirst;
1577 num++;
1578
1579 #ifdef BCMDBG
1580 if (BRCMF_GLOM_ON()) {
1581 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1582 num, pfirst, pfirst->data,
1583 pfirst->len, pfirst->next,
1584 pfirst->prev);
1585 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1586 pfirst->data,
1587 min_t(int, pfirst->len, 32));
1588 }
1589 #endif /* BCMDBG */
1590 }
1591 if (num) {
1592 up(&bus->sdsem);
1593 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1594 down(&bus->sdsem);
1595 }
1596
1597 bus->rxglomframes++;
1598 bus->rxglompkts += num;
1599 }
1600 return num;
1601 }
1602
1603 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1604 bool *pending)
1605 {
1606 DECLARE_WAITQUEUE(wait, current);
1607 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1608
1609 /* Wait until control frame is available */
1610 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1611 set_current_state(TASK_INTERRUPTIBLE);
1612
1613 while (!(*condition) && (!signal_pending(current) && timeout))
1614 timeout = schedule_timeout(timeout);
1615
1616 if (signal_pending(current))
1617 *pending = true;
1618
1619 set_current_state(TASK_RUNNING);
1620 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1621
1622 return timeout;
1623 }
1624
1625 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1626 {
1627 if (waitqueue_active(&bus->dcmd_resp_wait))
1628 wake_up_interruptible(&bus->dcmd_resp_wait);
1629
1630 return 0;
1631 }
1632 static void
1633 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1634 {
1635 uint rdlen, pad;
1636
1637 int sdret;
1638
1639 brcmf_dbg(TRACE, "Enter\n");
1640
1641 /* Set rxctl for frame (w/optional alignment) */
1642 bus->rxctl = bus->rxbuf;
1643 bus->rxctl += BRCMF_FIRSTREAD;
1644 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1645 if (pad)
1646 bus->rxctl += (BRCMF_SDALIGN - pad);
1647 bus->rxctl -= BRCMF_FIRSTREAD;
1648
1649 /* Copy the already-read portion over */
1650 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1651 if (len <= BRCMF_FIRSTREAD)
1652 goto gotpkt;
1653
1654 /* Raise rdlen to next SDIO block to avoid tail command */
1655 rdlen = len - BRCMF_FIRSTREAD;
1656 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1657 pad = bus->blocksize - (rdlen % bus->blocksize);
1658 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1659 ((len + pad) < bus->drvr->maxctl))
1660 rdlen += pad;
1661 } else if (rdlen % BRCMF_SDALIGN) {
1662 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1663 }
1664
1665 /* Satisfy length-alignment requirements */
1666 if (rdlen & (ALIGNMENT - 1))
1667 rdlen = roundup(rdlen, ALIGNMENT);
1668
1669 /* Drop if the read is too big or it exceeds our maximum */
1670 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1671 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1672 rdlen, bus->drvr->maxctl);
1673 bus->drvr->rx_errors++;
1674 brcmf_sdbrcm_rxfail(bus, false, false);
1675 goto done;
1676 }
1677
1678 if ((len - doff) > bus->drvr->maxctl) {
1679 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1680 len, len - doff, bus->drvr->maxctl);
1681 bus->drvr->rx_errors++;
1682 bus->rx_toolong++;
1683 brcmf_sdbrcm_rxfail(bus, false, false);
1684 goto done;
1685 }
1686
1687 /* Read remainder of frame body into the rxctl buffer */
1688 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1689 bus->sdiodev->sbwad,
1690 SDIO_FUNC_2,
1691 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1692 NULL);
1693 bus->f2rxdata++;
1694
1695 /* Control frame failures need retransmission */
1696 if (sdret < 0) {
1697 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1698 rdlen, sdret);
1699 bus->rxc_errors++;
1700 brcmf_sdbrcm_rxfail(bus, true, true);
1701 goto done;
1702 }
1703
1704 gotpkt:
1705
1706 #ifdef BCMDBG
1707 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1708 printk(KERN_DEBUG "RxCtrl:\n");
1709 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1710 }
1711 #endif
1712
1713 /* Point to valid data and indicate its length */
1714 bus->rxctl += doff;
1715 bus->rxlen = len - doff;
1716
1717 done:
1718 /* Awake any waiters */
1719 brcmf_sdbrcm_dcmd_resp_wake(bus);
1720 }
1721
1722 /* Pad read to blocksize for efficiency */
1723 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1724 {
1725 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1726 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1727 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1728 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1729 *rdlen += *pad;
1730 } else if (*rdlen % BRCMF_SDALIGN) {
1731 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1732 }
1733 }
1734
1735 static void
1736 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1737 struct sk_buff **pkt, u8 **rxbuf)
1738 {
1739 int sdret; /* Return code from calls */
1740
1741 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1742 if (*pkt == NULL)
1743 return;
1744
1745 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1746 *rxbuf = (u8 *) ((*pkt)->data);
1747 /* Read the entire frame */
1748 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1749 SDIO_FUNC_2, F2SYNC,
1750 *rxbuf, rdlen, *pkt);
1751 bus->f2rxdata++;
1752
1753 if (sdret < 0) {
1754 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1755 rdlen, sdret);
1756 brcmu_pkt_buf_free_skb(*pkt);
1757 bus->drvr->rx_errors++;
1758 /* Force retry w/normal header read.
1759 * Don't attempt NAK for
1760 * gSPI
1761 */
1762 brcmf_sdbrcm_rxfail(bus, true, true);
1763 *pkt = NULL;
1764 }
1765 }
1766
1767 /* Checks the header */
1768 static int
1769 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1770 u8 rxseq, u16 nextlen, u16 *len)
1771 {
1772 u16 check;
1773 bool len_consistent; /* Result of comparing readahead len and
1774 len from hw-hdr */
1775
1776 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1777
1778 /* Extract hardware header fields */
1779 *len = get_unaligned_le16(bus->rxhdr);
1780 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1781
1782 /* All zeros means readahead info was bad */
1783 if (!(*len | check)) {
1784 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1785 goto fail;
1786 }
1787
1788 /* Validate check bytes */
1789 if ((u16)~(*len ^ check)) {
1790 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1791 nextlen, *len, check);
1792 bus->rx_badhdr++;
1793 brcmf_sdbrcm_rxfail(bus, false, false);
1794 goto fail;
1795 }
1796
1797 /* Validate frame length */
1798 if (*len < SDPCM_HDRLEN) {
1799 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1800 *len);
1801 goto fail;
1802 }
1803
1804 /* Check for consistency with readahead info */
1805 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1806 if (len_consistent) {
1807 /* Mismatch, force retry w/normal
1808 header (may be >4K) */
1809 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1810 nextlen, *len, roundup(*len, 16),
1811 rxseq);
1812 brcmf_sdbrcm_rxfail(bus, true, true);
1813 goto fail;
1814 }
1815
1816 return 0;
1817
1818 fail:
1819 brcmf_sdbrcm_pktfree2(bus, pkt);
1820 return -EINVAL;
1821 }
1822
1823 /* Return true if there may be more frames to read */
1824 static uint
1825 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1826 {
1827 u16 len, check; /* Extracted hardware header fields */
1828 u8 chan, seq, doff; /* Extracted software header fields */
1829 u8 fcbits; /* Extracted fcbits from software header */
1830
1831 struct sk_buff *pkt; /* Packet for event or data frames */
1832 u16 pad; /* Number of pad bytes to read */
1833 u16 rdlen; /* Total number of bytes to read */
1834 u8 rxseq; /* Next sequence number to expect */
1835 uint rxleft = 0; /* Remaining number of frames allowed */
1836 int sdret; /* Return code from calls */
1837 u8 txmax; /* Maximum tx sequence offered */
1838 u8 *rxbuf;
1839 int ifidx = 0;
1840 uint rxcount = 0; /* Total frames read */
1841
1842 brcmf_dbg(TRACE, "Enter\n");
1843
1844 /* Not finished unless we encounter no more frames indication */
1845 *finished = false;
1846
1847 for (rxseq = bus->rx_seq, rxleft = maxframes;
1848 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1849 rxseq++, rxleft--) {
1850
1851 /* Handle glomming separately */
1852 if (bus->glom || bus->glomd) {
1853 u8 cnt;
1854 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1855 bus->glomd, bus->glom);
1856 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1857 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1858 rxseq += cnt - 1;
1859 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1860 continue;
1861 }
1862
1863 /* Try doing single read if we can */
1864 if (bus->nextlen) {
1865 u16 nextlen = bus->nextlen;
1866 bus->nextlen = 0;
1867
1868 rdlen = len = nextlen << 4;
1869 brcmf_pad(bus, &pad, &rdlen);
1870
1871 /*
1872 * After the frame is received we have to
1873 * distinguish whether it is data
1874 * or non-data frame.
1875 */
1876 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1877 if (pkt == NULL) {
1878 /* Give up on data, request rtx of events */
1879 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1880 len, rdlen, rxseq);
1881 continue;
1882 }
1883
1884 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1885 &len) < 0)
1886 continue;
1887
1888 /* Extract software header fields */
1889 chan = SDPCM_PACKET_CHANNEL(
1890 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1891 seq = SDPCM_PACKET_SEQUENCE(
1892 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1893 doff = SDPCM_DOFFSET_VALUE(
1894 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1895 txmax = SDPCM_WINDOW_VALUE(
1896 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1897
1898 bus->nextlen =
1899 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1900 SDPCM_NEXTLEN_OFFSET];
1901 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1902 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1903 bus->nextlen, seq);
1904 bus->nextlen = 0;
1905 }
1906
1907 bus->drvr->rx_readahead_cnt++;
1908
1909 /* Handle Flow Control */
1910 fcbits = SDPCM_FCMASK_VALUE(
1911 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1912
1913 if (bus->flowcontrol != fcbits) {
1914 if (~bus->flowcontrol & fcbits)
1915 bus->fc_xoff++;
1916
1917 if (bus->flowcontrol & ~fcbits)
1918 bus->fc_xon++;
1919
1920 bus->fc_rcvd++;
1921 bus->flowcontrol = fcbits;
1922 }
1923
1924 /* Check and update sequence number */
1925 if (rxseq != seq) {
1926 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1927 seq, rxseq);
1928 bus->rx_badseq++;
1929 rxseq = seq;
1930 }
1931
1932 /* Check window for sanity */
1933 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1934 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1935 txmax, bus->tx_seq);
1936 txmax = bus->tx_seq + 2;
1937 }
1938 bus->tx_max = txmax;
1939
1940 #ifdef BCMDBG
1941 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1942 printk(KERN_DEBUG "Rx Data:\n");
1943 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1944 rxbuf, len);
1945 } else if (BRCMF_HDRS_ON()) {
1946 printk(KERN_DEBUG "RxHdr:\n");
1947 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1948 bus->rxhdr, SDPCM_HDRLEN);
1949 }
1950 #endif
1951
1952 if (chan == SDPCM_CONTROL_CHANNEL) {
1953 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1954 seq);
1955 /* Force retry w/normal header read */
1956 bus->nextlen = 0;
1957 brcmf_sdbrcm_rxfail(bus, false, true);
1958 brcmf_sdbrcm_pktfree2(bus, pkt);
1959 continue;
1960 }
1961
1962 /* Validate data offset */
1963 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1964 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1965 doff, len, SDPCM_HDRLEN);
1966 brcmf_sdbrcm_rxfail(bus, false, false);
1967 brcmf_sdbrcm_pktfree2(bus, pkt);
1968 continue;
1969 }
1970
1971 /* All done with this one -- now deliver the packet */
1972 goto deliver;
1973 }
1974
1975 /* Read frame header (hardware and software) */
1976 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1977 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1978 BRCMF_FIRSTREAD, NULL);
1979 bus->f2rxhdrs++;
1980
1981 if (sdret < 0) {
1982 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1983 bus->rx_hdrfail++;
1984 brcmf_sdbrcm_rxfail(bus, true, true);
1985 continue;
1986 }
1987 #ifdef BCMDBG
1988 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1989 printk(KERN_DEBUG "RxHdr:\n");
1990 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1991 bus->rxhdr, SDPCM_HDRLEN);
1992 }
1993 #endif
1994
1995 /* Extract hardware header fields */
1996 len = get_unaligned_le16(bus->rxhdr);
1997 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1998
1999 /* All zeros means no more frames */
2000 if (!(len | check)) {
2001 *finished = true;
2002 break;
2003 }
2004
2005 /* Validate check bytes */
2006 if ((u16) ~(len ^ check)) {
2007 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2008 len, check);
2009 bus->rx_badhdr++;
2010 brcmf_sdbrcm_rxfail(bus, false, false);
2011 continue;
2012 }
2013
2014 /* Validate frame length */
2015 if (len < SDPCM_HDRLEN) {
2016 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2017 continue;
2018 }
2019
2020 /* Extract software header fields */
2021 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2022 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2023 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2024 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2025
2026 /* Validate data offset */
2027 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2028 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2029 doff, len, SDPCM_HDRLEN, seq);
2030 bus->rx_badhdr++;
2031 brcmf_sdbrcm_rxfail(bus, false, false);
2032 continue;
2033 }
2034
2035 /* Save the readahead length if there is one */
2036 bus->nextlen =
2037 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2038 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2039 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2040 bus->nextlen, seq);
2041 bus->nextlen = 0;
2042 }
2043
2044 /* Handle Flow Control */
2045 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2046
2047 if (bus->flowcontrol != fcbits) {
2048 if (~bus->flowcontrol & fcbits)
2049 bus->fc_xoff++;
2050
2051 if (bus->flowcontrol & ~fcbits)
2052 bus->fc_xon++;
2053
2054 bus->fc_rcvd++;
2055 bus->flowcontrol = fcbits;
2056 }
2057
2058 /* Check and update sequence number */
2059 if (rxseq != seq) {
2060 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2061 bus->rx_badseq++;
2062 rxseq = seq;
2063 }
2064
2065 /* Check window for sanity */
2066 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2067 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2068 txmax, bus->tx_seq);
2069 txmax = bus->tx_seq + 2;
2070 }
2071 bus->tx_max = txmax;
2072
2073 /* Call a separate function for control frames */
2074 if (chan == SDPCM_CONTROL_CHANNEL) {
2075 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2076 continue;
2077 }
2078
2079 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2080 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2081 SDPCM_GLOM_CHANNEL */
2082
2083 /* Length to read */
2084 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2085
2086 /* May pad read to blocksize for efficiency */
2087 if (bus->roundup && bus->blocksize &&
2088 (rdlen > bus->blocksize)) {
2089 pad = bus->blocksize - (rdlen % bus->blocksize);
2090 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2091 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2092 rdlen += pad;
2093 } else if (rdlen % BRCMF_SDALIGN) {
2094 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2095 }
2096
2097 /* Satisfy length-alignment requirements */
2098 if (rdlen & (ALIGNMENT - 1))
2099 rdlen = roundup(rdlen, ALIGNMENT);
2100
2101 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2102 /* Too long -- skip this frame */
2103 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2104 len, rdlen);
2105 bus->drvr->rx_errors++;
2106 bus->rx_toolong++;
2107 brcmf_sdbrcm_rxfail(bus, false, false);
2108 continue;
2109 }
2110
2111 pkt = brcmu_pkt_buf_get_skb(rdlen +
2112 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2113 if (!pkt) {
2114 /* Give up on data, request rtx of events */
2115 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2116 rdlen, chan);
2117 bus->drvr->rx_dropped++;
2118 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2119 continue;
2120 }
2121
2122 /* Leave room for what we already read, and align remainder */
2123 skb_pull(pkt, BRCMF_FIRSTREAD);
2124 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2125
2126 /* Read the remaining frame data */
2127 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2128 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2129 rdlen, pkt);
2130 bus->f2rxdata++;
2131
2132 if (sdret < 0) {
2133 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2134 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2135 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2136 : "test")), sdret);
2137 brcmu_pkt_buf_free_skb(pkt);
2138 bus->drvr->rx_errors++;
2139 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2140 continue;
2141 }
2142
2143 /* Copy the already-read portion */
2144 skb_push(pkt, BRCMF_FIRSTREAD);
2145 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2146
2147 #ifdef BCMDBG
2148 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2149 printk(KERN_DEBUG "Rx Data:\n");
2150 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2151 pkt->data, len);
2152 }
2153 #endif
2154
2155 deliver:
2156 /* Save superframe descriptor and allocate packet frame */
2157 if (chan == SDPCM_GLOM_CHANNEL) {
2158 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2159 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2160 len);
2161 #ifdef BCMDBG
2162 if (BRCMF_GLOM_ON()) {
2163 printk(KERN_DEBUG "Glom Data:\n");
2164 print_hex_dump_bytes("",
2165 DUMP_PREFIX_OFFSET,
2166 pkt->data, len);
2167 }
2168 #endif
2169 __skb_trim(pkt, len);
2170 skb_pull(pkt, SDPCM_HDRLEN);
2171 bus->glomd = pkt;
2172 } else {
2173 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2174 "descriptor!\n", __func__);
2175 brcmf_sdbrcm_rxfail(bus, false, false);
2176 }
2177 continue;
2178 }
2179
2180 /* Fill in packet len and prio, deliver upward */
2181 __skb_trim(pkt, len);
2182 skb_pull(pkt, doff);
2183
2184 if (pkt->len == 0) {
2185 brcmu_pkt_buf_free_skb(pkt);
2186 continue;
2187 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2188 brcmf_dbg(ERROR, "rx protocol error\n");
2189 brcmu_pkt_buf_free_skb(pkt);
2190 bus->drvr->rx_errors++;
2191 continue;
2192 }
2193
2194 /* Unlock during rx call */
2195 up(&bus->sdsem);
2196 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2197 down(&bus->sdsem);
2198 }
2199 rxcount = maxframes - rxleft;
2200 #ifdef BCMDBG
2201 /* Message if we hit the limit */
2202 if (!rxleft)
2203 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2204 maxframes);
2205 else
2206 #endif /* BCMDBG */
2207 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2208 /* Back off rxseq if awaiting rtx, update rx_seq */
2209 if (bus->rxskip)
2210 rxseq--;
2211 bus->rx_seq = rxseq;
2212
2213 return rxcount;
2214 }
2215
2216 static int
2217 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2218 u8 *buf, uint nbytes, struct sk_buff *pkt)
2219 {
2220 return brcmf_sdcard_send_buf
2221 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2222 }
2223
2224 static void
2225 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2226 {
2227 up(&bus->sdsem);
2228 wait_event_interruptible_timeout(bus->ctrl_wait,
2229 (*lockvar == false), HZ * 2);
2230 down(&bus->sdsem);
2231 return;
2232 }
2233
2234 static void
2235 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2236 {
2237 if (waitqueue_active(&bus->ctrl_wait))
2238 wake_up_interruptible(&bus->ctrl_wait);
2239 return;
2240 }
2241
2242 /* Writes a HW/SW header into the packet and sends it. */
2243 /* Assumes: (a) header space already there, (b) caller holds lock */
2244 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2245 uint chan, bool free_pkt)
2246 {
2247 int ret;
2248 u8 *frame;
2249 u16 len, pad = 0;
2250 u32 swheader;
2251 struct sk_buff *new;
2252 int i;
2253
2254 brcmf_dbg(TRACE, "Enter\n");
2255
2256 frame = (u8 *) (pkt->data);
2257
2258 /* Add alignment padding, allocate new packet if needed */
2259 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2260 if (pad) {
2261 if (skb_headroom(pkt) < pad) {
2262 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2263 skb_headroom(pkt), pad);
2264 bus->drvr->tx_realloc++;
2265 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2266 if (!new) {
2267 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2268 pkt->len + BRCMF_SDALIGN);
2269 ret = -ENOMEM;
2270 goto done;
2271 }
2272
2273 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2274 memcpy(new->data, pkt->data, pkt->len);
2275 if (free_pkt)
2276 brcmu_pkt_buf_free_skb(pkt);
2277 /* free the pkt if canned one is not used */
2278 free_pkt = true;
2279 pkt = new;
2280 frame = (u8 *) (pkt->data);
2281 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2282 pad = 0;
2283 } else {
2284 skb_push(pkt, pad);
2285 frame = (u8 *) (pkt->data);
2286 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2287 memset(frame, 0, pad + SDPCM_HDRLEN);
2288 }
2289 }
2290 /* precondition: pad < BRCMF_SDALIGN */
2291
2292 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2293 len = (u16) (pkt->len);
2294 *(__le16 *) frame = cpu_to_le16(len);
2295 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2296
2297 /* Software tag: channel, sequence number, data offset */
2298 swheader =
2299 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2300 (((pad +
2301 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2302
2303 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2304 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2305
2306 #ifdef BCMDBG
2307 tx_packets[pkt->priority]++;
2308 if (BRCMF_BYTES_ON() &&
2309 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2310 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2311 printk(KERN_DEBUG "Tx Frame:\n");
2312 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2313 } else if (BRCMF_HDRS_ON()) {
2314 printk(KERN_DEBUG "TxHdr:\n");
2315 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2316 frame, min_t(u16, len, 16));
2317 }
2318 #endif
2319
2320 /* Raise len to next SDIO block to eliminate tail command */
2321 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2322 u16 pad = bus->blocksize - (len % bus->blocksize);
2323 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2324 len += pad;
2325 } else if (len % BRCMF_SDALIGN) {
2326 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2327 }
2328
2329 /* Some controllers have trouble with odd bytes -- round to even */
2330 if (len & (ALIGNMENT - 1))
2331 len = roundup(len, ALIGNMENT);
2332
2333 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2334 SDIO_FUNC_2, F2SYNC, frame,
2335 len, pkt);
2336 bus->f2txdata++;
2337
2338 if (ret < 0) {
2339 /* On failure, abort the command and terminate the frame */
2340 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2341 ret);
2342 bus->tx_sderrs++;
2343
2344 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2345 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2346 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2347 NULL);
2348 bus->f1regdata++;
2349
2350 for (i = 0; i < 3; i++) {
2351 u8 hi, lo;
2352 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2353 SDIO_FUNC_1,
2354 SBSDIO_FUNC1_WFRAMEBCHI,
2355 NULL);
2356 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2357 SDIO_FUNC_1,
2358 SBSDIO_FUNC1_WFRAMEBCLO,
2359 NULL);
2360 bus->f1regdata += 2;
2361 if ((hi == 0) && (lo == 0))
2362 break;
2363 }
2364
2365 }
2366 if (ret == 0)
2367 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2368
2369 done:
2370 /* restore pkt buffer pointer before calling tx complete routine */
2371 skb_pull(pkt, SDPCM_HDRLEN + pad);
2372 up(&bus->sdsem);
2373 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2374 down(&bus->sdsem);
2375
2376 if (free_pkt)
2377 brcmu_pkt_buf_free_skb(pkt);
2378
2379 return ret;
2380 }
2381
2382 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2383 {
2384 struct sk_buff *pkt;
2385 u32 intstatus = 0;
2386 uint retries = 0;
2387 int ret = 0, prec_out;
2388 uint cnt = 0;
2389 uint datalen;
2390 u8 tx_prec_map;
2391
2392 struct brcmf_pub *drvr = bus->drvr;
2393
2394 brcmf_dbg(TRACE, "Enter\n");
2395
2396 tx_prec_map = ~bus->flowcontrol;
2397
2398 /* Send frames until the limit or some other event */
2399 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2400 spin_lock_bh(&bus->txqlock);
2401 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2402 if (pkt == NULL) {
2403 spin_unlock_bh(&bus->txqlock);
2404 break;
2405 }
2406 spin_unlock_bh(&bus->txqlock);
2407 datalen = pkt->len - SDPCM_HDRLEN;
2408
2409 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2410 if (ret)
2411 bus->drvr->tx_errors++;
2412 else
2413 bus->drvr->dstats.tx_bytes += datalen;
2414
2415 /* In poll mode, need to check for other events */
2416 if (!bus->intr && cnt) {
2417 /* Check device status, signal pending interrupt */
2418 r_sdreg32(bus, &intstatus,
2419 offsetof(struct sdpcmd_regs, intstatus),
2420 &retries);
2421 bus->f2txdata++;
2422 if (brcmf_sdcard_regfail(bus->sdiodev))
2423 break;
2424 if (intstatus & bus->hostintmask)
2425 bus->ipend = true;
2426 }
2427 }
2428
2429 /* Deflow-control stack if needed */
2430 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2431 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2432 brcmf_txflowcontrol(drvr, 0, OFF);
2433
2434 return cnt;
2435 }
2436
2437 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2438 {
2439 u32 intstatus, newstatus = 0;
2440 uint retries = 0;
2441 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2442 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2443 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2444 bool rxdone = true; /* Flag for no more read data */
2445 bool resched = false; /* Flag indicating resched wanted */
2446
2447 brcmf_dbg(TRACE, "Enter\n");
2448
2449 /* Start with leftover status bits */
2450 intstatus = bus->intstatus;
2451
2452 down(&bus->sdsem);
2453
2454 /* If waiting for HTAVAIL, check status */
2455 if (bus->clkstate == CLK_PENDING) {
2456 int err;
2457 u8 clkctl, devctl = 0;
2458
2459 #ifdef BCMDBG
2460 /* Check for inconsistent device control */
2461 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2462 SBSDIO_DEVICE_CTL, &err);
2463 if (err) {
2464 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2465 bus->drvr->busstate = BRCMF_BUS_DOWN;
2466 }
2467 #endif /* BCMDBG */
2468
2469 /* Read CSR, if clock on switch to AVAIL, else ignore */
2470 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2471 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2472 if (err) {
2473 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2474 err);
2475 bus->drvr->busstate = BRCMF_BUS_DOWN;
2476 }
2477
2478 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2479 devctl, clkctl);
2480
2481 if (SBSDIO_HTAV(clkctl)) {
2482 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2483 SDIO_FUNC_1,
2484 SBSDIO_DEVICE_CTL, &err);
2485 if (err) {
2486 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2487 err);
2488 bus->drvr->busstate = BRCMF_BUS_DOWN;
2489 }
2490 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2491 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2492 SBSDIO_DEVICE_CTL, devctl, &err);
2493 if (err) {
2494 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2495 err);
2496 bus->drvr->busstate = BRCMF_BUS_DOWN;
2497 }
2498 bus->clkstate = CLK_AVAIL;
2499 } else {
2500 goto clkwait;
2501 }
2502 }
2503
2504 bus_wake(bus);
2505
2506 /* Make sure backplane clock is on */
2507 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2508 if (bus->clkstate == CLK_PENDING)
2509 goto clkwait;
2510
2511 /* Pending interrupt indicates new device status */
2512 if (bus->ipend) {
2513 bus->ipend = false;
2514 r_sdreg32(bus, &newstatus,
2515 offsetof(struct sdpcmd_regs, intstatus), &retries);
2516 bus->f1regdata++;
2517 if (brcmf_sdcard_regfail(bus->sdiodev))
2518 newstatus = 0;
2519 newstatus &= bus->hostintmask;
2520 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2521 if (newstatus) {
2522 w_sdreg32(bus, newstatus,
2523 offsetof(struct sdpcmd_regs, intstatus),
2524 &retries);
2525 bus->f1regdata++;
2526 }
2527 }
2528
2529 /* Merge new bits with previous */
2530 intstatus |= newstatus;
2531 bus->intstatus = 0;
2532
2533 /* Handle flow-control change: read new state in case our ack
2534 * crossed another change interrupt. If change still set, assume
2535 * FC ON for safety, let next loop through do the debounce.
2536 */
2537 if (intstatus & I_HMB_FC_CHANGE) {
2538 intstatus &= ~I_HMB_FC_CHANGE;
2539 w_sdreg32(bus, I_HMB_FC_CHANGE,
2540 offsetof(struct sdpcmd_regs, intstatus), &retries);
2541
2542 r_sdreg32(bus, &newstatus,
2543 offsetof(struct sdpcmd_regs, intstatus), &retries);
2544 bus->f1regdata += 2;
2545 bus->fcstate =
2546 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2547 intstatus |= (newstatus & bus->hostintmask);
2548 }
2549
2550 /* Handle host mailbox indication */
2551 if (intstatus & I_HMB_HOST_INT) {
2552 intstatus &= ~I_HMB_HOST_INT;
2553 intstatus |= brcmf_sdbrcm_hostmail(bus);
2554 }
2555
2556 /* Generally don't ask for these, can get CRC errors... */
2557 if (intstatus & I_WR_OOSYNC) {
2558 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2559 intstatus &= ~I_WR_OOSYNC;
2560 }
2561
2562 if (intstatus & I_RD_OOSYNC) {
2563 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2564 intstatus &= ~I_RD_OOSYNC;
2565 }
2566
2567 if (intstatus & I_SBINT) {
2568 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2569 intstatus &= ~I_SBINT;
2570 }
2571
2572 /* Would be active due to wake-wlan in gSPI */
2573 if (intstatus & I_CHIPACTIVE) {
2574 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2575 intstatus &= ~I_CHIPACTIVE;
2576 }
2577
2578 /* Ignore frame indications if rxskip is set */
2579 if (bus->rxskip)
2580 intstatus &= ~I_HMB_FRAME_IND;
2581
2582 /* On frame indication, read available frames */
2583 if (PKT_AVAILABLE()) {
2584 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2585 if (rxdone || bus->rxskip)
2586 intstatus &= ~I_HMB_FRAME_IND;
2587 rxlimit -= min(framecnt, rxlimit);
2588 }
2589
2590 /* Keep still-pending events for next scheduling */
2591 bus->intstatus = intstatus;
2592
2593 clkwait:
2594 if (data_ok(bus) && bus->ctrl_frame_stat &&
2595 (bus->clkstate == CLK_AVAIL)) {
2596 int ret, i;
2597
2598 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2599 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2600 (u32) bus->ctrl_frame_len, NULL);
2601
2602 if (ret < 0) {
2603 /* On failure, abort the command and
2604 terminate the frame */
2605 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2606 ret);
2607 bus->tx_sderrs++;
2608
2609 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2610
2611 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2612 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2613 NULL);
2614 bus->f1regdata++;
2615
2616 for (i = 0; i < 3; i++) {
2617 u8 hi, lo;
2618 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2619 SDIO_FUNC_1,
2620 SBSDIO_FUNC1_WFRAMEBCHI,
2621 NULL);
2622 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2623 SDIO_FUNC_1,
2624 SBSDIO_FUNC1_WFRAMEBCLO,
2625 NULL);
2626 bus->f1regdata += 2;
2627 if ((hi == 0) && (lo == 0))
2628 break;
2629 }
2630
2631 }
2632 if (ret == 0)
2633 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2634
2635 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2636 bus->ctrl_frame_stat = false;
2637 brcmf_sdbrcm_wait_event_wakeup(bus);
2638 }
2639 /* Send queued frames (limit 1 if rx may still be pending) */
2640 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2641 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2642 && data_ok(bus)) {
2643 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2644 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2645 txlimit -= framecnt;
2646 }
2647
2648 /* Resched if events or tx frames are pending,
2649 else await next interrupt */
2650 /* On failed register access, all bets are off:
2651 no resched or interrupts */
2652 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2653 brcmf_sdcard_regfail(bus->sdiodev)) {
2654 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2655 brcmf_sdcard_regfail(bus->sdiodev));
2656 bus->drvr->busstate = BRCMF_BUS_DOWN;
2657 bus->intstatus = 0;
2658 } else if (bus->clkstate == CLK_PENDING) {
2659 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2660 resched = true;
2661 } else if (bus->intstatus || bus->ipend ||
2662 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2663 && data_ok(bus)) || PKT_AVAILABLE()) {
2664 resched = true;
2665 }
2666
2667 bus->dpc_sched = resched;
2668
2669 /* If we're done for now, turn off clock request. */
2670 if ((bus->clkstate != CLK_PENDING)
2671 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2672 bus->activity = false;
2673 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2674 }
2675
2676 up(&bus->sdsem);
2677
2678 return resched;
2679 }
2680
2681 static int brcmf_sdbrcm_dpc_thread(void *data)
2682 {
2683 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2684
2685 allow_signal(SIGTERM);
2686 /* Run until signal received */
2687 while (1) {
2688 if (kthread_should_stop())
2689 break;
2690 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2691 /* Call bus dpc unless it indicated down
2692 (then clean stop) */
2693 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2694 if (brcmf_sdbrcm_dpc(bus))
2695 complete(&bus->dpc_wait);
2696 } else {
2697 /* after stopping the bus, exit thread */
2698 brcmf_sdbrcm_bus_stop(bus);
2699 bus->dpc_tsk = NULL;
2700 break;
2701 }
2702 } else
2703 break;
2704 }
2705 return 0;
2706 }
2707
2708 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2709 {
2710 int ret = -EBADE;
2711 uint datalen, prec;
2712
2713 brcmf_dbg(TRACE, "Enter\n");
2714
2715 datalen = pkt->len;
2716
2717 /* Add space for the header */
2718 skb_push(pkt, SDPCM_HDRLEN);
2719 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2720
2721 prec = prio2prec((pkt->priority & PRIOMASK));
2722
2723 /* Check for existing queue, current flow-control,
2724 pending event, or pending clock */
2725 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2726 bus->fcqueued++;
2727
2728 /* Priority based enq */
2729 spin_lock_bh(&bus->txqlock);
2730 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2731 skb_pull(pkt, SDPCM_HDRLEN);
2732 brcmf_txcomplete(bus->drvr, pkt, false);
2733 brcmu_pkt_buf_free_skb(pkt);
2734 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2735 ret = -ENOSR;
2736 } else {
2737 ret = 0;
2738 }
2739 spin_unlock_bh(&bus->txqlock);
2740
2741 if (pktq_len(&bus->txq) >= TXHI)
2742 brcmf_txflowcontrol(bus->drvr, 0, ON);
2743
2744 #ifdef BCMDBG
2745 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2746 qcount[prec] = pktq_plen(&bus->txq, prec);
2747 #endif
2748 /* Schedule DPC if needed to send queued packet(s) */
2749 if (!bus->dpc_sched) {
2750 bus->dpc_sched = true;
2751 if (bus->dpc_tsk)
2752 complete(&bus->dpc_wait);
2753 }
2754
2755 return ret;
2756 }
2757
2758 static int
2759 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2760 uint size)
2761 {
2762 int bcmerror = 0;
2763 u32 sdaddr;
2764 uint dsize;
2765
2766 /* Determine initial transfer parameters */
2767 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2768 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2769 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2770 else
2771 dsize = size;
2772
2773 /* Set the backplane window to include the start address */
2774 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2775 if (bcmerror) {
2776 brcmf_dbg(ERROR, "window change failed\n");
2777 goto xfer_done;
2778 }
2779
2780 /* Do the transfer(s) */
2781 while (size) {
2782 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2783 write ? "write" : "read", dsize,
2784 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2785 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2786 sdaddr, data, dsize);
2787 if (bcmerror) {
2788 brcmf_dbg(ERROR, "membytes transfer failed\n");
2789 break;
2790 }
2791
2792 /* Adjust for next transfer (if any) */
2793 size -= dsize;
2794 if (size) {
2795 data += dsize;
2796 address += dsize;
2797 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2798 address);
2799 if (bcmerror) {
2800 brcmf_dbg(ERROR, "window change failed\n");
2801 break;
2802 }
2803 sdaddr = 0;
2804 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2805 }
2806 }
2807
2808 xfer_done:
2809 /* Return the window to backplane enumeration space for core access */
2810 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2811 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2812 bus->sdiodev->sbwad);
2813
2814 return bcmerror;
2815 }
2816
2817 #ifdef BCMDBG
2818 #define CONSOLE_LINE_MAX 192
2819
2820 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2821 {
2822 struct brcmf_console *c = &bus->console;
2823 u8 line[CONSOLE_LINE_MAX], ch;
2824 u32 n, idx, addr;
2825 int rv;
2826
2827 /* Don't do anything until FWREADY updates console address */
2828 if (bus->console_addr == 0)
2829 return 0;
2830
2831 /* Read console log struct */
2832 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2833 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2834 sizeof(c->log_le));
2835 if (rv < 0)
2836 return rv;
2837
2838 /* Allocate console buffer (one time only) */
2839 if (c->buf == NULL) {
2840 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2841 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2842 if (c->buf == NULL)
2843 return -ENOMEM;
2844 }
2845
2846 idx = le32_to_cpu(c->log_le.idx);
2847
2848 /* Protect against corrupt value */
2849 if (idx > c->bufsize)
2850 return -EBADE;
2851
2852 /* Skip reading the console buffer if the index pointer
2853 has not moved */
2854 if (idx == c->last)
2855 return 0;
2856
2857 /* Read the console buffer */
2858 addr = le32_to_cpu(c->log_le.buf);
2859 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2860 if (rv < 0)
2861 return rv;
2862
2863 while (c->last != idx) {
2864 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2865 if (c->last == idx) {
2866 /* This would output a partial line.
2867 * Instead, back up
2868 * the buffer pointer and output this
2869 * line next time around.
2870 */
2871 if (c->last >= n)
2872 c->last -= n;
2873 else
2874 c->last = c->bufsize - n;
2875 goto break2;
2876 }
2877 ch = c->buf[c->last];
2878 c->last = (c->last + 1) % c->bufsize;
2879 if (ch == '\n')
2880 break;
2881 line[n] = ch;
2882 }
2883
2884 if (n > 0) {
2885 if (line[n - 1] == '\r')
2886 n--;
2887 line[n] = 0;
2888 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2889 }
2890 }
2891 break2:
2892
2893 return 0;
2894 }
2895 #endif /* BCMDBG */
2896
2897 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2898 {
2899 int i;
2900 int ret;
2901
2902 bus->ctrl_frame_stat = false;
2903 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2904 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2905
2906 if (ret < 0) {
2907 /* On failure, abort the command and terminate the frame */
2908 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2909 ret);
2910 bus->tx_sderrs++;
2911
2912 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2913
2914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2915 SBSDIO_FUNC1_FRAMECTRL,
2916 SFC_WF_TERM, NULL);
2917 bus->f1regdata++;
2918
2919 for (i = 0; i < 3; i++) {
2920 u8 hi, lo;
2921 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2922 SBSDIO_FUNC1_WFRAMEBCHI,
2923 NULL);
2924 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2925 SBSDIO_FUNC1_WFRAMEBCLO,
2926 NULL);
2927 bus->f1regdata += 2;
2928 if (hi == 0 && lo == 0)
2929 break;
2930 }
2931 return ret;
2932 }
2933
2934 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2935
2936 return ret;
2937 }
2938
2939 int
2940 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2941 {
2942 u8 *frame;
2943 u16 len;
2944 u32 swheader;
2945 uint retries = 0;
2946 u8 doff = 0;
2947 int ret = -1;
2948
2949 brcmf_dbg(TRACE, "Enter\n");
2950
2951 /* Back the pointer to make a room for bus header */
2952 frame = msg - SDPCM_HDRLEN;
2953 len = (msglen += SDPCM_HDRLEN);
2954
2955 /* Add alignment padding (optional for ctl frames) */
2956 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2957 if (doff) {
2958 frame -= doff;
2959 len += doff;
2960 msglen += doff;
2961 memset(frame, 0, doff + SDPCM_HDRLEN);
2962 }
2963 /* precondition: doff < BRCMF_SDALIGN */
2964 doff += SDPCM_HDRLEN;
2965
2966 /* Round send length to next SDIO block */
2967 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2968 u16 pad = bus->blocksize - (len % bus->blocksize);
2969 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2970 len += pad;
2971 } else if (len % BRCMF_SDALIGN) {
2972 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2973 }
2974
2975 /* Satisfy length-alignment requirements */
2976 if (len & (ALIGNMENT - 1))
2977 len = roundup(len, ALIGNMENT);
2978
2979 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2980
2981 /* Need to lock here to protect txseq and SDIO tx calls */
2982 down(&bus->sdsem);
2983
2984 bus_wake(bus);
2985
2986 /* Make sure backplane clock is on */
2987 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2988
2989 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2990 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2991 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2992
2993 /* Software tag: channel, sequence number, data offset */
2994 swheader =
2995 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2996 SDPCM_CHANNEL_MASK)
2997 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2998 SDPCM_DOFFSET_MASK);
2999 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3000 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3001
3002 if (!data_ok(bus)) {
3003 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3004 bus->tx_max, bus->tx_seq);
3005 bus->ctrl_frame_stat = true;
3006 /* Send from dpc */
3007 bus->ctrl_frame_buf = frame;
3008 bus->ctrl_frame_len = len;
3009
3010 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3011
3012 if (bus->ctrl_frame_stat == false) {
3013 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3014 ret = 0;
3015 } else {
3016 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3017 ret = -1;
3018 }
3019 }
3020
3021 if (ret == -1) {
3022 #ifdef BCMDBG
3023 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3024 printk(KERN_DEBUG "Tx Frame:\n");
3025 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3026 frame, len);
3027 } else if (BRCMF_HDRS_ON()) {
3028 printk(KERN_DEBUG "TxHdr:\n");
3029 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3030 frame, min_t(u16, len, 16));
3031 }
3032 #endif
3033
3034 do {
3035 ret = brcmf_tx_frame(bus, frame, len);
3036 } while (ret < 0 && retries++ < TXRETRIES);
3037 }
3038
3039 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3040 bus->activity = false;
3041 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3042 }
3043
3044 up(&bus->sdsem);
3045
3046 if (ret)
3047 bus->drvr->tx_ctlerrs++;
3048 else
3049 bus->drvr->tx_ctlpkts++;
3050
3051 return ret ? -EIO : 0;
3052 }
3053
3054 int
3055 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3056 {
3057 int timeleft;
3058 uint rxlen = 0;
3059 bool pending;
3060
3061 brcmf_dbg(TRACE, "Enter\n");
3062
3063 /* Wait until control frame is available */
3064 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3065
3066 down(&bus->sdsem);
3067 rxlen = bus->rxlen;
3068 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3069 bus->rxlen = 0;
3070 up(&bus->sdsem);
3071
3072 if (rxlen) {
3073 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3074 rxlen, msglen);
3075 } else if (timeleft == 0) {
3076 brcmf_dbg(ERROR, "resumed on timeout\n");
3077 } else if (pending == true) {
3078 brcmf_dbg(CTL, "cancelled\n");
3079 return -ERESTARTSYS;
3080 } else {
3081 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3082 }
3083
3084 if (rxlen)
3085 bus->drvr->rx_ctlpkts++;
3086 else
3087 bus->drvr->rx_ctlerrs++;
3088
3089 return rxlen ? (int)rxlen : -ETIMEDOUT;
3090 }
3091
3092 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3093 {
3094 int bcmerror = 0;
3095
3096 brcmf_dbg(TRACE, "Enter\n");
3097
3098 /* Basic sanity checks */
3099 if (bus->drvr->up) {
3100 bcmerror = -EISCONN;
3101 goto err;
3102 }
3103 if (!len) {
3104 bcmerror = -EOVERFLOW;
3105 goto err;
3106 }
3107
3108 /* Free the old ones and replace with passed variables */
3109 kfree(bus->vars);
3110
3111 bus->vars = kmalloc(len, GFP_ATOMIC);
3112 bus->varsz = bus->vars ? len : 0;
3113 if (bus->vars == NULL) {
3114 bcmerror = -ENOMEM;
3115 goto err;
3116 }
3117
3118 /* Copy the passed variables, which should include the
3119 terminating double-null */
3120 memcpy(bus->vars, arg, bus->varsz);
3121 err:
3122 return bcmerror;
3123 }
3124
3125 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3126 {
3127 int bcmerror = 0;
3128 u32 varsize;
3129 u32 varaddr;
3130 u8 *vbuffer;
3131 u32 varsizew;
3132 __le32 varsizew_le;
3133 #ifdef BCMDBG
3134 char *nvram_ularray;
3135 #endif /* BCMDBG */
3136
3137 /* Even if there are no vars are to be written, we still
3138 need to set the ramsize. */
3139 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3140 varaddr = (bus->ramsize - 4) - varsize;
3141
3142 if (bus->vars) {
3143 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3144 if (!vbuffer)
3145 return -ENOMEM;
3146
3147 memcpy(vbuffer, bus->vars, bus->varsz);
3148
3149 /* Write the vars list */
3150 bcmerror =
3151 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3152 #ifdef BCMDBG
3153 /* Verify NVRAM bytes */
3154 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3155 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3156 if (!nvram_ularray)
3157 return -ENOMEM;
3158
3159 /* Upload image to verify downloaded contents. */
3160 memset(nvram_ularray, 0xaa, varsize);
3161
3162 /* Read the vars list to temp buffer for comparison */
3163 bcmerror =
3164 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3165 varsize);
3166 if (bcmerror) {
3167 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3168 bcmerror, varsize, varaddr);
3169 }
3170 /* Compare the org NVRAM with the one read from RAM */
3171 if (memcmp(vbuffer, nvram_ularray, varsize))
3172 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3173 else
3174 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3175
3176 kfree(nvram_ularray);
3177 #endif /* BCMDBG */
3178
3179 kfree(vbuffer);
3180 }
3181
3182 /* adjust to the user specified RAM */
3183 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3184 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3185 varaddr, varsize);
3186 varsize = ((bus->ramsize - 4) - varaddr);
3187
3188 /*
3189 * Determine the length token:
3190 * Varsize, converted to words, in lower 16-bits, checksum
3191 * in upper 16-bits.
3192 */
3193 if (bcmerror) {
3194 varsizew = 0;
3195 varsizew_le = cpu_to_le32(0);
3196 } else {
3197 varsizew = varsize / 4;
3198 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3199 varsizew_le = cpu_to_le32(varsizew);
3200 }
3201
3202 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3203 varsize, varsizew);
3204
3205 /* Write the length token to the last word */
3206 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3207 (u8 *)&varsizew_le, 4);
3208
3209 return bcmerror;
3210 }
3211
3212 static void
3213 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3214 {
3215 u32 regdata;
3216
3217 regdata = brcmf_sdcard_reg_read(sdiodev,
3218 CORE_SB(corebase, sbtmstatelow), 4);
3219 if (regdata & SBTML_RESET)
3220 return;
3221
3222 regdata = brcmf_sdcard_reg_read(sdiodev,
3223 CORE_SB(corebase, sbtmstatelow), 4);
3224 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3225 /*
3226 * set target reject and spin until busy is clear
3227 * (preserve core-specific bits)
3228 */
3229 regdata = brcmf_sdcard_reg_read(sdiodev,
3230 CORE_SB(corebase, sbtmstatelow), 4);
3231 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3232 4, regdata | SBTML_REJ);
3233
3234 regdata = brcmf_sdcard_reg_read(sdiodev,
3235 CORE_SB(corebase, sbtmstatelow), 4);
3236 udelay(1);
3237 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3238 CORE_SB(corebase, sbtmstatehigh), 4) &
3239 SBTMH_BUSY), 100000);
3240
3241 regdata = brcmf_sdcard_reg_read(sdiodev,
3242 CORE_SB(corebase, sbtmstatehigh), 4);
3243 if (regdata & SBTMH_BUSY)
3244 brcmf_dbg(ERROR, "ARM core still busy\n");
3245
3246 regdata = brcmf_sdcard_reg_read(sdiodev,
3247 CORE_SB(corebase, sbidlow), 4);
3248 if (regdata & SBIDL_INIT) {
3249 regdata = brcmf_sdcard_reg_read(sdiodev,
3250 CORE_SB(corebase, sbimstate), 4) |
3251 SBIM_RJ;
3252 brcmf_sdcard_reg_write(sdiodev,
3253 CORE_SB(corebase, sbimstate), 4,
3254 regdata);
3255 regdata = brcmf_sdcard_reg_read(sdiodev,
3256 CORE_SB(corebase, sbimstate), 4);
3257 udelay(1);
3258 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3259 CORE_SB(corebase, sbimstate), 4) &
3260 SBIM_BY), 100000);
3261 }
3262
3263 /* set reset and reject while enabling the clocks */
3264 brcmf_sdcard_reg_write(sdiodev,
3265 CORE_SB(corebase, sbtmstatelow), 4,
3266 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3267 SBTML_REJ | SBTML_RESET));
3268 regdata = brcmf_sdcard_reg_read(sdiodev,
3269 CORE_SB(corebase, sbtmstatelow), 4);
3270 udelay(10);
3271
3272 /* clear the initiator reject bit */
3273 regdata = brcmf_sdcard_reg_read(sdiodev,
3274 CORE_SB(corebase, sbidlow), 4);
3275 if (regdata & SBIDL_INIT) {
3276 regdata = brcmf_sdcard_reg_read(sdiodev,
3277 CORE_SB(corebase, sbimstate), 4) &
3278 ~SBIM_RJ;
3279 brcmf_sdcard_reg_write(sdiodev,
3280 CORE_SB(corebase, sbimstate), 4,
3281 regdata);
3282 }
3283 }
3284
3285 /* leave reset and reject asserted */
3286 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3287 (SBTML_REJ | SBTML_RESET));
3288 udelay(1);
3289 }
3290
3291 static void
3292 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3293 {
3294 u32 regdata;
3295
3296 /*
3297 * Must do the disable sequence first to work for
3298 * arbitrary current core state.
3299 */
3300 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3301
3302 /*
3303 * Now do the initialization sequence.
3304 * set reset while enabling the clock and
3305 * forcing them on throughout the core
3306 */
3307 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3308 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3309 SBTML_RESET);
3310 udelay(1);
3311
3312 regdata = brcmf_sdcard_reg_read(sdiodev,
3313 CORE_SB(corebase, sbtmstatehigh), 4);
3314 if (regdata & SBTMH_SERR)
3315 brcmf_sdcard_reg_write(sdiodev,
3316 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3317
3318 regdata = brcmf_sdcard_reg_read(sdiodev,
3319 CORE_SB(corebase, sbimstate), 4);
3320 if (regdata & (SBIM_IBE | SBIM_TO))
3321 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3322 regdata & ~(SBIM_IBE | SBIM_TO));
3323
3324 /* clear reset and allow it to propagate throughout the core */
3325 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3326 (SICF_FGC << SBTML_SICF_SHIFT) |
3327 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3328 udelay(1);
3329
3330 /* leave clock enabled */
3331 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3332 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3333 udelay(1);
3334 }
3335
3336 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3337 {
3338 uint retries;
3339 u32 regdata;
3340 int bcmerror = 0;
3341
3342 /* To enter download state, disable ARM and reset SOCRAM.
3343 * To exit download state, simply reset ARM (default is RAM boot).
3344 */
3345 if (enter) {
3346 bus->alp_only = true;
3347
3348 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3349 bus->ci->armcorebase);
3350
3351 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3352
3353 /* Clear the top bit of memory */
3354 if (bus->ramsize) {
3355 u32 zeros = 0;
3356 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3357 (u8 *)&zeros, 4);
3358 }
3359 } else {
3360 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3361 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3362 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3363 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3364 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3365 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3366 bcmerror = -EBADE;
3367 goto fail;
3368 }
3369
3370 bcmerror = brcmf_sdbrcm_write_vars(bus);
3371 if (bcmerror) {
3372 brcmf_dbg(ERROR, "no vars written to RAM\n");
3373 bcmerror = 0;
3374 }
3375
3376 w_sdreg32(bus, 0xFFFFFFFF,
3377 offsetof(struct sdpcmd_regs, intstatus), &retries);
3378
3379 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3380
3381 /* Allow HT Clock now that the ARM is running. */
3382 bus->alp_only = false;
3383
3384 bus->drvr->busstate = BRCMF_BUS_LOAD;
3385 }
3386 fail:
3387 return bcmerror;
3388 }
3389
3390 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3391 {
3392 if (bus->firmware->size < bus->fw_ptr + len)
3393 len = bus->firmware->size - bus->fw_ptr;
3394
3395 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3396 bus->fw_ptr += len;
3397 return len;
3398 }
3399
3400 MODULE_FIRMWARE(BCM4329_FW_NAME);
3401 MODULE_FIRMWARE(BCM4329_NV_NAME);
3402
3403 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3404 {
3405 int offset = 0;
3406 uint len;
3407 u8 *memblock = NULL, *memptr;
3408 int ret;
3409
3410 brcmf_dbg(INFO, "Enter\n");
3411
3412 bus->fw_name = BCM4329_FW_NAME;
3413 ret = request_firmware(&bus->firmware, bus->fw_name,
3414 &bus->sdiodev->func[2]->dev);
3415 if (ret) {
3416 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3417 return ret;
3418 }
3419 bus->fw_ptr = 0;
3420
3421 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3422 if (memblock == NULL) {
3423 ret = -ENOMEM;
3424 goto err;
3425 }
3426 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3427 memptr += (BRCMF_SDALIGN -
3428 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3429
3430 /* Download image */
3431 while ((len =
3432 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3433 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3434 if (ret) {
3435 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3436 ret, MEMBLOCK, offset);
3437 goto err;
3438 }
3439
3440 offset += MEMBLOCK;
3441 }
3442
3443 err:
3444 kfree(memblock);
3445
3446 release_firmware(bus->firmware);
3447 bus->fw_ptr = 0;
3448
3449 return ret;
3450 }
3451
3452 /*
3453 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3454 * and ending in a NUL.
3455 * Removes carriage returns, empty lines, comment lines, and converts
3456 * newlines to NULs.
3457 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3458 * by two NULs.
3459 */
3460
3461 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3462 {
3463 char *dp;
3464 bool findNewline;
3465 int column;
3466 uint buf_len, n;
3467
3468 dp = varbuf;
3469
3470 findNewline = false;
3471 column = 0;
3472
3473 for (n = 0; n < len; n++) {
3474 if (varbuf[n] == 0)
3475 break;
3476 if (varbuf[n] == '\r')
3477 continue;
3478 if (findNewline && varbuf[n] != '\n')
3479 continue;
3480 findNewline = false;
3481 if (varbuf[n] == '#') {
3482 findNewline = true;
3483 continue;
3484 }
3485 if (varbuf[n] == '\n') {
3486 if (column == 0)
3487 continue;
3488 *dp++ = 0;
3489 column = 0;
3490 continue;
3491 }
3492 *dp++ = varbuf[n];
3493 column++;
3494 }
3495 buf_len = dp - varbuf;
3496
3497 while (dp < varbuf + n)
3498 *dp++ = 0;
3499
3500 return buf_len;
3501 }
3502
3503 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3504 {
3505 uint len;
3506 char *memblock = NULL;
3507 char *bufp;
3508 int ret;
3509
3510 bus->nv_name = BCM4329_NV_NAME;
3511 ret = request_firmware(&bus->firmware, bus->nv_name,
3512 &bus->sdiodev->func[2]->dev);
3513 if (ret) {
3514 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3515 return ret;
3516 }
3517 bus->fw_ptr = 0;
3518
3519 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3520 if (memblock == NULL) {
3521 ret = -ENOMEM;
3522 goto err;
3523 }
3524
3525 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3526
3527 if (len > 0 && len < MEMBLOCK) {
3528 bufp = (char *)memblock;
3529 bufp[len] = 0;
3530 len = brcmf_process_nvram_vars(bufp, len);
3531 bufp += len;
3532 *bufp++ = 0;
3533 if (len)
3534 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3535 if (ret)
3536 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3537 } else {
3538 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3539 ret = -EIO;
3540 }
3541
3542 err:
3543 kfree(memblock);
3544
3545 release_firmware(bus->firmware);
3546 bus->fw_ptr = 0;
3547
3548 return ret;
3549 }
3550
3551 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3552 {
3553 int bcmerror = -1;
3554
3555 /* Keep arm in reset */
3556 if (brcmf_sdbrcm_download_state(bus, true)) {
3557 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3558 goto err;
3559 }
3560
3561 /* External image takes precedence if specified */
3562 if (brcmf_sdbrcm_download_code_file(bus)) {
3563 brcmf_dbg(ERROR, "dongle image file download failed\n");
3564 goto err;
3565 }
3566
3567 /* External nvram takes precedence if specified */
3568 if (brcmf_sdbrcm_download_nvram(bus))
3569 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3570
3571 /* Take arm out of reset */
3572 if (brcmf_sdbrcm_download_state(bus, false)) {
3573 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3574 goto err;
3575 }
3576
3577 bcmerror = 0;
3578
3579 err:
3580 return bcmerror;
3581 }
3582
3583 static bool
3584 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3585 {
3586 bool ret;
3587
3588 /* Download the firmware */
3589 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3590
3591 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3592
3593 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3594
3595 return ret;
3596 }
3597
3598 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3599 {
3600 u32 local_hostintmask;
3601 u8 saveclk;
3602 uint retries;
3603 int err;
3604
3605 brcmf_dbg(TRACE, "Enter\n");
3606
3607 if (bus->watchdog_tsk) {
3608 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3609 kthread_stop(bus->watchdog_tsk);
3610 bus->watchdog_tsk = NULL;
3611 }
3612
3613 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3614 send_sig(SIGTERM, bus->dpc_tsk, 1);
3615 kthread_stop(bus->dpc_tsk);
3616 bus->dpc_tsk = NULL;
3617 }
3618
3619 down(&bus->sdsem);
3620
3621 bus_wake(bus);
3622
3623 /* Enable clock for device interrupts */
3624 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3625
3626 /* Disable and clear interrupts at the chip level also */
3627 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3628 local_hostintmask = bus->hostintmask;
3629 bus->hostintmask = 0;
3630
3631 /* Change our idea of bus state */
3632 bus->drvr->busstate = BRCMF_BUS_DOWN;
3633
3634 /* Force clocks on backplane to be sure F2 interrupt propagates */
3635 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3636 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3637 if (!err) {
3638 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3639 SBSDIO_FUNC1_CHIPCLKCSR,
3640 (saveclk | SBSDIO_FORCE_HT), &err);
3641 }
3642 if (err)
3643 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3644
3645 /* Turn off the bus (F2), free any pending packets */
3646 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3647 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3648 SDIO_FUNC_ENABLE_1, NULL);
3649
3650 /* Clear any pending interrupts now that F2 is disabled */
3651 w_sdreg32(bus, local_hostintmask,
3652 offsetof(struct sdpcmd_regs, intstatus), &retries);
3653
3654 /* Turn off the backplane clock (only) */
3655 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3656
3657 /* Clear the data packet queues */
3658 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3659
3660 /* Clear any held glomming stuff */
3661 if (bus->glomd)
3662 brcmu_pkt_buf_free_skb(bus->glomd);
3663
3664 if (bus->glom)
3665 brcmu_pkt_buf_free_skb(bus->glom);
3666
3667 bus->glom = bus->glomd = NULL;
3668
3669 /* Clear rx control and wake any waiters */
3670 bus->rxlen = 0;
3671 brcmf_sdbrcm_dcmd_resp_wake(bus);
3672
3673 /* Reset some F2 state stuff */
3674 bus->rxskip = false;
3675 bus->tx_seq = bus->rx_seq = 0;
3676
3677 up(&bus->sdsem);
3678 }
3679
3680 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3681 {
3682 struct brcmf_bus *bus = drvr->bus;
3683 unsigned long timeout;
3684 uint retries = 0;
3685 u8 ready, enable;
3686 int err, ret = 0;
3687 u8 saveclk;
3688
3689 brcmf_dbg(TRACE, "Enter\n");
3690
3691 /* try to download image and nvram to the dongle */
3692 if (drvr->busstate == BRCMF_BUS_DOWN) {
3693 if (!(brcmf_sdbrcm_download_firmware(bus)))
3694 return -1;
3695 }
3696
3697 if (!bus->drvr)
3698 return 0;
3699
3700 /* Start the watchdog timer */
3701 bus->drvr->tickcnt = 0;
3702 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3703
3704 down(&bus->sdsem);
3705
3706 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3707 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3708 if (bus->clkstate != CLK_AVAIL)
3709 goto exit;
3710
3711 /* Force clocks on backplane to be sure F2 interrupt propagates */
3712 saveclk =
3713 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3714 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3715 if (!err) {
3716 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3717 SBSDIO_FUNC1_CHIPCLKCSR,
3718 (saveclk | SBSDIO_FORCE_HT), &err);
3719 }
3720 if (err) {
3721 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3722 goto exit;
3723 }
3724
3725 /* Enable function 2 (frame transfers) */
3726 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3727 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3728 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3729
3730 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3731 enable, NULL);
3732
3733 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3734 ready = 0;
3735 while (enable != ready) {
3736 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3737 SDIO_CCCR_IORx, NULL);
3738 if (time_after(jiffies, timeout))
3739 break;
3740 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3741 /* prevent busy waiting if it takes too long */
3742 msleep_interruptible(20);
3743 }
3744
3745 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3746
3747 /* If F2 successfully enabled, set core and enable interrupts */
3748 if (ready == enable) {
3749 /* Set up the interrupt mask and enable interrupts */
3750 bus->hostintmask = HOSTINTMASK;
3751 w_sdreg32(bus, bus->hostintmask,
3752 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3753
3754 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3755 SBSDIO_WATERMARK, 8, &err);
3756
3757 /* Set bus state according to enable result */
3758 drvr->busstate = BRCMF_BUS_DATA;
3759 }
3760
3761 else {
3762 /* Disable F2 again */
3763 enable = SDIO_FUNC_ENABLE_1;
3764 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3765 SDIO_CCCR_IOEx, enable, NULL);
3766 }
3767
3768 /* Restore previous clock setting */
3769 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3770 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3771
3772 /* If we didn't come up, turn off backplane clock */
3773 if (drvr->busstate != BRCMF_BUS_DATA)
3774 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3775
3776 exit:
3777 up(&bus->sdsem);
3778
3779 return ret;
3780 }
3781
3782 void brcmf_sdbrcm_isr(void *arg)
3783 {
3784 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3785
3786 brcmf_dbg(TRACE, "Enter\n");
3787
3788 if (!bus) {
3789 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3790 return;
3791 }
3792
3793 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3794 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3795 return;
3796 }
3797 /* Count the interrupt call */
3798 bus->intrcount++;
3799 bus->ipend = true;
3800
3801 /* Shouldn't get this interrupt if we're sleeping? */
3802 if (bus->sleeping) {
3803 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3804 return;
3805 }
3806
3807 /* Disable additional interrupts (is this needed now)? */
3808 if (!bus->intr)
3809 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3810
3811 bus->dpc_sched = true;
3812 if (bus->dpc_tsk)
3813 complete(&bus->dpc_wait);
3814 }
3815
3816 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3817 {
3818 struct brcmf_bus *bus;
3819
3820 brcmf_dbg(TIMER, "Enter\n");
3821
3822 bus = drvr->bus;
3823
3824 /* Ignore the timer if simulating bus down */
3825 if (bus->sleeping)
3826 return false;
3827
3828 down(&bus->sdsem);
3829
3830 /* Poll period: check device if appropriate. */
3831 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3832 u32 intstatus = 0;
3833
3834 /* Reset poll tick */
3835 bus->polltick = 0;
3836
3837 /* Check device if no interrupts */
3838 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3839
3840 if (!bus->dpc_sched) {
3841 u8 devpend;
3842 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3843 SDIO_FUNC_0, SDIO_CCCR_INTx,
3844 NULL);
3845 intstatus =
3846 devpend & (INTR_STATUS_FUNC1 |
3847 INTR_STATUS_FUNC2);
3848 }
3849
3850 /* If there is something, make like the ISR and
3851 schedule the DPC */
3852 if (intstatus) {
3853 bus->pollcnt++;
3854 bus->ipend = true;
3855
3856 bus->dpc_sched = true;
3857 if (bus->dpc_tsk)
3858 complete(&bus->dpc_wait);
3859 }
3860 }
3861
3862 /* Update interrupt tracking */
3863 bus->lastintrs = bus->intrcount;
3864 }
3865 #ifdef BCMDBG
3866 /* Poll for console output periodically */
3867 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3868 bus->console.count += BRCMF_WD_POLL_MS;
3869 if (bus->console.count >= bus->console_interval) {
3870 bus->console.count -= bus->console_interval;
3871 /* Make sure backplane clock is on */
3872 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3873 if (brcmf_sdbrcm_readconsole(bus) < 0)
3874 /* stop on error */
3875 bus->console_interval = 0;
3876 }
3877 }
3878 #endif /* BCMDBG */
3879
3880 /* On idle timeout clear activity flag and/or turn off clock */
3881 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3882 if (++bus->idlecount >= bus->idletime) {
3883 bus->idlecount = 0;
3884 if (bus->activity) {
3885 bus->activity = false;
3886 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3887 } else {
3888 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3889 }
3890 }
3891 }
3892
3893 up(&bus->sdsem);
3894
3895 return bus->ipend;
3896 }
3897
3898 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3899 {
3900 if (chipid == BCM4329_CHIP_ID)
3901 return true;
3902 return false;
3903 }
3904
3905 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3906 {
3907 brcmf_dbg(TRACE, "Enter\n");
3908
3909 kfree(bus->rxbuf);
3910 bus->rxctl = bus->rxbuf = NULL;
3911 bus->rxlen = 0;
3912
3913 kfree(bus->databuf);
3914 bus->databuf = NULL;
3915 }
3916
3917 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3918 {
3919 brcmf_dbg(TRACE, "Enter\n");
3920
3921 if (bus->drvr->maxctl) {
3922 bus->rxblen =
3923 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3924 ALIGNMENT) + BRCMF_SDALIGN;
3925 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3926 if (!(bus->rxbuf))
3927 goto fail;
3928 }
3929
3930 /* Allocate buffer to receive glomed packet */
3931 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3932 if (!(bus->databuf)) {
3933 /* release rxbuf which was already located as above */
3934 if (!bus->rxblen)
3935 kfree(bus->rxbuf);
3936 goto fail;
3937 }
3938
3939 /* Align the buffer */
3940 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3941 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3942 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3943 else
3944 bus->dataptr = bus->databuf;
3945
3946 return true;
3947
3948 fail:
3949 return false;
3950 }
3951
3952 /* SDIO Pad drive strength to select value mappings */
3953 struct sdiod_drive_str {
3954 u8 strength; /* Pad Drive Strength in mA */
3955 u8 sel; /* Chip-specific select value */
3956 };
3957
3958 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3959 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3960 {
3961 4, 0x2}, {
3962 2, 0x3}, {
3963 1, 0x0}, {
3964 0, 0x0}
3965 };
3966
3967 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3968 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3969 {
3970 12, 0x7}, {
3971 10, 0x6}, {
3972 8, 0x5}, {
3973 6, 0x4}, {
3974 4, 0x2}, {
3975 2, 0x1}, {
3976 0, 0x0}
3977 };
3978
3979 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3980 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3981 {
3982 32, 0x7}, {
3983 26, 0x6}, {
3984 22, 0x5}, {
3985 16, 0x4}, {
3986 12, 0x3}, {
3987 8, 0x2}, {
3988 4, 0x1}, {
3989 0, 0x0}
3990 };
3991
3992 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3993
3994 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
3995 u32 drivestrength) {
3996 struct sdiod_drive_str *str_tab = NULL;
3997 u32 str_mask = 0;
3998 u32 str_shift = 0;
3999 char chn[8];
4000
4001 if (!(bus->ci->cccaps & CC_CAP_PMU))
4002 return;
4003
4004 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4005 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4006 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4007 str_mask = 0x30000000;
4008 str_shift = 28;
4009 break;
4010 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4011 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4012 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4013 str_mask = 0x00003800;
4014 str_shift = 11;
4015 break;
4016 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4017 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4018 str_mask = 0x00003800;
4019 str_shift = 11;
4020 break;
4021 default:
4022 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4023 brcmu_chipname(bus->ci->chip, chn, 8),
4024 bus->ci->chiprev, bus->ci->pmurev);
4025 break;
4026 }
4027
4028 if (str_tab != NULL) {
4029 u32 drivestrength_sel = 0;
4030 u32 cc_data_temp;
4031 int i;
4032
4033 for (i = 0; str_tab[i].strength != 0; i++) {
4034 if (drivestrength >= str_tab[i].strength) {
4035 drivestrength_sel = str_tab[i].sel;
4036 break;
4037 }
4038 }
4039
4040 brcmf_sdcard_reg_write(bus->sdiodev,
4041 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4042 4, 1);
4043 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4044 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4045 cc_data_temp &= ~str_mask;
4046 drivestrength_sel <<= str_shift;
4047 cc_data_temp |= drivestrength_sel;
4048 brcmf_sdcard_reg_write(bus->sdiodev,
4049 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4050 4, cc_data_temp);
4051
4052 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4053 drivestrength, cc_data_temp);
4054 }
4055 }
4056
4057 static int
4058 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4059 struct chip_info *ci, u32 regs)
4060 {
4061 u32 regdata;
4062
4063 /*
4064 * Get CC core rev
4065 * Chipid is assume to be at offset 0 from regs arg
4066 * For different chiptypes or old sdio hosts w/o chipcommon,
4067 * other ways of recognition should be added here.
4068 */
4069 ci->cccorebase = regs;
4070 regdata = brcmf_sdcard_reg_read(sdiodev,
4071 CORE_CC_REG(ci->cccorebase, chipid), 4);
4072 ci->chip = regdata & CID_ID_MASK;
4073 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4074
4075 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4076
4077 /* Address of cores for new chips should be added here */
4078 switch (ci->chip) {
4079 case BCM4329_CHIP_ID:
4080 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4081 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4082 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4083 ci->ramsize = BCM4329_RAMSIZE;
4084 break;
4085 default:
4086 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4087 return -ENODEV;
4088 }
4089
4090 regdata = brcmf_sdcard_reg_read(sdiodev,
4091 CORE_SB(ci->cccorebase, sbidhigh), 4);
4092 ci->ccrev = SBCOREREV(regdata);
4093
4094 regdata = brcmf_sdcard_reg_read(sdiodev,
4095 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4096 ci->pmurev = regdata & PCAP_REV_MASK;
4097
4098 regdata = brcmf_sdcard_reg_read(sdiodev,
4099 CORE_SB(ci->buscorebase, sbidhigh), 4);
4100 ci->buscorerev = SBCOREREV(regdata);
4101 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4102
4103 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4104 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4105
4106 /* get chipcommon capabilites */
4107 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4108 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4109
4110 return 0;
4111 }
4112
4113 static int
4114 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4115 {
4116 struct chip_info *ci;
4117 int err;
4118 u8 clkval, clkset;
4119
4120 brcmf_dbg(TRACE, "Enter\n");
4121
4122 /* alloc chip_info_t */
4123 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4124 if (NULL == ci)
4125 return -ENOMEM;
4126
4127 /* bus/core/clk setup for register access */
4128 /* Try forcing SDIO core to do ALPAvail request only */
4129 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4130 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4131 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4132 if (err) {
4133 brcmf_dbg(ERROR, "error writing for HT off\n");
4134 goto fail;
4135 }
4136
4137 /* If register supported, wait for ALPAvail and then force ALP */
4138 /* This may take up to 15 milliseconds */
4139 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4140 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4141 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4142 SPINWAIT(((clkval =
4143 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4144 SBSDIO_FUNC1_CHIPCLKCSR,
4145 NULL)),
4146 !SBSDIO_ALPAV(clkval)),
4147 PMU_MAX_TRANSITION_DLY);
4148 if (!SBSDIO_ALPAV(clkval)) {
4149 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4150 clkval);
4151 err = -EBUSY;
4152 goto fail;
4153 }
4154 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4155 SBSDIO_FORCE_ALP;
4156 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4157 SBSDIO_FUNC1_CHIPCLKCSR,
4158 clkset, &err);
4159 udelay(65);
4160 } else {
4161 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4162 clkset, clkval);
4163 err = -EACCES;
4164 goto fail;
4165 }
4166
4167 /* Also, disable the extra SDIO pull-ups */
4168 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4169 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4170
4171 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4172 if (err)
4173 goto fail;
4174
4175 /*
4176 * Make sure any on-chip ARM is off (in case strapping is wrong),
4177 * or downloaded code was already running.
4178 */
4179 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4180
4181 brcmf_sdcard_reg_write(bus->sdiodev,
4182 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4183 brcmf_sdcard_reg_write(bus->sdiodev,
4184 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4185
4186 /* Disable F2 to clear any intermediate frame state on the dongle */
4187 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4188 SDIO_FUNC_ENABLE_1, NULL);
4189
4190 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4191 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4192 0, NULL);
4193
4194 /* Done with backplane-dependent accesses, can drop clock... */
4195 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4196 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4197
4198 bus->ci = ci;
4199 return 0;
4200 fail:
4201 bus->ci = NULL;
4202 kfree(ci);
4203 return err;
4204 }
4205
4206 static bool
4207 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4208 {
4209 u8 clkctl = 0;
4210 int err = 0;
4211 int reg_addr;
4212 u32 reg_val;
4213
4214 bus->alp_only = true;
4215
4216 /* Return the window to backplane enumeration space for core access */
4217 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4218 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4219
4220 #ifdef BCMDBG
4221 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4222 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4223
4224 #endif /* BCMDBG */
4225
4226 /*
4227 * Force PLL off until brcmf_sdbrcm_chip_attach()
4228 * programs PLL control regs
4229 */
4230
4231 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4232 SBSDIO_FUNC1_CHIPCLKCSR,
4233 BRCMF_INIT_CLKCTL1, &err);
4234 if (!err)
4235 clkctl =
4236 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4237 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4238
4239 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4240 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4241 err, BRCMF_INIT_CLKCTL1, clkctl);
4242 goto fail;
4243 }
4244
4245 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4246 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4247 goto fail;
4248 }
4249
4250 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4251 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4252 goto fail;
4253 }
4254
4255 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4256
4257 /* Get info on the ARM and SOCRAM cores... */
4258 brcmf_sdcard_reg_read(bus->sdiodev,
4259 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4260 bus->ramsize = bus->ci->ramsize;
4261 if (!(bus->ramsize)) {
4262 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4263 goto fail;
4264 }
4265
4266 /* Set core control so an SDIO reset does a backplane reset */
4267 reg_addr = bus->ci->buscorebase +
4268 offsetof(struct sdpcmd_regs, corecontrol);
4269 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4270 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4271 reg_val | CC_BPRESEN);
4272
4273 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4274
4275 /* Locate an appropriately-aligned portion of hdrbuf */
4276 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4277 BRCMF_SDALIGN);
4278
4279 /* Set the poll and/or interrupt flags */
4280 bus->intr = true;
4281 bus->poll = false;
4282 if (bus->poll)
4283 bus->pollrate = 1;
4284
4285 return true;
4286
4287 fail:
4288 return false;
4289 }
4290
4291 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4292 {
4293 brcmf_dbg(TRACE, "Enter\n");
4294
4295 /* Disable F2 to clear any intermediate frame state on the dongle */
4296 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4297 SDIO_FUNC_ENABLE_1, NULL);
4298
4299 bus->drvr->busstate = BRCMF_BUS_DOWN;
4300 bus->sleeping = false;
4301 bus->rxflow = false;
4302
4303 /* Done with backplane-dependent accesses, can drop clock... */
4304 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4305 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4306
4307 /* ...and initialize clock/power states */
4308 bus->clkstate = CLK_SDONLY;
4309 bus->idletime = BRCMF_IDLE_INTERVAL;
4310 bus->idleclock = BRCMF_IDLE_ACTIVE;
4311
4312 /* Query the F2 block size, set roundup accordingly */
4313 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4314 bus->roundup = min(max_roundup, bus->blocksize);
4315
4316 /* bus module does not support packet chaining */
4317 bus->use_rxchain = false;
4318 bus->sd_rxchain = false;
4319
4320 return true;
4321 }
4322
4323 static int
4324 brcmf_sdbrcm_watchdog_thread(void *data)
4325 {
4326 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4327
4328 allow_signal(SIGTERM);
4329 /* Run until signal received */
4330 while (1) {
4331 if (kthread_should_stop())
4332 break;
4333 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4334 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4335 /* Count the tick for reference */
4336 bus->drvr->tickcnt++;
4337 } else
4338 break;
4339 }
4340 return 0;
4341 }
4342
4343 static void
4344 brcmf_sdbrcm_watchdog(unsigned long data)
4345 {
4346 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4347
4348 if (bus->watchdog_tsk) {
4349 complete(&bus->watchdog_wait);
4350 /* Reschedule the watchdog */
4351 if (bus->wd_timer_valid)
4352 mod_timer(&bus->timer,
4353 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4354 }
4355 }
4356
4357 static void
4358 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4359 {
4360 brcmf_dbg(TRACE, "Enter\n");
4361
4362 kfree(bus->ci);
4363 bus->ci = NULL;
4364 }
4365
4366 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4367 {
4368 brcmf_dbg(TRACE, "Enter\n");
4369
4370 if (bus->ci) {
4371 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4372 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4373 brcmf_sdbrcm_chip_detach(bus);
4374 if (bus->vars && bus->varsz)
4375 kfree(bus->vars);
4376 bus->vars = NULL;
4377 }
4378
4379 brcmf_dbg(TRACE, "Disconnected\n");
4380 }
4381
4382 /* Detach and free everything */
4383 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4384 {
4385 brcmf_dbg(TRACE, "Enter\n");
4386
4387 if (bus) {
4388 /* De-register interrupt handler */
4389 brcmf_sdcard_intr_dereg(bus->sdiodev);
4390
4391 if (bus->drvr) {
4392 brcmf_detach(bus->drvr);
4393 brcmf_sdbrcm_release_dongle(bus);
4394 bus->drvr = NULL;
4395 }
4396
4397 brcmf_sdbrcm_release_malloc(bus);
4398
4399 kfree(bus);
4400 }
4401
4402 brcmf_dbg(TRACE, "Disconnected\n");
4403 }
4404
4405 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4406 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4407 {
4408 int ret;
4409 struct brcmf_bus *bus;
4410
4411 /* Init global variables at run-time, not as part of the declaration.
4412 * This is required to support init/de-init of the driver.
4413 * Initialization
4414 * of globals as part of the declaration results in non-deterministic
4415 * behavior since the value of the globals may be different on the
4416 * first time that the driver is initialized vs subsequent
4417 * initializations.
4418 */
4419 brcmf_c_init();
4420
4421 brcmf_dbg(TRACE, "Enter\n");
4422
4423 /* We make an assumption about address window mappings:
4424 * regsva == SI_ENUM_BASE*/
4425
4426 /* Allocate private bus interface state */
4427 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4428 if (!bus)
4429 goto fail;
4430
4431 bus->sdiodev = sdiodev;
4432 sdiodev->bus = bus;
4433 bus->txbound = BRCMF_TXBOUND;
4434 bus->rxbound = BRCMF_RXBOUND;
4435 bus->txminmax = BRCMF_TXMINMAX;
4436 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4437 bus->usebufpool = false; /* Use bufpool if allocated,
4438 else use locally malloced rxbuf */
4439
4440 /* attempt to attach to the dongle */
4441 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4442 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4443 goto fail;
4444 }
4445
4446 spin_lock_init(&bus->txqlock);
4447 init_waitqueue_head(&bus->ctrl_wait);
4448 init_waitqueue_head(&bus->dcmd_resp_wait);
4449
4450 /* Set up the watchdog timer */
4451 init_timer(&bus->timer);
4452 bus->timer.data = (unsigned long)bus;
4453 bus->timer.function = brcmf_sdbrcm_watchdog;
4454
4455 /* Initialize thread based operation and lock */
4456 sema_init(&bus->sdsem, 1);
4457
4458 /* Initialize watchdog thread */
4459 init_completion(&bus->watchdog_wait);
4460 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4461 bus, "brcmf_watchdog");
4462 if (IS_ERR(bus->watchdog_tsk)) {
4463 printk(KERN_WARNING
4464 "brcmf_watchdog thread failed to start\n");
4465 bus->watchdog_tsk = NULL;
4466 }
4467 /* Initialize DPC thread */
4468 init_completion(&bus->dpc_wait);
4469 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4470 bus, "brcmf_dpc");
4471 if (IS_ERR(bus->dpc_tsk)) {
4472 printk(KERN_WARNING
4473 "brcmf_dpc thread failed to start\n");
4474 bus->dpc_tsk = NULL;
4475 }
4476
4477 /* Attach to the brcmf/OS/network interface */
4478 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4479 if (!bus->drvr) {
4480 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4481 goto fail;
4482 }
4483
4484 /* Allocate buffers */
4485 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4486 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4487 goto fail;
4488 }
4489
4490 if (!(brcmf_sdbrcm_probe_init(bus))) {
4491 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4492 goto fail;
4493 }
4494
4495 /* Register interrupt callback, but mask it (not operational yet). */
4496 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4497 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4498 if (ret != 0) {
4499 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4500 goto fail;
4501 }
4502 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4503
4504 brcmf_dbg(INFO, "completed!!\n");
4505
4506 /* if firmware path present try to download and bring up bus */
4507 ret = brcmf_bus_start(bus->drvr);
4508 if (ret != 0) {
4509 if (ret == -ENOLINK) {
4510 brcmf_dbg(ERROR, "dongle is not responding\n");
4511 goto fail;
4512 }
4513 }
4514 /* Ok, have the per-port tell the stack we're open for business */
4515 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4516 brcmf_dbg(ERROR, "Net attach failed!!\n");
4517 goto fail;
4518 }
4519
4520 return bus;
4521
4522 fail:
4523 brcmf_sdbrcm_release(bus);
4524 return NULL;
4525 }
4526
4527 void brcmf_sdbrcm_disconnect(void *ptr)
4528 {
4529 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4530
4531 brcmf_dbg(TRACE, "Enter\n");
4532
4533 if (bus)
4534 brcmf_sdbrcm_release(bus);
4535
4536 brcmf_dbg(TRACE, "Disconnected\n");
4537 }
4538
4539 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4540 {
4541 return &bus->sdiodev->func[2]->dev;
4542 }
4543
4544 void
4545 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4546 {
4547 /* don't start the wd until fw is loaded */
4548 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4549 return;
4550
4551 /* Totally stop the timer */
4552 if (!wdtick && bus->wd_timer_valid == true) {
4553 del_timer_sync(&bus->timer);
4554 bus->wd_timer_valid = false;
4555 bus->save_ms = wdtick;
4556 return;
4557 }
4558
4559 if (wdtick) {
4560 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4561 if (bus->wd_timer_valid == true)
4562 /* Stop timer and restart at new value */
4563 del_timer_sync(&bus->timer);
4564
4565 /* Create timer again when watchdog period is
4566 dynamically changed or in the first instance
4567 */
4568 bus->timer.expires =
4569 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4570 add_timer(&bus->timer);
4571
4572 } else {
4573 /* Re arm the timer, at last watchdog period */
4574 mod_timer(&bus->timer,
4575 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4576 }
4577
4578 bus->wd_timer_valid = true;
4579 bus->save_ms = wdtick;
4580 }
4581 }
Linux kernel - Deliverables
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