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brcm80211: fmac: use sk_buff list for handling frames in receive path
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <asm/unaligned.h>
32 #include <defs.h>
33 #include <brcmu_wifi.h>
34 #include <brcmu_utils.h>
35 #include <brcm_hw_ids.h>
36 #include <soc.h>
37 #include "sdio_host.h"
38
39 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
40
41 #ifdef BCMDBG
42
43 #define BRCMF_TRAP_INFO_SIZE 80
44
45 #define CBUF_LEN (128)
46
47 struct rte_log_le {
48 __le32 buf; /* Can't be pointer on (64-bit) hosts */
49 __le32 buf_size;
50 __le32 idx;
51 char *_buf_compat; /* Redundant pointer for backward compat. */
52 };
53
54 struct rte_console {
55 /* Virtual UART
56 * When there is no UART (e.g. Quickturn),
57 * the host should write a complete
58 * input line directly into cbuf and then write
59 * the length into vcons_in.
60 * This may also be used when there is a real UART
61 * (at risk of conflicting with
62 * the real UART). vcons_out is currently unused.
63 */
64 uint vcons_in;
65 uint vcons_out;
66
67 /* Output (logging) buffer
68 * Console output is written to a ring buffer log_buf at index log_idx.
69 * The host may read the output when it sees log_idx advance.
70 * Output will be lost if the output wraps around faster than the host
71 * polls.
72 */
73 struct rte_log_le log_le;
74
75 /* Console input line buffer
76 * Characters are read one at a time into cbuf
77 * until <CR> is received, then
78 * the buffer is processed as a command line.
79 * Also used for virtual UART.
80 */
81 uint cbuf_idx;
82 char cbuf[CBUF_LEN];
83 };
84
85 #endif /* BCMDBG */
86 #include <chipcommon.h>
87
88 #include "dhd.h"
89 #include "dhd_bus.h"
90 #include "dhd_proto.h"
91 #include "dhd_dbg.h"
92 #include <bcmchip.h>
93
94 #define TXQLEN 2048 /* bulk tx queue length */
95 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
96 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
97 #define PRIOMASK 7
98
99 #define TXRETRIES 2 /* # of retries for tx frames */
100
101 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
102 one scheduling */
103
104 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
105 one scheduling */
106
107 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
108
109 #define MEMBLOCK 2048 /* Block size used for downloading
110 of dongle image */
111 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
112 biggest possible glom */
113
114 #define BRCMF_FIRSTREAD (1 << 6)
115
116
117 /* SBSDIO_DEVICE_CTL */
118
119 /* 1: device will assert busy signal when receiving CMD53 */
120 #define SBSDIO_DEVCTL_SETBUSY 0x01
121 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
122 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
123 /* 1: mask all interrupts to host except the chipActive (rev 8) */
124 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
125 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
126 * sdio bus power cycle to clear (rev 9) */
127 #define SBSDIO_DEVCTL_PADS_ISO 0x08
128 /* Force SD->SB reset mapping (rev 11) */
129 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
130 /* Determined by CoreControl bit */
131 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
132 /* Force backplane reset */
133 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
134 /* Force no backplane reset */
135 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
136
137 /* SBSDIO_FUNC1_CHIPCLKCSR */
138
139 /* Force ALP request to backplane */
140 #define SBSDIO_FORCE_ALP 0x01
141 /* Force HT request to backplane */
142 #define SBSDIO_FORCE_HT 0x02
143 /* Force ILP request to backplane */
144 #define SBSDIO_FORCE_ILP 0x04
145 /* Make ALP ready (power up xtal) */
146 #define SBSDIO_ALP_AVAIL_REQ 0x08
147 /* Make HT ready (power up PLL) */
148 #define SBSDIO_HT_AVAIL_REQ 0x10
149 /* Squelch clock requests from HW */
150 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
151 /* Status: ALP is ready */
152 #define SBSDIO_ALP_AVAIL 0x40
153 /* Status: HT is ready */
154 #define SBSDIO_HT_AVAIL 0x80
155
156 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
157 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
158 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
159 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
160
161 #define SBSDIO_CLKAV(regval, alponly) \
162 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
163
164 /* direct(mapped) cis space */
165
166 /* MAPPED common CIS address */
167 #define SBSDIO_CIS_BASE_COMMON 0x1000
168 /* maximum bytes in one CIS */
169 #define SBSDIO_CIS_SIZE_LIMIT 0x200
170 /* cis offset addr is < 17 bits */
171 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
172
173 /* manfid tuple length, include tuple, link bytes */
174 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
175
176 /* intstatus */
177 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
178 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
179 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
180 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
181 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
182 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
183 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
184 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
185 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
186 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
187 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
188 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
189 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
190 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
191 #define I_PC (1 << 10) /* descriptor error */
192 #define I_PD (1 << 11) /* data error */
193 #define I_DE (1 << 12) /* Descriptor protocol Error */
194 #define I_RU (1 << 13) /* Receive descriptor Underflow */
195 #define I_RO (1 << 14) /* Receive fifo Overflow */
196 #define I_XU (1 << 15) /* Transmit fifo Underflow */
197 #define I_RI (1 << 16) /* Receive Interrupt */
198 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
199 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
200 #define I_XI (1 << 24) /* Transmit Interrupt */
201 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
202 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
203 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
204 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
205 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
206 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
207 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
208 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
209 #define I_DMA (I_RI | I_XI | I_ERRORS)
210
211 /* corecontrol */
212 #define CC_CISRDY (1 << 0) /* CIS Ready */
213 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
214 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
215 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
216 #define CC_XMTDATAAVAIL_MODE (1 << 4)
217 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
218
219 /* SDA_FRAMECTRL */
220 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
221 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
222 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
223 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
224
225 /* HW frame tag */
226 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
227
228 /* Total length of frame header for dongle protocol */
229 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
230 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
231
232 /*
233 * Software allocation of To SB Mailbox resources
234 */
235
236 /* tosbmailbox bits corresponding to intstatus bits */
237 #define SMB_NAK (1 << 0) /* Frame NAK */
238 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
239 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
240 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
241
242 /* tosbmailboxdata */
243 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
244
245 /*
246 * Software allocation of To Host Mailbox resources
247 */
248
249 /* intstatus bits */
250 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
251 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
252 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
253 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
254
255 /* tohostmailboxdata */
256 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
257 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
258 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
259 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
260
261 #define HMB_DATA_FCDATA_MASK 0xff000000
262 #define HMB_DATA_FCDATA_SHIFT 24
263
264 #define HMB_DATA_VERSION_MASK 0x00ff0000
265 #define HMB_DATA_VERSION_SHIFT 16
266
267 /*
268 * Software-defined protocol header
269 */
270
271 /* Current protocol version */
272 #define SDPCM_PROT_VERSION 4
273
274 /* SW frame header */
275 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
276
277 #define SDPCM_CHANNEL_MASK 0x00000f00
278 #define SDPCM_CHANNEL_SHIFT 8
279 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
280
281 #define SDPCM_NEXTLEN_OFFSET 2
282
283 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
284 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
285 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
286 #define SDPCM_DOFFSET_MASK 0xff000000
287 #define SDPCM_DOFFSET_SHIFT 24
288 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
289 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
290 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
291 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
292
293 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
294
295 /* logical channel numbers */
296 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
297 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
298 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
299 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
300 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
301
302 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
303
304 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
305
306 /*
307 * Shared structure between dongle and the host.
308 * The structure contains pointers to trap or assert information.
309 */
310 #define SDPCM_SHARED_VERSION 0x0002
311 #define SDPCM_SHARED_VERSION_MASK 0x00FF
312 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
313 #define SDPCM_SHARED_ASSERT 0x0200
314 #define SDPCM_SHARED_TRAP 0x0400
315
316 /* Space for header read, limit for data packets */
317 #define MAX_HDR_READ (1 << 6)
318 #define MAX_RX_DATASZ 2048
319
320 /* Maximum milliseconds to wait for F2 to come up */
321 #define BRCMF_WAIT_F2RDY 3000
322
323 /* Bump up limit on waiting for HT to account for first startup;
324 * if the image is doing a CRC calculation before programming the PMU
325 * for HT availability, it could take a couple hundred ms more, so
326 * max out at a 1 second (1000000us).
327 */
328 #undef PMU_MAX_TRANSITION_DLY
329 #define PMU_MAX_TRANSITION_DLY 1000000
330
331 /* Value for ChipClockCSR during initial setup */
332 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
333 SBSDIO_ALP_AVAIL_REQ)
334
335 /* Flags for SDH calls */
336 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
337
338 /* sbimstate */
339 #define SBIM_IBE 0x20000 /* inbanderror */
340 #define SBIM_TO 0x40000 /* timeout */
341 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
342 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
343
344 /* sbtmstatelow */
345
346 /* reset */
347 #define SBTML_RESET 0x0001
348 /* reject field */
349 #define SBTML_REJ_MASK 0x0006
350 /* reject */
351 #define SBTML_REJ 0x0002
352 /* temporary reject, for error recovery */
353 #define SBTML_TMPREJ 0x0004
354
355 /* Shift to locate the SI control flags in sbtml */
356 #define SBTML_SICF_SHIFT 16
357
358 /* sbtmstatehigh */
359 #define SBTMH_SERR 0x0001 /* serror */
360 #define SBTMH_INT 0x0002 /* interrupt */
361 #define SBTMH_BUSY 0x0004 /* busy */
362 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
363
364 /* Shift to locate the SI status flags in sbtmh */
365 #define SBTMH_SISF_SHIFT 16
366
367 /* sbidlow */
368 #define SBIDL_INIT 0x80 /* initiator */
369
370 /* sbidhigh */
371 #define SBIDH_RC_MASK 0x000f /* revision code */
372 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
373 #define SBIDH_RCE_SHIFT 8
374 #define SBCOREREV(sbidh) \
375 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
376 ((sbidh) & SBIDH_RC_MASK))
377 #define SBIDH_CC_MASK 0x8ff0 /* core code */
378 #define SBIDH_CC_SHIFT 4
379 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
380 #define SBIDH_VC_SHIFT 16
381
382 /*
383 * Conversion of 802.1D priority to precedence level
384 */
385 static uint prio2prec(u32 prio)
386 {
387 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
388 (prio^2) : prio;
389 }
390
391 /*
392 * Core reg address translation.
393 * Both macro's returns a 32 bits byte address on the backplane bus.
394 */
395 #define CORE_CC_REG(base, field) \
396 (base + offsetof(struct chipcregs, field))
397 #define CORE_BUS_REG(base, field) \
398 (base + offsetof(struct sdpcmd_regs, field))
399 #define CORE_SB(base, field) \
400 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
401
402 /* core registers */
403 struct sdpcmd_regs {
404 u32 corecontrol; /* 0x00, rev8 */
405 u32 corestatus; /* rev8 */
406 u32 PAD[1];
407 u32 biststatus; /* rev8 */
408
409 /* PCMCIA access */
410 u16 pcmciamesportaladdr; /* 0x010, rev8 */
411 u16 PAD[1];
412 u16 pcmciamesportalmask; /* rev8 */
413 u16 PAD[1];
414 u16 pcmciawrframebc; /* rev8 */
415 u16 PAD[1];
416 u16 pcmciaunderflowtimer; /* rev8 */
417 u16 PAD[1];
418
419 /* interrupt */
420 u32 intstatus; /* 0x020, rev8 */
421 u32 hostintmask; /* rev8 */
422 u32 intmask; /* rev8 */
423 u32 sbintstatus; /* rev8 */
424 u32 sbintmask; /* rev8 */
425 u32 funcintmask; /* rev4 */
426 u32 PAD[2];
427 u32 tosbmailbox; /* 0x040, rev8 */
428 u32 tohostmailbox; /* rev8 */
429 u32 tosbmailboxdata; /* rev8 */
430 u32 tohostmailboxdata; /* rev8 */
431
432 /* synchronized access to registers in SDIO clock domain */
433 u32 sdioaccess; /* 0x050, rev8 */
434 u32 PAD[3];
435
436 /* PCMCIA frame control */
437 u8 pcmciaframectrl; /* 0x060, rev8 */
438 u8 PAD[3];
439 u8 pcmciawatermark; /* rev8 */
440 u8 PAD[155];
441
442 /* interrupt batching control */
443 u32 intrcvlazy; /* 0x100, rev8 */
444 u32 PAD[3];
445
446 /* counters */
447 u32 cmd52rd; /* 0x110, rev8 */
448 u32 cmd52wr; /* rev8 */
449 u32 cmd53rd; /* rev8 */
450 u32 cmd53wr; /* rev8 */
451 u32 abort; /* rev8 */
452 u32 datacrcerror; /* rev8 */
453 u32 rdoutofsync; /* rev8 */
454 u32 wroutofsync; /* rev8 */
455 u32 writebusy; /* rev8 */
456 u32 readwait; /* rev8 */
457 u32 readterm; /* rev8 */
458 u32 writeterm; /* rev8 */
459 u32 PAD[40];
460 u32 clockctlstatus; /* rev8 */
461 u32 PAD[7];
462
463 u32 PAD[128]; /* DMA engines */
464
465 /* SDIO/PCMCIA CIS region */
466 char cis[512]; /* 0x400-0x5ff, rev6 */
467
468 /* PCMCIA function control registers */
469 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
470 u16 PAD[55];
471
472 /* PCMCIA backplane access */
473 u16 backplanecsr; /* 0x76E, rev6 */
474 u16 backplaneaddr0; /* rev6 */
475 u16 backplaneaddr1; /* rev6 */
476 u16 backplaneaddr2; /* rev6 */
477 u16 backplaneaddr3; /* rev6 */
478 u16 backplanedata0; /* rev6 */
479 u16 backplanedata1; /* rev6 */
480 u16 backplanedata2; /* rev6 */
481 u16 backplanedata3; /* rev6 */
482 u16 PAD[31];
483
484 /* sprom "size" & "blank" info */
485 u16 spromstatus; /* 0x7BE, rev2 */
486 u32 PAD[464];
487
488 u16 PAD[0x80];
489 };
490
491 #ifdef BCMDBG
492 /* Device console log buffer state */
493 struct brcmf_console {
494 uint count; /* Poll interval msec counter */
495 uint log_addr; /* Log struct address (fixed) */
496 struct rte_log_le log_le; /* Log struct (host copy) */
497 uint bufsize; /* Size of log buffer */
498 u8 *buf; /* Log buffer (host copy) */
499 uint last; /* Last buffer read index */
500 };
501 #endif /* BCMDBG */
502
503 struct sdpcm_shared {
504 u32 flags;
505 u32 trap_addr;
506 u32 assert_exp_addr;
507 u32 assert_file_addr;
508 u32 assert_line;
509 u32 console_addr; /* Address of struct rte_console */
510 u32 msgtrace_addr;
511 u8 tag[32];
512 };
513
514 struct sdpcm_shared_le {
515 __le32 flags;
516 __le32 trap_addr;
517 __le32 assert_exp_addr;
518 __le32 assert_file_addr;
519 __le32 assert_line;
520 __le32 console_addr; /* Address of struct rte_console */
521 __le32 msgtrace_addr;
522 u8 tag[32];
523 };
524
525
526 /* misc chip info needed by some of the routines */
527 struct chip_info {
528 u32 chip;
529 u32 chiprev;
530 u32 cccorebase;
531 u32 ccrev;
532 u32 cccaps;
533 u32 buscorebase; /* 32 bits backplane bus address */
534 u32 buscorerev;
535 u32 buscoretype;
536 u32 ramcorebase;
537 u32 armcorebase;
538 u32 pmurev;
539 u32 ramsize;
540 };
541
542 /* Private data for SDIO bus interaction */
543 struct brcmf_bus {
544 struct brcmf_pub *drvr;
545
546 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
547 struct chip_info *ci; /* Chip info struct */
548 char *vars; /* Variables (from CIS and/or other) */
549 uint varsz; /* Size of variables buffer */
550
551 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
552
553 u32 hostintmask; /* Copy of Host Interrupt Mask */
554 u32 intstatus; /* Intstatus bits (events) pending */
555 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
556 bool fcstate; /* State of dongle flow-control */
557
558 uint blocksize; /* Block size of SDIO transfers */
559 uint roundup; /* Max roundup limit */
560
561 struct pktq txq; /* Queue length used for flow-control */
562 u8 flowcontrol; /* per prio flow control bitmask */
563 u8 tx_seq; /* Transmit sequence number (next) */
564 u8 tx_max; /* Maximum transmit sequence allowed */
565
566 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
567 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
568 u16 nextlen; /* Next Read Len from last header */
569 u8 rx_seq; /* Receive sequence number (expected) */
570 bool rxskip; /* Skip receive (awaiting NAK ACK) */
571
572 uint rxbound; /* Rx frames to read before resched */
573 uint txbound; /* Tx frames to send before resched */
574 uint txminmax;
575
576 struct sk_buff *glomd; /* Packet containing glomming descriptor */
577 struct sk_buff_head glom; /* Packet list for glommed superframe */
578 uint glomerr; /* Glom packet read errors */
579
580 u8 *rxbuf; /* Buffer for receiving control packets */
581 uint rxblen; /* Allocated length of rxbuf */
582 u8 *rxctl; /* Aligned pointer into rxbuf */
583 u8 *databuf; /* Buffer for receiving big glom packet */
584 u8 *dataptr; /* Aligned pointer into databuf */
585 uint rxlen; /* Length of valid data in buffer */
586
587 u8 sdpcm_ver; /* Bus protocol reported by dongle */
588
589 bool intr; /* Use interrupts */
590 bool poll; /* Use polling */
591 bool ipend; /* Device interrupt is pending */
592 uint intrcount; /* Count of device interrupt callbacks */
593 uint lastintrs; /* Count as of last watchdog timer */
594 uint spurious; /* Count of spurious interrupts */
595 uint pollrate; /* Ticks between device polls */
596 uint polltick; /* Tick counter */
597 uint pollcnt; /* Count of active polls */
598
599 #ifdef BCMDBG
600 uint console_interval;
601 struct brcmf_console console; /* Console output polling support */
602 uint console_addr; /* Console address from shared struct */
603 #endif /* BCMDBG */
604
605 uint regfails; /* Count of R_REG failures */
606
607 uint clkstate; /* State of sd and backplane clock(s) */
608 bool activity; /* Activity flag for clock down */
609 s32 idletime; /* Control for activity timeout */
610 s32 idlecount; /* Activity timeout counter */
611 s32 idleclock; /* How to set bus driver when idle */
612 s32 sd_rxchain;
613 bool use_rxchain; /* If brcmf should use PKT chains */
614 bool sleeping; /* Is SDIO bus sleeping? */
615 bool rxflow_mode; /* Rx flow control mode */
616 bool rxflow; /* Is rx flow control on */
617 bool alp_only; /* Don't use HT clock (ALP only) */
618 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
619 bool usebufpool;
620
621 /* Some additional counters */
622 uint tx_sderrs; /* Count of tx attempts with sd errors */
623 uint fcqueued; /* Tx packets that got queued */
624 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
625 uint rx_toolong; /* Receive frames too long to receive */
626 uint rxc_errors; /* SDIO errors when reading control frames */
627 uint rx_hdrfail; /* SDIO errors on header reads */
628 uint rx_badhdr; /* Bad received headers (roosync?) */
629 uint rx_badseq; /* Mismatched rx sequence number */
630 uint fc_rcvd; /* Number of flow-control events received */
631 uint fc_xoff; /* Number which turned on flow-control */
632 uint fc_xon; /* Number which turned off flow-control */
633 uint rxglomfail; /* Failed deglom attempts */
634 uint rxglomframes; /* Number of glom frames (superframes) */
635 uint rxglompkts; /* Number of packets from glom frames */
636 uint f2rxhdrs; /* Number of header reads */
637 uint f2rxdata; /* Number of frame data reads */
638 uint f2txdata; /* Number of f2 frame writes */
639 uint f1regdata; /* Number of f1 register accesses */
640
641 u8 *ctrl_frame_buf;
642 u32 ctrl_frame_len;
643 bool ctrl_frame_stat;
644
645 spinlock_t txqlock;
646 wait_queue_head_t ctrl_wait;
647 wait_queue_head_t dcmd_resp_wait;
648
649 struct timer_list timer;
650 struct completion watchdog_wait;
651 struct task_struct *watchdog_tsk;
652 bool wd_timer_valid;
653 uint save_ms;
654
655 struct task_struct *dpc_tsk;
656 struct completion dpc_wait;
657
658 struct semaphore sdsem;
659
660 const char *fw_name;
661 const struct firmware *firmware;
662 const char *nv_name;
663 u32 fw_ptr;
664 };
665
666 struct sbconfig {
667 u32 PAD[2];
668 u32 sbipsflag; /* initiator port ocp slave flag */
669 u32 PAD[3];
670 u32 sbtpsflag; /* target port ocp slave flag */
671 u32 PAD[11];
672 u32 sbtmerrloga; /* (sonics >= 2.3) */
673 u32 PAD;
674 u32 sbtmerrlog; /* (sonics >= 2.3) */
675 u32 PAD[3];
676 u32 sbadmatch3; /* address match3 */
677 u32 PAD;
678 u32 sbadmatch2; /* address match2 */
679 u32 PAD;
680 u32 sbadmatch1; /* address match1 */
681 u32 PAD[7];
682 u32 sbimstate; /* initiator agent state */
683 u32 sbintvec; /* interrupt mask */
684 u32 sbtmstatelow; /* target state */
685 u32 sbtmstatehigh; /* target state */
686 u32 sbbwa0; /* bandwidth allocation table0 */
687 u32 PAD;
688 u32 sbimconfiglow; /* initiator configuration */
689 u32 sbimconfighigh; /* initiator configuration */
690 u32 sbadmatch0; /* address match0 */
691 u32 PAD;
692 u32 sbtmconfiglow; /* target configuration */
693 u32 sbtmconfighigh; /* target configuration */
694 u32 sbbconfig; /* broadcast configuration */
695 u32 PAD;
696 u32 sbbstate; /* broadcast state */
697 u32 PAD[3];
698 u32 sbactcnfg; /* activate configuration */
699 u32 PAD[3];
700 u32 sbflagst; /* current sbflags */
701 u32 PAD[3];
702 u32 sbidlow; /* identification */
703 u32 sbidhigh; /* identification */
704 };
705
706 /* clkstate */
707 #define CLK_NONE 0
708 #define CLK_SDONLY 1
709 #define CLK_PENDING 2 /* Not used yet */
710 #define CLK_AVAIL 3
711
712 #ifdef BCMDBG
713 static int qcount[NUMPRIO];
714 static int tx_packets[NUMPRIO];
715 #endif /* BCMDBG */
716
717 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
718
719 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
720
721 /* Retry count for register access failures */
722 static const uint retry_limit = 2;
723
724 /* Limit on rounding up frames */
725 static const uint max_roundup = 512;
726
727 #define ALIGNMENT 4
728
729 static void pkt_align(struct sk_buff *p, int len, int align)
730 {
731 uint datalign;
732 datalign = (unsigned long)(p->data);
733 datalign = roundup(datalign, (align)) - datalign;
734 if (datalign)
735 skb_pull(p, datalign);
736 __skb_trim(p, len);
737 }
738
739 /* To check if there's window offered */
740 static bool data_ok(struct brcmf_bus *bus)
741 {
742 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
743 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
744 }
745
746 /*
747 * Reads a register in the SDIO hardware block. This block occupies a series of
748 * adresses on the 32 bit backplane bus.
749 */
750 static void
751 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
752 {
753 *retryvar = 0;
754 do {
755 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
756 bus->ci->buscorebase + reg_offset, sizeof(u32));
757 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
758 (++(*retryvar) <= retry_limit));
759 if (*retryvar) {
760 bus->regfails += (*retryvar-1);
761 if (*retryvar > retry_limit) {
762 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
763 *regvar = 0;
764 }
765 }
766 }
767
768 static void
769 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
770 {
771 *retryvar = 0;
772 do {
773 brcmf_sdcard_reg_write(bus->sdiodev,
774 bus->ci->buscorebase + reg_offset,
775 sizeof(u32), regval);
776 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
777 (++(*retryvar) <= retry_limit));
778 if (*retryvar) {
779 bus->regfails += (*retryvar-1);
780 if (*retryvar > retry_limit)
781 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
782 reg_offset);
783 }
784 }
785
786 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
787
788 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
789
790 /* Packet free applicable unconditionally for sdio and sdspi.
791 * Conditional if bufpool was present for gspi bus.
792 */
793 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
794 {
795 if (bus->usebufpool)
796 brcmu_pkt_buf_free_skb(pkt);
797 }
798
799 /* Turn backplane clock on or off */
800 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
801 {
802 int err;
803 u8 clkctl, clkreq, devctl;
804 unsigned long timeout;
805
806 brcmf_dbg(TRACE, "Enter\n");
807
808 clkctl = 0;
809
810 if (on) {
811 /* Request HT Avail */
812 clkreq =
813 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
814
815 if ((bus->ci->chip == BCM4329_CHIP_ID)
816 && (bus->ci->chiprev == 0))
817 clkreq |= SBSDIO_FORCE_ALP;
818
819 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
820 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
821 if (err) {
822 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
823 return -EBADE;
824 }
825
826 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
827 && (bus->ci->buscorerev == 9))) {
828 u32 dummy, retries;
829 r_sdreg32(bus, &dummy,
830 offsetof(struct sdpcmd_regs, clockctlstatus),
831 &retries);
832 }
833
834 /* Check current status */
835 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
836 SBSDIO_FUNC1_CHIPCLKCSR, &err);
837 if (err) {
838 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
839 return -EBADE;
840 }
841
842 /* Go to pending and await interrupt if appropriate */
843 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
844 /* Allow only clock-available interrupt */
845 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
846 SDIO_FUNC_1,
847 SBSDIO_DEVICE_CTL, &err);
848 if (err) {
849 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
850 err);
851 return -EBADE;
852 }
853
854 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
855 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
856 SBSDIO_DEVICE_CTL, devctl, &err);
857 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
858 bus->clkstate = CLK_PENDING;
859
860 return 0;
861 } else if (bus->clkstate == CLK_PENDING) {
862 /* Cancel CA-only interrupt filter */
863 devctl =
864 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
865 SBSDIO_DEVICE_CTL, &err);
866 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
867 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
868 SBSDIO_DEVICE_CTL, devctl, &err);
869 }
870
871 /* Otherwise, wait here (polling) for HT Avail */
872 timeout = jiffies +
873 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
874 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
875 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
876 SDIO_FUNC_1,
877 SBSDIO_FUNC1_CHIPCLKCSR,
878 &err);
879 if (time_after(jiffies, timeout))
880 break;
881 else
882 usleep_range(5000, 10000);
883 }
884 if (err) {
885 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
886 return -EBADE;
887 }
888 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
889 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
890 PMU_MAX_TRANSITION_DLY, clkctl);
891 return -EBADE;
892 }
893
894 /* Mark clock available */
895 bus->clkstate = CLK_AVAIL;
896 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
897
898 #if defined(BCMDBG)
899 if (bus->alp_only != true) {
900 if (SBSDIO_ALPONLY(clkctl))
901 brcmf_dbg(ERROR, "HT Clock should be on\n");
902 }
903 #endif /* defined (BCMDBG) */
904
905 bus->activity = true;
906 } else {
907 clkreq = 0;
908
909 if (bus->clkstate == CLK_PENDING) {
910 /* Cancel CA-only interrupt filter */
911 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
912 SDIO_FUNC_1,
913 SBSDIO_DEVICE_CTL, &err);
914 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
915 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
916 SBSDIO_DEVICE_CTL, devctl, &err);
917 }
918
919 bus->clkstate = CLK_SDONLY;
920 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
921 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
922 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
923 if (err) {
924 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
925 err);
926 return -EBADE;
927 }
928 }
929 return 0;
930 }
931
932 /* Change idle/active SD state */
933 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
934 {
935 brcmf_dbg(TRACE, "Enter\n");
936
937 if (on)
938 bus->clkstate = CLK_SDONLY;
939 else
940 bus->clkstate = CLK_NONE;
941
942 return 0;
943 }
944
945 /* Transition SD and backplane clock readiness */
946 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
947 {
948 #ifdef BCMDBG
949 uint oldstate = bus->clkstate;
950 #endif /* BCMDBG */
951
952 brcmf_dbg(TRACE, "Enter\n");
953
954 /* Early exit if we're already there */
955 if (bus->clkstate == target) {
956 if (target == CLK_AVAIL) {
957 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
958 bus->activity = true;
959 }
960 return 0;
961 }
962
963 switch (target) {
964 case CLK_AVAIL:
965 /* Make sure SD clock is available */
966 if (bus->clkstate == CLK_NONE)
967 brcmf_sdbrcm_sdclk(bus, true);
968 /* Now request HT Avail on the backplane */
969 brcmf_sdbrcm_htclk(bus, true, pendok);
970 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
971 bus->activity = true;
972 break;
973
974 case CLK_SDONLY:
975 /* Remove HT request, or bring up SD clock */
976 if (bus->clkstate == CLK_NONE)
977 brcmf_sdbrcm_sdclk(bus, true);
978 else if (bus->clkstate == CLK_AVAIL)
979 brcmf_sdbrcm_htclk(bus, false, false);
980 else
981 brcmf_dbg(ERROR, "request for %d -> %d\n",
982 bus->clkstate, target);
983 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
984 break;
985
986 case CLK_NONE:
987 /* Make sure to remove HT request */
988 if (bus->clkstate == CLK_AVAIL)
989 brcmf_sdbrcm_htclk(bus, false, false);
990 /* Now remove the SD clock */
991 brcmf_sdbrcm_sdclk(bus, false);
992 brcmf_sdbrcm_wd_timer(bus, 0);
993 break;
994 }
995 #ifdef BCMDBG
996 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
997 #endif /* BCMDBG */
998
999 return 0;
1000 }
1001
1002 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1003 {
1004 uint retries = 0;
1005
1006 brcmf_dbg(INFO, "request %s (currently %s)\n",
1007 sleep ? "SLEEP" : "WAKE",
1008 bus->sleeping ? "SLEEP" : "WAKE");
1009
1010 /* Done if we're already in the requested state */
1011 if (sleep == bus->sleeping)
1012 return 0;
1013
1014 /* Going to sleep: set the alarm and turn off the lights... */
1015 if (sleep) {
1016 /* Don't sleep if something is pending */
1017 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1018 return -EBUSY;
1019
1020 /* Make sure the controller has the bus up */
1021 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1022
1023 /* Tell device to start using OOB wakeup */
1024 w_sdreg32(bus, SMB_USE_OOB,
1025 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1026 if (retries > retry_limit)
1027 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1028
1029 /* Turn off our contribution to the HT clock request */
1030 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1031
1032 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1033 SBSDIO_FUNC1_CHIPCLKCSR,
1034 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1035
1036 /* Isolate the bus */
1037 if (bus->ci->chip != BCM4329_CHIP_ID) {
1038 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1039 SBSDIO_DEVICE_CTL,
1040 SBSDIO_DEVCTL_PADS_ISO, NULL);
1041 }
1042
1043 /* Change state */
1044 bus->sleeping = true;
1045
1046 } else {
1047 /* Waking up: bus power up is ok, set local state */
1048
1049 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1050 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1051
1052 /* Force pad isolation off if possible
1053 (in case power never toggled) */
1054 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1055 && (bus->ci->buscorerev >= 10))
1056 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1057 SBSDIO_DEVICE_CTL, 0, NULL);
1058
1059 /* Make sure the controller has the bus up */
1060 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1061
1062 /* Send misc interrupt to indicate OOB not needed */
1063 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1064 &retries);
1065 if (retries <= retry_limit)
1066 w_sdreg32(bus, SMB_DEV_INT,
1067 offsetof(struct sdpcmd_regs, tosbmailbox),
1068 &retries);
1069
1070 if (retries > retry_limit)
1071 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1072
1073 /* Make sure we have SD bus access */
1074 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1075
1076 /* Change state */
1077 bus->sleeping = false;
1078 }
1079
1080 return 0;
1081 }
1082
1083 static void bus_wake(struct brcmf_bus *bus)
1084 {
1085 if (bus->sleeping)
1086 brcmf_sdbrcm_bussleep(bus, false);
1087 }
1088
1089 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1090 {
1091 u32 intstatus = 0;
1092 u32 hmb_data;
1093 u8 fcbits;
1094 uint retries = 0;
1095
1096 brcmf_dbg(TRACE, "Enter\n");
1097
1098 /* Read mailbox data and ack that we did so */
1099 r_sdreg32(bus, &hmb_data,
1100 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1101
1102 if (retries <= retry_limit)
1103 w_sdreg32(bus, SMB_INT_ACK,
1104 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1105 bus->f1regdata += 2;
1106
1107 /* Dongle recomposed rx frames, accept them again */
1108 if (hmb_data & HMB_DATA_NAKHANDLED) {
1109 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1110 bus->rx_seq);
1111 if (!bus->rxskip)
1112 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1113
1114 bus->rxskip = false;
1115 intstatus |= I_HMB_FRAME_IND;
1116 }
1117
1118 /*
1119 * DEVREADY does not occur with gSPI.
1120 */
1121 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1122 bus->sdpcm_ver =
1123 (hmb_data & HMB_DATA_VERSION_MASK) >>
1124 HMB_DATA_VERSION_SHIFT;
1125 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1126 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1127 "expecting %d\n",
1128 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1129 else
1130 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1131 bus->sdpcm_ver);
1132 }
1133
1134 /*
1135 * Flow Control has been moved into the RX headers and this out of band
1136 * method isn't used any more.
1137 * remaining backward compatible with older dongles.
1138 */
1139 if (hmb_data & HMB_DATA_FC) {
1140 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1141 HMB_DATA_FCDATA_SHIFT;
1142
1143 if (fcbits & ~bus->flowcontrol)
1144 bus->fc_xoff++;
1145
1146 if (bus->flowcontrol & ~fcbits)
1147 bus->fc_xon++;
1148
1149 bus->fc_rcvd++;
1150 bus->flowcontrol = fcbits;
1151 }
1152
1153 /* Shouldn't be any others */
1154 if (hmb_data & ~(HMB_DATA_DEVREADY |
1155 HMB_DATA_NAKHANDLED |
1156 HMB_DATA_FC |
1157 HMB_DATA_FWREADY |
1158 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1159 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1160 hmb_data);
1161
1162 return intstatus;
1163 }
1164
1165 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1166 {
1167 uint retries = 0;
1168 u16 lastrbc;
1169 u8 hi, lo;
1170 int err;
1171
1172 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1173 abort ? "abort command, " : "",
1174 rtx ? ", send NAK" : "");
1175
1176 if (abort)
1177 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1178
1179 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1180 SBSDIO_FUNC1_FRAMECTRL,
1181 SFC_RF_TERM, &err);
1182 bus->f1regdata++;
1183
1184 /* Wait until the packet has been flushed (device/FIFO stable) */
1185 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1186 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1187 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1188 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1189 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1190 bus->f1regdata += 2;
1191
1192 if ((hi == 0) && (lo == 0))
1193 break;
1194
1195 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1196 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1197 lastrbc, (hi << 8) + lo);
1198 }
1199 lastrbc = (hi << 8) + lo;
1200 }
1201
1202 if (!retries)
1203 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1204 else
1205 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1206
1207 if (rtx) {
1208 bus->rxrtx++;
1209 w_sdreg32(bus, SMB_NAK,
1210 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1211
1212 bus->f1regdata++;
1213 if (retries <= retry_limit)
1214 bus->rxskip = true;
1215 }
1216
1217 /* Clear partial in any case */
1218 bus->nextlen = 0;
1219
1220 /* If we can't reach the device, signal failure */
1221 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1222 bus->drvr->busstate = BRCMF_BUS_DOWN;
1223 }
1224
1225 /* copy a buffer into a pkt buffer chain */
1226 static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
1227 {
1228 uint n, ret = 0;
1229 struct sk_buff *p;
1230 u8 *buf;
1231
1232 buf = bus->dataptr;
1233
1234 /* copy the data */
1235 skb_queue_walk(&bus->glom, p) {
1236 n = min_t(uint, p->len, len);
1237 memcpy(p->data, buf, n);
1238 buf += n;
1239 len -= n;
1240 ret += n;
1241 if (!len)
1242 break;
1243 }
1244
1245 return ret;
1246 }
1247
1248 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1249 {
1250 u16 dlen, totlen;
1251 u8 *dptr, num = 0;
1252
1253 u16 sublen, check;
1254 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1255
1256 int errcode;
1257 u8 chan, seq, doff, sfdoff;
1258 u8 txmax;
1259
1260 int ifidx = 0;
1261 bool usechain = bus->use_rxchain;
1262
1263 /* If packets, issue read(s) and send up packet chain */
1264 /* Return sequence numbers consumed? */
1265
1266 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1267 bus->glomd, skb_peek(&bus->glom));
1268
1269 /* If there's a descriptor, generate the packet chain */
1270 if (bus->glomd) {
1271 pfirst = plast = pnext = NULL;
1272 dlen = (u16) (bus->glomd->len);
1273 dptr = bus->glomd->data;
1274 if (!dlen || (dlen & 1)) {
1275 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1276 dlen);
1277 dlen = 0;
1278 }
1279
1280 for (totlen = num = 0; dlen; num++) {
1281 /* Get (and move past) next length */
1282 sublen = get_unaligned_le16(dptr);
1283 dlen -= sizeof(u16);
1284 dptr += sizeof(u16);
1285 if ((sublen < SDPCM_HDRLEN) ||
1286 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1287 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1288 num, sublen);
1289 pnext = NULL;
1290 break;
1291 }
1292 if (sublen % BRCMF_SDALIGN) {
1293 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1294 sublen, BRCMF_SDALIGN);
1295 usechain = false;
1296 }
1297 totlen += sublen;
1298
1299 /* For last frame, adjust read len so total
1300 is a block multiple */
1301 if (!dlen) {
1302 sublen +=
1303 (roundup(totlen, bus->blocksize) - totlen);
1304 totlen = roundup(totlen, bus->blocksize);
1305 }
1306
1307 /* Allocate/chain packet for next subframe */
1308 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1309 if (pnext == NULL) {
1310 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1311 num, sublen);
1312 break;
1313 }
1314 skb_queue_tail(&bus->glom, pnext);
1315
1316 /* Adhere to start alignment requirements */
1317 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1318 }
1319
1320 /* If all allocations succeeded, save packet chain
1321 in bus structure */
1322 if (pnext) {
1323 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1324 totlen, num);
1325 if (BRCMF_GLOM_ON() && bus->nextlen &&
1326 totlen != bus->nextlen) {
1327 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1328 bus->nextlen, totlen, rxseq);
1329 }
1330 pfirst = pnext = NULL;
1331 } else {
1332 if (!skb_queue_empty(&bus->glom))
1333 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1334 skb_unlink(pfirst, &bus->glom);
1335 brcmu_pkt_buf_free_skb(pfirst);
1336 }
1337 num = 0;
1338 }
1339
1340 /* Done with descriptor packet */
1341 brcmu_pkt_buf_free_skb(bus->glomd);
1342 bus->glomd = NULL;
1343 bus->nextlen = 0;
1344 }
1345
1346 /* Ok -- either we just generated a packet chain,
1347 or had one from before */
1348 if (!skb_queue_empty(&bus->glom)) {
1349 if (BRCMF_GLOM_ON()) {
1350 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1351 skb_queue_walk(&bus->glom, pnext) {
1352 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1353 pnext, (u8 *) (pnext->data),
1354 pnext->len, pnext->len);
1355 }
1356 }
1357
1358 pfirst = skb_peek(&bus->glom);
1359 dlen = (u16) brcmu_pkttotlen(pfirst);
1360
1361 /* Do an SDIO read for the superframe. Configurable iovar to
1362 * read directly into the chained packet, or allocate a large
1363 * packet and and copy into the chain.
1364 */
1365 if (usechain) {
1366 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1367 bus->sdiodev->sbwad,
1368 SDIO_FUNC_2,
1369 F2SYNC, (u8 *) pfirst->data, dlen,
1370 pfirst);
1371 } else if (bus->dataptr) {
1372 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1373 bus->sdiodev->sbwad,
1374 SDIO_FUNC_2,
1375 F2SYNC, bus->dataptr, dlen,
1376 NULL);
1377 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
1378 if (sublen != dlen) {
1379 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1380 dlen, sublen);
1381 errcode = -1;
1382 }
1383 pnext = NULL;
1384 } else {
1385 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1386 dlen);
1387 errcode = -1;
1388 }
1389 bus->f2rxdata++;
1390
1391 /* On failure, kill the superframe, allow a couple retries */
1392 if (errcode < 0) {
1393 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1394 dlen, errcode);
1395 bus->drvr->rx_errors++;
1396
1397 if (bus->glomerr++ < 3) {
1398 brcmf_sdbrcm_rxfail(bus, true, true);
1399 } else {
1400 bus->glomerr = 0;
1401 brcmf_sdbrcm_rxfail(bus, true, false);
1402 bus->rxglomfail++;
1403 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1404 skb_unlink(pfirst, &bus->glom);
1405 brcmu_pkt_buf_free_skb(pfirst);
1406 }
1407 }
1408 return 0;
1409 }
1410 #ifdef BCMDBG
1411 if (BRCMF_GLOM_ON()) {
1412 printk(KERN_DEBUG "SUPERFRAME:\n");
1413 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1414 pfirst->data, min_t(int, pfirst->len, 48));
1415 }
1416 #endif
1417
1418 /* Validate the superframe header */
1419 dptr = (u8 *) (pfirst->data);
1420 sublen = get_unaligned_le16(dptr);
1421 check = get_unaligned_le16(dptr + sizeof(u16));
1422
1423 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1424 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1425 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1426 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1427 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1428 bus->nextlen, seq);
1429 bus->nextlen = 0;
1430 }
1431 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1432 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1433
1434 errcode = 0;
1435 if ((u16)~(sublen ^ check)) {
1436 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1437 sublen, check);
1438 errcode = -1;
1439 } else if (roundup(sublen, bus->blocksize) != dlen) {
1440 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1441 sublen, roundup(sublen, bus->blocksize),
1442 dlen);
1443 errcode = -1;
1444 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1445 SDPCM_GLOM_CHANNEL) {
1446 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1447 SDPCM_PACKET_CHANNEL(
1448 &dptr[SDPCM_FRAMETAG_LEN]));
1449 errcode = -1;
1450 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1451 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1452 errcode = -1;
1453 } else if ((doff < SDPCM_HDRLEN) ||
1454 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1455 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1456 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1457 errcode = -1;
1458 }
1459
1460 /* Check sequence number of superframe SW header */
1461 if (rxseq != seq) {
1462 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1463 seq, rxseq);
1464 bus->rx_badseq++;
1465 rxseq = seq;
1466 }
1467
1468 /* Check window for sanity */
1469 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1470 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1471 txmax, bus->tx_seq);
1472 txmax = bus->tx_seq + 2;
1473 }
1474 bus->tx_max = txmax;
1475
1476 /* Remove superframe header, remember offset */
1477 skb_pull(pfirst, doff);
1478 sfdoff = doff;
1479
1480 /* Validate all the subframe headers */
1481 for (num = 0, pnext = pfirst; pnext && !errcode;
1482 num++, pnext = pnext->next) {
1483 dptr = (u8 *) (pnext->data);
1484 dlen = (u16) (pnext->len);
1485 sublen = get_unaligned_le16(dptr);
1486 check = get_unaligned_le16(dptr + sizeof(u16));
1487 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1488 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1489 #ifdef BCMDBG
1490 if (BRCMF_GLOM_ON()) {
1491 printk(KERN_DEBUG "subframe:\n");
1492 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1493 dptr, 32);
1494 }
1495 #endif
1496
1497 if ((u16)~(sublen ^ check)) {
1498 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1499 num, sublen, check);
1500 errcode = -1;
1501 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1502 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1503 num, sublen, dlen);
1504 errcode = -1;
1505 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1506 (chan != SDPCM_EVENT_CHANNEL)) {
1507 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1508 num, chan);
1509 errcode = -1;
1510 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1511 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1512 num, doff, sublen, SDPCM_HDRLEN);
1513 errcode = -1;
1514 }
1515 }
1516
1517 if (errcode) {
1518 /* Terminate frame on error, request
1519 a couple retries */
1520 if (bus->glomerr++ < 3) {
1521 /* Restore superframe header space */
1522 skb_push(pfirst, sfdoff);
1523 brcmf_sdbrcm_rxfail(bus, true, true);
1524 } else {
1525 bus->glomerr = 0;
1526 brcmf_sdbrcm_rxfail(bus, true, false);
1527 bus->rxglomfail++;
1528 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1529 skb_unlink(pfirst, &bus->glom);
1530 brcmu_pkt_buf_free_skb(pfirst);
1531 }
1532 }
1533 bus->nextlen = 0;
1534 return 0;
1535 }
1536
1537 /* Basic SD framing looks ok - process each packet (header) */
1538 save_pfirst = pfirst;
1539 plast = NULL;
1540
1541 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1542 pnext = pfirst->next;
1543 pfirst->next = NULL;
1544
1545 dptr = (u8 *) (pfirst->data);
1546 sublen = get_unaligned_le16(dptr);
1547 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1548 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1549 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1550
1551 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1552 num, pfirst, pfirst->data,
1553 pfirst->len, sublen, chan, seq);
1554
1555 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1556 chan == SDPCM_EVENT_CHANNEL */
1557
1558 if (rxseq != seq) {
1559 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1560 seq, rxseq);
1561 bus->rx_badseq++;
1562 rxseq = seq;
1563 }
1564 #ifdef BCMDBG
1565 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1566 printk(KERN_DEBUG "Rx Subframe Data:\n");
1567 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1568 dptr, dlen);
1569 }
1570 #endif
1571
1572 __skb_trim(pfirst, sublen);
1573 skb_pull(pfirst, doff);
1574
1575 if (pfirst->len == 0) {
1576 brcmu_pkt_buf_free_skb(pfirst);
1577 if (plast)
1578 plast->next = pnext;
1579 else
1580 save_pfirst = pnext;
1581
1582 continue;
1583 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1584 pfirst) != 0) {
1585 brcmf_dbg(ERROR, "rx protocol error\n");
1586 bus->drvr->rx_errors++;
1587 brcmu_pkt_buf_free_skb(pfirst);
1588 if (plast)
1589 plast->next = pnext;
1590 else
1591 save_pfirst = pnext;
1592
1593 continue;
1594 }
1595
1596 /* this packet will go up, link back into
1597 chain and count it */
1598 pfirst->next = pnext;
1599 plast = pfirst;
1600 num++;
1601
1602 #ifdef BCMDBG
1603 if (BRCMF_GLOM_ON()) {
1604 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1605 num, pfirst, pfirst->data,
1606 pfirst->len, pfirst->next,
1607 pfirst->prev);
1608 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1609 pfirst->data,
1610 min_t(int, pfirst->len, 32));
1611 }
1612 #endif /* BCMDBG */
1613 }
1614 if (num) {
1615 up(&bus->sdsem);
1616 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1617 down(&bus->sdsem);
1618 }
1619
1620 bus->rxglomframes++;
1621 bus->rxglompkts += num;
1622 }
1623 return num;
1624 }
1625
1626 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1627 bool *pending)
1628 {
1629 DECLARE_WAITQUEUE(wait, current);
1630 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1631
1632 /* Wait until control frame is available */
1633 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1634 set_current_state(TASK_INTERRUPTIBLE);
1635
1636 while (!(*condition) && (!signal_pending(current) && timeout))
1637 timeout = schedule_timeout(timeout);
1638
1639 if (signal_pending(current))
1640 *pending = true;
1641
1642 set_current_state(TASK_RUNNING);
1643 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1644
1645 return timeout;
1646 }
1647
1648 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1649 {
1650 if (waitqueue_active(&bus->dcmd_resp_wait))
1651 wake_up_interruptible(&bus->dcmd_resp_wait);
1652
1653 return 0;
1654 }
1655 static void
1656 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1657 {
1658 uint rdlen, pad;
1659
1660 int sdret;
1661
1662 brcmf_dbg(TRACE, "Enter\n");
1663
1664 /* Set rxctl for frame (w/optional alignment) */
1665 bus->rxctl = bus->rxbuf;
1666 bus->rxctl += BRCMF_FIRSTREAD;
1667 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1668 if (pad)
1669 bus->rxctl += (BRCMF_SDALIGN - pad);
1670 bus->rxctl -= BRCMF_FIRSTREAD;
1671
1672 /* Copy the already-read portion over */
1673 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1674 if (len <= BRCMF_FIRSTREAD)
1675 goto gotpkt;
1676
1677 /* Raise rdlen to next SDIO block to avoid tail command */
1678 rdlen = len - BRCMF_FIRSTREAD;
1679 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1680 pad = bus->blocksize - (rdlen % bus->blocksize);
1681 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1682 ((len + pad) < bus->drvr->maxctl))
1683 rdlen += pad;
1684 } else if (rdlen % BRCMF_SDALIGN) {
1685 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1686 }
1687
1688 /* Satisfy length-alignment requirements */
1689 if (rdlen & (ALIGNMENT - 1))
1690 rdlen = roundup(rdlen, ALIGNMENT);
1691
1692 /* Drop if the read is too big or it exceeds our maximum */
1693 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1694 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1695 rdlen, bus->drvr->maxctl);
1696 bus->drvr->rx_errors++;
1697 brcmf_sdbrcm_rxfail(bus, false, false);
1698 goto done;
1699 }
1700
1701 if ((len - doff) > bus->drvr->maxctl) {
1702 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1703 len, len - doff, bus->drvr->maxctl);
1704 bus->drvr->rx_errors++;
1705 bus->rx_toolong++;
1706 brcmf_sdbrcm_rxfail(bus, false, false);
1707 goto done;
1708 }
1709
1710 /* Read remainder of frame body into the rxctl buffer */
1711 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1712 bus->sdiodev->sbwad,
1713 SDIO_FUNC_2,
1714 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1715 NULL);
1716 bus->f2rxdata++;
1717
1718 /* Control frame failures need retransmission */
1719 if (sdret < 0) {
1720 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1721 rdlen, sdret);
1722 bus->rxc_errors++;
1723 brcmf_sdbrcm_rxfail(bus, true, true);
1724 goto done;
1725 }
1726
1727 gotpkt:
1728
1729 #ifdef BCMDBG
1730 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1731 printk(KERN_DEBUG "RxCtrl:\n");
1732 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1733 }
1734 #endif
1735
1736 /* Point to valid data and indicate its length */
1737 bus->rxctl += doff;
1738 bus->rxlen = len - doff;
1739
1740 done:
1741 /* Awake any waiters */
1742 brcmf_sdbrcm_dcmd_resp_wake(bus);
1743 }
1744
1745 /* Pad read to blocksize for efficiency */
1746 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1747 {
1748 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1749 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1750 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1751 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1752 *rdlen += *pad;
1753 } else if (*rdlen % BRCMF_SDALIGN) {
1754 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1755 }
1756 }
1757
1758 static void
1759 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1760 struct sk_buff **pkt, u8 **rxbuf)
1761 {
1762 int sdret; /* Return code from calls */
1763
1764 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1765 if (*pkt == NULL)
1766 return;
1767
1768 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1769 *rxbuf = (u8 *) ((*pkt)->data);
1770 /* Read the entire frame */
1771 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1772 SDIO_FUNC_2, F2SYNC,
1773 *rxbuf, rdlen, *pkt);
1774 bus->f2rxdata++;
1775
1776 if (sdret < 0) {
1777 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1778 rdlen, sdret);
1779 brcmu_pkt_buf_free_skb(*pkt);
1780 bus->drvr->rx_errors++;
1781 /* Force retry w/normal header read.
1782 * Don't attempt NAK for
1783 * gSPI
1784 */
1785 brcmf_sdbrcm_rxfail(bus, true, true);
1786 *pkt = NULL;
1787 }
1788 }
1789
1790 /* Checks the header */
1791 static int
1792 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1793 u8 rxseq, u16 nextlen, u16 *len)
1794 {
1795 u16 check;
1796 bool len_consistent; /* Result of comparing readahead len and
1797 len from hw-hdr */
1798
1799 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1800
1801 /* Extract hardware header fields */
1802 *len = get_unaligned_le16(bus->rxhdr);
1803 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1804
1805 /* All zeros means readahead info was bad */
1806 if (!(*len | check)) {
1807 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1808 goto fail;
1809 }
1810
1811 /* Validate check bytes */
1812 if ((u16)~(*len ^ check)) {
1813 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1814 nextlen, *len, check);
1815 bus->rx_badhdr++;
1816 brcmf_sdbrcm_rxfail(bus, false, false);
1817 goto fail;
1818 }
1819
1820 /* Validate frame length */
1821 if (*len < SDPCM_HDRLEN) {
1822 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1823 *len);
1824 goto fail;
1825 }
1826
1827 /* Check for consistency with readahead info */
1828 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1829 if (len_consistent) {
1830 /* Mismatch, force retry w/normal
1831 header (may be >4K) */
1832 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1833 nextlen, *len, roundup(*len, 16),
1834 rxseq);
1835 brcmf_sdbrcm_rxfail(bus, true, true);
1836 goto fail;
1837 }
1838
1839 return 0;
1840
1841 fail:
1842 brcmf_sdbrcm_pktfree2(bus, pkt);
1843 return -EINVAL;
1844 }
1845
1846 /* Return true if there may be more frames to read */
1847 static uint
1848 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1849 {
1850 u16 len, check; /* Extracted hardware header fields */
1851 u8 chan, seq, doff; /* Extracted software header fields */
1852 u8 fcbits; /* Extracted fcbits from software header */
1853
1854 struct sk_buff *pkt; /* Packet for event or data frames */
1855 u16 pad; /* Number of pad bytes to read */
1856 u16 rdlen; /* Total number of bytes to read */
1857 u8 rxseq; /* Next sequence number to expect */
1858 uint rxleft = 0; /* Remaining number of frames allowed */
1859 int sdret; /* Return code from calls */
1860 u8 txmax; /* Maximum tx sequence offered */
1861 u8 *rxbuf;
1862 int ifidx = 0;
1863 uint rxcount = 0; /* Total frames read */
1864
1865 brcmf_dbg(TRACE, "Enter\n");
1866
1867 /* Not finished unless we encounter no more frames indication */
1868 *finished = false;
1869
1870 for (rxseq = bus->rx_seq, rxleft = maxframes;
1871 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1872 rxseq++, rxleft--) {
1873
1874 /* Handle glomming separately */
1875 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1876 u8 cnt;
1877 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1878 bus->glomd, skb_peek(&bus->glom));
1879 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1880 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1881 rxseq += cnt - 1;
1882 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1883 continue;
1884 }
1885
1886 /* Try doing single read if we can */
1887 if (bus->nextlen) {
1888 u16 nextlen = bus->nextlen;
1889 bus->nextlen = 0;
1890
1891 rdlen = len = nextlen << 4;
1892 brcmf_pad(bus, &pad, &rdlen);
1893
1894 /*
1895 * After the frame is received we have to
1896 * distinguish whether it is data
1897 * or non-data frame.
1898 */
1899 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1900 if (pkt == NULL) {
1901 /* Give up on data, request rtx of events */
1902 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1903 len, rdlen, rxseq);
1904 continue;
1905 }
1906
1907 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1908 &len) < 0)
1909 continue;
1910
1911 /* Extract software header fields */
1912 chan = SDPCM_PACKET_CHANNEL(
1913 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1914 seq = SDPCM_PACKET_SEQUENCE(
1915 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1916 doff = SDPCM_DOFFSET_VALUE(
1917 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1918 txmax = SDPCM_WINDOW_VALUE(
1919 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1920
1921 bus->nextlen =
1922 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1923 SDPCM_NEXTLEN_OFFSET];
1924 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1925 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1926 bus->nextlen, seq);
1927 bus->nextlen = 0;
1928 }
1929
1930 bus->drvr->rx_readahead_cnt++;
1931
1932 /* Handle Flow Control */
1933 fcbits = SDPCM_FCMASK_VALUE(
1934 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1935
1936 if (bus->flowcontrol != fcbits) {
1937 if (~bus->flowcontrol & fcbits)
1938 bus->fc_xoff++;
1939
1940 if (bus->flowcontrol & ~fcbits)
1941 bus->fc_xon++;
1942
1943 bus->fc_rcvd++;
1944 bus->flowcontrol = fcbits;
1945 }
1946
1947 /* Check and update sequence number */
1948 if (rxseq != seq) {
1949 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1950 seq, rxseq);
1951 bus->rx_badseq++;
1952 rxseq = seq;
1953 }
1954
1955 /* Check window for sanity */
1956 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1957 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1958 txmax, bus->tx_seq);
1959 txmax = bus->tx_seq + 2;
1960 }
1961 bus->tx_max = txmax;
1962
1963 #ifdef BCMDBG
1964 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1965 printk(KERN_DEBUG "Rx Data:\n");
1966 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1967 rxbuf, len);
1968 } else if (BRCMF_HDRS_ON()) {
1969 printk(KERN_DEBUG "RxHdr:\n");
1970 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1971 bus->rxhdr, SDPCM_HDRLEN);
1972 }
1973 #endif
1974
1975 if (chan == SDPCM_CONTROL_CHANNEL) {
1976 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1977 seq);
1978 /* Force retry w/normal header read */
1979 bus->nextlen = 0;
1980 brcmf_sdbrcm_rxfail(bus, false, true);
1981 brcmf_sdbrcm_pktfree2(bus, pkt);
1982 continue;
1983 }
1984
1985 /* Validate data offset */
1986 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1987 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1988 doff, len, SDPCM_HDRLEN);
1989 brcmf_sdbrcm_rxfail(bus, false, false);
1990 brcmf_sdbrcm_pktfree2(bus, pkt);
1991 continue;
1992 }
1993
1994 /* All done with this one -- now deliver the packet */
1995 goto deliver;
1996 }
1997
1998 /* Read frame header (hardware and software) */
1999 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2000 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
2001 BRCMF_FIRSTREAD, NULL);
2002 bus->f2rxhdrs++;
2003
2004 if (sdret < 0) {
2005 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
2006 bus->rx_hdrfail++;
2007 brcmf_sdbrcm_rxfail(bus, true, true);
2008 continue;
2009 }
2010 #ifdef BCMDBG
2011 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
2012 printk(KERN_DEBUG "RxHdr:\n");
2013 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2014 bus->rxhdr, SDPCM_HDRLEN);
2015 }
2016 #endif
2017
2018 /* Extract hardware header fields */
2019 len = get_unaligned_le16(bus->rxhdr);
2020 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
2021
2022 /* All zeros means no more frames */
2023 if (!(len | check)) {
2024 *finished = true;
2025 break;
2026 }
2027
2028 /* Validate check bytes */
2029 if ((u16) ~(len ^ check)) {
2030 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2031 len, check);
2032 bus->rx_badhdr++;
2033 brcmf_sdbrcm_rxfail(bus, false, false);
2034 continue;
2035 }
2036
2037 /* Validate frame length */
2038 if (len < SDPCM_HDRLEN) {
2039 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2040 continue;
2041 }
2042
2043 /* Extract software header fields */
2044 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2045 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2046 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2047 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2048
2049 /* Validate data offset */
2050 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2051 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2052 doff, len, SDPCM_HDRLEN, seq);
2053 bus->rx_badhdr++;
2054 brcmf_sdbrcm_rxfail(bus, false, false);
2055 continue;
2056 }
2057
2058 /* Save the readahead length if there is one */
2059 bus->nextlen =
2060 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2061 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2062 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2063 bus->nextlen, seq);
2064 bus->nextlen = 0;
2065 }
2066
2067 /* Handle Flow Control */
2068 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2069
2070 if (bus->flowcontrol != fcbits) {
2071 if (~bus->flowcontrol & fcbits)
2072 bus->fc_xoff++;
2073
2074 if (bus->flowcontrol & ~fcbits)
2075 bus->fc_xon++;
2076
2077 bus->fc_rcvd++;
2078 bus->flowcontrol = fcbits;
2079 }
2080
2081 /* Check and update sequence number */
2082 if (rxseq != seq) {
2083 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2084 bus->rx_badseq++;
2085 rxseq = seq;
2086 }
2087
2088 /* Check window for sanity */
2089 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2090 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2091 txmax, bus->tx_seq);
2092 txmax = bus->tx_seq + 2;
2093 }
2094 bus->tx_max = txmax;
2095
2096 /* Call a separate function for control frames */
2097 if (chan == SDPCM_CONTROL_CHANNEL) {
2098 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2099 continue;
2100 }
2101
2102 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2103 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2104 SDPCM_GLOM_CHANNEL */
2105
2106 /* Length to read */
2107 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2108
2109 /* May pad read to blocksize for efficiency */
2110 if (bus->roundup && bus->blocksize &&
2111 (rdlen > bus->blocksize)) {
2112 pad = bus->blocksize - (rdlen % bus->blocksize);
2113 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2114 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2115 rdlen += pad;
2116 } else if (rdlen % BRCMF_SDALIGN) {
2117 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2118 }
2119
2120 /* Satisfy length-alignment requirements */
2121 if (rdlen & (ALIGNMENT - 1))
2122 rdlen = roundup(rdlen, ALIGNMENT);
2123
2124 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2125 /* Too long -- skip this frame */
2126 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2127 len, rdlen);
2128 bus->drvr->rx_errors++;
2129 bus->rx_toolong++;
2130 brcmf_sdbrcm_rxfail(bus, false, false);
2131 continue;
2132 }
2133
2134 pkt = brcmu_pkt_buf_get_skb(rdlen +
2135 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2136 if (!pkt) {
2137 /* Give up on data, request rtx of events */
2138 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2139 rdlen, chan);
2140 bus->drvr->rx_dropped++;
2141 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2142 continue;
2143 }
2144
2145 /* Leave room for what we already read, and align remainder */
2146 skb_pull(pkt, BRCMF_FIRSTREAD);
2147 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2148
2149 /* Read the remaining frame data */
2150 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2151 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2152 rdlen, pkt);
2153 bus->f2rxdata++;
2154
2155 if (sdret < 0) {
2156 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2157 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2158 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2159 : "test")), sdret);
2160 brcmu_pkt_buf_free_skb(pkt);
2161 bus->drvr->rx_errors++;
2162 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2163 continue;
2164 }
2165
2166 /* Copy the already-read portion */
2167 skb_push(pkt, BRCMF_FIRSTREAD);
2168 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2169
2170 #ifdef BCMDBG
2171 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2172 printk(KERN_DEBUG "Rx Data:\n");
2173 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2174 pkt->data, len);
2175 }
2176 #endif
2177
2178 deliver:
2179 /* Save superframe descriptor and allocate packet frame */
2180 if (chan == SDPCM_GLOM_CHANNEL) {
2181 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2182 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2183 len);
2184 #ifdef BCMDBG
2185 if (BRCMF_GLOM_ON()) {
2186 printk(KERN_DEBUG "Glom Data:\n");
2187 print_hex_dump_bytes("",
2188 DUMP_PREFIX_OFFSET,
2189 pkt->data, len);
2190 }
2191 #endif
2192 __skb_trim(pkt, len);
2193 skb_pull(pkt, SDPCM_HDRLEN);
2194 bus->glomd = pkt;
2195 } else {
2196 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2197 "descriptor!\n", __func__);
2198 brcmf_sdbrcm_rxfail(bus, false, false);
2199 }
2200 continue;
2201 }
2202
2203 /* Fill in packet len and prio, deliver upward */
2204 __skb_trim(pkt, len);
2205 skb_pull(pkt, doff);
2206
2207 if (pkt->len == 0) {
2208 brcmu_pkt_buf_free_skb(pkt);
2209 continue;
2210 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2211 brcmf_dbg(ERROR, "rx protocol error\n");
2212 brcmu_pkt_buf_free_skb(pkt);
2213 bus->drvr->rx_errors++;
2214 continue;
2215 }
2216
2217 /* Unlock during rx call */
2218 up(&bus->sdsem);
2219 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2220 down(&bus->sdsem);
2221 }
2222 rxcount = maxframes - rxleft;
2223 #ifdef BCMDBG
2224 /* Message if we hit the limit */
2225 if (!rxleft)
2226 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2227 maxframes);
2228 else
2229 #endif /* BCMDBG */
2230 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2231 /* Back off rxseq if awaiting rtx, update rx_seq */
2232 if (bus->rxskip)
2233 rxseq--;
2234 bus->rx_seq = rxseq;
2235
2236 return rxcount;
2237 }
2238
2239 static int
2240 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2241 u8 *buf, uint nbytes, struct sk_buff *pkt)
2242 {
2243 return brcmf_sdcard_send_buf
2244 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2245 }
2246
2247 static void
2248 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2249 {
2250 up(&bus->sdsem);
2251 wait_event_interruptible_timeout(bus->ctrl_wait,
2252 (*lockvar == false), HZ * 2);
2253 down(&bus->sdsem);
2254 return;
2255 }
2256
2257 static void
2258 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2259 {
2260 if (waitqueue_active(&bus->ctrl_wait))
2261 wake_up_interruptible(&bus->ctrl_wait);
2262 return;
2263 }
2264
2265 /* Writes a HW/SW header into the packet and sends it. */
2266 /* Assumes: (a) header space already there, (b) caller holds lock */
2267 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2268 uint chan, bool free_pkt)
2269 {
2270 int ret;
2271 u8 *frame;
2272 u16 len, pad = 0;
2273 u32 swheader;
2274 struct sk_buff *new;
2275 int i;
2276
2277 brcmf_dbg(TRACE, "Enter\n");
2278
2279 frame = (u8 *) (pkt->data);
2280
2281 /* Add alignment padding, allocate new packet if needed */
2282 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2283 if (pad) {
2284 if (skb_headroom(pkt) < pad) {
2285 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2286 skb_headroom(pkt), pad);
2287 bus->drvr->tx_realloc++;
2288 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2289 if (!new) {
2290 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2291 pkt->len + BRCMF_SDALIGN);
2292 ret = -ENOMEM;
2293 goto done;
2294 }
2295
2296 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2297 memcpy(new->data, pkt->data, pkt->len);
2298 if (free_pkt)
2299 brcmu_pkt_buf_free_skb(pkt);
2300 /* free the pkt if canned one is not used */
2301 free_pkt = true;
2302 pkt = new;
2303 frame = (u8 *) (pkt->data);
2304 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2305 pad = 0;
2306 } else {
2307 skb_push(pkt, pad);
2308 frame = (u8 *) (pkt->data);
2309 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2310 memset(frame, 0, pad + SDPCM_HDRLEN);
2311 }
2312 }
2313 /* precondition: pad < BRCMF_SDALIGN */
2314
2315 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2316 len = (u16) (pkt->len);
2317 *(__le16 *) frame = cpu_to_le16(len);
2318 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2319
2320 /* Software tag: channel, sequence number, data offset */
2321 swheader =
2322 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2323 (((pad +
2324 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2325
2326 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2327 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2328
2329 #ifdef BCMDBG
2330 tx_packets[pkt->priority]++;
2331 if (BRCMF_BYTES_ON() &&
2332 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2333 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2334 printk(KERN_DEBUG "Tx Frame:\n");
2335 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2336 } else if (BRCMF_HDRS_ON()) {
2337 printk(KERN_DEBUG "TxHdr:\n");
2338 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2339 frame, min_t(u16, len, 16));
2340 }
2341 #endif
2342
2343 /* Raise len to next SDIO block to eliminate tail command */
2344 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2345 u16 pad = bus->blocksize - (len % bus->blocksize);
2346 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2347 len += pad;
2348 } else if (len % BRCMF_SDALIGN) {
2349 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2350 }
2351
2352 /* Some controllers have trouble with odd bytes -- round to even */
2353 if (len & (ALIGNMENT - 1))
2354 len = roundup(len, ALIGNMENT);
2355
2356 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2357 SDIO_FUNC_2, F2SYNC, frame,
2358 len, pkt);
2359 bus->f2txdata++;
2360
2361 if (ret < 0) {
2362 /* On failure, abort the command and terminate the frame */
2363 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2364 ret);
2365 bus->tx_sderrs++;
2366
2367 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2368 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2369 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2370 NULL);
2371 bus->f1regdata++;
2372
2373 for (i = 0; i < 3; i++) {
2374 u8 hi, lo;
2375 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2376 SDIO_FUNC_1,
2377 SBSDIO_FUNC1_WFRAMEBCHI,
2378 NULL);
2379 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2380 SDIO_FUNC_1,
2381 SBSDIO_FUNC1_WFRAMEBCLO,
2382 NULL);
2383 bus->f1regdata += 2;
2384 if ((hi == 0) && (lo == 0))
2385 break;
2386 }
2387
2388 }
2389 if (ret == 0)
2390 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2391
2392 done:
2393 /* restore pkt buffer pointer before calling tx complete routine */
2394 skb_pull(pkt, SDPCM_HDRLEN + pad);
2395 up(&bus->sdsem);
2396 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2397 down(&bus->sdsem);
2398
2399 if (free_pkt)
2400 brcmu_pkt_buf_free_skb(pkt);
2401
2402 return ret;
2403 }
2404
2405 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2406 {
2407 struct sk_buff *pkt;
2408 u32 intstatus = 0;
2409 uint retries = 0;
2410 int ret = 0, prec_out;
2411 uint cnt = 0;
2412 uint datalen;
2413 u8 tx_prec_map;
2414
2415 struct brcmf_pub *drvr = bus->drvr;
2416
2417 brcmf_dbg(TRACE, "Enter\n");
2418
2419 tx_prec_map = ~bus->flowcontrol;
2420
2421 /* Send frames until the limit or some other event */
2422 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2423 spin_lock_bh(&bus->txqlock);
2424 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2425 if (pkt == NULL) {
2426 spin_unlock_bh(&bus->txqlock);
2427 break;
2428 }
2429 spin_unlock_bh(&bus->txqlock);
2430 datalen = pkt->len - SDPCM_HDRLEN;
2431
2432 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2433 if (ret)
2434 bus->drvr->tx_errors++;
2435 else
2436 bus->drvr->dstats.tx_bytes += datalen;
2437
2438 /* In poll mode, need to check for other events */
2439 if (!bus->intr && cnt) {
2440 /* Check device status, signal pending interrupt */
2441 r_sdreg32(bus, &intstatus,
2442 offsetof(struct sdpcmd_regs, intstatus),
2443 &retries);
2444 bus->f2txdata++;
2445 if (brcmf_sdcard_regfail(bus->sdiodev))
2446 break;
2447 if (intstatus & bus->hostintmask)
2448 bus->ipend = true;
2449 }
2450 }
2451
2452 /* Deflow-control stack if needed */
2453 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2454 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2455 brcmf_txflowcontrol(drvr, 0, OFF);
2456
2457 return cnt;
2458 }
2459
2460 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2461 {
2462 u32 intstatus, newstatus = 0;
2463 uint retries = 0;
2464 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2465 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2466 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2467 bool rxdone = true; /* Flag for no more read data */
2468 bool resched = false; /* Flag indicating resched wanted */
2469
2470 brcmf_dbg(TRACE, "Enter\n");
2471
2472 /* Start with leftover status bits */
2473 intstatus = bus->intstatus;
2474
2475 down(&bus->sdsem);
2476
2477 /* If waiting for HTAVAIL, check status */
2478 if (bus->clkstate == CLK_PENDING) {
2479 int err;
2480 u8 clkctl, devctl = 0;
2481
2482 #ifdef BCMDBG
2483 /* Check for inconsistent device control */
2484 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2485 SBSDIO_DEVICE_CTL, &err);
2486 if (err) {
2487 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2488 bus->drvr->busstate = BRCMF_BUS_DOWN;
2489 }
2490 #endif /* BCMDBG */
2491
2492 /* Read CSR, if clock on switch to AVAIL, else ignore */
2493 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2494 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2495 if (err) {
2496 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2497 err);
2498 bus->drvr->busstate = BRCMF_BUS_DOWN;
2499 }
2500
2501 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2502 devctl, clkctl);
2503
2504 if (SBSDIO_HTAV(clkctl)) {
2505 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2506 SDIO_FUNC_1,
2507 SBSDIO_DEVICE_CTL, &err);
2508 if (err) {
2509 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2510 err);
2511 bus->drvr->busstate = BRCMF_BUS_DOWN;
2512 }
2513 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2514 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2515 SBSDIO_DEVICE_CTL, devctl, &err);
2516 if (err) {
2517 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2518 err);
2519 bus->drvr->busstate = BRCMF_BUS_DOWN;
2520 }
2521 bus->clkstate = CLK_AVAIL;
2522 } else {
2523 goto clkwait;
2524 }
2525 }
2526
2527 bus_wake(bus);
2528
2529 /* Make sure backplane clock is on */
2530 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2531 if (bus->clkstate == CLK_PENDING)
2532 goto clkwait;
2533
2534 /* Pending interrupt indicates new device status */
2535 if (bus->ipend) {
2536 bus->ipend = false;
2537 r_sdreg32(bus, &newstatus,
2538 offsetof(struct sdpcmd_regs, intstatus), &retries);
2539 bus->f1regdata++;
2540 if (brcmf_sdcard_regfail(bus->sdiodev))
2541 newstatus = 0;
2542 newstatus &= bus->hostintmask;
2543 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2544 if (newstatus) {
2545 w_sdreg32(bus, newstatus,
2546 offsetof(struct sdpcmd_regs, intstatus),
2547 &retries);
2548 bus->f1regdata++;
2549 }
2550 }
2551
2552 /* Merge new bits with previous */
2553 intstatus |= newstatus;
2554 bus->intstatus = 0;
2555
2556 /* Handle flow-control change: read new state in case our ack
2557 * crossed another change interrupt. If change still set, assume
2558 * FC ON for safety, let next loop through do the debounce.
2559 */
2560 if (intstatus & I_HMB_FC_CHANGE) {
2561 intstatus &= ~I_HMB_FC_CHANGE;
2562 w_sdreg32(bus, I_HMB_FC_CHANGE,
2563 offsetof(struct sdpcmd_regs, intstatus), &retries);
2564
2565 r_sdreg32(bus, &newstatus,
2566 offsetof(struct sdpcmd_regs, intstatus), &retries);
2567 bus->f1regdata += 2;
2568 bus->fcstate =
2569 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2570 intstatus |= (newstatus & bus->hostintmask);
2571 }
2572
2573 /* Handle host mailbox indication */
2574 if (intstatus & I_HMB_HOST_INT) {
2575 intstatus &= ~I_HMB_HOST_INT;
2576 intstatus |= brcmf_sdbrcm_hostmail(bus);
2577 }
2578
2579 /* Generally don't ask for these, can get CRC errors... */
2580 if (intstatus & I_WR_OOSYNC) {
2581 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2582 intstatus &= ~I_WR_OOSYNC;
2583 }
2584
2585 if (intstatus & I_RD_OOSYNC) {
2586 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2587 intstatus &= ~I_RD_OOSYNC;
2588 }
2589
2590 if (intstatus & I_SBINT) {
2591 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2592 intstatus &= ~I_SBINT;
2593 }
2594
2595 /* Would be active due to wake-wlan in gSPI */
2596 if (intstatus & I_CHIPACTIVE) {
2597 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2598 intstatus &= ~I_CHIPACTIVE;
2599 }
2600
2601 /* Ignore frame indications if rxskip is set */
2602 if (bus->rxskip)
2603 intstatus &= ~I_HMB_FRAME_IND;
2604
2605 /* On frame indication, read available frames */
2606 if (PKT_AVAILABLE()) {
2607 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2608 if (rxdone || bus->rxskip)
2609 intstatus &= ~I_HMB_FRAME_IND;
2610 rxlimit -= min(framecnt, rxlimit);
2611 }
2612
2613 /* Keep still-pending events for next scheduling */
2614 bus->intstatus = intstatus;
2615
2616 clkwait:
2617 if (data_ok(bus) && bus->ctrl_frame_stat &&
2618 (bus->clkstate == CLK_AVAIL)) {
2619 int ret, i;
2620
2621 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2622 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2623 (u32) bus->ctrl_frame_len, NULL);
2624
2625 if (ret < 0) {
2626 /* On failure, abort the command and
2627 terminate the frame */
2628 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2629 ret);
2630 bus->tx_sderrs++;
2631
2632 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2633
2634 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2635 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2636 NULL);
2637 bus->f1regdata++;
2638
2639 for (i = 0; i < 3; i++) {
2640 u8 hi, lo;
2641 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2642 SDIO_FUNC_1,
2643 SBSDIO_FUNC1_WFRAMEBCHI,
2644 NULL);
2645 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2646 SDIO_FUNC_1,
2647 SBSDIO_FUNC1_WFRAMEBCLO,
2648 NULL);
2649 bus->f1regdata += 2;
2650 if ((hi == 0) && (lo == 0))
2651 break;
2652 }
2653
2654 }
2655 if (ret == 0)
2656 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2657
2658 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2659 bus->ctrl_frame_stat = false;
2660 brcmf_sdbrcm_wait_event_wakeup(bus);
2661 }
2662 /* Send queued frames (limit 1 if rx may still be pending) */
2663 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2664 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2665 && data_ok(bus)) {
2666 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2667 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2668 txlimit -= framecnt;
2669 }
2670
2671 /* Resched if events or tx frames are pending,
2672 else await next interrupt */
2673 /* On failed register access, all bets are off:
2674 no resched or interrupts */
2675 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2676 brcmf_sdcard_regfail(bus->sdiodev)) {
2677 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2678 brcmf_sdcard_regfail(bus->sdiodev));
2679 bus->drvr->busstate = BRCMF_BUS_DOWN;
2680 bus->intstatus = 0;
2681 } else if (bus->clkstate == CLK_PENDING) {
2682 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2683 resched = true;
2684 } else if (bus->intstatus || bus->ipend ||
2685 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2686 && data_ok(bus)) || PKT_AVAILABLE()) {
2687 resched = true;
2688 }
2689
2690 bus->dpc_sched = resched;
2691
2692 /* If we're done for now, turn off clock request. */
2693 if ((bus->clkstate != CLK_PENDING)
2694 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2695 bus->activity = false;
2696 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2697 }
2698
2699 up(&bus->sdsem);
2700
2701 return resched;
2702 }
2703
2704 static int brcmf_sdbrcm_dpc_thread(void *data)
2705 {
2706 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2707
2708 allow_signal(SIGTERM);
2709 /* Run until signal received */
2710 while (1) {
2711 if (kthread_should_stop())
2712 break;
2713 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2714 /* Call bus dpc unless it indicated down
2715 (then clean stop) */
2716 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2717 if (brcmf_sdbrcm_dpc(bus))
2718 complete(&bus->dpc_wait);
2719 } else {
2720 /* after stopping the bus, exit thread */
2721 brcmf_sdbrcm_bus_stop(bus);
2722 bus->dpc_tsk = NULL;
2723 break;
2724 }
2725 } else
2726 break;
2727 }
2728 return 0;
2729 }
2730
2731 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2732 {
2733 int ret = -EBADE;
2734 uint datalen, prec;
2735
2736 brcmf_dbg(TRACE, "Enter\n");
2737
2738 datalen = pkt->len;
2739
2740 /* Add space for the header */
2741 skb_push(pkt, SDPCM_HDRLEN);
2742 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2743
2744 prec = prio2prec((pkt->priority & PRIOMASK));
2745
2746 /* Check for existing queue, current flow-control,
2747 pending event, or pending clock */
2748 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2749 bus->fcqueued++;
2750
2751 /* Priority based enq */
2752 spin_lock_bh(&bus->txqlock);
2753 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2754 skb_pull(pkt, SDPCM_HDRLEN);
2755 brcmf_txcomplete(bus->drvr, pkt, false);
2756 brcmu_pkt_buf_free_skb(pkt);
2757 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2758 ret = -ENOSR;
2759 } else {
2760 ret = 0;
2761 }
2762 spin_unlock_bh(&bus->txqlock);
2763
2764 if (pktq_len(&bus->txq) >= TXHI)
2765 brcmf_txflowcontrol(bus->drvr, 0, ON);
2766
2767 #ifdef BCMDBG
2768 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2769 qcount[prec] = pktq_plen(&bus->txq, prec);
2770 #endif
2771 /* Schedule DPC if needed to send queued packet(s) */
2772 if (!bus->dpc_sched) {
2773 bus->dpc_sched = true;
2774 if (bus->dpc_tsk)
2775 complete(&bus->dpc_wait);
2776 }
2777
2778 return ret;
2779 }
2780
2781 static int
2782 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2783 uint size)
2784 {
2785 int bcmerror = 0;
2786 u32 sdaddr;
2787 uint dsize;
2788
2789 /* Determine initial transfer parameters */
2790 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2791 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2792 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2793 else
2794 dsize = size;
2795
2796 /* Set the backplane window to include the start address */
2797 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2798 if (bcmerror) {
2799 brcmf_dbg(ERROR, "window change failed\n");
2800 goto xfer_done;
2801 }
2802
2803 /* Do the transfer(s) */
2804 while (size) {
2805 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2806 write ? "write" : "read", dsize,
2807 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2808 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2809 sdaddr, data, dsize);
2810 if (bcmerror) {
2811 brcmf_dbg(ERROR, "membytes transfer failed\n");
2812 break;
2813 }
2814
2815 /* Adjust for next transfer (if any) */
2816 size -= dsize;
2817 if (size) {
2818 data += dsize;
2819 address += dsize;
2820 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2821 address);
2822 if (bcmerror) {
2823 brcmf_dbg(ERROR, "window change failed\n");
2824 break;
2825 }
2826 sdaddr = 0;
2827 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2828 }
2829 }
2830
2831 xfer_done:
2832 /* Return the window to backplane enumeration space for core access */
2833 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2834 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2835 bus->sdiodev->sbwad);
2836
2837 return bcmerror;
2838 }
2839
2840 #ifdef BCMDBG
2841 #define CONSOLE_LINE_MAX 192
2842
2843 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2844 {
2845 struct brcmf_console *c = &bus->console;
2846 u8 line[CONSOLE_LINE_MAX], ch;
2847 u32 n, idx, addr;
2848 int rv;
2849
2850 /* Don't do anything until FWREADY updates console address */
2851 if (bus->console_addr == 0)
2852 return 0;
2853
2854 /* Read console log struct */
2855 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2856 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2857 sizeof(c->log_le));
2858 if (rv < 0)
2859 return rv;
2860
2861 /* Allocate console buffer (one time only) */
2862 if (c->buf == NULL) {
2863 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2864 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2865 if (c->buf == NULL)
2866 return -ENOMEM;
2867 }
2868
2869 idx = le32_to_cpu(c->log_le.idx);
2870
2871 /* Protect against corrupt value */
2872 if (idx > c->bufsize)
2873 return -EBADE;
2874
2875 /* Skip reading the console buffer if the index pointer
2876 has not moved */
2877 if (idx == c->last)
2878 return 0;
2879
2880 /* Read the console buffer */
2881 addr = le32_to_cpu(c->log_le.buf);
2882 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2883 if (rv < 0)
2884 return rv;
2885
2886 while (c->last != idx) {
2887 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2888 if (c->last == idx) {
2889 /* This would output a partial line.
2890 * Instead, back up
2891 * the buffer pointer and output this
2892 * line next time around.
2893 */
2894 if (c->last >= n)
2895 c->last -= n;
2896 else
2897 c->last = c->bufsize - n;
2898 goto break2;
2899 }
2900 ch = c->buf[c->last];
2901 c->last = (c->last + 1) % c->bufsize;
2902 if (ch == '\n')
2903 break;
2904 line[n] = ch;
2905 }
2906
2907 if (n > 0) {
2908 if (line[n - 1] == '\r')
2909 n--;
2910 line[n] = 0;
2911 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2912 }
2913 }
2914 break2:
2915
2916 return 0;
2917 }
2918 #endif /* BCMDBG */
2919
2920 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2921 {
2922 int i;
2923 int ret;
2924
2925 bus->ctrl_frame_stat = false;
2926 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2927 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2928
2929 if (ret < 0) {
2930 /* On failure, abort the command and terminate the frame */
2931 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2932 ret);
2933 bus->tx_sderrs++;
2934
2935 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2936
2937 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2938 SBSDIO_FUNC1_FRAMECTRL,
2939 SFC_WF_TERM, NULL);
2940 bus->f1regdata++;
2941
2942 for (i = 0; i < 3; i++) {
2943 u8 hi, lo;
2944 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2945 SBSDIO_FUNC1_WFRAMEBCHI,
2946 NULL);
2947 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2948 SBSDIO_FUNC1_WFRAMEBCLO,
2949 NULL);
2950 bus->f1regdata += 2;
2951 if (hi == 0 && lo == 0)
2952 break;
2953 }
2954 return ret;
2955 }
2956
2957 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2958
2959 return ret;
2960 }
2961
2962 int
2963 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2964 {
2965 u8 *frame;
2966 u16 len;
2967 u32 swheader;
2968 uint retries = 0;
2969 u8 doff = 0;
2970 int ret = -1;
2971
2972 brcmf_dbg(TRACE, "Enter\n");
2973
2974 /* Back the pointer to make a room for bus header */
2975 frame = msg - SDPCM_HDRLEN;
2976 len = (msglen += SDPCM_HDRLEN);
2977
2978 /* Add alignment padding (optional for ctl frames) */
2979 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2980 if (doff) {
2981 frame -= doff;
2982 len += doff;
2983 msglen += doff;
2984 memset(frame, 0, doff + SDPCM_HDRLEN);
2985 }
2986 /* precondition: doff < BRCMF_SDALIGN */
2987 doff += SDPCM_HDRLEN;
2988
2989 /* Round send length to next SDIO block */
2990 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2991 u16 pad = bus->blocksize - (len % bus->blocksize);
2992 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2993 len += pad;
2994 } else if (len % BRCMF_SDALIGN) {
2995 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2996 }
2997
2998 /* Satisfy length-alignment requirements */
2999 if (len & (ALIGNMENT - 1))
3000 len = roundup(len, ALIGNMENT);
3001
3002 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
3003
3004 /* Need to lock here to protect txseq and SDIO tx calls */
3005 down(&bus->sdsem);
3006
3007 bus_wake(bus);
3008
3009 /* Make sure backplane clock is on */
3010 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3011
3012 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
3013 *(__le16 *) frame = cpu_to_le16((u16) msglen);
3014 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
3015
3016 /* Software tag: channel, sequence number, data offset */
3017 swheader =
3018 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
3019 SDPCM_CHANNEL_MASK)
3020 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
3021 SDPCM_DOFFSET_MASK);
3022 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3023 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3024
3025 if (!data_ok(bus)) {
3026 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3027 bus->tx_max, bus->tx_seq);
3028 bus->ctrl_frame_stat = true;
3029 /* Send from dpc */
3030 bus->ctrl_frame_buf = frame;
3031 bus->ctrl_frame_len = len;
3032
3033 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3034
3035 if (bus->ctrl_frame_stat == false) {
3036 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3037 ret = 0;
3038 } else {
3039 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3040 ret = -1;
3041 }
3042 }
3043
3044 if (ret == -1) {
3045 #ifdef BCMDBG
3046 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3047 printk(KERN_DEBUG "Tx Frame:\n");
3048 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3049 frame, len);
3050 } else if (BRCMF_HDRS_ON()) {
3051 printk(KERN_DEBUG "TxHdr:\n");
3052 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3053 frame, min_t(u16, len, 16));
3054 }
3055 #endif
3056
3057 do {
3058 ret = brcmf_tx_frame(bus, frame, len);
3059 } while (ret < 0 && retries++ < TXRETRIES);
3060 }
3061
3062 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3063 bus->activity = false;
3064 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3065 }
3066
3067 up(&bus->sdsem);
3068
3069 if (ret)
3070 bus->drvr->tx_ctlerrs++;
3071 else
3072 bus->drvr->tx_ctlpkts++;
3073
3074 return ret ? -EIO : 0;
3075 }
3076
3077 int
3078 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3079 {
3080 int timeleft;
3081 uint rxlen = 0;
3082 bool pending;
3083
3084 brcmf_dbg(TRACE, "Enter\n");
3085
3086 /* Wait until control frame is available */
3087 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3088
3089 down(&bus->sdsem);
3090 rxlen = bus->rxlen;
3091 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3092 bus->rxlen = 0;
3093 up(&bus->sdsem);
3094
3095 if (rxlen) {
3096 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3097 rxlen, msglen);
3098 } else if (timeleft == 0) {
3099 brcmf_dbg(ERROR, "resumed on timeout\n");
3100 } else if (pending == true) {
3101 brcmf_dbg(CTL, "cancelled\n");
3102 return -ERESTARTSYS;
3103 } else {
3104 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3105 }
3106
3107 if (rxlen)
3108 bus->drvr->rx_ctlpkts++;
3109 else
3110 bus->drvr->rx_ctlerrs++;
3111
3112 return rxlen ? (int)rxlen : -ETIMEDOUT;
3113 }
3114
3115 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3116 {
3117 int bcmerror = 0;
3118
3119 brcmf_dbg(TRACE, "Enter\n");
3120
3121 /* Basic sanity checks */
3122 if (bus->drvr->up) {
3123 bcmerror = -EISCONN;
3124 goto err;
3125 }
3126 if (!len) {
3127 bcmerror = -EOVERFLOW;
3128 goto err;
3129 }
3130
3131 /* Free the old ones and replace with passed variables */
3132 kfree(bus->vars);
3133
3134 bus->vars = kmalloc(len, GFP_ATOMIC);
3135 bus->varsz = bus->vars ? len : 0;
3136 if (bus->vars == NULL) {
3137 bcmerror = -ENOMEM;
3138 goto err;
3139 }
3140
3141 /* Copy the passed variables, which should include the
3142 terminating double-null */
3143 memcpy(bus->vars, arg, bus->varsz);
3144 err:
3145 return bcmerror;
3146 }
3147
3148 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3149 {
3150 int bcmerror = 0;
3151 u32 varsize;
3152 u32 varaddr;
3153 u8 *vbuffer;
3154 u32 varsizew;
3155 __le32 varsizew_le;
3156 #ifdef BCMDBG
3157 char *nvram_ularray;
3158 #endif /* BCMDBG */
3159
3160 /* Even if there are no vars are to be written, we still
3161 need to set the ramsize. */
3162 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3163 varaddr = (bus->ramsize - 4) - varsize;
3164
3165 if (bus->vars) {
3166 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3167 if (!vbuffer)
3168 return -ENOMEM;
3169
3170 memcpy(vbuffer, bus->vars, bus->varsz);
3171
3172 /* Write the vars list */
3173 bcmerror =
3174 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3175 #ifdef BCMDBG
3176 /* Verify NVRAM bytes */
3177 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3178 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3179 if (!nvram_ularray)
3180 return -ENOMEM;
3181
3182 /* Upload image to verify downloaded contents. */
3183 memset(nvram_ularray, 0xaa, varsize);
3184
3185 /* Read the vars list to temp buffer for comparison */
3186 bcmerror =
3187 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3188 varsize);
3189 if (bcmerror) {
3190 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3191 bcmerror, varsize, varaddr);
3192 }
3193 /* Compare the org NVRAM with the one read from RAM */
3194 if (memcmp(vbuffer, nvram_ularray, varsize))
3195 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3196 else
3197 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3198
3199 kfree(nvram_ularray);
3200 #endif /* BCMDBG */
3201
3202 kfree(vbuffer);
3203 }
3204
3205 /* adjust to the user specified RAM */
3206 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3207 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3208 varaddr, varsize);
3209 varsize = ((bus->ramsize - 4) - varaddr);
3210
3211 /*
3212 * Determine the length token:
3213 * Varsize, converted to words, in lower 16-bits, checksum
3214 * in upper 16-bits.
3215 */
3216 if (bcmerror) {
3217 varsizew = 0;
3218 varsizew_le = cpu_to_le32(0);
3219 } else {
3220 varsizew = varsize / 4;
3221 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3222 varsizew_le = cpu_to_le32(varsizew);
3223 }
3224
3225 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3226 varsize, varsizew);
3227
3228 /* Write the length token to the last word */
3229 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3230 (u8 *)&varsizew_le, 4);
3231
3232 return bcmerror;
3233 }
3234
3235 static void
3236 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3237 {
3238 u32 regdata;
3239
3240 regdata = brcmf_sdcard_reg_read(sdiodev,
3241 CORE_SB(corebase, sbtmstatelow), 4);
3242 if (regdata & SBTML_RESET)
3243 return;
3244
3245 regdata = brcmf_sdcard_reg_read(sdiodev,
3246 CORE_SB(corebase, sbtmstatelow), 4);
3247 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3248 /*
3249 * set target reject and spin until busy is clear
3250 * (preserve core-specific bits)
3251 */
3252 regdata = brcmf_sdcard_reg_read(sdiodev,
3253 CORE_SB(corebase, sbtmstatelow), 4);
3254 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3255 4, regdata | SBTML_REJ);
3256
3257 regdata = brcmf_sdcard_reg_read(sdiodev,
3258 CORE_SB(corebase, sbtmstatelow), 4);
3259 udelay(1);
3260 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3261 CORE_SB(corebase, sbtmstatehigh), 4) &
3262 SBTMH_BUSY), 100000);
3263
3264 regdata = brcmf_sdcard_reg_read(sdiodev,
3265 CORE_SB(corebase, sbtmstatehigh), 4);
3266 if (regdata & SBTMH_BUSY)
3267 brcmf_dbg(ERROR, "ARM core still busy\n");
3268
3269 regdata = brcmf_sdcard_reg_read(sdiodev,
3270 CORE_SB(corebase, sbidlow), 4);
3271 if (regdata & SBIDL_INIT) {
3272 regdata = brcmf_sdcard_reg_read(sdiodev,
3273 CORE_SB(corebase, sbimstate), 4) |
3274 SBIM_RJ;
3275 brcmf_sdcard_reg_write(sdiodev,
3276 CORE_SB(corebase, sbimstate), 4,
3277 regdata);
3278 regdata = brcmf_sdcard_reg_read(sdiodev,
3279 CORE_SB(corebase, sbimstate), 4);
3280 udelay(1);
3281 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3282 CORE_SB(corebase, sbimstate), 4) &
3283 SBIM_BY), 100000);
3284 }
3285
3286 /* set reset and reject while enabling the clocks */
3287 brcmf_sdcard_reg_write(sdiodev,
3288 CORE_SB(corebase, sbtmstatelow), 4,
3289 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3290 SBTML_REJ | SBTML_RESET));
3291 regdata = brcmf_sdcard_reg_read(sdiodev,
3292 CORE_SB(corebase, sbtmstatelow), 4);
3293 udelay(10);
3294
3295 /* clear the initiator reject bit */
3296 regdata = brcmf_sdcard_reg_read(sdiodev,
3297 CORE_SB(corebase, sbidlow), 4);
3298 if (regdata & SBIDL_INIT) {
3299 regdata = brcmf_sdcard_reg_read(sdiodev,
3300 CORE_SB(corebase, sbimstate), 4) &
3301 ~SBIM_RJ;
3302 brcmf_sdcard_reg_write(sdiodev,
3303 CORE_SB(corebase, sbimstate), 4,
3304 regdata);
3305 }
3306 }
3307
3308 /* leave reset and reject asserted */
3309 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3310 (SBTML_REJ | SBTML_RESET));
3311 udelay(1);
3312 }
3313
3314 static void
3315 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3316 {
3317 u32 regdata;
3318
3319 /*
3320 * Must do the disable sequence first to work for
3321 * arbitrary current core state.
3322 */
3323 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3324
3325 /*
3326 * Now do the initialization sequence.
3327 * set reset while enabling the clock and
3328 * forcing them on throughout the core
3329 */
3330 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3331 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3332 SBTML_RESET);
3333 udelay(1);
3334
3335 regdata = brcmf_sdcard_reg_read(sdiodev,
3336 CORE_SB(corebase, sbtmstatehigh), 4);
3337 if (regdata & SBTMH_SERR)
3338 brcmf_sdcard_reg_write(sdiodev,
3339 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3340
3341 regdata = brcmf_sdcard_reg_read(sdiodev,
3342 CORE_SB(corebase, sbimstate), 4);
3343 if (regdata & (SBIM_IBE | SBIM_TO))
3344 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3345 regdata & ~(SBIM_IBE | SBIM_TO));
3346
3347 /* clear reset and allow it to propagate throughout the core */
3348 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3349 (SICF_FGC << SBTML_SICF_SHIFT) |
3350 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3351 udelay(1);
3352
3353 /* leave clock enabled */
3354 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3355 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3356 udelay(1);
3357 }
3358
3359 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3360 {
3361 uint retries;
3362 u32 regdata;
3363 int bcmerror = 0;
3364
3365 /* To enter download state, disable ARM and reset SOCRAM.
3366 * To exit download state, simply reset ARM (default is RAM boot).
3367 */
3368 if (enter) {
3369 bus->alp_only = true;
3370
3371 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3372 bus->ci->armcorebase);
3373
3374 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3375
3376 /* Clear the top bit of memory */
3377 if (bus->ramsize) {
3378 u32 zeros = 0;
3379 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3380 (u8 *)&zeros, 4);
3381 }
3382 } else {
3383 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3384 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3385 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3386 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3387 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3388 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3389 bcmerror = -EBADE;
3390 goto fail;
3391 }
3392
3393 bcmerror = brcmf_sdbrcm_write_vars(bus);
3394 if (bcmerror) {
3395 brcmf_dbg(ERROR, "no vars written to RAM\n");
3396 bcmerror = 0;
3397 }
3398
3399 w_sdreg32(bus, 0xFFFFFFFF,
3400 offsetof(struct sdpcmd_regs, intstatus), &retries);
3401
3402 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3403
3404 /* Allow HT Clock now that the ARM is running. */
3405 bus->alp_only = false;
3406
3407 bus->drvr->busstate = BRCMF_BUS_LOAD;
3408 }
3409 fail:
3410 return bcmerror;
3411 }
3412
3413 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3414 {
3415 if (bus->firmware->size < bus->fw_ptr + len)
3416 len = bus->firmware->size - bus->fw_ptr;
3417
3418 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3419 bus->fw_ptr += len;
3420 return len;
3421 }
3422
3423 MODULE_FIRMWARE(BCM4329_FW_NAME);
3424 MODULE_FIRMWARE(BCM4329_NV_NAME);
3425
3426 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3427 {
3428 int offset = 0;
3429 uint len;
3430 u8 *memblock = NULL, *memptr;
3431 int ret;
3432
3433 brcmf_dbg(INFO, "Enter\n");
3434
3435 bus->fw_name = BCM4329_FW_NAME;
3436 ret = request_firmware(&bus->firmware, bus->fw_name,
3437 &bus->sdiodev->func[2]->dev);
3438 if (ret) {
3439 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3440 return ret;
3441 }
3442 bus->fw_ptr = 0;
3443
3444 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3445 if (memblock == NULL) {
3446 ret = -ENOMEM;
3447 goto err;
3448 }
3449 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3450 memptr += (BRCMF_SDALIGN -
3451 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3452
3453 /* Download image */
3454 while ((len =
3455 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3456 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3457 if (ret) {
3458 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3459 ret, MEMBLOCK, offset);
3460 goto err;
3461 }
3462
3463 offset += MEMBLOCK;
3464 }
3465
3466 err:
3467 kfree(memblock);
3468
3469 release_firmware(bus->firmware);
3470 bus->fw_ptr = 0;
3471
3472 return ret;
3473 }
3474
3475 /*
3476 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3477 * and ending in a NUL.
3478 * Removes carriage returns, empty lines, comment lines, and converts
3479 * newlines to NULs.
3480 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3481 * by two NULs.
3482 */
3483
3484 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3485 {
3486 char *dp;
3487 bool findNewline;
3488 int column;
3489 uint buf_len, n;
3490
3491 dp = varbuf;
3492
3493 findNewline = false;
3494 column = 0;
3495
3496 for (n = 0; n < len; n++) {
3497 if (varbuf[n] == 0)
3498 break;
3499 if (varbuf[n] == '\r')
3500 continue;
3501 if (findNewline && varbuf[n] != '\n')
3502 continue;
3503 findNewline = false;
3504 if (varbuf[n] == '#') {
3505 findNewline = true;
3506 continue;
3507 }
3508 if (varbuf[n] == '\n') {
3509 if (column == 0)
3510 continue;
3511 *dp++ = 0;
3512 column = 0;
3513 continue;
3514 }
3515 *dp++ = varbuf[n];
3516 column++;
3517 }
3518 buf_len = dp - varbuf;
3519
3520 while (dp < varbuf + n)
3521 *dp++ = 0;
3522
3523 return buf_len;
3524 }
3525
3526 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3527 {
3528 uint len;
3529 char *memblock = NULL;
3530 char *bufp;
3531 int ret;
3532
3533 bus->nv_name = BCM4329_NV_NAME;
3534 ret = request_firmware(&bus->firmware, bus->nv_name,
3535 &bus->sdiodev->func[2]->dev);
3536 if (ret) {
3537 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3538 return ret;
3539 }
3540 bus->fw_ptr = 0;
3541
3542 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3543 if (memblock == NULL) {
3544 ret = -ENOMEM;
3545 goto err;
3546 }
3547
3548 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3549
3550 if (len > 0 && len < MEMBLOCK) {
3551 bufp = (char *)memblock;
3552 bufp[len] = 0;
3553 len = brcmf_process_nvram_vars(bufp, len);
3554 bufp += len;
3555 *bufp++ = 0;
3556 if (len)
3557 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3558 if (ret)
3559 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3560 } else {
3561 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3562 ret = -EIO;
3563 }
3564
3565 err:
3566 kfree(memblock);
3567
3568 release_firmware(bus->firmware);
3569 bus->fw_ptr = 0;
3570
3571 return ret;
3572 }
3573
3574 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3575 {
3576 int bcmerror = -1;
3577
3578 /* Keep arm in reset */
3579 if (brcmf_sdbrcm_download_state(bus, true)) {
3580 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3581 goto err;
3582 }
3583
3584 /* External image takes precedence if specified */
3585 if (brcmf_sdbrcm_download_code_file(bus)) {
3586 brcmf_dbg(ERROR, "dongle image file download failed\n");
3587 goto err;
3588 }
3589
3590 /* External nvram takes precedence if specified */
3591 if (brcmf_sdbrcm_download_nvram(bus))
3592 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3593
3594 /* Take arm out of reset */
3595 if (brcmf_sdbrcm_download_state(bus, false)) {
3596 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3597 goto err;
3598 }
3599
3600 bcmerror = 0;
3601
3602 err:
3603 return bcmerror;
3604 }
3605
3606 static bool
3607 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3608 {
3609 bool ret;
3610
3611 /* Download the firmware */
3612 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3613
3614 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3615
3616 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3617
3618 return ret;
3619 }
3620
3621 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3622 {
3623 u32 local_hostintmask;
3624 u8 saveclk;
3625 uint retries;
3626 int err;
3627 struct sk_buff *cur;
3628 struct sk_buff *next;
3629
3630 brcmf_dbg(TRACE, "Enter\n");
3631
3632 if (bus->watchdog_tsk) {
3633 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3634 kthread_stop(bus->watchdog_tsk);
3635 bus->watchdog_tsk = NULL;
3636 }
3637
3638 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3639 send_sig(SIGTERM, bus->dpc_tsk, 1);
3640 kthread_stop(bus->dpc_tsk);
3641 bus->dpc_tsk = NULL;
3642 }
3643
3644 down(&bus->sdsem);
3645
3646 bus_wake(bus);
3647
3648 /* Enable clock for device interrupts */
3649 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3650
3651 /* Disable and clear interrupts at the chip level also */
3652 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3653 local_hostintmask = bus->hostintmask;
3654 bus->hostintmask = 0;
3655
3656 /* Change our idea of bus state */
3657 bus->drvr->busstate = BRCMF_BUS_DOWN;
3658
3659 /* Force clocks on backplane to be sure F2 interrupt propagates */
3660 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3661 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3662 if (!err) {
3663 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3664 SBSDIO_FUNC1_CHIPCLKCSR,
3665 (saveclk | SBSDIO_FORCE_HT), &err);
3666 }
3667 if (err)
3668 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3669
3670 /* Turn off the bus (F2), free any pending packets */
3671 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3672 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3673 SDIO_FUNC_ENABLE_1, NULL);
3674
3675 /* Clear any pending interrupts now that F2 is disabled */
3676 w_sdreg32(bus, local_hostintmask,
3677 offsetof(struct sdpcmd_regs, intstatus), &retries);
3678
3679 /* Turn off the backplane clock (only) */
3680 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3681
3682 /* Clear the data packet queues */
3683 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3684
3685 /* Clear any held glomming stuff */
3686 if (bus->glomd)
3687 brcmu_pkt_buf_free_skb(bus->glomd);
3688 if (!skb_queue_empty(&bus->glom))
3689 skb_queue_walk_safe(&bus->glom, cur, next) {
3690 skb_unlink(cur, &bus->glom);
3691 brcmu_pkt_buf_free_skb(cur);
3692 }
3693
3694 /* Clear rx control and wake any waiters */
3695 bus->rxlen = 0;
3696 brcmf_sdbrcm_dcmd_resp_wake(bus);
3697
3698 /* Reset some F2 state stuff */
3699 bus->rxskip = false;
3700 bus->tx_seq = bus->rx_seq = 0;
3701
3702 up(&bus->sdsem);
3703 }
3704
3705 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3706 {
3707 struct brcmf_bus *bus = drvr->bus;
3708 unsigned long timeout;
3709 uint retries = 0;
3710 u8 ready, enable;
3711 int err, ret = 0;
3712 u8 saveclk;
3713
3714 brcmf_dbg(TRACE, "Enter\n");
3715
3716 /* try to download image and nvram to the dongle */
3717 if (drvr->busstate == BRCMF_BUS_DOWN) {
3718 if (!(brcmf_sdbrcm_download_firmware(bus)))
3719 return -1;
3720 }
3721
3722 if (!bus->drvr)
3723 return 0;
3724
3725 /* Start the watchdog timer */
3726 bus->drvr->tickcnt = 0;
3727 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3728
3729 down(&bus->sdsem);
3730
3731 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3732 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3733 if (bus->clkstate != CLK_AVAIL)
3734 goto exit;
3735
3736 /* Force clocks on backplane to be sure F2 interrupt propagates */
3737 saveclk =
3738 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3739 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3740 if (!err) {
3741 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3742 SBSDIO_FUNC1_CHIPCLKCSR,
3743 (saveclk | SBSDIO_FORCE_HT), &err);
3744 }
3745 if (err) {
3746 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3747 goto exit;
3748 }
3749
3750 /* Enable function 2 (frame transfers) */
3751 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3752 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3753 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3754
3755 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3756 enable, NULL);
3757
3758 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3759 ready = 0;
3760 while (enable != ready) {
3761 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3762 SDIO_CCCR_IORx, NULL);
3763 if (time_after(jiffies, timeout))
3764 break;
3765 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3766 /* prevent busy waiting if it takes too long */
3767 msleep_interruptible(20);
3768 }
3769
3770 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3771
3772 /* If F2 successfully enabled, set core and enable interrupts */
3773 if (ready == enable) {
3774 /* Set up the interrupt mask and enable interrupts */
3775 bus->hostintmask = HOSTINTMASK;
3776 w_sdreg32(bus, bus->hostintmask,
3777 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3778
3779 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3780 SBSDIO_WATERMARK, 8, &err);
3781
3782 /* Set bus state according to enable result */
3783 drvr->busstate = BRCMF_BUS_DATA;
3784 }
3785
3786 else {
3787 /* Disable F2 again */
3788 enable = SDIO_FUNC_ENABLE_1;
3789 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3790 SDIO_CCCR_IOEx, enable, NULL);
3791 }
3792
3793 /* Restore previous clock setting */
3794 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3795 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3796
3797 /* If we didn't come up, turn off backplane clock */
3798 if (drvr->busstate != BRCMF_BUS_DATA)
3799 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3800
3801 exit:
3802 up(&bus->sdsem);
3803
3804 return ret;
3805 }
3806
3807 void brcmf_sdbrcm_isr(void *arg)
3808 {
3809 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3810
3811 brcmf_dbg(TRACE, "Enter\n");
3812
3813 if (!bus) {
3814 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3815 return;
3816 }
3817
3818 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3819 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3820 return;
3821 }
3822 /* Count the interrupt call */
3823 bus->intrcount++;
3824 bus->ipend = true;
3825
3826 /* Shouldn't get this interrupt if we're sleeping? */
3827 if (bus->sleeping) {
3828 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3829 return;
3830 }
3831
3832 /* Disable additional interrupts (is this needed now)? */
3833 if (!bus->intr)
3834 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3835
3836 bus->dpc_sched = true;
3837 if (bus->dpc_tsk)
3838 complete(&bus->dpc_wait);
3839 }
3840
3841 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3842 {
3843 struct brcmf_bus *bus;
3844
3845 brcmf_dbg(TIMER, "Enter\n");
3846
3847 bus = drvr->bus;
3848
3849 /* Ignore the timer if simulating bus down */
3850 if (bus->sleeping)
3851 return false;
3852
3853 down(&bus->sdsem);
3854
3855 /* Poll period: check device if appropriate. */
3856 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3857 u32 intstatus = 0;
3858
3859 /* Reset poll tick */
3860 bus->polltick = 0;
3861
3862 /* Check device if no interrupts */
3863 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3864
3865 if (!bus->dpc_sched) {
3866 u8 devpend;
3867 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3868 SDIO_FUNC_0, SDIO_CCCR_INTx,
3869 NULL);
3870 intstatus =
3871 devpend & (INTR_STATUS_FUNC1 |
3872 INTR_STATUS_FUNC2);
3873 }
3874
3875 /* If there is something, make like the ISR and
3876 schedule the DPC */
3877 if (intstatus) {
3878 bus->pollcnt++;
3879 bus->ipend = true;
3880
3881 bus->dpc_sched = true;
3882 if (bus->dpc_tsk)
3883 complete(&bus->dpc_wait);
3884 }
3885 }
3886
3887 /* Update interrupt tracking */
3888 bus->lastintrs = bus->intrcount;
3889 }
3890 #ifdef BCMDBG
3891 /* Poll for console output periodically */
3892 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3893 bus->console.count += BRCMF_WD_POLL_MS;
3894 if (bus->console.count >= bus->console_interval) {
3895 bus->console.count -= bus->console_interval;
3896 /* Make sure backplane clock is on */
3897 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3898 if (brcmf_sdbrcm_readconsole(bus) < 0)
3899 /* stop on error */
3900 bus->console_interval = 0;
3901 }
3902 }
3903 #endif /* BCMDBG */
3904
3905 /* On idle timeout clear activity flag and/or turn off clock */
3906 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3907 if (++bus->idlecount >= bus->idletime) {
3908 bus->idlecount = 0;
3909 if (bus->activity) {
3910 bus->activity = false;
3911 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3912 } else {
3913 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3914 }
3915 }
3916 }
3917
3918 up(&bus->sdsem);
3919
3920 return bus->ipend;
3921 }
3922
3923 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3924 {
3925 if (chipid == BCM4329_CHIP_ID)
3926 return true;
3927 return false;
3928 }
3929
3930 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3931 {
3932 brcmf_dbg(TRACE, "Enter\n");
3933
3934 kfree(bus->rxbuf);
3935 bus->rxctl = bus->rxbuf = NULL;
3936 bus->rxlen = 0;
3937
3938 kfree(bus->databuf);
3939 bus->databuf = NULL;
3940 }
3941
3942 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3943 {
3944 brcmf_dbg(TRACE, "Enter\n");
3945
3946 if (bus->drvr->maxctl) {
3947 bus->rxblen =
3948 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3949 ALIGNMENT) + BRCMF_SDALIGN;
3950 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3951 if (!(bus->rxbuf))
3952 goto fail;
3953 }
3954
3955 /* Allocate buffer to receive glomed packet */
3956 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3957 if (!(bus->databuf)) {
3958 /* release rxbuf which was already located as above */
3959 if (!bus->rxblen)
3960 kfree(bus->rxbuf);
3961 goto fail;
3962 }
3963
3964 /* Align the buffer */
3965 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3966 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3967 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3968 else
3969 bus->dataptr = bus->databuf;
3970
3971 return true;
3972
3973 fail:
3974 return false;
3975 }
3976
3977 /* SDIO Pad drive strength to select value mappings */
3978 struct sdiod_drive_str {
3979 u8 strength; /* Pad Drive Strength in mA */
3980 u8 sel; /* Chip-specific select value */
3981 };
3982
3983 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3984 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3985 {
3986 4, 0x2}, {
3987 2, 0x3}, {
3988 1, 0x0}, {
3989 0, 0x0}
3990 };
3991
3992 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3993 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3994 {
3995 12, 0x7}, {
3996 10, 0x6}, {
3997 8, 0x5}, {
3998 6, 0x4}, {
3999 4, 0x2}, {
4000 2, 0x1}, {
4001 0, 0x0}
4002 };
4003
4004 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
4005 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
4006 {
4007 32, 0x7}, {
4008 26, 0x6}, {
4009 22, 0x5}, {
4010 16, 0x4}, {
4011 12, 0x3}, {
4012 8, 0x2}, {
4013 4, 0x1}, {
4014 0, 0x0}
4015 };
4016
4017 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
4018
4019 static char *brcmf_chipname(uint chipid, char *buf, uint len)
4020 {
4021 const char *fmt;
4022
4023 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
4024 snprintf(buf, len, fmt, chipid);
4025 return buf;
4026 }
4027
4028 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4029 u32 drivestrength) {
4030 struct sdiod_drive_str *str_tab = NULL;
4031 u32 str_mask = 0;
4032 u32 str_shift = 0;
4033 char chn[8];
4034
4035 if (!(bus->ci->cccaps & CC_CAP_PMU))
4036 return;
4037
4038 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4039 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4040 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4041 str_mask = 0x30000000;
4042 str_shift = 28;
4043 break;
4044 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4045 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4046 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4047 str_mask = 0x00003800;
4048 str_shift = 11;
4049 break;
4050 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4051 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4052 str_mask = 0x00003800;
4053 str_shift = 11;
4054 break;
4055 default:
4056 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4057 brcmf_chipname(bus->ci->chip, chn, 8),
4058 bus->ci->chiprev, bus->ci->pmurev);
4059 break;
4060 }
4061
4062 if (str_tab != NULL) {
4063 u32 drivestrength_sel = 0;
4064 u32 cc_data_temp;
4065 int i;
4066
4067 for (i = 0; str_tab[i].strength != 0; i++) {
4068 if (drivestrength >= str_tab[i].strength) {
4069 drivestrength_sel = str_tab[i].sel;
4070 break;
4071 }
4072 }
4073
4074 brcmf_sdcard_reg_write(bus->sdiodev,
4075 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4076 4, 1);
4077 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4078 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4079 cc_data_temp &= ~str_mask;
4080 drivestrength_sel <<= str_shift;
4081 cc_data_temp |= drivestrength_sel;
4082 brcmf_sdcard_reg_write(bus->sdiodev,
4083 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4084 4, cc_data_temp);
4085
4086 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4087 drivestrength, cc_data_temp);
4088 }
4089 }
4090
4091 static int
4092 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4093 struct chip_info *ci, u32 regs)
4094 {
4095 u32 regdata;
4096
4097 /*
4098 * Get CC core rev
4099 * Chipid is assume to be at offset 0 from regs arg
4100 * For different chiptypes or old sdio hosts w/o chipcommon,
4101 * other ways of recognition should be added here.
4102 */
4103 ci->cccorebase = regs;
4104 regdata = brcmf_sdcard_reg_read(sdiodev,
4105 CORE_CC_REG(ci->cccorebase, chipid), 4);
4106 ci->chip = regdata & CID_ID_MASK;
4107 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4108
4109 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4110
4111 /* Address of cores for new chips should be added here */
4112 switch (ci->chip) {
4113 case BCM4329_CHIP_ID:
4114 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4115 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4116 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4117 ci->ramsize = BCM4329_RAMSIZE;
4118 break;
4119 default:
4120 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4121 return -ENODEV;
4122 }
4123
4124 regdata = brcmf_sdcard_reg_read(sdiodev,
4125 CORE_SB(ci->cccorebase, sbidhigh), 4);
4126 ci->ccrev = SBCOREREV(regdata);
4127
4128 regdata = brcmf_sdcard_reg_read(sdiodev,
4129 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4130 ci->pmurev = regdata & PCAP_REV_MASK;
4131
4132 regdata = brcmf_sdcard_reg_read(sdiodev,
4133 CORE_SB(ci->buscorebase, sbidhigh), 4);
4134 ci->buscorerev = SBCOREREV(regdata);
4135 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4136
4137 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4138 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4139
4140 /* get chipcommon capabilites */
4141 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4142 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4143
4144 return 0;
4145 }
4146
4147 static int
4148 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4149 {
4150 struct chip_info *ci;
4151 int err;
4152 u8 clkval, clkset;
4153
4154 brcmf_dbg(TRACE, "Enter\n");
4155
4156 /* alloc chip_info_t */
4157 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4158 if (NULL == ci)
4159 return -ENOMEM;
4160
4161 /* bus/core/clk setup for register access */
4162 /* Try forcing SDIO core to do ALPAvail request only */
4163 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4164 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4165 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4166 if (err) {
4167 brcmf_dbg(ERROR, "error writing for HT off\n");
4168 goto fail;
4169 }
4170
4171 /* If register supported, wait for ALPAvail and then force ALP */
4172 /* This may take up to 15 milliseconds */
4173 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4174 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4175 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4176 SPINWAIT(((clkval =
4177 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4178 SBSDIO_FUNC1_CHIPCLKCSR,
4179 NULL)),
4180 !SBSDIO_ALPAV(clkval)),
4181 PMU_MAX_TRANSITION_DLY);
4182 if (!SBSDIO_ALPAV(clkval)) {
4183 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4184 clkval);
4185 err = -EBUSY;
4186 goto fail;
4187 }
4188 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4189 SBSDIO_FORCE_ALP;
4190 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4191 SBSDIO_FUNC1_CHIPCLKCSR,
4192 clkset, &err);
4193 udelay(65);
4194 } else {
4195 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4196 clkset, clkval);
4197 err = -EACCES;
4198 goto fail;
4199 }
4200
4201 /* Also, disable the extra SDIO pull-ups */
4202 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4203 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4204
4205 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4206 if (err)
4207 goto fail;
4208
4209 /*
4210 * Make sure any on-chip ARM is off (in case strapping is wrong),
4211 * or downloaded code was already running.
4212 */
4213 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4214
4215 brcmf_sdcard_reg_write(bus->sdiodev,
4216 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4217 brcmf_sdcard_reg_write(bus->sdiodev,
4218 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4219
4220 /* Disable F2 to clear any intermediate frame state on the dongle */
4221 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4222 SDIO_FUNC_ENABLE_1, NULL);
4223
4224 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4225 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4226 0, NULL);
4227
4228 /* Done with backplane-dependent accesses, can drop clock... */
4229 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4230 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4231
4232 bus->ci = ci;
4233 return 0;
4234 fail:
4235 bus->ci = NULL;
4236 kfree(ci);
4237 return err;
4238 }
4239
4240 static bool
4241 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4242 {
4243 u8 clkctl = 0;
4244 int err = 0;
4245 int reg_addr;
4246 u32 reg_val;
4247
4248 bus->alp_only = true;
4249
4250 /* Return the window to backplane enumeration space for core access */
4251 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4252 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4253
4254 #ifdef BCMDBG
4255 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4256 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4257
4258 #endif /* BCMDBG */
4259
4260 /*
4261 * Force PLL off until brcmf_sdbrcm_chip_attach()
4262 * programs PLL control regs
4263 */
4264
4265 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4266 SBSDIO_FUNC1_CHIPCLKCSR,
4267 BRCMF_INIT_CLKCTL1, &err);
4268 if (!err)
4269 clkctl =
4270 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4271 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4272
4273 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4274 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4275 err, BRCMF_INIT_CLKCTL1, clkctl);
4276 goto fail;
4277 }
4278
4279 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4280 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4281 goto fail;
4282 }
4283
4284 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4285 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4286 goto fail;
4287 }
4288
4289 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4290
4291 /* Get info on the ARM and SOCRAM cores... */
4292 brcmf_sdcard_reg_read(bus->sdiodev,
4293 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4294 bus->ramsize = bus->ci->ramsize;
4295 if (!(bus->ramsize)) {
4296 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4297 goto fail;
4298 }
4299
4300 /* Set core control so an SDIO reset does a backplane reset */
4301 reg_addr = bus->ci->buscorebase +
4302 offsetof(struct sdpcmd_regs, corecontrol);
4303 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4304 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4305 reg_val | CC_BPRESEN);
4306
4307 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4308
4309 /* Locate an appropriately-aligned portion of hdrbuf */
4310 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4311 BRCMF_SDALIGN);
4312
4313 /* Set the poll and/or interrupt flags */
4314 bus->intr = true;
4315 bus->poll = false;
4316 if (bus->poll)
4317 bus->pollrate = 1;
4318
4319 return true;
4320
4321 fail:
4322 return false;
4323 }
4324
4325 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4326 {
4327 brcmf_dbg(TRACE, "Enter\n");
4328
4329 /* Disable F2 to clear any intermediate frame state on the dongle */
4330 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4331 SDIO_FUNC_ENABLE_1, NULL);
4332
4333 bus->drvr->busstate = BRCMF_BUS_DOWN;
4334 bus->sleeping = false;
4335 bus->rxflow = false;
4336
4337 /* Done with backplane-dependent accesses, can drop clock... */
4338 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4339 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4340
4341 /* ...and initialize clock/power states */
4342 bus->clkstate = CLK_SDONLY;
4343 bus->idletime = BRCMF_IDLE_INTERVAL;
4344 bus->idleclock = BRCMF_IDLE_ACTIVE;
4345
4346 /* Query the F2 block size, set roundup accordingly */
4347 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4348 bus->roundup = min(max_roundup, bus->blocksize);
4349
4350 /* bus module does not support packet chaining */
4351 bus->use_rxchain = false;
4352 bus->sd_rxchain = false;
4353
4354 return true;
4355 }
4356
4357 static int
4358 brcmf_sdbrcm_watchdog_thread(void *data)
4359 {
4360 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4361
4362 allow_signal(SIGTERM);
4363 /* Run until signal received */
4364 while (1) {
4365 if (kthread_should_stop())
4366 break;
4367 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4368 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4369 /* Count the tick for reference */
4370 bus->drvr->tickcnt++;
4371 } else
4372 break;
4373 }
4374 return 0;
4375 }
4376
4377 static void
4378 brcmf_sdbrcm_watchdog(unsigned long data)
4379 {
4380 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4381
4382 if (bus->watchdog_tsk) {
4383 complete(&bus->watchdog_wait);
4384 /* Reschedule the watchdog */
4385 if (bus->wd_timer_valid)
4386 mod_timer(&bus->timer,
4387 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4388 }
4389 }
4390
4391 static void
4392 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4393 {
4394 brcmf_dbg(TRACE, "Enter\n");
4395
4396 kfree(bus->ci);
4397 bus->ci = NULL;
4398 }
4399
4400 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4401 {
4402 brcmf_dbg(TRACE, "Enter\n");
4403
4404 if (bus->ci) {
4405 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4406 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4407 brcmf_sdbrcm_chip_detach(bus);
4408 if (bus->vars && bus->varsz)
4409 kfree(bus->vars);
4410 bus->vars = NULL;
4411 }
4412
4413 brcmf_dbg(TRACE, "Disconnected\n");
4414 }
4415
4416 /* Detach and free everything */
4417 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4418 {
4419 brcmf_dbg(TRACE, "Enter\n");
4420
4421 if (bus) {
4422 /* De-register interrupt handler */
4423 brcmf_sdcard_intr_dereg(bus->sdiodev);
4424
4425 if (bus->drvr) {
4426 brcmf_detach(bus->drvr);
4427 brcmf_sdbrcm_release_dongle(bus);
4428 bus->drvr = NULL;
4429 }
4430
4431 brcmf_sdbrcm_release_malloc(bus);
4432
4433 kfree(bus);
4434 }
4435
4436 brcmf_dbg(TRACE, "Disconnected\n");
4437 }
4438
4439 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4440 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4441 {
4442 int ret;
4443 struct brcmf_bus *bus;
4444
4445 /* Init global variables at run-time, not as part of the declaration.
4446 * This is required to support init/de-init of the driver.
4447 * Initialization
4448 * of globals as part of the declaration results in non-deterministic
4449 * behavior since the value of the globals may be different on the
4450 * first time that the driver is initialized vs subsequent
4451 * initializations.
4452 */
4453 brcmf_c_init();
4454
4455 brcmf_dbg(TRACE, "Enter\n");
4456
4457 /* We make an assumption about address window mappings:
4458 * regsva == SI_ENUM_BASE*/
4459
4460 /* Allocate private bus interface state */
4461 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4462 if (!bus)
4463 goto fail;
4464
4465 bus->sdiodev = sdiodev;
4466 sdiodev->bus = bus;
4467 skb_queue_head_init(&bus->glom);
4468 bus->txbound = BRCMF_TXBOUND;
4469 bus->rxbound = BRCMF_RXBOUND;
4470 bus->txminmax = BRCMF_TXMINMAX;
4471 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4472 bus->usebufpool = false; /* Use bufpool if allocated,
4473 else use locally malloced rxbuf */
4474
4475 /* attempt to attach to the dongle */
4476 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4477 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4478 goto fail;
4479 }
4480
4481 spin_lock_init(&bus->txqlock);
4482 init_waitqueue_head(&bus->ctrl_wait);
4483 init_waitqueue_head(&bus->dcmd_resp_wait);
4484
4485 /* Set up the watchdog timer */
4486 init_timer(&bus->timer);
4487 bus->timer.data = (unsigned long)bus;
4488 bus->timer.function = brcmf_sdbrcm_watchdog;
4489
4490 /* Initialize thread based operation and lock */
4491 sema_init(&bus->sdsem, 1);
4492
4493 /* Initialize watchdog thread */
4494 init_completion(&bus->watchdog_wait);
4495 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4496 bus, "brcmf_watchdog");
4497 if (IS_ERR(bus->watchdog_tsk)) {
4498 printk(KERN_WARNING
4499 "brcmf_watchdog thread failed to start\n");
4500 bus->watchdog_tsk = NULL;
4501 }
4502 /* Initialize DPC thread */
4503 init_completion(&bus->dpc_wait);
4504 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4505 bus, "brcmf_dpc");
4506 if (IS_ERR(bus->dpc_tsk)) {
4507 printk(KERN_WARNING
4508 "brcmf_dpc thread failed to start\n");
4509 bus->dpc_tsk = NULL;
4510 }
4511
4512 /* Attach to the brcmf/OS/network interface */
4513 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4514 if (!bus->drvr) {
4515 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4516 goto fail;
4517 }
4518
4519 /* Allocate buffers */
4520 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4521 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4522 goto fail;
4523 }
4524
4525 if (!(brcmf_sdbrcm_probe_init(bus))) {
4526 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4527 goto fail;
4528 }
4529
4530 /* Register interrupt callback, but mask it (not operational yet). */
4531 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4532 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4533 if (ret != 0) {
4534 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4535 goto fail;
4536 }
4537 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4538
4539 brcmf_dbg(INFO, "completed!!\n");
4540
4541 /* if firmware path present try to download and bring up bus */
4542 ret = brcmf_bus_start(bus->drvr);
4543 if (ret != 0) {
4544 if (ret == -ENOLINK) {
4545 brcmf_dbg(ERROR, "dongle is not responding\n");
4546 goto fail;
4547 }
4548 }
4549 /* Ok, have the per-port tell the stack we're open for business */
4550 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4551 brcmf_dbg(ERROR, "Net attach failed!!\n");
4552 goto fail;
4553 }
4554
4555 return bus;
4556
4557 fail:
4558 brcmf_sdbrcm_release(bus);
4559 return NULL;
4560 }
4561
4562 void brcmf_sdbrcm_disconnect(void *ptr)
4563 {
4564 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4565
4566 brcmf_dbg(TRACE, "Enter\n");
4567
4568 if (bus)
4569 brcmf_sdbrcm_release(bus);
4570
4571 brcmf_dbg(TRACE, "Disconnected\n");
4572 }
4573
4574 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4575 {
4576 return &bus->sdiodev->func[2]->dev;
4577 }
4578
4579 void
4580 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4581 {
4582 /* don't start the wd until fw is loaded */
4583 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4584 return;
4585
4586 /* Totally stop the timer */
4587 if (!wdtick && bus->wd_timer_valid == true) {
4588 del_timer_sync(&bus->timer);
4589 bus->wd_timer_valid = false;
4590 bus->save_ms = wdtick;
4591 return;
4592 }
4593
4594 if (wdtick) {
4595 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4596 if (bus->wd_timer_valid == true)
4597 /* Stop timer and restart at new value */
4598 del_timer_sync(&bus->timer);
4599
4600 /* Create timer again when watchdog period is
4601 dynamically changed or in the first instance
4602 */
4603 bus->timer.expires =
4604 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4605 add_timer(&bus->timer);
4606
4607 } else {
4608 /* Re arm the timer, at last watchdog period */
4609 mod_timer(&bus->timer,
4610 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4611 }
4612
4613 bus->wd_timer_valid = true;
4614 bus->save_ms = wdtick;
4615 }
4616 }
Linux kernel - Deliverables
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