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net: usb: Use eth_<foo>_addr instead of memset
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/semaphore.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/bcma/bcma.h>
33 #include <linux/debugfs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/platform_data/brcmfmac-sdio.h>
36 #include <linux/moduleparam.h>
37 #include <asm/unaligned.h>
38 #include <defs.h>
39 #include <brcmu_wifi.h>
40 #include <brcmu_utils.h>
41 #include <brcm_hw_ids.h>
42 #include <soc.h>
43 #include "sdio.h"
44 #include "chip.h"
45 #include "firmware.h"
46
47 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
48 #define CTL_DONE_TIMEOUT 2000 /* In milli second */
49
50 #ifdef DEBUG
51
52 #define BRCMF_TRAP_INFO_SIZE 80
53
54 #define CBUF_LEN (128)
55
56 /* Device console log buffer state */
57 #define CONSOLE_BUFFER_MAX 2024
58
59 struct rte_log_le {
60 __le32 buf; /* Can't be pointer on (64-bit) hosts */
61 __le32 buf_size;
62 __le32 idx;
63 char *_buf_compat; /* Redundant pointer for backward compat. */
64 };
65
66 struct rte_console {
67 /* Virtual UART
68 * When there is no UART (e.g. Quickturn),
69 * the host should write a complete
70 * input line directly into cbuf and then write
71 * the length into vcons_in.
72 * This may also be used when there is a real UART
73 * (at risk of conflicting with
74 * the real UART). vcons_out is currently unused.
75 */
76 uint vcons_in;
77 uint vcons_out;
78
79 /* Output (logging) buffer
80 * Console output is written to a ring buffer log_buf at index log_idx.
81 * The host may read the output when it sees log_idx advance.
82 * Output will be lost if the output wraps around faster than the host
83 * polls.
84 */
85 struct rte_log_le log_le;
86
87 /* Console input line buffer
88 * Characters are read one at a time into cbuf
89 * until <CR> is received, then
90 * the buffer is processed as a command line.
91 * Also used for virtual UART.
92 */
93 uint cbuf_idx;
94 char cbuf[CBUF_LEN];
95 };
96
97 #endif /* DEBUG */
98 #include <chipcommon.h>
99
100 #include "bus.h"
101 #include "debug.h"
102 #include "tracepoint.h"
103
104 #define TXQLEN 2048 /* bulk tx queue length */
105 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
106 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
107 #define PRIOMASK 7
108
109 #define TXRETRIES 2 /* # of retries for tx frames */
110
111 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
112 one scheduling */
113
114 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
115 one scheduling */
116
117 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
118
119 #define MEMBLOCK 2048 /* Block size used for downloading
120 of dongle image */
121 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
122 biggest possible glom */
123
124 #define BRCMF_FIRSTREAD (1 << 6)
125
126
127 /* SBSDIO_DEVICE_CTL */
128
129 /* 1: device will assert busy signal when receiving CMD53 */
130 #define SBSDIO_DEVCTL_SETBUSY 0x01
131 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
132 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
133 /* 1: mask all interrupts to host except the chipActive (rev 8) */
134 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
135 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
136 * sdio bus power cycle to clear (rev 9) */
137 #define SBSDIO_DEVCTL_PADS_ISO 0x08
138 /* Force SD->SB reset mapping (rev 11) */
139 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
140 /* Determined by CoreControl bit */
141 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
142 /* Force backplane reset */
143 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
144 /* Force no backplane reset */
145 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
146
147 /* direct(mapped) cis space */
148
149 /* MAPPED common CIS address */
150 #define SBSDIO_CIS_BASE_COMMON 0x1000
151 /* maximum bytes in one CIS */
152 #define SBSDIO_CIS_SIZE_LIMIT 0x200
153 /* cis offset addr is < 17 bits */
154 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
155
156 /* manfid tuple length, include tuple, link bytes */
157 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
158
159 #define CORE_BUS_REG(base, field) \
160 (base + offsetof(struct sdpcmd_regs, field))
161
162 /* SDIO function 1 register CHIPCLKCSR */
163 /* Force ALP request to backplane */
164 #define SBSDIO_FORCE_ALP 0x01
165 /* Force HT request to backplane */
166 #define SBSDIO_FORCE_HT 0x02
167 /* Force ILP request to backplane */
168 #define SBSDIO_FORCE_ILP 0x04
169 /* Make ALP ready (power up xtal) */
170 #define SBSDIO_ALP_AVAIL_REQ 0x08
171 /* Make HT ready (power up PLL) */
172 #define SBSDIO_HT_AVAIL_REQ 0x10
173 /* Squelch clock requests from HW */
174 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
175 /* Status: ALP is ready */
176 #define SBSDIO_ALP_AVAIL 0x40
177 /* Status: HT is ready */
178 #define SBSDIO_HT_AVAIL 0x80
179 #define SBSDIO_CSR_MASK 0x1F
180 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
186
187 /* intstatus */
188 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
189 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
190 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
191 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
192 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
193 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
194 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
195 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
196 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
197 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
198 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
199 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
200 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
201 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
202 #define I_PC (1 << 10) /* descriptor error */
203 #define I_PD (1 << 11) /* data error */
204 #define I_DE (1 << 12) /* Descriptor protocol Error */
205 #define I_RU (1 << 13) /* Receive descriptor Underflow */
206 #define I_RO (1 << 14) /* Receive fifo Overflow */
207 #define I_XU (1 << 15) /* Transmit fifo Underflow */
208 #define I_RI (1 << 16) /* Receive Interrupt */
209 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
210 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
211 #define I_XI (1 << 24) /* Transmit Interrupt */
212 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
213 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
214 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
215 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
216 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
217 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
218 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
219 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
220 #define I_DMA (I_RI | I_XI | I_ERRORS)
221
222 /* corecontrol */
223 #define CC_CISRDY (1 << 0) /* CIS Ready */
224 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
225 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
226 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
227 #define CC_XMTDATAAVAIL_MODE (1 << 4)
228 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
229
230 /* SDA_FRAMECTRL */
231 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
232 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
233 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
234 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
235
236 /*
237 * Software allocation of To SB Mailbox resources
238 */
239
240 /* tosbmailbox bits corresponding to intstatus bits */
241 #define SMB_NAK (1 << 0) /* Frame NAK */
242 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
243 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
244 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
245
246 /* tosbmailboxdata */
247 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
248
249 /*
250 * Software allocation of To Host Mailbox resources
251 */
252
253 /* intstatus bits */
254 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
255 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
256 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
257 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
258
259 /* tohostmailboxdata */
260 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
261 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
262 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
263 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
264
265 #define HMB_DATA_FCDATA_MASK 0xff000000
266 #define HMB_DATA_FCDATA_SHIFT 24
267
268 #define HMB_DATA_VERSION_MASK 0x00ff0000
269 #define HMB_DATA_VERSION_SHIFT 16
270
271 /*
272 * Software-defined protocol header
273 */
274
275 /* Current protocol version */
276 #define SDPCM_PROT_VERSION 4
277
278 /*
279 * Shared structure between dongle and the host.
280 * The structure contains pointers to trap or assert information.
281 */
282 #define SDPCM_SHARED_VERSION 0x0003
283 #define SDPCM_SHARED_VERSION_MASK 0x00FF
284 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
285 #define SDPCM_SHARED_ASSERT 0x0200
286 #define SDPCM_SHARED_TRAP 0x0400
287
288 /* Space for header read, limit for data packets */
289 #define MAX_HDR_READ (1 << 6)
290 #define MAX_RX_DATASZ 2048
291
292 /* Bump up limit on waiting for HT to account for first startup;
293 * if the image is doing a CRC calculation before programming the PMU
294 * for HT availability, it could take a couple hundred ms more, so
295 * max out at a 1 second (1000000us).
296 */
297 #undef PMU_MAX_TRANSITION_DLY
298 #define PMU_MAX_TRANSITION_DLY 1000000
299
300 /* Value for ChipClockCSR during initial setup */
301 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
302 SBSDIO_ALP_AVAIL_REQ)
303
304 /* Flags for SDH calls */
305 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
306
307 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
308 * when idle
309 */
310 #define BRCMF_IDLE_INTERVAL 1
311
312 #define KSO_WAIT_US 50
313 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
314
315 /*
316 * Conversion of 802.1D priority to precedence level
317 */
318 static uint prio2prec(u32 prio)
319 {
320 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
321 (prio^2) : prio;
322 }
323
324 #ifdef DEBUG
325 /* Device console log buffer state */
326 struct brcmf_console {
327 uint count; /* Poll interval msec counter */
328 uint log_addr; /* Log struct address (fixed) */
329 struct rte_log_le log_le; /* Log struct (host copy) */
330 uint bufsize; /* Size of log buffer */
331 u8 *buf; /* Log buffer (host copy) */
332 uint last; /* Last buffer read index */
333 };
334
335 struct brcmf_trap_info {
336 __le32 type;
337 __le32 epc;
338 __le32 cpsr;
339 __le32 spsr;
340 __le32 r0; /* a1 */
341 __le32 r1; /* a2 */
342 __le32 r2; /* a3 */
343 __le32 r3; /* a4 */
344 __le32 r4; /* v1 */
345 __le32 r5; /* v2 */
346 __le32 r6; /* v3 */
347 __le32 r7; /* v4 */
348 __le32 r8; /* v5 */
349 __le32 r9; /* sb/v6 */
350 __le32 r10; /* sl/v7 */
351 __le32 r11; /* fp/v8 */
352 __le32 r12; /* ip */
353 __le32 r13; /* sp */
354 __le32 r14; /* lr */
355 __le32 pc; /* r15 */
356 };
357 #endif /* DEBUG */
358
359 struct sdpcm_shared {
360 u32 flags;
361 u32 trap_addr;
362 u32 assert_exp_addr;
363 u32 assert_file_addr;
364 u32 assert_line;
365 u32 console_addr; /* Address of struct rte_console */
366 u32 msgtrace_addr;
367 u8 tag[32];
368 u32 brpt_addr;
369 };
370
371 struct sdpcm_shared_le {
372 __le32 flags;
373 __le32 trap_addr;
374 __le32 assert_exp_addr;
375 __le32 assert_file_addr;
376 __le32 assert_line;
377 __le32 console_addr; /* Address of struct rte_console */
378 __le32 msgtrace_addr;
379 u8 tag[32];
380 __le32 brpt_addr;
381 };
382
383 /* dongle SDIO bus specific header info */
384 struct brcmf_sdio_hdrinfo {
385 u8 seq_num;
386 u8 channel;
387 u16 len;
388 u16 len_left;
389 u16 len_nxtfrm;
390 u8 dat_offset;
391 bool lastfrm;
392 u16 tail_pad;
393 };
394
395 /*
396 * hold counter variables
397 */
398 struct brcmf_sdio_count {
399 uint intrcount; /* Count of device interrupt callbacks */
400 uint lastintrs; /* Count as of last watchdog timer */
401 uint pollcnt; /* Count of active polls */
402 uint regfails; /* Count of R_REG failures */
403 uint tx_sderrs; /* Count of tx attempts with sd errors */
404 uint fcqueued; /* Tx packets that got queued */
405 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
406 uint rx_toolong; /* Receive frames too long to receive */
407 uint rxc_errors; /* SDIO errors when reading control frames */
408 uint rx_hdrfail; /* SDIO errors on header reads */
409 uint rx_badhdr; /* Bad received headers (roosync?) */
410 uint rx_badseq; /* Mismatched rx sequence number */
411 uint fc_rcvd; /* Number of flow-control events received */
412 uint fc_xoff; /* Number which turned on flow-control */
413 uint fc_xon; /* Number which turned off flow-control */
414 uint rxglomfail; /* Failed deglom attempts */
415 uint rxglomframes; /* Number of glom frames (superframes) */
416 uint rxglompkts; /* Number of packets from glom frames */
417 uint f2rxhdrs; /* Number of header reads */
418 uint f2rxdata; /* Number of frame data reads */
419 uint f2txdata; /* Number of f2 frame writes */
420 uint f1regdata; /* Number of f1 register accesses */
421 uint tickcnt; /* Number of watchdog been schedule */
422 ulong tx_ctlerrs; /* Err of sending ctrl frames */
423 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
424 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
425 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
426 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
427 };
428
429 /* misc chip info needed by some of the routines */
430 /* Private data for SDIO bus interaction */
431 struct brcmf_sdio {
432 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
433 struct brcmf_chip *ci; /* Chip info struct */
434
435 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
436
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
440
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
443
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
448
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
456
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
459 uint txminmax;
460
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
463 uint glomerr; /* Glom packet read errors */
464
465 u8 *rxbuf; /* Buffer for receiving control packets */
466 uint rxblen; /* Allocated length of rxbuf */
467 u8 *rxctl; /* Aligned pointer into rxbuf */
468 u8 *rxctl_orig; /* pointer for freeing rxctl */
469 uint rxlen; /* Length of valid data in buffer */
470 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
471
472 u8 sdpcm_ver; /* Bus protocol reported by dongle */
473
474 bool intr; /* Use interrupts */
475 bool poll; /* Use polling */
476 atomic_t ipend; /* Device interrupt is pending */
477 uint spurious; /* Count of spurious interrupts */
478 uint pollrate; /* Ticks between device polls */
479 uint polltick; /* Tick counter */
480
481 #ifdef DEBUG
482 uint console_interval;
483 struct brcmf_console console; /* Console output polling support */
484 uint console_addr; /* Console address from shared struct */
485 #endif /* DEBUG */
486
487 uint clkstate; /* State of sd and backplane clock(s) */
488 bool activity; /* Activity flag for clock down */
489 s32 idletime; /* Control for activity timeout */
490 s32 idlecount; /* Activity timeout counter */
491 s32 idleclock; /* How to set bus driver when idle */
492 bool rxflow_mode; /* Rx flow control mode */
493 bool rxflow; /* Is rx flow control on */
494 bool alp_only; /* Don't use HT clock (ALP only) */
495
496 u8 *ctrl_frame_buf;
497 u16 ctrl_frame_len;
498 bool ctrl_frame_stat;
499 int ctrl_frame_err;
500
501 spinlock_t txq_lock; /* protect bus->txq */
502 wait_queue_head_t ctrl_wait;
503 wait_queue_head_t dcmd_resp_wait;
504
505 struct timer_list timer;
506 struct completion watchdog_wait;
507 struct task_struct *watchdog_tsk;
508 bool wd_timer_valid;
509 uint save_ms;
510
511 struct workqueue_struct *brcmf_wq;
512 struct work_struct datawork;
513 atomic_t dpc_tskcnt;
514
515 bool txoff; /* Transmit flow-controlled */
516 struct brcmf_sdio_count sdcnt;
517 bool sr_enabled; /* SaveRestore enabled */
518
519 u8 tx_hdrlen; /* sdio bus header length for tx packet */
520 bool txglom; /* host tx glomming enable flag */
521 u16 head_align; /* buffer pointer alignment */
522 u16 sgentry_align; /* scatter-gather buffer alignment */
523 };
524
525 /* clkstate */
526 #define CLK_NONE 0
527 #define CLK_SDONLY 1
528 #define CLK_PENDING 2
529 #define CLK_AVAIL 3
530
531 #ifdef DEBUG
532 static int qcount[NUMPRIO];
533 #endif /* DEBUG */
534
535 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536
537 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538
539 /* Retry count for register access failures */
540 static const uint retry_limit = 2;
541
542 /* Limit on rounding up frames */
543 static const uint max_roundup = 512;
544
545 #define ALIGNMENT 4
546
547 enum brcmf_sdio_frmtype {
548 BRCMF_SDIO_FT_NORMAL,
549 BRCMF_SDIO_FT_SUPER,
550 BRCMF_SDIO_FT_SUB,
551 };
552
553 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
554
555 /* SDIO Pad drive strength to select value mappings */
556 struct sdiod_drive_str {
557 u8 strength; /* Pad Drive Strength in mA */
558 u8 sel; /* Chip-specific select value */
559 };
560
561 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
562 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
563 {32, 0x6},
564 {26, 0x7},
565 {22, 0x4},
566 {16, 0x5},
567 {12, 0x2},
568 {8, 0x3},
569 {4, 0x0},
570 {0, 0x1}
571 };
572
573 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
574 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
575 {6, 0x7},
576 {5, 0x6},
577 {4, 0x5},
578 {3, 0x4},
579 {2, 0x2},
580 {1, 0x1},
581 {0, 0x0}
582 };
583
584 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
585 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
586 {3, 0x3},
587 {2, 0x2},
588 {1, 0x1},
589 {0, 0x0} };
590
591 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
592 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
593 {16, 0x7},
594 {12, 0x5},
595 {8, 0x3},
596 {4, 0x1}
597 };
598
599 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
600 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
601 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
602 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
603 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
604 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
605 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
606 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
607 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
608 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
609 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
610 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
611 #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
612 #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
613 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
614 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
615 #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
616 #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
617 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
618 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
619 #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin"
620 #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt"
621
622 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
623 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
624 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
625 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
626 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
627 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
628 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
629 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
630 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
631 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
632 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
633 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
634 MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
635 MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
636 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
637 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
638 MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
639 MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
640 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
641 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
642 MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME);
643 MODULE_FIRMWARE(BCM4354_NVRAM_NAME);
644
645 struct brcmf_firmware_names {
646 u32 chipid;
647 u32 revmsk;
648 const char *bin;
649 const char *nv;
650 };
651
652 enum brcmf_firmware_type {
653 BRCMF_FIRMWARE_BIN,
654 BRCMF_FIRMWARE_NVRAM
655 };
656
657 #define BRCMF_FIRMWARE_NVRAM(name) \
658 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
659
660 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
661 { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
662 { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
663 { BRCM_CC_43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
664 { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
665 { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
666 { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
667 { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
668 { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
669 { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
670 { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
671 { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
672 };
673
674 static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
675 struct brcmf_sdio_dev *sdiodev)
676 {
677 int i;
678 char end;
679
680 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
681 if (brcmf_fwname_data[i].chipid == ci->chip &&
682 brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
683 break;
684 }
685
686 if (i == ARRAY_SIZE(brcmf_fwname_data)) {
687 brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
688 return -ENODEV;
689 }
690
691 /* check if firmware path is provided by module parameter */
692 if (brcmf_firmware_path[0] != '\0') {
693 strlcpy(sdiodev->fw_name, brcmf_firmware_path,
694 sizeof(sdiodev->fw_name));
695 strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
696 sizeof(sdiodev->nvram_name));
697
698 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
699 if (end != '/') {
700 strlcat(sdiodev->fw_name, "/",
701 sizeof(sdiodev->fw_name));
702 strlcat(sdiodev->nvram_name, "/",
703 sizeof(sdiodev->nvram_name));
704 }
705 }
706 strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
707 sizeof(sdiodev->fw_name));
708 strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
709 sizeof(sdiodev->nvram_name));
710
711 return 0;
712 }
713
714 static void pkt_align(struct sk_buff *p, int len, int align)
715 {
716 uint datalign;
717 datalign = (unsigned long)(p->data);
718 datalign = roundup(datalign, (align)) - datalign;
719 if (datalign)
720 skb_pull(p, datalign);
721 __skb_trim(p, len);
722 }
723
724 /* To check if there's window offered */
725 static bool data_ok(struct brcmf_sdio *bus)
726 {
727 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
728 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
729 }
730
731 /*
732 * Reads a register in the SDIO hardware block. This block occupies a series of
733 * adresses on the 32 bit backplane bus.
734 */
735 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
736 {
737 struct brcmf_core *core;
738 int ret;
739
740 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
741 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
742
743 return ret;
744 }
745
746 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
747 {
748 struct brcmf_core *core;
749 int ret;
750
751 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
752 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
753
754 return ret;
755 }
756
757 static int
758 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
759 {
760 u8 wr_val = 0, rd_val, cmp_val, bmask;
761 int err = 0;
762 int try_cnt = 0;
763
764 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
765
766 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
767 /* 1st KSO write goes to AOS wake up core if device is asleep */
768 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
769 wr_val, &err);
770
771 if (on) {
772 /* device WAKEUP through KSO:
773 * write bit 0 & read back until
774 * both bits 0 (kso bit) & 1 (dev on status) are set
775 */
776 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
777 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
778 bmask = cmp_val;
779 usleep_range(2000, 3000);
780 } else {
781 /* Put device to sleep, turn off KSO */
782 cmp_val = 0;
783 /* only check for bit0, bit1(dev on status) may not
784 * get cleared right away
785 */
786 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
787 }
788
789 do {
790 /* reliable KSO bit set/clr:
791 * the sdiod sleep write access is synced to PMU 32khz clk
792 * just one write attempt may fail,
793 * read it back until it matches written value
794 */
795 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
796 &err);
797 if (((rd_val & bmask) == cmp_val) && !err)
798 break;
799
800 udelay(KSO_WAIT_US);
801 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
802 wr_val, &err);
803 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
804
805 if (try_cnt > 2)
806 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
807 rd_val, err);
808
809 if (try_cnt > MAX_KSO_ATTEMPTS)
810 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
811
812 return err;
813 }
814
815 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
816
817 /* Turn backplane clock on or off */
818 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
819 {
820 int err;
821 u8 clkctl, clkreq, devctl;
822 unsigned long timeout;
823
824 brcmf_dbg(SDIO, "Enter\n");
825
826 clkctl = 0;
827
828 if (bus->sr_enabled) {
829 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
830 return 0;
831 }
832
833 if (on) {
834 /* Request HT Avail */
835 clkreq =
836 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
837
838 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
839 clkreq, &err);
840 if (err) {
841 brcmf_err("HT Avail request error: %d\n", err);
842 return -EBADE;
843 }
844
845 /* Check current status */
846 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
847 SBSDIO_FUNC1_CHIPCLKCSR, &err);
848 if (err) {
849 brcmf_err("HT Avail read error: %d\n", err);
850 return -EBADE;
851 }
852
853 /* Go to pending and await interrupt if appropriate */
854 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
855 /* Allow only clock-available interrupt */
856 devctl = brcmf_sdiod_regrb(bus->sdiodev,
857 SBSDIO_DEVICE_CTL, &err);
858 if (err) {
859 brcmf_err("Devctl error setting CA: %d\n",
860 err);
861 return -EBADE;
862 }
863
864 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
865 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
866 devctl, &err);
867 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
868 bus->clkstate = CLK_PENDING;
869
870 return 0;
871 } else if (bus->clkstate == CLK_PENDING) {
872 /* Cancel CA-only interrupt filter */
873 devctl = brcmf_sdiod_regrb(bus->sdiodev,
874 SBSDIO_DEVICE_CTL, &err);
875 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
876 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
877 devctl, &err);
878 }
879
880 /* Otherwise, wait here (polling) for HT Avail */
881 timeout = jiffies +
882 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
883 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
884 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
885 SBSDIO_FUNC1_CHIPCLKCSR,
886 &err);
887 if (time_after(jiffies, timeout))
888 break;
889 else
890 usleep_range(5000, 10000);
891 }
892 if (err) {
893 brcmf_err("HT Avail request error: %d\n", err);
894 return -EBADE;
895 }
896 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
897 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
898 PMU_MAX_TRANSITION_DLY, clkctl);
899 return -EBADE;
900 }
901
902 /* Mark clock available */
903 bus->clkstate = CLK_AVAIL;
904 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
905
906 #if defined(DEBUG)
907 if (!bus->alp_only) {
908 if (SBSDIO_ALPONLY(clkctl))
909 brcmf_err("HT Clock should be on\n");
910 }
911 #endif /* defined (DEBUG) */
912
913 } else {
914 clkreq = 0;
915
916 if (bus->clkstate == CLK_PENDING) {
917 /* Cancel CA-only interrupt filter */
918 devctl = brcmf_sdiod_regrb(bus->sdiodev,
919 SBSDIO_DEVICE_CTL, &err);
920 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
921 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
922 devctl, &err);
923 }
924
925 bus->clkstate = CLK_SDONLY;
926 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
927 clkreq, &err);
928 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
929 if (err) {
930 brcmf_err("Failed access turning clock off: %d\n",
931 err);
932 return -EBADE;
933 }
934 }
935 return 0;
936 }
937
938 /* Change idle/active SD state */
939 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
940 {
941 brcmf_dbg(SDIO, "Enter\n");
942
943 if (on)
944 bus->clkstate = CLK_SDONLY;
945 else
946 bus->clkstate = CLK_NONE;
947
948 return 0;
949 }
950
951 /* Transition SD and backplane clock readiness */
952 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
953 {
954 #ifdef DEBUG
955 uint oldstate = bus->clkstate;
956 #endif /* DEBUG */
957
958 brcmf_dbg(SDIO, "Enter\n");
959
960 /* Early exit if we're already there */
961 if (bus->clkstate == target) {
962 if (target == CLK_AVAIL) {
963 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
964 bus->activity = true;
965 }
966 return 0;
967 }
968
969 switch (target) {
970 case CLK_AVAIL:
971 /* Make sure SD clock is available */
972 if (bus->clkstate == CLK_NONE)
973 brcmf_sdio_sdclk(bus, true);
974 /* Now request HT Avail on the backplane */
975 brcmf_sdio_htclk(bus, true, pendok);
976 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
977 bus->activity = true;
978 break;
979
980 case CLK_SDONLY:
981 /* Remove HT request, or bring up SD clock */
982 if (bus->clkstate == CLK_NONE)
983 brcmf_sdio_sdclk(bus, true);
984 else if (bus->clkstate == CLK_AVAIL)
985 brcmf_sdio_htclk(bus, false, false);
986 else
987 brcmf_err("request for %d -> %d\n",
988 bus->clkstate, target);
989 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
990 break;
991
992 case CLK_NONE:
993 /* Make sure to remove HT request */
994 if (bus->clkstate == CLK_AVAIL)
995 brcmf_sdio_htclk(bus, false, false);
996 /* Now remove the SD clock */
997 brcmf_sdio_sdclk(bus, false);
998 brcmf_sdio_wd_timer(bus, 0);
999 break;
1000 }
1001 #ifdef DEBUG
1002 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
1003 #endif /* DEBUG */
1004
1005 return 0;
1006 }
1007
1008 static int
1009 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
1010 {
1011 int err = 0;
1012 u8 clkcsr;
1013
1014 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
1015 (sleep ? "SLEEP" : "WAKE"),
1016 (bus->sdiodev->sleeping ? "SLEEP" : "WAKE"));
1017
1018 /* If SR is enabled control bus state with KSO */
1019 if (bus->sr_enabled) {
1020 /* Done if we're already in the requested state */
1021 if (sleep == bus->sdiodev->sleeping)
1022 goto end;
1023
1024 /* Going to sleep */
1025 if (sleep) {
1026 /* Don't sleep if something is pending */
1027 if (atomic_read(&bus->intstatus) ||
1028 atomic_read(&bus->ipend) > 0 ||
1029 (!atomic_read(&bus->fcstate) &&
1030 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
1031 data_ok(bus))) {
1032 err = -EBUSY;
1033 goto done;
1034 }
1035
1036 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
1037 SBSDIO_FUNC1_CHIPCLKCSR,
1038 &err);
1039 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
1040 brcmf_dbg(SDIO, "no clock, set ALP\n");
1041 brcmf_sdiod_regwb(bus->sdiodev,
1042 SBSDIO_FUNC1_CHIPCLKCSR,
1043 SBSDIO_ALP_AVAIL_REQ, &err);
1044 }
1045 err = brcmf_sdio_kso_control(bus, false);
1046 /* disable watchdog */
1047 if (!err)
1048 brcmf_sdio_wd_timer(bus, 0);
1049 } else {
1050 bus->idlecount = 0;
1051 err = brcmf_sdio_kso_control(bus, true);
1052 }
1053 if (err) {
1054 brcmf_err("error while changing bus sleep state %d\n",
1055 err);
1056 goto done;
1057 }
1058 }
1059
1060 end:
1061 /* control clocks */
1062 if (sleep) {
1063 if (!bus->sr_enabled)
1064 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1065 } else {
1066 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1067 }
1068 bus->sdiodev->sleeping = sleep;
1069 if (sleep)
1070 wake_up(&bus->sdiodev->idle_wait);
1071 brcmf_dbg(SDIO, "new state %s\n",
1072 (sleep ? "SLEEP" : "WAKE"));
1073 done:
1074 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1075 return err;
1076
1077 }
1078
1079 #ifdef DEBUG
1080 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1081 {
1082 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1083 }
1084
1085 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1086 struct sdpcm_shared *sh)
1087 {
1088 u32 addr;
1089 int rv;
1090 u32 shaddr = 0;
1091 struct sdpcm_shared_le sh_le;
1092 __le32 addr_le;
1093
1094 shaddr = bus->ci->rambase + bus->ramsize - 4;
1095
1096 /*
1097 * Read last word in socram to determine
1098 * address of sdpcm_shared structure
1099 */
1100 sdio_claim_host(bus->sdiodev->func[1]);
1101 brcmf_sdio_bus_sleep(bus, false, false);
1102 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
1103 sdio_release_host(bus->sdiodev->func[1]);
1104 if (rv < 0)
1105 return rv;
1106
1107 addr = le32_to_cpu(addr_le);
1108
1109 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
1110
1111 /*
1112 * Check if addr is valid.
1113 * NVRAM length at the end of memory should have been overwritten.
1114 */
1115 if (!brcmf_sdio_valid_shared_address(addr)) {
1116 brcmf_err("invalid sdpcm_shared address 0x%08X\n",
1117 addr);
1118 return -EINVAL;
1119 }
1120
1121 /* Read hndrte_shared structure */
1122 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1123 sizeof(struct sdpcm_shared_le));
1124 if (rv < 0)
1125 return rv;
1126
1127 /* Endianness */
1128 sh->flags = le32_to_cpu(sh_le.flags);
1129 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1130 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1131 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1132 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1133 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1134 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1135
1136 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1137 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1138 SDPCM_SHARED_VERSION,
1139 sh->flags & SDPCM_SHARED_VERSION_MASK);
1140 return -EPROTO;
1141 }
1142
1143 return 0;
1144 }
1145
1146 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1147 {
1148 struct sdpcm_shared sh;
1149
1150 if (brcmf_sdio_readshared(bus, &sh) == 0)
1151 bus->console_addr = sh.console_addr;
1152 }
1153 #else
1154 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1155 {
1156 }
1157 #endif /* DEBUG */
1158
1159 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1160 {
1161 u32 intstatus = 0;
1162 u32 hmb_data;
1163 u8 fcbits;
1164 int ret;
1165
1166 brcmf_dbg(SDIO, "Enter\n");
1167
1168 /* Read mailbox data and ack that we did so */
1169 ret = r_sdreg32(bus, &hmb_data,
1170 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1171
1172 if (ret == 0)
1173 w_sdreg32(bus, SMB_INT_ACK,
1174 offsetof(struct sdpcmd_regs, tosbmailbox));
1175 bus->sdcnt.f1regdata += 2;
1176
1177 /* Dongle recomposed rx frames, accept them again */
1178 if (hmb_data & HMB_DATA_NAKHANDLED) {
1179 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1180 bus->rx_seq);
1181 if (!bus->rxskip)
1182 brcmf_err("unexpected NAKHANDLED!\n");
1183
1184 bus->rxskip = false;
1185 intstatus |= I_HMB_FRAME_IND;
1186 }
1187
1188 /*
1189 * DEVREADY does not occur with gSPI.
1190 */
1191 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1192 bus->sdpcm_ver =
1193 (hmb_data & HMB_DATA_VERSION_MASK) >>
1194 HMB_DATA_VERSION_SHIFT;
1195 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1196 brcmf_err("Version mismatch, dongle reports %d, "
1197 "expecting %d\n",
1198 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1199 else
1200 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1201 bus->sdpcm_ver);
1202
1203 /*
1204 * Retrieve console state address now that firmware should have
1205 * updated it.
1206 */
1207 brcmf_sdio_get_console_addr(bus);
1208 }
1209
1210 /*
1211 * Flow Control has been moved into the RX headers and this out of band
1212 * method isn't used any more.
1213 * remaining backward compatible with older dongles.
1214 */
1215 if (hmb_data & HMB_DATA_FC) {
1216 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1217 HMB_DATA_FCDATA_SHIFT;
1218
1219 if (fcbits & ~bus->flowcontrol)
1220 bus->sdcnt.fc_xoff++;
1221
1222 if (bus->flowcontrol & ~fcbits)
1223 bus->sdcnt.fc_xon++;
1224
1225 bus->sdcnt.fc_rcvd++;
1226 bus->flowcontrol = fcbits;
1227 }
1228
1229 /* Shouldn't be any others */
1230 if (hmb_data & ~(HMB_DATA_DEVREADY |
1231 HMB_DATA_NAKHANDLED |
1232 HMB_DATA_FC |
1233 HMB_DATA_FWREADY |
1234 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1235 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1236 hmb_data);
1237
1238 return intstatus;
1239 }
1240
1241 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1242 {
1243 uint retries = 0;
1244 u16 lastrbc;
1245 u8 hi, lo;
1246 int err;
1247
1248 brcmf_err("%sterminate frame%s\n",
1249 abort ? "abort command, " : "",
1250 rtx ? ", send NAK" : "");
1251
1252 if (abort)
1253 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1254
1255 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1256 SFC_RF_TERM, &err);
1257 bus->sdcnt.f1regdata++;
1258
1259 /* Wait until the packet has been flushed (device/FIFO stable) */
1260 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1261 hi = brcmf_sdiod_regrb(bus->sdiodev,
1262 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1263 lo = brcmf_sdiod_regrb(bus->sdiodev,
1264 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1265 bus->sdcnt.f1regdata += 2;
1266
1267 if ((hi == 0) && (lo == 0))
1268 break;
1269
1270 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1271 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1272 lastrbc, (hi << 8) + lo);
1273 }
1274 lastrbc = (hi << 8) + lo;
1275 }
1276
1277 if (!retries)
1278 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1279 else
1280 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1281
1282 if (rtx) {
1283 bus->sdcnt.rxrtx++;
1284 err = w_sdreg32(bus, SMB_NAK,
1285 offsetof(struct sdpcmd_regs, tosbmailbox));
1286
1287 bus->sdcnt.f1regdata++;
1288 if (err == 0)
1289 bus->rxskip = true;
1290 }
1291
1292 /* Clear partial in any case */
1293 bus->cur_read.len = 0;
1294 }
1295
1296 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1297 {
1298 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1299 u8 i, hi, lo;
1300
1301 /* On failure, abort the command and terminate the frame */
1302 brcmf_err("sdio error, abort command and terminate frame\n");
1303 bus->sdcnt.tx_sderrs++;
1304
1305 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1306 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1307 bus->sdcnt.f1regdata++;
1308
1309 for (i = 0; i < 3; i++) {
1310 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1311 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1312 bus->sdcnt.f1regdata += 2;
1313 if ((hi == 0) && (lo == 0))
1314 break;
1315 }
1316 }
1317
1318 /* return total length of buffer chain */
1319 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1320 {
1321 struct sk_buff *p;
1322 uint total;
1323
1324 total = 0;
1325 skb_queue_walk(&bus->glom, p)
1326 total += p->len;
1327 return total;
1328 }
1329
1330 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1331 {
1332 struct sk_buff *cur, *next;
1333
1334 skb_queue_walk_safe(&bus->glom, cur, next) {
1335 skb_unlink(cur, &bus->glom);
1336 brcmu_pkt_buf_free_skb(cur);
1337 }
1338 }
1339
1340 /**
1341 * brcmfmac sdio bus specific header
1342 * This is the lowest layer header wrapped on the packets transmitted between
1343 * host and WiFi dongle which contains information needed for SDIO core and
1344 * firmware
1345 *
1346 * It consists of 3 parts: hardware header, hardware extension header and
1347 * software header
1348 * hardware header (frame tag) - 4 bytes
1349 * Byte 0~1: Frame length
1350 * Byte 2~3: Checksum, bit-wise inverse of frame length
1351 * hardware extension header - 8 bytes
1352 * Tx glom mode only, N/A for Rx or normal Tx
1353 * Byte 0~1: Packet length excluding hw frame tag
1354 * Byte 2: Reserved
1355 * Byte 3: Frame flags, bit 0: last frame indication
1356 * Byte 4~5: Reserved
1357 * Byte 6~7: Tail padding length
1358 * software header - 8 bytes
1359 * Byte 0: Rx/Tx sequence number
1360 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1361 * Byte 2: Length of next data frame, reserved for Tx
1362 * Byte 3: Data offset
1363 * Byte 4: Flow control bits, reserved for Tx
1364 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1365 * Byte 6~7: Reserved
1366 */
1367 #define SDPCM_HWHDR_LEN 4
1368 #define SDPCM_HWEXT_LEN 8
1369 #define SDPCM_SWHDR_LEN 8
1370 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1371 /* software header */
1372 #define SDPCM_SEQ_MASK 0x000000ff
1373 #define SDPCM_SEQ_WRAP 256
1374 #define SDPCM_CHANNEL_MASK 0x00000f00
1375 #define SDPCM_CHANNEL_SHIFT 8
1376 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1377 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1378 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1379 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1380 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1381 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1382 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1383 #define SDPCM_NEXTLEN_SHIFT 16
1384 #define SDPCM_DOFFSET_MASK 0xff000000
1385 #define SDPCM_DOFFSET_SHIFT 24
1386 #define SDPCM_FCMASK_MASK 0x000000ff
1387 #define SDPCM_WINDOW_MASK 0x0000ff00
1388 #define SDPCM_WINDOW_SHIFT 8
1389
1390 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1391 {
1392 u32 hdrvalue;
1393 hdrvalue = *(u32 *)swheader;
1394 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1395 }
1396
1397 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1398 struct brcmf_sdio_hdrinfo *rd,
1399 enum brcmf_sdio_frmtype type)
1400 {
1401 u16 len, checksum;
1402 u8 rx_seq, fc, tx_seq_max;
1403 u32 swheader;
1404
1405 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1406
1407 /* hw header */
1408 len = get_unaligned_le16(header);
1409 checksum = get_unaligned_le16(header + sizeof(u16));
1410 /* All zero means no more to read */
1411 if (!(len | checksum)) {
1412 bus->rxpending = false;
1413 return -ENODATA;
1414 }
1415 if ((u16)(~(len ^ checksum))) {
1416 brcmf_err("HW header checksum error\n");
1417 bus->sdcnt.rx_badhdr++;
1418 brcmf_sdio_rxfail(bus, false, false);
1419 return -EIO;
1420 }
1421 if (len < SDPCM_HDRLEN) {
1422 brcmf_err("HW header length error\n");
1423 return -EPROTO;
1424 }
1425 if (type == BRCMF_SDIO_FT_SUPER &&
1426 (roundup(len, bus->blocksize) != rd->len)) {
1427 brcmf_err("HW superframe header length error\n");
1428 return -EPROTO;
1429 }
1430 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1431 brcmf_err("HW subframe header length error\n");
1432 return -EPROTO;
1433 }
1434 rd->len = len;
1435
1436 /* software header */
1437 header += SDPCM_HWHDR_LEN;
1438 swheader = le32_to_cpu(*(__le32 *)header);
1439 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1440 brcmf_err("Glom descriptor found in superframe head\n");
1441 rd->len = 0;
1442 return -EINVAL;
1443 }
1444 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1445 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1446 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1447 type != BRCMF_SDIO_FT_SUPER) {
1448 brcmf_err("HW header length too long\n");
1449 bus->sdcnt.rx_toolong++;
1450 brcmf_sdio_rxfail(bus, false, false);
1451 rd->len = 0;
1452 return -EPROTO;
1453 }
1454 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1455 brcmf_err("Wrong channel for superframe\n");
1456 rd->len = 0;
1457 return -EINVAL;
1458 }
1459 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1460 rd->channel != SDPCM_EVENT_CHANNEL) {
1461 brcmf_err("Wrong channel for subframe\n");
1462 rd->len = 0;
1463 return -EINVAL;
1464 }
1465 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1466 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1467 brcmf_err("seq %d: bad data offset\n", rx_seq);
1468 bus->sdcnt.rx_badhdr++;
1469 brcmf_sdio_rxfail(bus, false, false);
1470 rd->len = 0;
1471 return -ENXIO;
1472 }
1473 if (rd->seq_num != rx_seq) {
1474 brcmf_err("seq %d: sequence number error, expect %d\n",
1475 rx_seq, rd->seq_num);
1476 bus->sdcnt.rx_badseq++;
1477 rd->seq_num = rx_seq;
1478 }
1479 /* no need to check the reset for subframe */
1480 if (type == BRCMF_SDIO_FT_SUB)
1481 return 0;
1482 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1483 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1484 /* only warm for NON glom packet */
1485 if (rd->channel != SDPCM_GLOM_CHANNEL)
1486 brcmf_err("seq %d: next length error\n", rx_seq);
1487 rd->len_nxtfrm = 0;
1488 }
1489 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1490 fc = swheader & SDPCM_FCMASK_MASK;
1491 if (bus->flowcontrol != fc) {
1492 if (~bus->flowcontrol & fc)
1493 bus->sdcnt.fc_xoff++;
1494 if (bus->flowcontrol & ~fc)
1495 bus->sdcnt.fc_xon++;
1496 bus->sdcnt.fc_rcvd++;
1497 bus->flowcontrol = fc;
1498 }
1499 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1500 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1501 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1502 tx_seq_max = bus->tx_seq + 2;
1503 }
1504 bus->tx_max = tx_seq_max;
1505
1506 return 0;
1507 }
1508
1509 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1510 {
1511 *(__le16 *)header = cpu_to_le16(frm_length);
1512 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1513 }
1514
1515 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1516 struct brcmf_sdio_hdrinfo *hd_info)
1517 {
1518 u32 hdrval;
1519 u8 hdr_offset;
1520
1521 brcmf_sdio_update_hwhdr(header, hd_info->len);
1522 hdr_offset = SDPCM_HWHDR_LEN;
1523
1524 if (bus->txglom) {
1525 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1526 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1527 hdrval = (u16)hd_info->tail_pad << 16;
1528 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1529 hdr_offset += SDPCM_HWEXT_LEN;
1530 }
1531
1532 hdrval = hd_info->seq_num;
1533 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1534 SDPCM_CHANNEL_MASK;
1535 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1536 SDPCM_DOFFSET_MASK;
1537 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1538 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1539 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1540 }
1541
1542 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1543 {
1544 u16 dlen, totlen;
1545 u8 *dptr, num = 0;
1546 u16 sublen;
1547 struct sk_buff *pfirst, *pnext;
1548
1549 int errcode;
1550 u8 doff, sfdoff;
1551
1552 struct brcmf_sdio_hdrinfo rd_new;
1553
1554 /* If packets, issue read(s) and send up packet chain */
1555 /* Return sequence numbers consumed? */
1556
1557 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1558 bus->glomd, skb_peek(&bus->glom));
1559
1560 /* If there's a descriptor, generate the packet chain */
1561 if (bus->glomd) {
1562 pfirst = pnext = NULL;
1563 dlen = (u16) (bus->glomd->len);
1564 dptr = bus->glomd->data;
1565 if (!dlen || (dlen & 1)) {
1566 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1567 dlen);
1568 dlen = 0;
1569 }
1570
1571 for (totlen = num = 0; dlen; num++) {
1572 /* Get (and move past) next length */
1573 sublen = get_unaligned_le16(dptr);
1574 dlen -= sizeof(u16);
1575 dptr += sizeof(u16);
1576 if ((sublen < SDPCM_HDRLEN) ||
1577 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1578 brcmf_err("descriptor len %d bad: %d\n",
1579 num, sublen);
1580 pnext = NULL;
1581 break;
1582 }
1583 if (sublen % bus->sgentry_align) {
1584 brcmf_err("sublen %d not multiple of %d\n",
1585 sublen, bus->sgentry_align);
1586 }
1587 totlen += sublen;
1588
1589 /* For last frame, adjust read len so total
1590 is a block multiple */
1591 if (!dlen) {
1592 sublen +=
1593 (roundup(totlen, bus->blocksize) - totlen);
1594 totlen = roundup(totlen, bus->blocksize);
1595 }
1596
1597 /* Allocate/chain packet for next subframe */
1598 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1599 if (pnext == NULL) {
1600 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1601 num, sublen);
1602 break;
1603 }
1604 skb_queue_tail(&bus->glom, pnext);
1605
1606 /* Adhere to start alignment requirements */
1607 pkt_align(pnext, sublen, bus->sgentry_align);
1608 }
1609
1610 /* If all allocations succeeded, save packet chain
1611 in bus structure */
1612 if (pnext) {
1613 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1614 totlen, num);
1615 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1616 totlen != bus->cur_read.len) {
1617 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1618 bus->cur_read.len, totlen, rxseq);
1619 }
1620 pfirst = pnext = NULL;
1621 } else {
1622 brcmf_sdio_free_glom(bus);
1623 num = 0;
1624 }
1625
1626 /* Done with descriptor packet */
1627 brcmu_pkt_buf_free_skb(bus->glomd);
1628 bus->glomd = NULL;
1629 bus->cur_read.len = 0;
1630 }
1631
1632 /* Ok -- either we just generated a packet chain,
1633 or had one from before */
1634 if (!skb_queue_empty(&bus->glom)) {
1635 if (BRCMF_GLOM_ON()) {
1636 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1637 skb_queue_walk(&bus->glom, pnext) {
1638 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1639 pnext, (u8 *) (pnext->data),
1640 pnext->len, pnext->len);
1641 }
1642 }
1643
1644 pfirst = skb_peek(&bus->glom);
1645 dlen = (u16) brcmf_sdio_glom_len(bus);
1646
1647 /* Do an SDIO read for the superframe. Configurable iovar to
1648 * read directly into the chained packet, or allocate a large
1649 * packet and and copy into the chain.
1650 */
1651 sdio_claim_host(bus->sdiodev->func[1]);
1652 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1653 &bus->glom, dlen);
1654 sdio_release_host(bus->sdiodev->func[1]);
1655 bus->sdcnt.f2rxdata++;
1656
1657 /* On failure, kill the superframe, allow a couple retries */
1658 if (errcode < 0) {
1659 brcmf_err("glom read of %d bytes failed: %d\n",
1660 dlen, errcode);
1661
1662 sdio_claim_host(bus->sdiodev->func[1]);
1663 if (bus->glomerr++ < 3) {
1664 brcmf_sdio_rxfail(bus, true, true);
1665 } else {
1666 bus->glomerr = 0;
1667 brcmf_sdio_rxfail(bus, true, false);
1668 bus->sdcnt.rxglomfail++;
1669 brcmf_sdio_free_glom(bus);
1670 }
1671 sdio_release_host(bus->sdiodev->func[1]);
1672 return 0;
1673 }
1674
1675 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1676 pfirst->data, min_t(int, pfirst->len, 48),
1677 "SUPERFRAME:\n");
1678
1679 rd_new.seq_num = rxseq;
1680 rd_new.len = dlen;
1681 sdio_claim_host(bus->sdiodev->func[1]);
1682 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1683 BRCMF_SDIO_FT_SUPER);
1684 sdio_release_host(bus->sdiodev->func[1]);
1685 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1686
1687 /* Remove superframe header, remember offset */
1688 skb_pull(pfirst, rd_new.dat_offset);
1689 sfdoff = rd_new.dat_offset;
1690 num = 0;
1691
1692 /* Validate all the subframe headers */
1693 skb_queue_walk(&bus->glom, pnext) {
1694 /* leave when invalid subframe is found */
1695 if (errcode)
1696 break;
1697
1698 rd_new.len = pnext->len;
1699 rd_new.seq_num = rxseq++;
1700 sdio_claim_host(bus->sdiodev->func[1]);
1701 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1702 BRCMF_SDIO_FT_SUB);
1703 sdio_release_host(bus->sdiodev->func[1]);
1704 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1705 pnext->data, 32, "subframe:\n");
1706
1707 num++;
1708 }
1709
1710 if (errcode) {
1711 /* Terminate frame on error, request
1712 a couple retries */
1713 sdio_claim_host(bus->sdiodev->func[1]);
1714 if (bus->glomerr++ < 3) {
1715 /* Restore superframe header space */
1716 skb_push(pfirst, sfdoff);
1717 brcmf_sdio_rxfail(bus, true, true);
1718 } else {
1719 bus->glomerr = 0;
1720 brcmf_sdio_rxfail(bus, true, false);
1721 bus->sdcnt.rxglomfail++;
1722 brcmf_sdio_free_glom(bus);
1723 }
1724 sdio_release_host(bus->sdiodev->func[1]);
1725 bus->cur_read.len = 0;
1726 return 0;
1727 }
1728
1729 /* Basic SD framing looks ok - process each packet (header) */
1730
1731 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1732 dptr = (u8 *) (pfirst->data);
1733 sublen = get_unaligned_le16(dptr);
1734 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1735
1736 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1737 dptr, pfirst->len,
1738 "Rx Subframe Data:\n");
1739
1740 __skb_trim(pfirst, sublen);
1741 skb_pull(pfirst, doff);
1742
1743 if (pfirst->len == 0) {
1744 skb_unlink(pfirst, &bus->glom);
1745 brcmu_pkt_buf_free_skb(pfirst);
1746 continue;
1747 }
1748
1749 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1750 pfirst->data,
1751 min_t(int, pfirst->len, 32),
1752 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1753 bus->glom.qlen, pfirst, pfirst->data,
1754 pfirst->len, pfirst->next,
1755 pfirst->prev);
1756 skb_unlink(pfirst, &bus->glom);
1757 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1758 bus->sdcnt.rxglompkts++;
1759 }
1760
1761 bus->sdcnt.rxglomframes++;
1762 }
1763 return num;
1764 }
1765
1766 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1767 bool *pending)
1768 {
1769 DECLARE_WAITQUEUE(wait, current);
1770 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1771
1772 /* Wait until control frame is available */
1773 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1774 set_current_state(TASK_INTERRUPTIBLE);
1775
1776 while (!(*condition) && (!signal_pending(current) && timeout))
1777 timeout = schedule_timeout(timeout);
1778
1779 if (signal_pending(current))
1780 *pending = true;
1781
1782 set_current_state(TASK_RUNNING);
1783 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1784
1785 return timeout;
1786 }
1787
1788 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1789 {
1790 if (waitqueue_active(&bus->dcmd_resp_wait))
1791 wake_up_interruptible(&bus->dcmd_resp_wait);
1792
1793 return 0;
1794 }
1795 static void
1796 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1797 {
1798 uint rdlen, pad;
1799 u8 *buf = NULL, *rbuf;
1800 int sdret;
1801
1802 brcmf_dbg(TRACE, "Enter\n");
1803
1804 if (bus->rxblen)
1805 buf = vzalloc(bus->rxblen);
1806 if (!buf)
1807 goto done;
1808
1809 rbuf = bus->rxbuf;
1810 pad = ((unsigned long)rbuf % bus->head_align);
1811 if (pad)
1812 rbuf += (bus->head_align - pad);
1813
1814 /* Copy the already-read portion over */
1815 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1816 if (len <= BRCMF_FIRSTREAD)
1817 goto gotpkt;
1818
1819 /* Raise rdlen to next SDIO block to avoid tail command */
1820 rdlen = len - BRCMF_FIRSTREAD;
1821 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1822 pad = bus->blocksize - (rdlen % bus->blocksize);
1823 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1824 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1825 rdlen += pad;
1826 } else if (rdlen % bus->head_align) {
1827 rdlen += bus->head_align - (rdlen % bus->head_align);
1828 }
1829
1830 /* Drop if the read is too big or it exceeds our maximum */
1831 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1832 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1833 rdlen, bus->sdiodev->bus_if->maxctl);
1834 brcmf_sdio_rxfail(bus, false, false);
1835 goto done;
1836 }
1837
1838 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1839 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1840 len, len - doff, bus->sdiodev->bus_if->maxctl);
1841 bus->sdcnt.rx_toolong++;
1842 brcmf_sdio_rxfail(bus, false, false);
1843 goto done;
1844 }
1845
1846 /* Read remain of frame body */
1847 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1848 bus->sdcnt.f2rxdata++;
1849
1850 /* Control frame failures need retransmission */
1851 if (sdret < 0) {
1852 brcmf_err("read %d control bytes failed: %d\n",
1853 rdlen, sdret);
1854 bus->sdcnt.rxc_errors++;
1855 brcmf_sdio_rxfail(bus, true, true);
1856 goto done;
1857 } else
1858 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1859
1860 gotpkt:
1861
1862 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1863 buf, len, "RxCtrl:\n");
1864
1865 /* Point to valid data and indicate its length */
1866 spin_lock_bh(&bus->rxctl_lock);
1867 if (bus->rxctl) {
1868 brcmf_err("last control frame is being processed.\n");
1869 spin_unlock_bh(&bus->rxctl_lock);
1870 vfree(buf);
1871 goto done;
1872 }
1873 bus->rxctl = buf + doff;
1874 bus->rxctl_orig = buf;
1875 bus->rxlen = len - doff;
1876 spin_unlock_bh(&bus->rxctl_lock);
1877
1878 done:
1879 /* Awake any waiters */
1880 brcmf_sdio_dcmd_resp_wake(bus);
1881 }
1882
1883 /* Pad read to blocksize for efficiency */
1884 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1885 {
1886 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1887 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1888 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1889 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1890 *rdlen += *pad;
1891 } else if (*rdlen % bus->head_align) {
1892 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1893 }
1894 }
1895
1896 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1897 {
1898 struct sk_buff *pkt; /* Packet for event or data frames */
1899 u16 pad; /* Number of pad bytes to read */
1900 uint rxleft = 0; /* Remaining number of frames allowed */
1901 int ret; /* Return code from calls */
1902 uint rxcount = 0; /* Total frames read */
1903 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1904 u8 head_read = 0;
1905
1906 brcmf_dbg(TRACE, "Enter\n");
1907
1908 /* Not finished unless we encounter no more frames indication */
1909 bus->rxpending = true;
1910
1911 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1912 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_STATE_DATA;
1913 rd->seq_num++, rxleft--) {
1914
1915 /* Handle glomming separately */
1916 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1917 u8 cnt;
1918 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1919 bus->glomd, skb_peek(&bus->glom));
1920 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1921 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1922 rd->seq_num += cnt - 1;
1923 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1924 continue;
1925 }
1926
1927 rd->len_left = rd->len;
1928 /* read header first for unknow frame length */
1929 sdio_claim_host(bus->sdiodev->func[1]);
1930 if (!rd->len) {
1931 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1932 bus->rxhdr, BRCMF_FIRSTREAD);
1933 bus->sdcnt.f2rxhdrs++;
1934 if (ret < 0) {
1935 brcmf_err("RXHEADER FAILED: %d\n",
1936 ret);
1937 bus->sdcnt.rx_hdrfail++;
1938 brcmf_sdio_rxfail(bus, true, true);
1939 sdio_release_host(bus->sdiodev->func[1]);
1940 continue;
1941 }
1942
1943 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1944 bus->rxhdr, SDPCM_HDRLEN,
1945 "RxHdr:\n");
1946
1947 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1948 BRCMF_SDIO_FT_NORMAL)) {
1949 sdio_release_host(bus->sdiodev->func[1]);
1950 if (!bus->rxpending)
1951 break;
1952 else
1953 continue;
1954 }
1955
1956 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1957 brcmf_sdio_read_control(bus, bus->rxhdr,
1958 rd->len,
1959 rd->dat_offset);
1960 /* prepare the descriptor for the next read */
1961 rd->len = rd->len_nxtfrm << 4;
1962 rd->len_nxtfrm = 0;
1963 /* treat all packet as event if we don't know */
1964 rd->channel = SDPCM_EVENT_CHANNEL;
1965 sdio_release_host(bus->sdiodev->func[1]);
1966 continue;
1967 }
1968 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1969 rd->len - BRCMF_FIRSTREAD : 0;
1970 head_read = BRCMF_FIRSTREAD;
1971 }
1972
1973 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1974
1975 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1976 bus->head_align);
1977 if (!pkt) {
1978 /* Give up on data, request rtx of events */
1979 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1980 brcmf_sdio_rxfail(bus, false,
1981 RETRYCHAN(rd->channel));
1982 sdio_release_host(bus->sdiodev->func[1]);
1983 continue;
1984 }
1985 skb_pull(pkt, head_read);
1986 pkt_align(pkt, rd->len_left, bus->head_align);
1987
1988 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1989 bus->sdcnt.f2rxdata++;
1990 sdio_release_host(bus->sdiodev->func[1]);
1991
1992 if (ret < 0) {
1993 brcmf_err("read %d bytes from channel %d failed: %d\n",
1994 rd->len, rd->channel, ret);
1995 brcmu_pkt_buf_free_skb(pkt);
1996 sdio_claim_host(bus->sdiodev->func[1]);
1997 brcmf_sdio_rxfail(bus, true,
1998 RETRYCHAN(rd->channel));
1999 sdio_release_host(bus->sdiodev->func[1]);
2000 continue;
2001 }
2002
2003 if (head_read) {
2004 skb_push(pkt, head_read);
2005 memcpy(pkt->data, bus->rxhdr, head_read);
2006 head_read = 0;
2007 } else {
2008 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
2009 rd_new.seq_num = rd->seq_num;
2010 sdio_claim_host(bus->sdiodev->func[1]);
2011 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
2012 BRCMF_SDIO_FT_NORMAL)) {
2013 rd->len = 0;
2014 brcmu_pkt_buf_free_skb(pkt);
2015 }
2016 bus->sdcnt.rx_readahead_cnt++;
2017 if (rd->len != roundup(rd_new.len, 16)) {
2018 brcmf_err("frame length mismatch:read %d, should be %d\n",
2019 rd->len,
2020 roundup(rd_new.len, 16) >> 4);
2021 rd->len = 0;
2022 brcmf_sdio_rxfail(bus, true, true);
2023 sdio_release_host(bus->sdiodev->func[1]);
2024 brcmu_pkt_buf_free_skb(pkt);
2025 continue;
2026 }
2027 sdio_release_host(bus->sdiodev->func[1]);
2028 rd->len_nxtfrm = rd_new.len_nxtfrm;
2029 rd->channel = rd_new.channel;
2030 rd->dat_offset = rd_new.dat_offset;
2031
2032 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2033 BRCMF_DATA_ON()) &&
2034 BRCMF_HDRS_ON(),
2035 bus->rxhdr, SDPCM_HDRLEN,
2036 "RxHdr:\n");
2037
2038 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2039 brcmf_err("readahead on control packet %d?\n",
2040 rd_new.seq_num);
2041 /* Force retry w/normal header read */
2042 rd->len = 0;
2043 sdio_claim_host(bus->sdiodev->func[1]);
2044 brcmf_sdio_rxfail(bus, false, true);
2045 sdio_release_host(bus->sdiodev->func[1]);
2046 brcmu_pkt_buf_free_skb(pkt);
2047 continue;
2048 }
2049 }
2050
2051 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2052 pkt->data, rd->len, "Rx Data:\n");
2053
2054 /* Save superframe descriptor and allocate packet frame */
2055 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2056 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2057 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2058 rd->len);
2059 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2060 pkt->data, rd->len,
2061 "Glom Data:\n");
2062 __skb_trim(pkt, rd->len);
2063 skb_pull(pkt, SDPCM_HDRLEN);
2064 bus->glomd = pkt;
2065 } else {
2066 brcmf_err("%s: glom superframe w/o "
2067 "descriptor!\n", __func__);
2068 sdio_claim_host(bus->sdiodev->func[1]);
2069 brcmf_sdio_rxfail(bus, false, false);
2070 sdio_release_host(bus->sdiodev->func[1]);
2071 }
2072 /* prepare the descriptor for the next read */
2073 rd->len = rd->len_nxtfrm << 4;
2074 rd->len_nxtfrm = 0;
2075 /* treat all packet as event if we don't know */
2076 rd->channel = SDPCM_EVENT_CHANNEL;
2077 continue;
2078 }
2079
2080 /* Fill in packet len and prio, deliver upward */
2081 __skb_trim(pkt, rd->len);
2082 skb_pull(pkt, rd->dat_offset);
2083
2084 /* prepare the descriptor for the next read */
2085 rd->len = rd->len_nxtfrm << 4;
2086 rd->len_nxtfrm = 0;
2087 /* treat all packet as event if we don't know */
2088 rd->channel = SDPCM_EVENT_CHANNEL;
2089
2090 if (pkt->len == 0) {
2091 brcmu_pkt_buf_free_skb(pkt);
2092 continue;
2093 }
2094
2095 brcmf_rx_frame(bus->sdiodev->dev, pkt);
2096 }
2097
2098 rxcount = maxframes - rxleft;
2099 /* Message if we hit the limit */
2100 if (!rxleft)
2101 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2102 else
2103 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2104 /* Back off rxseq if awaiting rtx, update rx_seq */
2105 if (bus->rxskip)
2106 rd->seq_num--;
2107 bus->rx_seq = rd->seq_num;
2108
2109 return rxcount;
2110 }
2111
2112 static void
2113 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2114 {
2115 if (waitqueue_active(&bus->ctrl_wait))
2116 wake_up_interruptible(&bus->ctrl_wait);
2117 return;
2118 }
2119
2120 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2121 {
2122 u16 head_pad;
2123 u8 *dat_buf;
2124
2125 dat_buf = (u8 *)(pkt->data);
2126
2127 /* Check head padding */
2128 head_pad = ((unsigned long)dat_buf % bus->head_align);
2129 if (head_pad) {
2130 if (skb_headroom(pkt) < head_pad) {
2131 bus->sdiodev->bus_if->tx_realloc++;
2132 head_pad = 0;
2133 if (skb_cow(pkt, head_pad))
2134 return -ENOMEM;
2135 }
2136 skb_push(pkt, head_pad);
2137 dat_buf = (u8 *)(pkt->data);
2138 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2139 }
2140 return head_pad;
2141 }
2142
2143 /**
2144 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2145 * bus layer usage.
2146 */
2147 /* flag marking a dummy skb added for DMA alignment requirement */
2148 #define ALIGN_SKB_FLAG 0x8000
2149 /* bit mask of data length chopped from the previous packet */
2150 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2151
2152 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2153 struct sk_buff_head *pktq,
2154 struct sk_buff *pkt, u16 total_len)
2155 {
2156 struct brcmf_sdio_dev *sdiodev;
2157 struct sk_buff *pkt_pad;
2158 u16 tail_pad, tail_chop, chain_pad;
2159 unsigned int blksize;
2160 bool lastfrm;
2161 int ntail, ret;
2162
2163 sdiodev = bus->sdiodev;
2164 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2165 /* sg entry alignment should be a divisor of block size */
2166 WARN_ON(blksize % bus->sgentry_align);
2167
2168 /* Check tail padding */
2169 lastfrm = skb_queue_is_last(pktq, pkt);
2170 tail_pad = 0;
2171 tail_chop = pkt->len % bus->sgentry_align;
2172 if (tail_chop)
2173 tail_pad = bus->sgentry_align - tail_chop;
2174 chain_pad = (total_len + tail_pad) % blksize;
2175 if (lastfrm && chain_pad)
2176 tail_pad += blksize - chain_pad;
2177 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2178 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2179 bus->head_align);
2180 if (pkt_pad == NULL)
2181 return -ENOMEM;
2182 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2183 if (unlikely(ret < 0)) {
2184 kfree_skb(pkt_pad);
2185 return ret;
2186 }
2187 memcpy(pkt_pad->data,
2188 pkt->data + pkt->len - tail_chop,
2189 tail_chop);
2190 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2191 skb_trim(pkt, pkt->len - tail_chop);
2192 skb_trim(pkt_pad, tail_pad + tail_chop);
2193 __skb_queue_after(pktq, pkt, pkt_pad);
2194 } else {
2195 ntail = pkt->data_len + tail_pad -
2196 (pkt->end - pkt->tail);
2197 if (skb_cloned(pkt) || ntail > 0)
2198 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2199 return -ENOMEM;
2200 if (skb_linearize(pkt))
2201 return -ENOMEM;
2202 __skb_put(pkt, tail_pad);
2203 }
2204
2205 return tail_pad;
2206 }
2207
2208 /**
2209 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2210 * @bus: brcmf_sdio structure pointer
2211 * @pktq: packet list pointer
2212 * @chan: virtual channel to transmit the packet
2213 *
2214 * Processes to be applied to the packet
2215 * - Align data buffer pointer
2216 * - Align data buffer length
2217 * - Prepare header
2218 * Return: negative value if there is error
2219 */
2220 static int
2221 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2222 uint chan)
2223 {
2224 u16 head_pad, total_len;
2225 struct sk_buff *pkt_next;
2226 u8 txseq;
2227 int ret;
2228 struct brcmf_sdio_hdrinfo hd_info = {0};
2229
2230 txseq = bus->tx_seq;
2231 total_len = 0;
2232 skb_queue_walk(pktq, pkt_next) {
2233 /* alignment packet inserted in previous
2234 * loop cycle can be skipped as it is
2235 * already properly aligned and does not
2236 * need an sdpcm header.
2237 */
2238 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2239 continue;
2240
2241 /* align packet data pointer */
2242 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2243 if (ret < 0)
2244 return ret;
2245 head_pad = (u16)ret;
2246 if (head_pad)
2247 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2248
2249 total_len += pkt_next->len;
2250
2251 hd_info.len = pkt_next->len;
2252 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2253 if (bus->txglom && pktq->qlen > 1) {
2254 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2255 pkt_next, total_len);
2256 if (ret < 0)
2257 return ret;
2258 hd_info.tail_pad = (u16)ret;
2259 total_len += (u16)ret;
2260 }
2261
2262 hd_info.channel = chan;
2263 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2264 hd_info.seq_num = txseq++;
2265
2266 /* Now fill the header */
2267 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2268
2269 if (BRCMF_BYTES_ON() &&
2270 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2271 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2272 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2273 "Tx Frame:\n");
2274 else if (BRCMF_HDRS_ON())
2275 brcmf_dbg_hex_dump(true, pkt_next->data,
2276 head_pad + bus->tx_hdrlen,
2277 "Tx Header:\n");
2278 }
2279 /* Hardware length tag of the first packet should be total
2280 * length of the chain (including padding)
2281 */
2282 if (bus->txglom)
2283 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2284 return 0;
2285 }
2286
2287 /**
2288 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2289 * @bus: brcmf_sdio structure pointer
2290 * @pktq: packet list pointer
2291 *
2292 * Processes to be applied to the packet
2293 * - Remove head padding
2294 * - Remove tail padding
2295 */
2296 static void
2297 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2298 {
2299 u8 *hdr;
2300 u32 dat_offset;
2301 u16 tail_pad;
2302 u16 dummy_flags, chop_len;
2303 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2304
2305 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2306 dummy_flags = *(u16 *)(pkt_next->cb);
2307 if (dummy_flags & ALIGN_SKB_FLAG) {
2308 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2309 if (chop_len) {
2310 pkt_prev = pkt_next->prev;
2311 skb_put(pkt_prev, chop_len);
2312 }
2313 __skb_unlink(pkt_next, pktq);
2314 brcmu_pkt_buf_free_skb(pkt_next);
2315 } else {
2316 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2317 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2318 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2319 SDPCM_DOFFSET_SHIFT;
2320 skb_pull(pkt_next, dat_offset);
2321 if (bus->txglom) {
2322 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2323 skb_trim(pkt_next, pkt_next->len - tail_pad);
2324 }
2325 }
2326 }
2327 }
2328
2329 /* Writes a HW/SW header into the packet and sends it. */
2330 /* Assumes: (a) header space already there, (b) caller holds lock */
2331 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2332 uint chan)
2333 {
2334 int ret;
2335 struct sk_buff *pkt_next, *tmp;
2336
2337 brcmf_dbg(TRACE, "Enter\n");
2338
2339 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2340 if (ret)
2341 goto done;
2342
2343 sdio_claim_host(bus->sdiodev->func[1]);
2344 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2345 bus->sdcnt.f2txdata++;
2346
2347 if (ret < 0)
2348 brcmf_sdio_txfail(bus);
2349
2350 sdio_release_host(bus->sdiodev->func[1]);
2351
2352 done:
2353 brcmf_sdio_txpkt_postp(bus, pktq);
2354 if (ret == 0)
2355 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2356 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2357 __skb_unlink(pkt_next, pktq);
2358 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2359 }
2360 return ret;
2361 }
2362
2363 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2364 {
2365 struct sk_buff *pkt;
2366 struct sk_buff_head pktq;
2367 u32 intstatus = 0;
2368 int ret = 0, prec_out, i;
2369 uint cnt = 0;
2370 u8 tx_prec_map, pkt_num;
2371
2372 brcmf_dbg(TRACE, "Enter\n");
2373
2374 tx_prec_map = ~bus->flowcontrol;
2375
2376 /* Send frames until the limit or some other event */
2377 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2378 pkt_num = 1;
2379 if (bus->txglom)
2380 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2381 bus->sdiodev->txglomsz);
2382 pkt_num = min_t(u32, pkt_num,
2383 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2384 __skb_queue_head_init(&pktq);
2385 spin_lock_bh(&bus->txq_lock);
2386 for (i = 0; i < pkt_num; i++) {
2387 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2388 &prec_out);
2389 if (pkt == NULL)
2390 break;
2391 __skb_queue_tail(&pktq, pkt);
2392 }
2393 spin_unlock_bh(&bus->txq_lock);
2394 if (i == 0)
2395 break;
2396
2397 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2398
2399 cnt += i;
2400
2401 /* In poll mode, need to check for other events */
2402 if (!bus->intr) {
2403 /* Check device status, signal pending interrupt */
2404 sdio_claim_host(bus->sdiodev->func[1]);
2405 ret = r_sdreg32(bus, &intstatus,
2406 offsetof(struct sdpcmd_regs,
2407 intstatus));
2408 sdio_release_host(bus->sdiodev->func[1]);
2409 bus->sdcnt.f2txdata++;
2410 if (ret != 0)
2411 break;
2412 if (intstatus & bus->hostintmask)
2413 atomic_set(&bus->ipend, 1);
2414 }
2415 }
2416
2417 /* Deflow-control stack if needed */
2418 if ((bus->sdiodev->state == BRCMF_STATE_DATA) &&
2419 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2420 bus->txoff = false;
2421 brcmf_txflowblock(bus->sdiodev->dev, false);
2422 }
2423
2424 return cnt;
2425 }
2426
2427 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2428 {
2429 u8 doff;
2430 u16 pad;
2431 uint retries = 0;
2432 struct brcmf_sdio_hdrinfo hd_info = {0};
2433 int ret;
2434
2435 brcmf_dbg(TRACE, "Enter\n");
2436
2437 /* Back the pointer to make room for bus header */
2438 frame -= bus->tx_hdrlen;
2439 len += bus->tx_hdrlen;
2440
2441 /* Add alignment padding (optional for ctl frames) */
2442 doff = ((unsigned long)frame % bus->head_align);
2443 if (doff) {
2444 frame -= doff;
2445 len += doff;
2446 memset(frame + bus->tx_hdrlen, 0, doff);
2447 }
2448
2449 /* Round send length to next SDIO block */
2450 pad = 0;
2451 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2452 pad = bus->blocksize - (len % bus->blocksize);
2453 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2454 pad = 0;
2455 } else if (len % bus->head_align) {
2456 pad = bus->head_align - (len % bus->head_align);
2457 }
2458 len += pad;
2459
2460 hd_info.len = len - pad;
2461 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2462 hd_info.dat_offset = doff + bus->tx_hdrlen;
2463 hd_info.seq_num = bus->tx_seq;
2464 hd_info.lastfrm = true;
2465 hd_info.tail_pad = pad;
2466 brcmf_sdio_hdpack(bus, frame, &hd_info);
2467
2468 if (bus->txglom)
2469 brcmf_sdio_update_hwhdr(frame, len);
2470
2471 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2472 frame, len, "Tx Frame:\n");
2473 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2474 BRCMF_HDRS_ON(),
2475 frame, min_t(u16, len, 16), "TxHdr:\n");
2476
2477 do {
2478 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2479
2480 if (ret < 0)
2481 brcmf_sdio_txfail(bus);
2482 else
2483 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2484 } while (ret < 0 && retries++ < TXRETRIES);
2485
2486 return ret;
2487 }
2488
2489 static void brcmf_sdio_bus_stop(struct device *dev)
2490 {
2491 u32 local_hostintmask;
2492 u8 saveclk;
2493 int err;
2494 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2495 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2496 struct brcmf_sdio *bus = sdiodev->bus;
2497
2498 brcmf_dbg(TRACE, "Enter\n");
2499
2500 if (bus->watchdog_tsk) {
2501 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2502 kthread_stop(bus->watchdog_tsk);
2503 bus->watchdog_tsk = NULL;
2504 }
2505
2506 if (sdiodev->state != BRCMF_STATE_NOMEDIUM) {
2507 sdio_claim_host(sdiodev->func[1]);
2508
2509 /* Enable clock for device interrupts */
2510 brcmf_sdio_bus_sleep(bus, false, false);
2511
2512 /* Disable and clear interrupts at the chip level also */
2513 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2514 local_hostintmask = bus->hostintmask;
2515 bus->hostintmask = 0;
2516
2517 /* Force backplane clocks to assure F2 interrupt propagates */
2518 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2519 &err);
2520 if (!err)
2521 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2522 (saveclk | SBSDIO_FORCE_HT), &err);
2523 if (err)
2524 brcmf_err("Failed to force clock for F2: err %d\n",
2525 err);
2526
2527 /* Turn off the bus (F2), free any pending packets */
2528 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2529 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2530
2531 /* Clear any pending interrupts now that F2 is disabled */
2532 w_sdreg32(bus, local_hostintmask,
2533 offsetof(struct sdpcmd_regs, intstatus));
2534
2535 sdio_release_host(sdiodev->func[1]);
2536 }
2537 /* Clear the data packet queues */
2538 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2539
2540 /* Clear any held glomming stuff */
2541 brcmu_pkt_buf_free_skb(bus->glomd);
2542 brcmf_sdio_free_glom(bus);
2543
2544 /* Clear rx control and wake any waiters */
2545 spin_lock_bh(&bus->rxctl_lock);
2546 bus->rxlen = 0;
2547 spin_unlock_bh(&bus->rxctl_lock);
2548 brcmf_sdio_dcmd_resp_wake(bus);
2549
2550 /* Reset some F2 state stuff */
2551 bus->rxskip = false;
2552 bus->tx_seq = bus->rx_seq = 0;
2553 }
2554
2555 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2556 {
2557 unsigned long flags;
2558
2559 if (bus->sdiodev->oob_irq_requested) {
2560 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2561 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2562 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2563 bus->sdiodev->irq_en = true;
2564 }
2565 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2566 }
2567 }
2568
2569 static void atomic_orr(int val, atomic_t *v)
2570 {
2571 int old_val;
2572
2573 old_val = atomic_read(v);
2574 while (atomic_cmpxchg(v, old_val, val | old_val) != old_val)
2575 old_val = atomic_read(v);
2576 }
2577
2578 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2579 {
2580 struct brcmf_core *buscore;
2581 u32 addr;
2582 unsigned long val;
2583 int ret;
2584
2585 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2586 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2587
2588 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2589 bus->sdcnt.f1regdata++;
2590 if (ret != 0)
2591 return ret;
2592
2593 val &= bus->hostintmask;
2594 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2595
2596 /* Clear interrupts */
2597 if (val) {
2598 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2599 bus->sdcnt.f1regdata++;
2600 atomic_orr(val, &bus->intstatus);
2601 }
2602
2603 return ret;
2604 }
2605
2606 static int brcmf_sdio_pm_resume_wait(struct brcmf_sdio_dev *sdiodev)
2607 {
2608 #ifdef CONFIG_PM_SLEEP
2609 int retry;
2610
2611 /* Wait for possible resume to complete */
2612 retry = 0;
2613 while ((atomic_read(&sdiodev->suspend)) && (retry++ != 50))
2614 msleep(20);
2615 if (atomic_read(&sdiodev->suspend))
2616 return -EIO;
2617 #endif
2618 return 0;
2619 }
2620
2621 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2622 {
2623 u32 newstatus = 0;
2624 unsigned long intstatus;
2625 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2626 uint framecnt; /* Temporary counter of tx/rx frames */
2627 int err = 0;
2628
2629 brcmf_dbg(TRACE, "Enter\n");
2630
2631 if (brcmf_sdio_pm_resume_wait(bus->sdiodev))
2632 return;
2633
2634 sdio_claim_host(bus->sdiodev->func[1]);
2635
2636 /* If waiting for HTAVAIL, check status */
2637 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2638 u8 clkctl, devctl = 0;
2639
2640 #ifdef DEBUG
2641 /* Check for inconsistent device control */
2642 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2643 SBSDIO_DEVICE_CTL, &err);
2644 #endif /* DEBUG */
2645
2646 /* Read CSR, if clock on switch to AVAIL, else ignore */
2647 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2648 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2649
2650 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2651 devctl, clkctl);
2652
2653 if (SBSDIO_HTAV(clkctl)) {
2654 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2655 SBSDIO_DEVICE_CTL, &err);
2656 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2657 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2658 devctl, &err);
2659 bus->clkstate = CLK_AVAIL;
2660 }
2661 }
2662
2663 /* Make sure backplane clock is on */
2664 brcmf_sdio_bus_sleep(bus, false, true);
2665
2666 /* Pending interrupt indicates new device status */
2667 if (atomic_read(&bus->ipend) > 0) {
2668 atomic_set(&bus->ipend, 0);
2669 err = brcmf_sdio_intr_rstatus(bus);
2670 }
2671
2672 /* Start with leftover status bits */
2673 intstatus = atomic_xchg(&bus->intstatus, 0);
2674
2675 /* Handle flow-control change: read new state in case our ack
2676 * crossed another change interrupt. If change still set, assume
2677 * FC ON for safety, let next loop through do the debounce.
2678 */
2679 if (intstatus & I_HMB_FC_CHANGE) {
2680 intstatus &= ~I_HMB_FC_CHANGE;
2681 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2682 offsetof(struct sdpcmd_regs, intstatus));
2683
2684 err = r_sdreg32(bus, &newstatus,
2685 offsetof(struct sdpcmd_regs, intstatus));
2686 bus->sdcnt.f1regdata += 2;
2687 atomic_set(&bus->fcstate,
2688 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2689 intstatus |= (newstatus & bus->hostintmask);
2690 }
2691
2692 /* Handle host mailbox indication */
2693 if (intstatus & I_HMB_HOST_INT) {
2694 intstatus &= ~I_HMB_HOST_INT;
2695 intstatus |= brcmf_sdio_hostmail(bus);
2696 }
2697
2698 sdio_release_host(bus->sdiodev->func[1]);
2699
2700 /* Generally don't ask for these, can get CRC errors... */
2701 if (intstatus & I_WR_OOSYNC) {
2702 brcmf_err("Dongle reports WR_OOSYNC\n");
2703 intstatus &= ~I_WR_OOSYNC;
2704 }
2705
2706 if (intstatus & I_RD_OOSYNC) {
2707 brcmf_err("Dongle reports RD_OOSYNC\n");
2708 intstatus &= ~I_RD_OOSYNC;
2709 }
2710
2711 if (intstatus & I_SBINT) {
2712 brcmf_err("Dongle reports SBINT\n");
2713 intstatus &= ~I_SBINT;
2714 }
2715
2716 /* Would be active due to wake-wlan in gSPI */
2717 if (intstatus & I_CHIPACTIVE) {
2718 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2719 intstatus &= ~I_CHIPACTIVE;
2720 }
2721
2722 /* Ignore frame indications if rxskip is set */
2723 if (bus->rxskip)
2724 intstatus &= ~I_HMB_FRAME_IND;
2725
2726 /* On frame indication, read available frames */
2727 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2728 brcmf_sdio_readframes(bus, bus->rxbound);
2729 if (!bus->rxpending)
2730 intstatus &= ~I_HMB_FRAME_IND;
2731 }
2732
2733 /* Keep still-pending events for next scheduling */
2734 if (intstatus)
2735 atomic_orr(intstatus, &bus->intstatus);
2736
2737 brcmf_sdio_clrintr(bus);
2738
2739 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2740 data_ok(bus)) {
2741 sdio_claim_host(bus->sdiodev->func[1]);
2742 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2743 bus->ctrl_frame_len);
2744 sdio_release_host(bus->sdiodev->func[1]);
2745 bus->ctrl_frame_err = err;
2746 bus->ctrl_frame_stat = false;
2747 brcmf_sdio_wait_event_wakeup(bus);
2748 }
2749 /* Send queued frames (limit 1 if rx may still be pending) */
2750 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2751 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2752 data_ok(bus)) {
2753 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2754 txlimit;
2755 brcmf_sdio_sendfromq(bus, framecnt);
2756 }
2757
2758 if ((bus->sdiodev->state != BRCMF_STATE_DATA) || (err != 0)) {
2759 brcmf_err("failed backplane access over SDIO, halting operation\n");
2760 atomic_set(&bus->intstatus, 0);
2761 } else if (atomic_read(&bus->intstatus) ||
2762 atomic_read(&bus->ipend) > 0 ||
2763 (!atomic_read(&bus->fcstate) &&
2764 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2765 data_ok(bus))) {
2766 atomic_inc(&bus->dpc_tskcnt);
2767 }
2768 }
2769
2770 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2771 {
2772 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2773 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2774 struct brcmf_sdio *bus = sdiodev->bus;
2775
2776 return &bus->txq;
2777 }
2778
2779 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2780 {
2781 struct sk_buff *p;
2782 int eprec = -1; /* precedence to evict from */
2783
2784 /* Fast case, precedence queue is not full and we are also not
2785 * exceeding total queue length
2786 */
2787 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2788 brcmu_pktq_penq(q, prec, pkt);
2789 return true;
2790 }
2791
2792 /* Determine precedence from which to evict packet, if any */
2793 if (pktq_pfull(q, prec)) {
2794 eprec = prec;
2795 } else if (pktq_full(q)) {
2796 p = brcmu_pktq_peek_tail(q, &eprec);
2797 if (eprec > prec)
2798 return false;
2799 }
2800
2801 /* Evict if needed */
2802 if (eprec >= 0) {
2803 /* Detect queueing to unconfigured precedence */
2804 if (eprec == prec)
2805 return false; /* refuse newer (incoming) packet */
2806 /* Evict packet according to discard policy */
2807 p = brcmu_pktq_pdeq_tail(q, eprec);
2808 if (p == NULL)
2809 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2810 brcmu_pkt_buf_free_skb(p);
2811 }
2812
2813 /* Enqueue */
2814 p = brcmu_pktq_penq(q, prec, pkt);
2815 if (p == NULL)
2816 brcmf_err("brcmu_pktq_penq() failed\n");
2817
2818 return p != NULL;
2819 }
2820
2821 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2822 {
2823 int ret = -EBADE;
2824 uint prec;
2825 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2826 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2827 struct brcmf_sdio *bus = sdiodev->bus;
2828
2829 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2830
2831 /* Add space for the header */
2832 skb_push(pkt, bus->tx_hdrlen);
2833 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2834
2835 prec = prio2prec((pkt->priority & PRIOMASK));
2836
2837 /* Check for existing queue, current flow-control,
2838 pending event, or pending clock */
2839 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2840 bus->sdcnt.fcqueued++;
2841
2842 /* Priority based enq */
2843 spin_lock_bh(&bus->txq_lock);
2844 /* reset bus_flags in packet cb */
2845 *(u16 *)(pkt->cb) = 0;
2846 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2847 skb_pull(pkt, bus->tx_hdrlen);
2848 brcmf_err("out of bus->txq !!!\n");
2849 ret = -ENOSR;
2850 } else {
2851 ret = 0;
2852 }
2853
2854 if (pktq_len(&bus->txq) >= TXHI) {
2855 bus->txoff = true;
2856 brcmf_txflowblock(dev, true);
2857 }
2858 spin_unlock_bh(&bus->txq_lock);
2859
2860 #ifdef DEBUG
2861 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2862 qcount[prec] = pktq_plen(&bus->txq, prec);
2863 #endif
2864
2865 if (atomic_read(&bus->dpc_tskcnt) == 0) {
2866 atomic_inc(&bus->dpc_tskcnt);
2867 queue_work(bus->brcmf_wq, &bus->datawork);
2868 }
2869
2870 return ret;
2871 }
2872
2873 #ifdef DEBUG
2874 #define CONSOLE_LINE_MAX 192
2875
2876 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2877 {
2878 struct brcmf_console *c = &bus->console;
2879 u8 line[CONSOLE_LINE_MAX], ch;
2880 u32 n, idx, addr;
2881 int rv;
2882
2883 /* Don't do anything until FWREADY updates console address */
2884 if (bus->console_addr == 0)
2885 return 0;
2886
2887 /* Read console log struct */
2888 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2889 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2890 sizeof(c->log_le));
2891 if (rv < 0)
2892 return rv;
2893
2894 /* Allocate console buffer (one time only) */
2895 if (c->buf == NULL) {
2896 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2897 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2898 if (c->buf == NULL)
2899 return -ENOMEM;
2900 }
2901
2902 idx = le32_to_cpu(c->log_le.idx);
2903
2904 /* Protect against corrupt value */
2905 if (idx > c->bufsize)
2906 return -EBADE;
2907
2908 /* Skip reading the console buffer if the index pointer
2909 has not moved */
2910 if (idx == c->last)
2911 return 0;
2912
2913 /* Read the console buffer */
2914 addr = le32_to_cpu(c->log_le.buf);
2915 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2916 if (rv < 0)
2917 return rv;
2918
2919 while (c->last != idx) {
2920 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2921 if (c->last == idx) {
2922 /* This would output a partial line.
2923 * Instead, back up
2924 * the buffer pointer and output this
2925 * line next time around.
2926 */
2927 if (c->last >= n)
2928 c->last -= n;
2929 else
2930 c->last = c->bufsize - n;
2931 goto break2;
2932 }
2933 ch = c->buf[c->last];
2934 c->last = (c->last + 1) % c->bufsize;
2935 if (ch == '\n')
2936 break;
2937 line[n] = ch;
2938 }
2939
2940 if (n > 0) {
2941 if (line[n - 1] == '\r')
2942 n--;
2943 line[n] = 0;
2944 pr_debug("CONSOLE: %s\n", line);
2945 }
2946 }
2947 break2:
2948
2949 return 0;
2950 }
2951 #endif /* DEBUG */
2952
2953 static int
2954 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2955 {
2956 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2957 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2958 struct brcmf_sdio *bus = sdiodev->bus;
2959 int ret;
2960
2961 brcmf_dbg(TRACE, "Enter\n");
2962
2963 /* Send from dpc */
2964 bus->ctrl_frame_buf = msg;
2965 bus->ctrl_frame_len = msglen;
2966 bus->ctrl_frame_stat = true;
2967 if (atomic_read(&bus->dpc_tskcnt) == 0) {
2968 atomic_inc(&bus->dpc_tskcnt);
2969 queue_work(bus->brcmf_wq, &bus->datawork);
2970 }
2971
2972 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2973 msecs_to_jiffies(CTL_DONE_TIMEOUT));
2974
2975 if (!bus->ctrl_frame_stat) {
2976 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2977 bus->ctrl_frame_err);
2978 ret = bus->ctrl_frame_err;
2979 } else {
2980 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2981 bus->ctrl_frame_stat = false;
2982 ret = -ETIMEDOUT;
2983 }
2984
2985 if (ret)
2986 bus->sdcnt.tx_ctlerrs++;
2987 else
2988 bus->sdcnt.tx_ctlpkts++;
2989
2990 return ret;
2991 }
2992
2993 #ifdef DEBUG
2994 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2995 struct sdpcm_shared *sh)
2996 {
2997 u32 addr, console_ptr, console_size, console_index;
2998 char *conbuf = NULL;
2999 __le32 sh_val;
3000 int rv;
3001
3002 /* obtain console information from device memory */
3003 addr = sh->console_addr + offsetof(struct rte_console, log_le);
3004 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3005 (u8 *)&sh_val, sizeof(u32));
3006 if (rv < 0)
3007 return rv;
3008 console_ptr = le32_to_cpu(sh_val);
3009
3010 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
3011 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3012 (u8 *)&sh_val, sizeof(u32));
3013 if (rv < 0)
3014 return rv;
3015 console_size = le32_to_cpu(sh_val);
3016
3017 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
3018 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3019 (u8 *)&sh_val, sizeof(u32));
3020 if (rv < 0)
3021 return rv;
3022 console_index = le32_to_cpu(sh_val);
3023
3024 /* allocate buffer for console data */
3025 if (console_size <= CONSOLE_BUFFER_MAX)
3026 conbuf = vzalloc(console_size+1);
3027
3028 if (!conbuf)
3029 return -ENOMEM;
3030
3031 /* obtain the console data from device */
3032 conbuf[console_size] = '\0';
3033 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3034 console_size);
3035 if (rv < 0)
3036 goto done;
3037
3038 rv = seq_write(seq, conbuf + console_index,
3039 console_size - console_index);
3040 if (rv < 0)
3041 goto done;
3042
3043 if (console_index > 0)
3044 rv = seq_write(seq, conbuf, console_index - 1);
3045
3046 done:
3047 vfree(conbuf);
3048 return rv;
3049 }
3050
3051 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3052 struct sdpcm_shared *sh)
3053 {
3054 int error;
3055 struct brcmf_trap_info tr;
3056
3057 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3058 brcmf_dbg(INFO, "no trap in firmware\n");
3059 return 0;
3060 }
3061
3062 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3063 sizeof(struct brcmf_trap_info));
3064 if (error < 0)
3065 return error;
3066
3067 seq_printf(seq,
3068 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3069 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3070 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3071 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3072 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3073 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3074 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3075 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3076 le32_to_cpu(tr.pc), sh->trap_addr,
3077 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3078 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3079 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3080 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3081
3082 return 0;
3083 }
3084
3085 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3086 struct sdpcm_shared *sh)
3087 {
3088 int error = 0;
3089 char file[80] = "?";
3090 char expr[80] = "<???>";
3091
3092 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3093 brcmf_dbg(INFO, "firmware not built with -assert\n");
3094 return 0;
3095 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3096 brcmf_dbg(INFO, "no assert in dongle\n");
3097 return 0;
3098 }
3099
3100 sdio_claim_host(bus->sdiodev->func[1]);
3101 if (sh->assert_file_addr != 0) {
3102 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3103 sh->assert_file_addr, (u8 *)file, 80);
3104 if (error < 0)
3105 return error;
3106 }
3107 if (sh->assert_exp_addr != 0) {
3108 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3109 sh->assert_exp_addr, (u8 *)expr, 80);
3110 if (error < 0)
3111 return error;
3112 }
3113 sdio_release_host(bus->sdiodev->func[1]);
3114
3115 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3116 file, sh->assert_line, expr);
3117 return 0;
3118 }
3119
3120 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3121 {
3122 int error;
3123 struct sdpcm_shared sh;
3124
3125 error = brcmf_sdio_readshared(bus, &sh);
3126
3127 if (error < 0)
3128 return error;
3129
3130 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3131 brcmf_dbg(INFO, "firmware not built with -assert\n");
3132 else if (sh.flags & SDPCM_SHARED_ASSERT)
3133 brcmf_err("assertion in dongle\n");
3134
3135 if (sh.flags & SDPCM_SHARED_TRAP)
3136 brcmf_err("firmware trap in dongle\n");
3137
3138 return 0;
3139 }
3140
3141 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3142 {
3143 int error = 0;
3144 struct sdpcm_shared sh;
3145
3146 error = brcmf_sdio_readshared(bus, &sh);
3147 if (error < 0)
3148 goto done;
3149
3150 error = brcmf_sdio_assert_info(seq, bus, &sh);
3151 if (error < 0)
3152 goto done;
3153
3154 error = brcmf_sdio_trap_info(seq, bus, &sh);
3155 if (error < 0)
3156 goto done;
3157
3158 error = brcmf_sdio_dump_console(seq, bus, &sh);
3159
3160 done:
3161 return error;
3162 }
3163
3164 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3165 {
3166 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3167 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3168
3169 return brcmf_sdio_died_dump(seq, bus);
3170 }
3171
3172 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3173 {
3174 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3175 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3176 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3177
3178 seq_printf(seq,
3179 "intrcount: %u\nlastintrs: %u\n"
3180 "pollcnt: %u\nregfails: %u\n"
3181 "tx_sderrs: %u\nfcqueued: %u\n"
3182 "rxrtx: %u\nrx_toolong: %u\n"
3183 "rxc_errors: %u\nrx_hdrfail: %u\n"
3184 "rx_badhdr: %u\nrx_badseq: %u\n"
3185 "fc_rcvd: %u\nfc_xoff: %u\n"
3186 "fc_xon: %u\nrxglomfail: %u\n"
3187 "rxglomframes: %u\nrxglompkts: %u\n"
3188 "f2rxhdrs: %u\nf2rxdata: %u\n"
3189 "f2txdata: %u\nf1regdata: %u\n"
3190 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3191 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3192 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3193 sdcnt->intrcount, sdcnt->lastintrs,
3194 sdcnt->pollcnt, sdcnt->regfails,
3195 sdcnt->tx_sderrs, sdcnt->fcqueued,
3196 sdcnt->rxrtx, sdcnt->rx_toolong,
3197 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3198 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3199 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3200 sdcnt->fc_xon, sdcnt->rxglomfail,
3201 sdcnt->rxglomframes, sdcnt->rxglompkts,
3202 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3203 sdcnt->f2txdata, sdcnt->f1regdata,
3204 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3205 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3206 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3207
3208 return 0;
3209 }
3210
3211 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3212 {
3213 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3214 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3215
3216 if (IS_ERR_OR_NULL(dentry))
3217 return;
3218
3219 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3220 brcmf_debugfs_add_entry(drvr, "counters",
3221 brcmf_debugfs_sdio_count_read);
3222 debugfs_create_u32("console_interval", 0644, dentry,
3223 &bus->console_interval);
3224 }
3225 #else
3226 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3227 {
3228 return 0;
3229 }
3230
3231 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3232 {
3233 }
3234 #endif /* DEBUG */
3235
3236 static int
3237 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3238 {
3239 int timeleft;
3240 uint rxlen = 0;
3241 bool pending;
3242 u8 *buf;
3243 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3244 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3245 struct brcmf_sdio *bus = sdiodev->bus;
3246
3247 brcmf_dbg(TRACE, "Enter\n");
3248
3249 /* Wait until control frame is available */
3250 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3251
3252 spin_lock_bh(&bus->rxctl_lock);
3253 rxlen = bus->rxlen;
3254 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3255 bus->rxctl = NULL;
3256 buf = bus->rxctl_orig;
3257 bus->rxctl_orig = NULL;
3258 bus->rxlen = 0;
3259 spin_unlock_bh(&bus->rxctl_lock);
3260 vfree(buf);
3261
3262 if (rxlen) {
3263 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3264 rxlen, msglen);
3265 } else if (timeleft == 0) {
3266 brcmf_err("resumed on timeout\n");
3267 brcmf_sdio_checkdied(bus);
3268 } else if (pending) {
3269 brcmf_dbg(CTL, "cancelled\n");
3270 return -ERESTARTSYS;
3271 } else {
3272 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3273 brcmf_sdio_checkdied(bus);
3274 }
3275
3276 if (rxlen)
3277 bus->sdcnt.rx_ctlpkts++;
3278 else
3279 bus->sdcnt.rx_ctlerrs++;
3280
3281 return rxlen ? (int)rxlen : -ETIMEDOUT;
3282 }
3283
3284 #ifdef DEBUG
3285 static bool
3286 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3287 u8 *ram_data, uint ram_sz)
3288 {
3289 char *ram_cmp;
3290 int err;
3291 bool ret = true;
3292 int address;
3293 int offset;
3294 int len;
3295
3296 /* read back and verify */
3297 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3298 ram_sz);
3299 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3300 /* do not proceed while no memory but */
3301 if (!ram_cmp)
3302 return true;
3303
3304 address = ram_addr;
3305 offset = 0;
3306 while (offset < ram_sz) {
3307 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3308 ram_sz - offset;
3309 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3310 if (err) {
3311 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3312 err, len, address);
3313 ret = false;
3314 break;
3315 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3316 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3317 offset, len);
3318 ret = false;
3319 break;
3320 }
3321 offset += len;
3322 address += len;
3323 }
3324
3325 kfree(ram_cmp);
3326
3327 return ret;
3328 }
3329 #else /* DEBUG */
3330 static bool
3331 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3332 u8 *ram_data, uint ram_sz)
3333 {
3334 return true;
3335 }
3336 #endif /* DEBUG */
3337
3338 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3339 const struct firmware *fw)
3340 {
3341 int err;
3342
3343 brcmf_dbg(TRACE, "Enter\n");
3344
3345 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3346 (u8 *)fw->data, fw->size);
3347 if (err)
3348 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3349 err, (int)fw->size, bus->ci->rambase);
3350 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3351 (u8 *)fw->data, fw->size))
3352 err = -EIO;
3353
3354 return err;
3355 }
3356
3357 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3358 void *vars, u32 varsz)
3359 {
3360 int address;
3361 int err;
3362
3363 brcmf_dbg(TRACE, "Enter\n");
3364
3365 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3366 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3367 if (err)
3368 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3369 err, varsz, address);
3370 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3371 err = -EIO;
3372
3373 return err;
3374 }
3375
3376 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3377 const struct firmware *fw,
3378 void *nvram, u32 nvlen)
3379 {
3380 int bcmerror = -EFAULT;
3381 u32 rstvec;
3382
3383 sdio_claim_host(bus->sdiodev->func[1]);
3384 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3385
3386 /* Keep arm in reset */
3387 brcmf_chip_enter_download(bus->ci);
3388
3389 rstvec = get_unaligned_le32(fw->data);
3390 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3391
3392 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3393 release_firmware(fw);
3394 if (bcmerror) {
3395 brcmf_err("dongle image file download failed\n");
3396 brcmf_fw_nvram_free(nvram);
3397 goto err;
3398 }
3399
3400 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3401 brcmf_fw_nvram_free(nvram);
3402 if (bcmerror) {
3403 brcmf_err("dongle nvram file download failed\n");
3404 goto err;
3405 }
3406
3407 /* Take arm out of reset */
3408 if (!brcmf_chip_exit_download(bus->ci, rstvec)) {
3409 brcmf_err("error getting out of ARM core reset\n");
3410 goto err;
3411 }
3412
3413 /* Allow full data communication using DPC from now on. */
3414 bus->sdiodev->state = BRCMF_STATE_DATA;
3415 bcmerror = 0;
3416
3417 err:
3418 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3419 sdio_release_host(bus->sdiodev->func[1]);
3420 return bcmerror;
3421 }
3422
3423 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3424 {
3425 int err = 0;
3426 u8 val;
3427
3428 brcmf_dbg(TRACE, "Enter\n");
3429
3430 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3431 if (err) {
3432 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3433 return;
3434 }
3435
3436 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3437 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3438 if (err) {
3439 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3440 return;
3441 }
3442
3443 /* Add CMD14 Support */
3444 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3445 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3446 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3447 &err);
3448 if (err) {
3449 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3450 return;
3451 }
3452
3453 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3454 SBSDIO_FORCE_HT, &err);
3455 if (err) {
3456 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3457 return;
3458 }
3459
3460 /* set flag */
3461 bus->sr_enabled = true;
3462 brcmf_dbg(INFO, "SR enabled\n");
3463 }
3464
3465 /* enable KSO bit */
3466 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3467 {
3468 u8 val;
3469 int err = 0;
3470
3471 brcmf_dbg(TRACE, "Enter\n");
3472
3473 /* KSO bit added in SDIO core rev 12 */
3474 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3475 return 0;
3476
3477 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3478 if (err) {
3479 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3480 return err;
3481 }
3482
3483 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3484 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3485 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3486 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3487 val, &err);
3488 if (err) {
3489 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3490 return err;
3491 }
3492 }
3493
3494 return 0;
3495 }
3496
3497
3498 static int brcmf_sdio_bus_preinit(struct device *dev)
3499 {
3500 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3501 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3502 struct brcmf_sdio *bus = sdiodev->bus;
3503 uint pad_size;
3504 u32 value;
3505 int err;
3506
3507 /* the commands below use the terms tx and rx from
3508 * a device perspective, ie. bus:txglom affects the
3509 * bus transfers from device to host.
3510 */
3511 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3512 /* for sdio core rev < 12, disable txgloming */
3513 value = 0;
3514 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3515 sizeof(u32));
3516 } else {
3517 /* otherwise, set txglomalign */
3518 value = 4;
3519 if (sdiodev->pdata)
3520 value = sdiodev->pdata->sd_sgentry_align;
3521 /* SDIO ADMA requires at least 32 bit alignment */
3522 value = max_t(u32, value, 4);
3523 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3524 sizeof(u32));
3525 }
3526
3527 if (err < 0)
3528 goto done;
3529
3530 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3531 if (sdiodev->sg_support) {
3532 bus->txglom = false;
3533 value = 1;
3534 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3535 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3536 &value, sizeof(u32));
3537 if (err < 0) {
3538 /* bus:rxglom is allowed to fail */
3539 err = 0;
3540 } else {
3541 bus->txglom = true;
3542 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3543 }
3544 }
3545 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3546
3547 done:
3548 return err;
3549 }
3550
3551 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3552 {
3553 brcmf_dbg(TRACE, "Enter\n");
3554
3555 if (!bus) {
3556 brcmf_err("bus is null pointer, exiting\n");
3557 return;
3558 }
3559
3560 if (bus->sdiodev->state != BRCMF_STATE_DATA) {
3561 brcmf_err("bus is down. we have nothing to do\n");
3562 return;
3563 }
3564 /* Count the interrupt call */
3565 bus->sdcnt.intrcount++;
3566 if (in_interrupt())
3567 atomic_set(&bus->ipend, 1);
3568 else
3569 if (brcmf_sdio_intr_rstatus(bus)) {
3570 brcmf_err("failed backplane access\n");
3571 }
3572
3573 /* Disable additional interrupts (is this needed now)? */
3574 if (!bus->intr)
3575 brcmf_err("isr w/o interrupt configured!\n");
3576
3577 atomic_inc(&bus->dpc_tskcnt);
3578 queue_work(bus->brcmf_wq, &bus->datawork);
3579 }
3580
3581 static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3582 {
3583 brcmf_dbg(TIMER, "Enter\n");
3584
3585 /* Poll period: check device if appropriate. */
3586 if (!bus->sr_enabled &&
3587 bus->poll && (++bus->polltick >= bus->pollrate)) {
3588 u32 intstatus = 0;
3589
3590 /* Reset poll tick */
3591 bus->polltick = 0;
3592
3593 /* Check device if no interrupts */
3594 if (!bus->intr ||
3595 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3596
3597 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3598 u8 devpend;
3599
3600 sdio_claim_host(bus->sdiodev->func[1]);
3601 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3602 SDIO_CCCR_INTx,
3603 NULL);
3604 sdio_release_host(bus->sdiodev->func[1]);
3605 intstatus =
3606 devpend & (INTR_STATUS_FUNC1 |
3607 INTR_STATUS_FUNC2);
3608 }
3609
3610 /* If there is something, make like the ISR and
3611 schedule the DPC */
3612 if (intstatus) {
3613 bus->sdcnt.pollcnt++;
3614 atomic_set(&bus->ipend, 1);
3615
3616 atomic_inc(&bus->dpc_tskcnt);
3617 queue_work(bus->brcmf_wq, &bus->datawork);
3618 }
3619 }
3620
3621 /* Update interrupt tracking */
3622 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3623 }
3624 #ifdef DEBUG
3625 /* Poll for console output periodically */
3626 if (bus->sdiodev->state == BRCMF_STATE_DATA &&
3627 bus->console_interval != 0) {
3628 bus->console.count += BRCMF_WD_POLL_MS;
3629 if (bus->console.count >= bus->console_interval) {
3630 bus->console.count -= bus->console_interval;
3631 sdio_claim_host(bus->sdiodev->func[1]);
3632 /* Make sure backplane clock is on */
3633 brcmf_sdio_bus_sleep(bus, false, false);
3634 if (brcmf_sdio_readconsole(bus) < 0)
3635 /* stop on error */
3636 bus->console_interval = 0;
3637 sdio_release_host(bus->sdiodev->func[1]);
3638 }
3639 }
3640 #endif /* DEBUG */
3641
3642 /* On idle timeout clear activity flag and/or turn off clock */
3643 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3644 if (++bus->idlecount >= bus->idletime) {
3645 bus->idlecount = 0;
3646 if (bus->activity) {
3647 bus->activity = false;
3648 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
3649 } else {
3650 brcmf_dbg(SDIO, "idle\n");
3651 sdio_claim_host(bus->sdiodev->func[1]);
3652 brcmf_sdio_bus_sleep(bus, true, false);
3653 sdio_release_host(bus->sdiodev->func[1]);
3654 }
3655 }
3656 }
3657
3658 return (atomic_read(&bus->ipend) > 0);
3659 }
3660
3661 static void brcmf_sdio_dataworker(struct work_struct *work)
3662 {
3663 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3664 datawork);
3665
3666 while (atomic_read(&bus->dpc_tskcnt)) {
3667 atomic_set(&bus->dpc_tskcnt, 0);
3668 brcmf_sdio_dpc(bus);
3669 }
3670 }
3671
3672 static void
3673 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3674 struct brcmf_chip *ci, u32 drivestrength)
3675 {
3676 const struct sdiod_drive_str *str_tab = NULL;
3677 u32 str_mask;
3678 u32 str_shift;
3679 u32 base;
3680 u32 i;
3681 u32 drivestrength_sel = 0;
3682 u32 cc_data_temp;
3683 u32 addr;
3684
3685 if (!(ci->cc_caps & CC_CAP_PMU))
3686 return;
3687
3688 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3689 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3690 str_tab = sdiod_drvstr_tab1_1v8;
3691 str_mask = 0x00003800;
3692 str_shift = 11;
3693 break;
3694 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3695 str_tab = sdiod_drvstr_tab6_1v8;
3696 str_mask = 0x00001800;
3697 str_shift = 11;
3698 break;
3699 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3700 /* note: 43143 does not support tristate */
3701 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3702 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3703 str_tab = sdiod_drvstr_tab2_3v3;
3704 str_mask = 0x00000007;
3705 str_shift = 0;
3706 } else
3707 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3708 ci->name, drivestrength);
3709 break;
3710 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3711 str_tab = sdiod_drive_strength_tab5_1v8;
3712 str_mask = 0x00003800;
3713 str_shift = 11;
3714 break;
3715 default:
3716 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3717 ci->name, ci->chiprev, ci->pmurev);
3718 break;
3719 }
3720
3721 if (str_tab != NULL) {
3722 for (i = 0; str_tab[i].strength != 0; i++) {
3723 if (drivestrength >= str_tab[i].strength) {
3724 drivestrength_sel = str_tab[i].sel;
3725 break;
3726 }
3727 }
3728 base = brcmf_chip_get_chipcommon(ci)->base;
3729 addr = CORE_CC_REG(base, chipcontrol_addr);
3730 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3731 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3732 cc_data_temp &= ~str_mask;
3733 drivestrength_sel <<= str_shift;
3734 cc_data_temp |= drivestrength_sel;
3735 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3736
3737 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3738 str_tab[i].strength, drivestrength, cc_data_temp);
3739 }
3740 }
3741
3742 static int brcmf_sdio_buscoreprep(void *ctx)
3743 {
3744 struct brcmf_sdio_dev *sdiodev = ctx;
3745 int err = 0;
3746 u8 clkval, clkset;
3747
3748 /* Try forcing SDIO core to do ALPAvail request only */
3749 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3750 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3751 if (err) {
3752 brcmf_err("error writing for HT off\n");
3753 return err;
3754 }
3755
3756 /* If register supported, wait for ALPAvail and then force ALP */
3757 /* This may take up to 15 milliseconds */
3758 clkval = brcmf_sdiod_regrb(sdiodev,
3759 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3760
3761 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3762 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3763 clkset, clkval);
3764 return -EACCES;
3765 }
3766
3767 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3768 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3769 !SBSDIO_ALPAV(clkval)),
3770 PMU_MAX_TRANSITION_DLY);
3771 if (!SBSDIO_ALPAV(clkval)) {
3772 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3773 clkval);
3774 return -EBUSY;
3775 }
3776
3777 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3778 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3779 udelay(65);
3780
3781 /* Also, disable the extra SDIO pull-ups */
3782 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3783
3784 return 0;
3785 }
3786
3787 static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
3788 u32 rstvec)
3789 {
3790 struct brcmf_sdio_dev *sdiodev = ctx;
3791 struct brcmf_core *core;
3792 u32 reg_addr;
3793
3794 /* clear all interrupts */
3795 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3796 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3797 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3798
3799 if (rstvec)
3800 /* Write reset vector to address 0 */
3801 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3802 sizeof(rstvec));
3803 }
3804
3805 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3806 {
3807 struct brcmf_sdio_dev *sdiodev = ctx;
3808 u32 val, rev;
3809
3810 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3811 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3812 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3813 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3814 if (rev >= 2) {
3815 val &= ~CID_ID_MASK;
3816 val |= BRCM_CC_4339_CHIP_ID;
3817 }
3818 }
3819 return val;
3820 }
3821
3822 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3823 {
3824 struct brcmf_sdio_dev *sdiodev = ctx;
3825
3826 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3827 }
3828
3829 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3830 .prepare = brcmf_sdio_buscoreprep,
3831 .exit_dl = brcmf_sdio_buscore_exitdl,
3832 .read32 = brcmf_sdio_buscore_read32,
3833 .write32 = brcmf_sdio_buscore_write32,
3834 };
3835
3836 static bool
3837 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3838 {
3839 u8 clkctl = 0;
3840 int err = 0;
3841 int reg_addr;
3842 u32 reg_val;
3843 u32 drivestrength;
3844
3845 sdio_claim_host(bus->sdiodev->func[1]);
3846
3847 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3848 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3849
3850 /*
3851 * Force PLL off until brcmf_chip_attach()
3852 * programs PLL control regs
3853 */
3854
3855 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3856 BRCMF_INIT_CLKCTL1, &err);
3857 if (!err)
3858 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3859 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3860
3861 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3862 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3863 err, BRCMF_INIT_CLKCTL1, clkctl);
3864 goto fail;
3865 }
3866
3867 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3868 if (IS_ERR(bus->ci)) {
3869 brcmf_err("brcmf_chip_attach failed!\n");
3870 bus->ci = NULL;
3871 goto fail;
3872 }
3873
3874 if (brcmf_sdio_kso_init(bus)) {
3875 brcmf_err("error enabling KSO\n");
3876 goto fail;
3877 }
3878
3879 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3880 drivestrength = bus->sdiodev->pdata->drive_strength;
3881 else
3882 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3883 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3884
3885 /* Get info on the SOCRAM cores... */
3886 bus->ramsize = bus->ci->ramsize;
3887 if (!(bus->ramsize)) {
3888 brcmf_err("failed to find SOCRAM memory!\n");
3889 goto fail;
3890 }
3891
3892 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3893 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3894 SDIO_CCCR_BRCM_CARDCTRL, &err);
3895 if (err)
3896 goto fail;
3897
3898 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3899
3900 brcmf_sdiod_regwb(bus->sdiodev,
3901 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3902 if (err)
3903 goto fail;
3904
3905 /* set PMUControl so a backplane reset does PMU state reload */
3906 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
3907 pmucontrol);
3908 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
3909 if (err)
3910 goto fail;
3911
3912 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3913
3914 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
3915 if (err)
3916 goto fail;
3917
3918 sdio_release_host(bus->sdiodev->func[1]);
3919
3920 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3921
3922 /* allocate header buffer */
3923 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3924 if (!bus->hdrbuf)
3925 return false;
3926 /* Locate an appropriately-aligned portion of hdrbuf */
3927 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3928 bus->head_align);
3929
3930 /* Set the poll and/or interrupt flags */
3931 bus->intr = true;
3932 bus->poll = false;
3933 if (bus->poll)
3934 bus->pollrate = 1;
3935
3936 return true;
3937
3938 fail:
3939 sdio_release_host(bus->sdiodev->func[1]);
3940 return false;
3941 }
3942
3943 static int
3944 brcmf_sdio_watchdog_thread(void *data)
3945 {
3946 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3947
3948 allow_signal(SIGTERM);
3949 /* Run until signal received */
3950 while (1) {
3951 if (kthread_should_stop())
3952 break;
3953 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
3954 brcmf_sdio_bus_watchdog(bus);
3955 /* Count the tick for reference */
3956 bus->sdcnt.tickcnt++;
3957 reinit_completion(&bus->watchdog_wait);
3958 } else
3959 break;
3960 }
3961 return 0;
3962 }
3963
3964 static void
3965 brcmf_sdio_watchdog(unsigned long data)
3966 {
3967 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3968
3969 if (bus->watchdog_tsk) {
3970 complete(&bus->watchdog_wait);
3971 /* Reschedule the watchdog */
3972 if (bus->wd_timer_valid)
3973 mod_timer(&bus->timer,
3974 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
3975 }
3976 }
3977
3978 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3979 .stop = brcmf_sdio_bus_stop,
3980 .preinit = brcmf_sdio_bus_preinit,
3981 .txdata = brcmf_sdio_bus_txdata,
3982 .txctl = brcmf_sdio_bus_txctl,
3983 .rxctl = brcmf_sdio_bus_rxctl,
3984 .gettxq = brcmf_sdio_bus_gettxq,
3985 .wowl_config = brcmf_sdio_wowl_config
3986 };
3987
3988 static void brcmf_sdio_firmware_callback(struct device *dev,
3989 const struct firmware *code,
3990 void *nvram, u32 nvram_len)
3991 {
3992 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3993 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3994 struct brcmf_sdio *bus = sdiodev->bus;
3995 int err = 0;
3996 u8 saveclk;
3997
3998 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3999
4000 if (!bus_if->drvr)
4001 return;
4002
4003 /* try to download image and nvram to the dongle */
4004 bus->alp_only = true;
4005 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4006 if (err)
4007 goto fail;
4008 bus->alp_only = false;
4009
4010 /* Start the watchdog timer */
4011 bus->sdcnt.tickcnt = 0;
4012 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
4013
4014 sdio_claim_host(sdiodev->func[1]);
4015
4016 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4017 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4018 if (bus->clkstate != CLK_AVAIL)
4019 goto release;
4020
4021 /* Force clocks on backplane to be sure F2 interrupt propagates */
4022 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4023 if (!err) {
4024 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4025 (saveclk | SBSDIO_FORCE_HT), &err);
4026 }
4027 if (err) {
4028 brcmf_err("Failed to force clock for F2: err %d\n", err);
4029 goto release;
4030 }
4031
4032 /* Enable function 2 (frame transfers) */
4033 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4034 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4035 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4036
4037
4038 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4039
4040 /* If F2 successfully enabled, set core and enable interrupts */
4041 if (!err) {
4042 /* Set up the interrupt mask and enable interrupts */
4043 bus->hostintmask = HOSTINTMASK;
4044 w_sdreg32(bus, bus->hostintmask,
4045 offsetof(struct sdpcmd_regs, hostintmask));
4046
4047 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4048 } else {
4049 /* Disable F2 again */
4050 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4051 goto release;
4052 }
4053
4054 if (brcmf_chip_sr_capable(bus->ci)) {
4055 brcmf_sdio_sr_init(bus);
4056 } else {
4057 /* Restore previous clock setting */
4058 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4059 saveclk, &err);
4060 }
4061
4062 if (err == 0) {
4063 err = brcmf_sdiod_intr_register(sdiodev);
4064 if (err != 0)
4065 brcmf_err("intr register failed:%d\n", err);
4066 }
4067
4068 /* If we didn't come up, turn off backplane clock */
4069 if (err != 0)
4070 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4071
4072 sdio_release_host(sdiodev->func[1]);
4073
4074 err = brcmf_bus_start(dev);
4075 if (err != 0) {
4076 brcmf_err("dongle is not responding\n");
4077 goto fail;
4078 }
4079 return;
4080
4081 release:
4082 sdio_release_host(sdiodev->func[1]);
4083 fail:
4084 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4085 device_release_driver(dev);
4086 }
4087
4088 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4089 {
4090 int ret;
4091 struct brcmf_sdio *bus;
4092
4093 brcmf_dbg(TRACE, "Enter\n");
4094
4095 /* Allocate private bus interface state */
4096 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4097 if (!bus)
4098 goto fail;
4099
4100 bus->sdiodev = sdiodev;
4101 sdiodev->bus = bus;
4102 skb_queue_head_init(&bus->glom);
4103 bus->txbound = BRCMF_TXBOUND;
4104 bus->rxbound = BRCMF_RXBOUND;
4105 bus->txminmax = BRCMF_TXMINMAX;
4106 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4107
4108 /* platform specific configuration:
4109 * alignments must be at least 4 bytes for ADMA
4110 */
4111 bus->head_align = ALIGNMENT;
4112 bus->sgentry_align = ALIGNMENT;
4113 if (sdiodev->pdata) {
4114 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4115 bus->head_align = sdiodev->pdata->sd_head_align;
4116 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4117 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4118 }
4119
4120 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4121 bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
4122 if (bus->brcmf_wq == NULL) {
4123 brcmf_err("insufficient memory to create txworkqueue\n");
4124 goto fail;
4125 }
4126
4127 /* attempt to attach to the dongle */
4128 if (!(brcmf_sdio_probe_attach(bus))) {
4129 brcmf_err("brcmf_sdio_probe_attach failed\n");
4130 goto fail;
4131 }
4132
4133 spin_lock_init(&bus->rxctl_lock);
4134 spin_lock_init(&bus->txq_lock);
4135 init_waitqueue_head(&bus->ctrl_wait);
4136 init_waitqueue_head(&bus->dcmd_resp_wait);
4137
4138 /* Set up the watchdog timer */
4139 init_timer(&bus->timer);
4140 bus->timer.data = (unsigned long)bus;
4141 bus->timer.function = brcmf_sdio_watchdog;
4142
4143 /* Initialize watchdog thread */
4144 init_completion(&bus->watchdog_wait);
4145 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4146 bus, "brcmf_watchdog");
4147 if (IS_ERR(bus->watchdog_tsk)) {
4148 pr_warn("brcmf_watchdog thread failed to start\n");
4149 bus->watchdog_tsk = NULL;
4150 }
4151 /* Initialize DPC thread */
4152 atomic_set(&bus->dpc_tskcnt, 0);
4153
4154 /* Assign bus interface call back */
4155 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4156 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4157 bus->sdiodev->bus_if->chip = bus->ci->chip;
4158 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4159
4160 /* default sdio bus header length for tx packet */
4161 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4162
4163 /* Attach to the common layer, reserve hdr space */
4164 ret = brcmf_attach(bus->sdiodev->dev);
4165 if (ret != 0) {
4166 brcmf_err("brcmf_attach failed\n");
4167 goto fail;
4168 }
4169
4170 /* Query the F2 block size, set roundup accordingly */
4171 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4172 bus->roundup = min(max_roundup, bus->blocksize);
4173
4174 /* Allocate buffers */
4175 if (bus->sdiodev->bus_if->maxctl) {
4176 bus->sdiodev->bus_if->maxctl += bus->roundup;
4177 bus->rxblen =
4178 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4179 ALIGNMENT) + bus->head_align;
4180 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4181 if (!(bus->rxbuf)) {
4182 brcmf_err("rxbuf allocation failed\n");
4183 goto fail;
4184 }
4185 }
4186
4187 sdio_claim_host(bus->sdiodev->func[1]);
4188
4189 /* Disable F2 to clear any intermediate frame state on the dongle */
4190 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4191
4192 bus->rxflow = false;
4193
4194 /* Done with backplane-dependent accesses, can drop clock... */
4195 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4196
4197 sdio_release_host(bus->sdiodev->func[1]);
4198
4199 /* ...and initialize clock/power states */
4200 bus->clkstate = CLK_SDONLY;
4201 bus->idletime = BRCMF_IDLE_INTERVAL;
4202 bus->idleclock = BRCMF_IDLE_ACTIVE;
4203
4204 /* SR state */
4205 bus->sr_enabled = false;
4206
4207 brcmf_sdio_debugfs_create(bus);
4208 brcmf_dbg(INFO, "completed!!\n");
4209
4210 ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
4211 if (ret)
4212 goto fail;
4213
4214 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4215 sdiodev->fw_name, sdiodev->nvram_name,
4216 brcmf_sdio_firmware_callback);
4217 if (ret != 0) {
4218 brcmf_err("async firmware request failed: %d\n", ret);
4219 goto fail;
4220 }
4221
4222 return bus;
4223
4224 fail:
4225 brcmf_sdio_remove(bus);
4226 return NULL;
4227 }
4228
4229 /* Detach and free everything */
4230 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4231 {
4232 brcmf_dbg(TRACE, "Enter\n");
4233
4234 if (bus) {
4235 /* De-register interrupt handler */
4236 brcmf_sdiod_intr_unregister(bus->sdiodev);
4237
4238 brcmf_detach(bus->sdiodev->dev);
4239
4240 cancel_work_sync(&bus->datawork);
4241 if (bus->brcmf_wq)
4242 destroy_workqueue(bus->brcmf_wq);
4243
4244 if (bus->ci) {
4245 if (bus->sdiodev->state != BRCMF_STATE_NOMEDIUM) {
4246 sdio_claim_host(bus->sdiodev->func[1]);
4247 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4248 /* Leave the device in state where it is
4249 * 'quiet'. This is done by putting it in
4250 * download_state which essentially resets
4251 * all necessary cores.
4252 */
4253 msleep(20);
4254 brcmf_chip_enter_download(bus->ci);
4255 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4256 sdio_release_host(bus->sdiodev->func[1]);
4257 }
4258 brcmf_chip_detach(bus->ci);
4259 }
4260
4261 kfree(bus->rxbuf);
4262 kfree(bus->hdrbuf);
4263 kfree(bus);
4264 }
4265
4266 brcmf_dbg(TRACE, "Disconnected\n");
4267 }
4268
4269 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4270 {
4271 /* Totally stop the timer */
4272 if (!wdtick && bus->wd_timer_valid) {
4273 del_timer_sync(&bus->timer);
4274 bus->wd_timer_valid = false;
4275 bus->save_ms = wdtick;
4276 return;
4277 }
4278
4279 /* don't start the wd until fw is loaded */
4280 if (bus->sdiodev->state != BRCMF_STATE_DATA)
4281 return;
4282
4283 if (wdtick) {
4284 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4285 if (bus->wd_timer_valid)
4286 /* Stop timer and restart at new value */
4287 del_timer_sync(&bus->timer);
4288
4289 /* Create timer again when watchdog period is
4290 dynamically changed or in the first instance
4291 */
4292 bus->timer.expires =
4293 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4294 add_timer(&bus->timer);
4295
4296 } else {
4297 /* Re arm the timer, at last watchdog period */
4298 mod_timer(&bus->timer,
4299 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4300 }
4301
4302 bus->wd_timer_valid = true;
4303 bus->save_ms = wdtick;
4304 }
4305 }
Linux kernel - Deliverables
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