2 * Copyright (c) 2011 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCMFMAC_SDIO_CHIP_H_
18 #define _BRCMFMAC_SDIO_CHIP_H_
21 * Core reg address translation.
22 * Both macro's returns a 32 bits byte address on the backplane bus.
24 #define CORE_CC_REG(base, field) \
25 (base + offsetof(struct chipcregs, field))
26 #define CORE_BUS_REG(base, field) \
27 (base + offsetof(struct sdpcmd_regs, field))
28 #define CORE_SB(base, field) \
29 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
31 /* SDIO function 1 register CHIPCLKCSR */
32 /* Force ALP request to backplane */
33 #define SBSDIO_FORCE_ALP 0x01
34 /* Force HT request to backplane */
35 #define SBSDIO_FORCE_HT 0x02
36 /* Force ILP request to backplane */
37 #define SBSDIO_FORCE_ILP 0x04
38 /* Make ALP ready (power up xtal) */
39 #define SBSDIO_ALP_AVAIL_REQ 0x08
40 /* Make HT ready (power up PLL) */
41 #define SBSDIO_HT_AVAIL_REQ 0x10
42 /* Squelch clock requests from HW */
43 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
44 /* Status: ALP is ready */
45 #define SBSDIO_ALP_AVAIL 0x40
46 /* Status: HT is ready */
47 #define SBSDIO_HT_AVAIL 0x80
48 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
49 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
50 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
51 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
52 #define SBSDIO_CLKAV(regval, alponly) \
53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
56 #define SBIM_IBE 0x20000 /* inbanderror */
57 #define SBIM_TO 0x40000 /* timeout */
58 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
59 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
62 #define SBTML_RESET 0x0001 /* reset */
63 #define SBTML_REJ_MASK 0x0006 /* reject field */
64 #define SBTML_REJ 0x0002 /* reject */
65 #define SBTML_TMPREJ 0x0004 /* temporary reject(error recovery) */
66 /* Shift to locate the SI control flags in sbtml */
67 #define SBTML_SICF_SHIFT 16
70 #define SBTMH_SERR 0x0001 /* serror */
71 #define SBTMH_INT 0x0002 /* interrupt */
72 #define SBTMH_BUSY 0x0004 /* busy */
73 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
74 /* Shift to locate the SI status flags in sbtmh */
75 #define SBTMH_SISF_SHIFT 16
78 #define SBIDL_INIT 0x80 /* initiator */
86 u32 buscorebase
; /* 32 bits backplane bus address */
98 u32 sbipsflag
; /* initiator port ocp slave flag */
100 u32 sbtpsflag
; /* target port ocp slave flag */
102 u32 sbtmerrloga
; /* (sonics >= 2.3) */
104 u32 sbtmerrlog
; /* (sonics >= 2.3) */
106 u32 sbadmatch3
; /* address match3 */
108 u32 sbadmatch2
; /* address match2 */
110 u32 sbadmatch1
; /* address match1 */
112 u32 sbimstate
; /* initiator agent state */
113 u32 sbintvec
; /* interrupt mask */
114 u32 sbtmstatelow
; /* target state */
115 u32 sbtmstatehigh
; /* target state */
116 u32 sbbwa0
; /* bandwidth allocation table0 */
118 u32 sbimconfiglow
; /* initiator configuration */
119 u32 sbimconfighigh
; /* initiator configuration */
120 u32 sbadmatch0
; /* address match0 */
122 u32 sbtmconfiglow
; /* target configuration */
123 u32 sbtmconfighigh
; /* target configuration */
124 u32 sbbconfig
; /* broadcast configuration */
126 u32 sbbstate
; /* broadcast state */
128 u32 sbactcnfg
; /* activate configuration */
130 u32 sbflagst
; /* current sbflags */
132 u32 sbidlow
; /* identification */
133 u32 sbidhigh
; /* identification */
137 extern void brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev
*sdiodev
,
139 extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev
*sdiodev
,
140 struct chip_info
**ci_ptr
, u32 regs
);
142 #endif /* _BRCMFMAC_SDIO_CHIP_H_ */
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