2 * Copyright (c) 2011 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCMFMAC_SDIO_CHIP_H_
18 #define _BRCMFMAC_SDIO_CHIP_H_
21 * Core reg address translation.
22 * Both macro's returns a 32 bits byte address on the backplane bus.
24 #define CORE_CC_REG(base, field) \
25 (base + offsetof(struct chipcregs, field))
26 #define CORE_BUS_REG(base, field) \
27 (base + offsetof(struct sdpcmd_regs, field))
28 #define CORE_SB(base, field) \
29 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
31 /* SDIO function 1 register CHIPCLKCSR */
32 /* Force ALP request to backplane */
33 #define SBSDIO_FORCE_ALP 0x01
34 /* Force HT request to backplane */
35 #define SBSDIO_FORCE_HT 0x02
36 /* Force ILP request to backplane */
37 #define SBSDIO_FORCE_ILP 0x04
38 /* Make ALP ready (power up xtal) */
39 #define SBSDIO_ALP_AVAIL_REQ 0x08
40 /* Make HT ready (power up PLL) */
41 #define SBSDIO_HT_AVAIL_REQ 0x10
42 /* Squelch clock requests from HW */
43 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
44 /* Status: ALP is ready */
45 #define SBSDIO_ALP_AVAIL 0x40
46 /* Status: HT is ready */
47 #define SBSDIO_HT_AVAIL 0x80
48 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
49 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
50 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
51 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
52 #define SBSDIO_CLKAV(regval, alponly) \
53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
55 #define BRCMF_MAX_CORENUM 6
58 #define SDIO_DEVICE_ID_BROADCOM_43143 43143
59 #define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
60 #define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
61 #define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
62 #define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
63 #define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
65 struct chip_core_info
{
79 /* always put chipcommon core at 0, bus core at 1 */
80 struct chip_core_info c_inf
[BRCMF_MAX_CORENUM
];
85 u32 rst_vec
; /* reset vertor for ARM CR4 core */
87 bool (*iscoreup
)(struct brcmf_sdio_dev
*sdiodev
, struct chip_info
*ci
,
89 u32 (*corerev
)(struct brcmf_sdio_dev
*sdiodev
, struct chip_info
*ci
,
91 void (*coredisable
)(struct brcmf_sdio_dev
*sdiodev
,
92 struct chip_info
*ci
, u16 coreid
, u32 core_bits
);
93 void (*resetcore
)(struct brcmf_sdio_dev
*sdiodev
,
94 struct chip_info
*ci
, u16 coreid
, u32 core_bits
);
99 u32 sbipsflag
; /* initiator port ocp slave flag */
101 u32 sbtpsflag
; /* target port ocp slave flag */
103 u32 sbtmerrloga
; /* (sonics >= 2.3) */
105 u32 sbtmerrlog
; /* (sonics >= 2.3) */
107 u32 sbadmatch3
; /* address match3 */
109 u32 sbadmatch2
; /* address match2 */
111 u32 sbadmatch1
; /* address match1 */
113 u32 sbimstate
; /* initiator agent state */
114 u32 sbintvec
; /* interrupt mask */
115 u32 sbtmstatelow
; /* target state */
116 u32 sbtmstatehigh
; /* target state */
117 u32 sbbwa0
; /* bandwidth allocation table0 */
119 u32 sbimconfiglow
; /* initiator configuration */
120 u32 sbimconfighigh
; /* initiator configuration */
121 u32 sbadmatch0
; /* address match0 */
123 u32 sbtmconfiglow
; /* target configuration */
124 u32 sbtmconfighigh
; /* target configuration */
125 u32 sbbconfig
; /* broadcast configuration */
127 u32 sbbstate
; /* broadcast state */
129 u32 sbactcnfg
; /* activate configuration */
131 u32 sbflagst
; /* current sbflags */
133 u32 sbidlow
; /* identification */
134 u32 sbidhigh
; /* identification */
137 /* sdio core registers */
139 u32 corecontrol
; /* 0x00, rev8 */
140 u32 corestatus
; /* rev8 */
142 u32 biststatus
; /* rev8 */
145 u16 pcmciamesportaladdr
; /* 0x010, rev8 */
147 u16 pcmciamesportalmask
; /* rev8 */
149 u16 pcmciawrframebc
; /* rev8 */
151 u16 pcmciaunderflowtimer
; /* rev8 */
155 u32 intstatus
; /* 0x020, rev8 */
156 u32 hostintmask
; /* rev8 */
157 u32 intmask
; /* rev8 */
158 u32 sbintstatus
; /* rev8 */
159 u32 sbintmask
; /* rev8 */
160 u32 funcintmask
; /* rev4 */
162 u32 tosbmailbox
; /* 0x040, rev8 */
163 u32 tohostmailbox
; /* rev8 */
164 u32 tosbmailboxdata
; /* rev8 */
165 u32 tohostmailboxdata
; /* rev8 */
167 /* synchronized access to registers in SDIO clock domain */
168 u32 sdioaccess
; /* 0x050, rev8 */
171 /* PCMCIA frame control */
172 u8 pcmciaframectrl
; /* 0x060, rev8 */
174 u8 pcmciawatermark
; /* rev8 */
177 /* interrupt batching control */
178 u32 intrcvlazy
; /* 0x100, rev8 */
182 u32 cmd52rd
; /* 0x110, rev8 */
183 u32 cmd52wr
; /* rev8 */
184 u32 cmd53rd
; /* rev8 */
185 u32 cmd53wr
; /* rev8 */
186 u32 abort
; /* rev8 */
187 u32 datacrcerror
; /* rev8 */
188 u32 rdoutofsync
; /* rev8 */
189 u32 wroutofsync
; /* rev8 */
190 u32 writebusy
; /* rev8 */
191 u32 readwait
; /* rev8 */
192 u32 readterm
; /* rev8 */
193 u32 writeterm
; /* rev8 */
195 u32 clockctlstatus
; /* rev8 */
198 u32 PAD
[128]; /* DMA engines */
200 /* SDIO/PCMCIA CIS region */
201 char cis
[512]; /* 0x400-0x5ff, rev6 */
203 /* PCMCIA function control registers */
204 char pcmciafcr
[256]; /* 0x600-6ff, rev6 */
207 /* PCMCIA backplane access */
208 u16 backplanecsr
; /* 0x76E, rev6 */
209 u16 backplaneaddr0
; /* rev6 */
210 u16 backplaneaddr1
; /* rev6 */
211 u16 backplaneaddr2
; /* rev6 */
212 u16 backplaneaddr3
; /* rev6 */
213 u16 backplanedata0
; /* rev6 */
214 u16 backplanedata1
; /* rev6 */
215 u16 backplanedata2
; /* rev6 */
216 u16 backplanedata3
; /* rev6 */
219 /* sprom "size" & "blank" info */
220 u16 spromstatus
; /* 0x7BE, rev2 */
226 int brcmf_sdio_chip_attach(struct brcmf_sdio_dev
*sdiodev
,
227 struct chip_info
**ci_ptr
, u32 regs
);
228 void brcmf_sdio_chip_detach(struct chip_info
**ci_ptr
);
229 void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev
*sdiodev
,
230 struct chip_info
*ci
, u32 drivestrength
);
231 u8
brcmf_sdio_chip_getinfidx(struct chip_info
*ci
, u16 coreid
);
232 void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev
*sdiodev
,
233 struct chip_info
*ci
);
234 bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev
*sdiodev
,
235 struct chip_info
*ci
, char *nvram_dat
,
238 #endif /* _BRCMFMAC_SDIO_CHIP_H_ */
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