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brcmsmac: use sprom from bcma
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmsmac / main.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/mac80211.h>
22 #include <brcm_hw_ids.h>
23 #include <aiutils.h>
24 #include <chipcommon.h>
25 #include "rate.h"
26 #include "scb.h"
27 #include "phy/phy_hal.h"
28 #include "channel.h"
29 #include "antsel.h"
30 #include "stf.h"
31 #include "ampdu.h"
32 #include "mac80211_if.h"
33 #include "ucode_loader.h"
34 #include "main.h"
35 #include "soc.h"
36
37 /*
38 * Indication for txflowcontrol that all priority bits in
39 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
40 */
41 #define ALLPRIO -1
42
43 /* watchdog timer, in unit of ms */
44 #define TIMER_INTERVAL_WATCHDOG 1000
45 /* radio monitor timer, in unit of ms */
46 #define TIMER_INTERVAL_RADIOCHK 800
47
48 /* beacon interval, in unit of 1024TU */
49 #define BEACON_INTERVAL_DEFAULT 100
50
51 /* n-mode support capability */
52 /* 2x2 includes both 1x1 & 2x2 devices
53 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
54 * control it independently
55 */
56 #define WL_11N_2x2 1
57 #define WL_11N_3x3 3
58 #define WL_11N_4x4 4
59
60 #define EDCF_ACI_MASK 0x60
61 #define EDCF_ACI_SHIFT 5
62 #define EDCF_ECWMIN_MASK 0x0f
63 #define EDCF_ECWMAX_SHIFT 4
64 #define EDCF_AIFSN_MASK 0x0f
65 #define EDCF_AIFSN_MAX 15
66 #define EDCF_ECWMAX_MASK 0xf0
67
68 #define EDCF_AC_BE_TXOP_STA 0x0000
69 #define EDCF_AC_BK_TXOP_STA 0x0000
70 #define EDCF_AC_VO_ACI_STA 0x62
71 #define EDCF_AC_VO_ECW_STA 0x32
72 #define EDCF_AC_VI_ACI_STA 0x42
73 #define EDCF_AC_VI_ECW_STA 0x43
74 #define EDCF_AC_BK_ECW_STA 0xA4
75 #define EDCF_AC_VI_TXOP_STA 0x005e
76 #define EDCF_AC_VO_TXOP_STA 0x002f
77 #define EDCF_AC_BE_ACI_STA 0x03
78 #define EDCF_AC_BE_ECW_STA 0xA4
79 #define EDCF_AC_BK_ACI_STA 0x27
80 #define EDCF_AC_VO_TXOP_AP 0x002f
81
82 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
83 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
84
85 #define APHY_SYMBOL_TIME 4
86 #define APHY_PREAMBLE_TIME 16
87 #define APHY_SIGNAL_TIME 4
88 #define APHY_SIFS_TIME 16
89 #define APHY_SERVICE_NBITS 16
90 #define APHY_TAIL_NBITS 6
91 #define BPHY_SIFS_TIME 10
92 #define BPHY_PLCP_SHORT_TIME 96
93
94 #define PREN_PREAMBLE 24
95 #define PREN_MM_EXT 12
96 #define PREN_PREAMBLE_EXT 4
97
98 #define DOT11_MAC_HDR_LEN 24
99 #define DOT11_ACK_LEN 10
100 #define DOT11_BA_LEN 4
101 #define DOT11_OFDM_SIGNAL_EXTENSION 6
102 #define DOT11_MIN_FRAG_LEN 256
103 #define DOT11_RTS_LEN 16
104 #define DOT11_CTS_LEN 10
105 #define DOT11_BA_BITMAP_LEN 128
106 #define DOT11_MIN_BEACON_PERIOD 1
107 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
108 #define DOT11_MAXNUMFRAGS 16
109 #define DOT11_MAX_FRAG_LEN 2346
110
111 #define BPHY_PLCP_TIME 192
112 #define RIFS_11N_TIME 2
113
114 /* length of the BCN template area */
115 #define BCN_TMPL_LEN 512
116
117 /* brcms_bss_info flag bit values */
118 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
119
120 /* chip rx buffer offset */
121 #define BRCMS_HWRXOFF 38
122
123 /* rfdisable delay timer 500 ms, runs of ALP clock */
124 #define RFDISABLE_DEFAULT 10000000
125
126 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
127
128 /* precedences numbers for wlc queues. These are twice as may levels as
129 * 802.1D priorities.
130 * Odd numbers are used for HI priority traffic at same precedence levels
131 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
132 * elsewhere.
133 */
134 #define _BRCMS_PREC_NONE 0 /* None = - */
135 #define _BRCMS_PREC_BK 2 /* BK - Background */
136 #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
137 #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
138 #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
139 #define _BRCMS_PREC_VI 10 /* Vi - Video */
140 #define _BRCMS_PREC_VO 12 /* Vo - Voice */
141 #define _BRCMS_PREC_NC 14 /* NC - Network Control */
142
143 /* synthpu_dly times in us */
144 #define SYNTHPU_DLY_APHY_US 3700
145 #define SYNTHPU_DLY_BPHY_US 1050
146 #define SYNTHPU_DLY_NPHY_US 2048
147 #define SYNTHPU_DLY_LPPHY_US 300
148
149 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
150
151 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
152 #define EDCF_SHORT_S 0
153 #define EDCF_SFB_S 4
154 #define EDCF_LONG_S 8
155 #define EDCF_LFB_S 12
156 #define EDCF_SHORT_M BITFIELD_MASK(4)
157 #define EDCF_SFB_M BITFIELD_MASK(4)
158 #define EDCF_LONG_M BITFIELD_MASK(4)
159 #define EDCF_LFB_M BITFIELD_MASK(4)
160
161 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
162 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
163 #define RETRY_LONG_DEF 4 /* Default Long retry count */
164 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
165 #define RETRY_LONG_FB 2 /* Long count for fb rate */
166
167 #define APHY_CWMIN 15
168 #define PHY_CWMAX 1023
169
170 #define EDCF_AIFSN_MIN 1
171
172 #define FRAGNUM_MASK 0xF
173
174 #define APHY_SLOT_TIME 9
175 #define BPHY_SLOT_TIME 20
176
177 #define WL_SPURAVOID_OFF 0
178 #define WL_SPURAVOID_ON1 1
179 #define WL_SPURAVOID_ON2 2
180
181 /* invalid core flags, use the saved coreflags */
182 #define BRCMS_USE_COREFLAGS 0xffffffff
183
184 /* values for PLCPHdr_override */
185 #define BRCMS_PLCP_AUTO -1
186 #define BRCMS_PLCP_SHORT 0
187 #define BRCMS_PLCP_LONG 1
188
189 /* values for g_protection_override and n_protection_override */
190 #define BRCMS_PROTECTION_AUTO -1
191 #define BRCMS_PROTECTION_OFF 0
192 #define BRCMS_PROTECTION_ON 1
193 #define BRCMS_PROTECTION_MMHDR_ONLY 2
194 #define BRCMS_PROTECTION_CTS_ONLY 3
195
196 /* values for g_protection_control and n_protection_control */
197 #define BRCMS_PROTECTION_CTL_OFF 0
198 #define BRCMS_PROTECTION_CTL_LOCAL 1
199 #define BRCMS_PROTECTION_CTL_OVERLAP 2
200
201 /* values for n_protection */
202 #define BRCMS_N_PROTECTION_OFF 0
203 #define BRCMS_N_PROTECTION_OPTIONAL 1
204 #define BRCMS_N_PROTECTION_20IN40 2
205 #define BRCMS_N_PROTECTION_MIXEDMODE 3
206
207 /* values for band specific 40MHz capabilities */
208 #define BRCMS_N_BW_20ALL 0
209 #define BRCMS_N_BW_40ALL 1
210 #define BRCMS_N_BW_20IN2G_40IN5G 2
211
212 /* bitflags for SGI support (sgi_rx iovar) */
213 #define BRCMS_N_SGI_20 0x01
214 #define BRCMS_N_SGI_40 0x02
215
216 /* defines used by the nrate iovar */
217 /* MSC in use,indicates b0-6 holds an mcs */
218 #define NRATE_MCS_INUSE 0x00000080
219 /* rate/mcs value */
220 #define NRATE_RATE_MASK 0x0000007f
221 /* stf mode mask: siso, cdd, stbc, sdm */
222 #define NRATE_STF_MASK 0x0000ff00
223 /* stf mode shift */
224 #define NRATE_STF_SHIFT 8
225 /* bit indicate to override mcs only */
226 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
227 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
228 #define NRATE_SGI_SHIFT 23 /* sgi mode */
229 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
230 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
231
232 #define NRATE_STF_SISO 0 /* stf mode SISO */
233 #define NRATE_STF_CDD 1 /* stf mode CDD */
234 #define NRATE_STF_STBC 2 /* stf mode STBC */
235 #define NRATE_STF_SDM 3 /* stf mode SDM */
236
237 #define MAX_DMA_SEGS 4
238
239 /* Max # of entries in Tx FIFO based on 4kb page size */
240 #define NTXD 256
241 /* Max # of entries in Rx FIFO based on 4kb page size */
242 #define NRXD 256
243
244 /* try to keep this # rbufs posted to the chip */
245 #define NRXBUFPOST 32
246
247 /* data msg txq hiwat mark */
248 #define BRCMS_DATAHIWAT 50
249
250 /* max # frames to process in brcms_c_recv() */
251 #define RXBND 8
252 /* max # tx status to process in wlc_txstatus() */
253 #define TXSBND 8
254
255 /* brcmu_format_flags() bit description structure */
256 struct brcms_c_bit_desc {
257 u32 bit;
258 const char *name;
259 };
260
261 /*
262 * The following table lists the buffer memory allocated to xmt fifos in HW.
263 * the size is in units of 256bytes(one block), total size is HW dependent
264 * ucode has default fifo partition, sw can overwrite if necessary
265 *
266 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
267 * the twiki is updated before making changes.
268 */
269
270 /* Starting corerev for the fifo size table */
271 #define XMTFIFOTBL_STARTREV 20
272
273 struct d11init {
274 __le16 addr;
275 __le16 size;
276 __le32 value;
277 };
278
279 struct edcf_acparam {
280 u8 ACI;
281 u8 ECW;
282 u16 TXOP;
283 } __packed;
284
285 const u8 prio2fifo[NUMPRIO] = {
286 TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
287 TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
288 TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
289 TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
290 TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
291 TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
292 TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
293 TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
294 };
295
296 /* debug/trace */
297 uint brcm_msg_level =
298 #if defined(DEBUG)
299 LOG_ERROR_VAL;
300 #else
301 0;
302 #endif /* DEBUG */
303
304 /* TX FIFO number to WME/802.1E Access Category */
305 static const u8 wme_fifo2ac[] = {
306 IEEE80211_AC_BK,
307 IEEE80211_AC_BE,
308 IEEE80211_AC_VI,
309 IEEE80211_AC_VO,
310 IEEE80211_AC_BE,
311 IEEE80211_AC_BE
312 };
313
314 /* ieee80211 Access Category to TX FIFO number */
315 static const u8 wme_ac2fifo[] = {
316 TX_AC_VO_FIFO,
317 TX_AC_VI_FIFO,
318 TX_AC_BE_FIFO,
319 TX_AC_BK_FIFO
320 };
321
322 /* 802.1D Priority to precedence queue mapping */
323 const u8 wlc_prio2prec_map[] = {
324 _BRCMS_PREC_BE, /* 0 BE - Best-effort */
325 _BRCMS_PREC_BK, /* 1 BK - Background */
326 _BRCMS_PREC_NONE, /* 2 None = - */
327 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
328 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
329 _BRCMS_PREC_VI, /* 5 Vi - Video */
330 _BRCMS_PREC_VO, /* 6 Vo - Voice */
331 _BRCMS_PREC_NC, /* 7 NC - Network Control */
332 };
333
334 static const u16 xmtfifo_sz[][NFIFO] = {
335 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
336 {20, 192, 192, 21, 17, 5},
337 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
338 {9, 58, 22, 14, 14, 5},
339 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
340 {20, 192, 192, 21, 17, 5},
341 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
342 {20, 192, 192, 21, 17, 5},
343 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
344 {9, 58, 22, 14, 14, 5},
345 };
346
347 #ifdef DEBUG
348 static const char * const fifo_names[] = {
349 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
350 #else
351 static const char fifo_names[6][0];
352 #endif
353
354 #ifdef DEBUG
355 /* pointer to most recently allocated wl/wlc */
356 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
357 #endif
358
359 /* Find basic rate for a given rate */
360 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
361 {
362 if (is_mcs_rate(rspec))
363 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
364 .leg_ofdm];
365 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
366 }
367
368 static u16 frametype(u32 rspec, u8 mimoframe)
369 {
370 if (is_mcs_rate(rspec))
371 return mimoframe;
372 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
373 }
374
375 /* currently the best mechanism for determining SIFS is the band in use */
376 static u16 get_sifs(struct brcms_band *band)
377 {
378 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
379 BPHY_SIFS_TIME;
380 }
381
382 /*
383 * Detect Card removed.
384 * Even checking an sbconfig register read will not false trigger when the core
385 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
386 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
387 * reg with fixed 0/1 pattern (some platforms return all 0).
388 * If clocks are present, call the sb routine which will figure out if the
389 * device is removed.
390 */
391 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
392 {
393 u32 macctrl;
394
395 if (!wlc->hw->clk)
396 return ai_deviceremoved(wlc->hw->sih);
397 macctrl = bcma_read32(wlc->hw->d11core,
398 D11REGOFFS(maccontrol));
399 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
400 }
401
402 /* sum the individual fifo tx pending packet counts */
403 static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
404 {
405 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
406 wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
407 }
408
409 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
410 {
411 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
412 }
413
414 static int brcms_chspec_bw(u16 chanspec)
415 {
416 if (CHSPEC_IS40(chanspec))
417 return BRCMS_40_MHZ;
418 if (CHSPEC_IS20(chanspec))
419 return BRCMS_20_MHZ;
420
421 return BRCMS_10_MHZ;
422 }
423
424 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
425 {
426 if (cfg == NULL)
427 return;
428
429 kfree(cfg->current_bss);
430 kfree(cfg);
431 }
432
433 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
434 {
435 if (wlc == NULL)
436 return;
437
438 brcms_c_bsscfg_mfree(wlc->bsscfg);
439 kfree(wlc->pub);
440 kfree(wlc->modulecb);
441 kfree(wlc->default_bss);
442 kfree(wlc->protection);
443 kfree(wlc->stf);
444 kfree(wlc->bandstate[0]);
445 kfree(wlc->corestate->macstat_snapshot);
446 kfree(wlc->corestate);
447 kfree(wlc->hw->bandstate[0]);
448 kfree(wlc->hw);
449
450 /* free the wlc */
451 kfree(wlc);
452 wlc = NULL;
453 }
454
455 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
456 {
457 struct brcms_bss_cfg *cfg;
458
459 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
460 if (cfg == NULL)
461 goto fail;
462
463 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
464 if (cfg->current_bss == NULL)
465 goto fail;
466
467 return cfg;
468
469 fail:
470 brcms_c_bsscfg_mfree(cfg);
471 return NULL;
472 }
473
474 static struct brcms_c_info *
475 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
476 {
477 struct brcms_c_info *wlc;
478
479 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
480 if (wlc == NULL) {
481 *err = 1002;
482 goto fail;
483 }
484
485 /* allocate struct brcms_c_pub state structure */
486 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
487 if (wlc->pub == NULL) {
488 *err = 1003;
489 goto fail;
490 }
491 wlc->pub->wlc = wlc;
492
493 /* allocate struct brcms_hardware state structure */
494
495 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
496 if (wlc->hw == NULL) {
497 *err = 1005;
498 goto fail;
499 }
500 wlc->hw->wlc = wlc;
501
502 wlc->hw->bandstate[0] =
503 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
504 if (wlc->hw->bandstate[0] == NULL) {
505 *err = 1006;
506 goto fail;
507 } else {
508 int i;
509
510 for (i = 1; i < MAXBANDS; i++)
511 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
512 ((unsigned long)wlc->hw->bandstate[0] +
513 (sizeof(struct brcms_hw_band) * i));
514 }
515
516 wlc->modulecb =
517 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
518 if (wlc->modulecb == NULL) {
519 *err = 1009;
520 goto fail;
521 }
522
523 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
524 if (wlc->default_bss == NULL) {
525 *err = 1010;
526 goto fail;
527 }
528
529 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
530 if (wlc->bsscfg == NULL) {
531 *err = 1011;
532 goto fail;
533 }
534
535 wlc->protection = kzalloc(sizeof(struct brcms_protection),
536 GFP_ATOMIC);
537 if (wlc->protection == NULL) {
538 *err = 1016;
539 goto fail;
540 }
541
542 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
543 if (wlc->stf == NULL) {
544 *err = 1017;
545 goto fail;
546 }
547
548 wlc->bandstate[0] =
549 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
550 if (wlc->bandstate[0] == NULL) {
551 *err = 1025;
552 goto fail;
553 } else {
554 int i;
555
556 for (i = 1; i < MAXBANDS; i++)
557 wlc->bandstate[i] = (struct brcms_band *)
558 ((unsigned long)wlc->bandstate[0]
559 + (sizeof(struct brcms_band)*i));
560 }
561
562 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
563 if (wlc->corestate == NULL) {
564 *err = 1026;
565 goto fail;
566 }
567
568 wlc->corestate->macstat_snapshot =
569 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
570 if (wlc->corestate->macstat_snapshot == NULL) {
571 *err = 1027;
572 goto fail;
573 }
574
575 return wlc;
576
577 fail:
578 brcms_c_detach_mfree(wlc);
579 return NULL;
580 }
581
582 /*
583 * Update the slot timing for standard 11b/g (20us slots)
584 * or shortslot 11g (9us slots)
585 * The PSM needs to be suspended for this call.
586 */
587 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
588 bool shortslot)
589 {
590 struct bcma_device *core = wlc_hw->d11core;
591
592 if (shortslot) {
593 /* 11g short slot: 11a timing */
594 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
595 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
596 } else {
597 /* 11g long slot: 11b timing */
598 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
599 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
600 }
601 }
602
603 /*
604 * calculate frame duration of a given rate and length, return
605 * time in usec unit
606 */
607 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
608 u8 preamble_type, uint mac_len)
609 {
610 uint nsyms, dur = 0, Ndps, kNdps;
611 uint rate = rspec2rate(ratespec);
612
613 if (rate == 0) {
614 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
615 wlc->pub->unit);
616 rate = BRCM_RATE_1M;
617 }
618
619 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
620 wlc->pub->unit, ratespec, preamble_type, mac_len);
621
622 if (is_mcs_rate(ratespec)) {
623 uint mcs = ratespec & RSPEC_RATE_MASK;
624 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
625
626 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
627 if (preamble_type == BRCMS_MM_PREAMBLE)
628 dur += PREN_MM_EXT;
629 /* 1000Ndbps = kbps * 4 */
630 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
631 rspec_issgi(ratespec)) * 4;
632
633 if (rspec_stc(ratespec) == 0)
634 nsyms =
635 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
636 APHY_TAIL_NBITS) * 1000, kNdps);
637 else
638 /* STBC needs to have even number of symbols */
639 nsyms =
640 2 *
641 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
642 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
643
644 dur += APHY_SYMBOL_TIME * nsyms;
645 if (wlc->band->bandtype == BRCM_BAND_2G)
646 dur += DOT11_OFDM_SIGNAL_EXTENSION;
647 } else if (is_ofdm_rate(rate)) {
648 dur = APHY_PREAMBLE_TIME;
649 dur += APHY_SIGNAL_TIME;
650 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
651 Ndps = rate * 2;
652 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
653 nsyms =
654 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
655 Ndps);
656 dur += APHY_SYMBOL_TIME * nsyms;
657 if (wlc->band->bandtype == BRCM_BAND_2G)
658 dur += DOT11_OFDM_SIGNAL_EXTENSION;
659 } else {
660 /*
661 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
662 * will divide out
663 */
664 mac_len = mac_len * 8 * 2;
665 /* calc ceiling of bits/rate = microseconds of air time */
666 dur = (mac_len + rate - 1) / rate;
667 if (preamble_type & BRCMS_SHORT_PREAMBLE)
668 dur += BPHY_PLCP_SHORT_TIME;
669 else
670 dur += BPHY_PLCP_TIME;
671 }
672 return dur;
673 }
674
675 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
676 const struct d11init *inits)
677 {
678 struct bcma_device *core = wlc_hw->d11core;
679 int i;
680 uint offset;
681 u16 size;
682 u32 value;
683
684 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
685
686 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
687 size = le16_to_cpu(inits[i].size);
688 offset = le16_to_cpu(inits[i].addr);
689 value = le32_to_cpu(inits[i].value);
690 if (size == 2)
691 bcma_write16(core, offset, value);
692 else if (size == 4)
693 bcma_write32(core, offset, value);
694 else
695 break;
696 }
697 }
698
699 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
700 {
701 u8 idx;
702 u16 addr[] = {
703 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
704 M_HOST_FLAGS5
705 };
706
707 for (idx = 0; idx < MHFMAX; idx++)
708 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
709 }
710
711 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
712 {
713 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
714 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
715
716 /* init microcode host flags */
717 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
718
719 /* do band-specific ucode IHR, SHM, and SCR inits */
720 if (D11REV_IS(wlc_hw->corerev, 23)) {
721 if (BRCMS_ISNPHY(wlc_hw->band))
722 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
723 else
724 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
725 " %d\n", __func__, wlc_hw->unit,
726 wlc_hw->corerev);
727 } else {
728 if (D11REV_IS(wlc_hw->corerev, 24)) {
729 if (BRCMS_ISLCNPHY(wlc_hw->band))
730 brcms_c_write_inits(wlc_hw,
731 ucode->d11lcn0bsinitvals24);
732 else
733 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
734 " core rev %d\n", __func__,
735 wlc_hw->unit, wlc_hw->corerev);
736 } else {
737 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
738 __func__, wlc_hw->unit, wlc_hw->corerev);
739 }
740 }
741 }
742
743 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
744 {
745 struct bcma_device *core = wlc_hw->d11core;
746 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
747
748 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
749 }
750
751 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
752 {
753 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
754
755 wlc_hw->phyclk = clk;
756
757 if (OFF == clk) { /* clear gmode bit, put phy into reset */
758
759 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
760 (SICF_PRST | SICF_FGC));
761 udelay(1);
762 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
763 udelay(1);
764
765 } else { /* take phy out of reset */
766
767 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
768 udelay(1);
769 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
770 udelay(1);
771
772 }
773 }
774
775 /* low-level band switch utility routine */
776 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
777 {
778 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
779 bandunit);
780
781 wlc_hw->band = wlc_hw->bandstate[bandunit];
782
783 /*
784 * BMAC_NOTE:
785 * until we eliminate need for wlc->band refs in low level code
786 */
787 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
788
789 /* set gmode core flag */
790 if (wlc_hw->sbclk && !wlc_hw->noreset) {
791 u32 gmode = 0;
792
793 if (bandunit == 0)
794 gmode = SICF_GMODE;
795
796 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
797 }
798 }
799
800 /* switch to new band but leave it inactive */
801 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
802 {
803 struct brcms_hardware *wlc_hw = wlc->hw;
804 u32 macintmask;
805 u32 macctrl;
806
807 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
808 macctrl = bcma_read32(wlc_hw->d11core,
809 D11REGOFFS(maccontrol));
810 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
811
812 /* disable interrupts */
813 macintmask = brcms_intrsoff(wlc->wl);
814
815 /* radio off */
816 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
817
818 brcms_b_core_phy_clk(wlc_hw, OFF);
819
820 brcms_c_setxband(wlc_hw, bandunit);
821
822 return macintmask;
823 }
824
825 /* process an individual struct tx_status */
826 static bool
827 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
828 {
829 struct sk_buff *p;
830 uint queue;
831 struct d11txh *txh;
832 struct scb *scb = NULL;
833 bool free_pdu;
834 int tx_rts, tx_frame_count, tx_rts_count;
835 uint totlen, supr_status;
836 bool lastframe;
837 struct ieee80211_hdr *h;
838 u16 mcl;
839 struct ieee80211_tx_info *tx_info;
840 struct ieee80211_tx_rate *txrate;
841 int i;
842
843 /* discard intermediate indications for ucode with one legitimate case:
844 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
845 * but the subsequent tx of DATA failed. so it will start rts/cts
846 * from the beginning (resetting the rts transmission count)
847 */
848 if (!(txs->status & TX_STATUS_AMPDU)
849 && (txs->status & TX_STATUS_INTERMEDIATE)) {
850 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
851 return false;
852 }
853
854 queue = txs->frameid & TXFID_QUEUE_MASK;
855 if (queue >= NFIFO) {
856 p = NULL;
857 goto fatal;
858 }
859
860 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
861 if (p == NULL)
862 goto fatal;
863
864 txh = (struct d11txh *) (p->data);
865 mcl = le16_to_cpu(txh->MacTxControlLow);
866
867 if (txs->phyerr) {
868 if (brcm_msg_level & LOG_ERROR_VAL) {
869 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
870 txs->phyerr, txh->MainRates);
871 brcms_c_print_txdesc(txh);
872 }
873 brcms_c_print_txstatus(txs);
874 }
875
876 if (txs->frameid != le16_to_cpu(txh->TxFrameID))
877 goto fatal;
878 tx_info = IEEE80211_SKB_CB(p);
879 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
880
881 if (tx_info->control.sta)
882 scb = &wlc->pri_scb;
883
884 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
885 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
886 return false;
887 }
888
889 supr_status = txs->status & TX_STATUS_SUPR_MASK;
890 if (supr_status == TX_STATUS_SUPR_BADCH)
891 BCMMSG(wlc->wiphy,
892 "%s: Pkt tx suppressed, possibly channel %d\n",
893 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
894
895 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
896 tx_frame_count =
897 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
898 tx_rts_count =
899 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
900
901 lastframe = !ieee80211_has_morefrags(h->frame_control);
902
903 if (!lastframe) {
904 wiphy_err(wlc->wiphy, "Not last frame!\n");
905 } else {
906 /*
907 * Set information to be consumed by Minstrel ht.
908 *
909 * The "fallback limit" is the number of tx attempts a given
910 * MPDU is sent at the "primary" rate. Tx attempts beyond that
911 * limit are sent at the "secondary" rate.
912 * A 'short frame' does not exceed RTS treshold.
913 */
914 u16 sfbl, /* Short Frame Rate Fallback Limit */
915 lfbl, /* Long Frame Rate Fallback Limit */
916 fbl;
917
918 if (queue < IEEE80211_NUM_ACS) {
919 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
920 EDCF_SFB);
921 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
922 EDCF_LFB);
923 } else {
924 sfbl = wlc->SFBL;
925 lfbl = wlc->LFBL;
926 }
927
928 txrate = tx_info->status.rates;
929 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
930 fbl = lfbl;
931 else
932 fbl = sfbl;
933
934 ieee80211_tx_info_clear_status(tx_info);
935
936 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
937 /*
938 * rate selection requested a fallback rate
939 * and we used it
940 */
941 txrate[0].count = fbl;
942 txrate[1].count = tx_frame_count - fbl;
943 } else {
944 /*
945 * rate selection did not request fallback rate, or
946 * we didn't need it
947 */
948 txrate[0].count = tx_frame_count;
949 /*
950 * rc80211_minstrel.c:minstrel_tx_status() expects
951 * unused rates to be marked with idx = -1
952 */
953 txrate[1].idx = -1;
954 txrate[1].count = 0;
955 }
956
957 /* clear the rest of the rates */
958 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
959 txrate[i].idx = -1;
960 txrate[i].count = 0;
961 }
962
963 if (txs->status & TX_STATUS_ACK_RCV)
964 tx_info->flags |= IEEE80211_TX_STAT_ACK;
965 }
966
967 totlen = p->len;
968 free_pdu = true;
969
970 brcms_c_txfifo_complete(wlc, queue, 1);
971
972 if (lastframe) {
973 /* remove PLCP & Broadcom tx descriptor header */
974 skb_pull(p, D11_PHY_HDR_LEN);
975 skb_pull(p, D11_TXH_LEN);
976 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
977 } else {
978 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
979 "tx_status\n", __func__);
980 }
981
982 return false;
983
984 fatal:
985 if (p)
986 brcmu_pkt_buf_free_skb(p);
987
988 return true;
989
990 }
991
992 /* process tx completion events in BMAC
993 * Return true if more tx status need to be processed. false otherwise.
994 */
995 static bool
996 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
997 {
998 bool morepending = false;
999 struct brcms_c_info *wlc = wlc_hw->wlc;
1000 struct bcma_device *core;
1001 struct tx_status txstatus, *txs;
1002 u32 s1, s2;
1003 uint n = 0;
1004 /*
1005 * Param 'max_tx_num' indicates max. # tx status to process before
1006 * break out.
1007 */
1008 uint max_tx_num = bound ? TXSBND : -1;
1009
1010 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1011
1012 txs = &txstatus;
1013 core = wlc_hw->d11core;
1014 *fatal = false;
1015 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1016 while (!(*fatal)
1017 && (s1 & TXS_V)) {
1018
1019 if (s1 == 0xffffffff) {
1020 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1021 wlc_hw->unit, __func__);
1022 return morepending;
1023 }
1024 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1025
1026 txs->status = s1 & TXS_STATUS_MASK;
1027 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1028 txs->sequence = s2 & TXS_SEQ_MASK;
1029 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1030 txs->lasttxtime = 0;
1031
1032 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1033
1034 /* !give others some time to run! */
1035 if (++n >= max_tx_num)
1036 break;
1037 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1038 }
1039
1040 if (*fatal)
1041 return 0;
1042
1043 if (n >= max_tx_num)
1044 morepending = true;
1045
1046 if (!pktq_empty(&wlc->pkt_queue->q))
1047 brcms_c_send_q(wlc);
1048
1049 return morepending;
1050 }
1051
1052 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1053 {
1054 if (!wlc->bsscfg->BSS)
1055 /*
1056 * DirFrmQ is now valid...defer setting until end
1057 * of ATIM window
1058 */
1059 wlc->qvalid |= MCMD_DIRFRMQVAL;
1060 }
1061
1062 /* set initial host flags value */
1063 static void
1064 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1065 {
1066 struct brcms_hardware *wlc_hw = wlc->hw;
1067
1068 memset(mhfs, 0, MHFMAX * sizeof(u16));
1069
1070 mhfs[MHF2] |= mhf2_init;
1071
1072 /* prohibit use of slowclock on multifunction boards */
1073 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1074 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1075
1076 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1077 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1078 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1079 }
1080 }
1081
1082 static uint
1083 dmareg(uint direction, uint fifonum)
1084 {
1085 if (direction == DMA_TX)
1086 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1087 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1088 }
1089
1090 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1091 {
1092 uint i;
1093 char name[8];
1094 /*
1095 * ucode host flag 2 needed for pio mode, independent of band and fifo
1096 */
1097 u16 pio_mhf2 = 0;
1098 struct brcms_hardware *wlc_hw = wlc->hw;
1099 uint unit = wlc_hw->unit;
1100 struct wiphy *wiphy = wlc->wiphy;
1101
1102 /* name and offsets for dma_attach */
1103 snprintf(name, sizeof(name), "wl%d", unit);
1104
1105 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1106 int dma_attach_err = 0;
1107
1108 /*
1109 * FIFO 0
1110 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1111 * RX: RX_FIFO (RX data packets)
1112 */
1113 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1114 (wme ? dmareg(DMA_TX, 0) : 0),
1115 dmareg(DMA_RX, 0),
1116 (wme ? NTXD : 0), NRXD,
1117 RXBUFSZ, -1, NRXBUFPOST,
1118 BRCMS_HWRXOFF, &brcm_msg_level);
1119 dma_attach_err |= (NULL == wlc_hw->di[0]);
1120
1121 /*
1122 * FIFO 1
1123 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1124 * (legacy) TX_DATA_FIFO (TX data packets)
1125 * RX: UNUSED
1126 */
1127 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1128 dmareg(DMA_TX, 1), 0,
1129 NTXD, 0, 0, -1, 0, 0,
1130 &brcm_msg_level);
1131 dma_attach_err |= (NULL == wlc_hw->di[1]);
1132
1133 /*
1134 * FIFO 2
1135 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1136 * RX: UNUSED
1137 */
1138 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1139 dmareg(DMA_TX, 2), 0,
1140 NTXD, 0, 0, -1, 0, 0,
1141 &brcm_msg_level);
1142 dma_attach_err |= (NULL == wlc_hw->di[2]);
1143 /*
1144 * FIFO 3
1145 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1146 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1147 */
1148 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1149 dmareg(DMA_TX, 3),
1150 0, NTXD, 0, 0, -1,
1151 0, 0, &brcm_msg_level);
1152 dma_attach_err |= (NULL == wlc_hw->di[3]);
1153 /* Cleaner to leave this as if with AP defined */
1154
1155 if (dma_attach_err) {
1156 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1157 "\n", unit);
1158 return false;
1159 }
1160
1161 /* get pointer to dma engine tx flow control variable */
1162 for (i = 0; i < NFIFO; i++)
1163 if (wlc_hw->di[i])
1164 wlc_hw->txavail[i] =
1165 (uint *) dma_getvar(wlc_hw->di[i],
1166 "&txavail");
1167 }
1168
1169 /* initial ucode host flags */
1170 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1171
1172 return true;
1173 }
1174
1175 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1176 {
1177 uint j;
1178
1179 for (j = 0; j < NFIFO; j++) {
1180 if (wlc_hw->di[j]) {
1181 dma_detach(wlc_hw->di[j]);
1182 wlc_hw->di[j] = NULL;
1183 }
1184 }
1185 }
1186
1187 /*
1188 * Initialize brcms_c_info default values ...
1189 * may get overrides later in this function
1190 * BMAC_NOTES, move low out and resolve the dangling ones
1191 */
1192 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1193 {
1194 struct brcms_c_info *wlc = wlc_hw->wlc;
1195
1196 /* set default sw macintmask value */
1197 wlc->defmacintmask = DEF_MACINTMASK;
1198
1199 /* various 802.11g modes */
1200 wlc_hw->shortslot = false;
1201
1202 wlc_hw->SFBL = RETRY_SHORT_FB;
1203 wlc_hw->LFBL = RETRY_LONG_FB;
1204
1205 /* default mac retry limits */
1206 wlc_hw->SRL = RETRY_SHORT_DEF;
1207 wlc_hw->LRL = RETRY_LONG_DEF;
1208 wlc_hw->chanspec = ch20mhz_chspec(1);
1209 }
1210
1211 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1212 {
1213 /* delay before first read of ucode state */
1214 udelay(40);
1215
1216 /* wait until ucode is no longer asleep */
1217 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1218 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1219 }
1220
1221 /* control chip clock to save power, enable dynamic clock or force fast clock */
1222 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1223 {
1224 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1225 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1226 * on backplane, but mac core will still run on ALP(not HT) when
1227 * it enters powersave mode, which means the FCA bit may not be
1228 * set. Should wakeup mac if driver wants it to run on HT.
1229 */
1230
1231 if (wlc_hw->clk) {
1232 if (mode == CLK_FAST) {
1233 bcma_set32(wlc_hw->d11core,
1234 D11REGOFFS(clk_ctl_st),
1235 CCS_FORCEHT);
1236
1237 udelay(64);
1238
1239 SPINWAIT(
1240 ((bcma_read32(wlc_hw->d11core,
1241 D11REGOFFS(clk_ctl_st)) &
1242 CCS_HTAVAIL) == 0),
1243 PMU_MAX_TRANSITION_DLY);
1244 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1245 D11REGOFFS(clk_ctl_st)) &
1246 CCS_HTAVAIL));
1247 } else {
1248 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1249 (bcma_read32(wlc_hw->d11core,
1250 D11REGOFFS(clk_ctl_st)) &
1251 (CCS_FORCEHT | CCS_HTAREQ)))
1252 SPINWAIT(
1253 ((bcma_read32(wlc_hw->d11core,
1254 offsetof(struct d11regs,
1255 clk_ctl_st)) &
1256 CCS_HTAVAIL) == 0),
1257 PMU_MAX_TRANSITION_DLY);
1258 bcma_mask32(wlc_hw->d11core,
1259 D11REGOFFS(clk_ctl_st),
1260 ~CCS_FORCEHT);
1261 }
1262 }
1263 wlc_hw->forcefastclk = (mode == CLK_FAST);
1264 } else {
1265
1266 /* old chips w/o PMU, force HT through cc,
1267 * then use FCA to verify mac is running fast clock
1268 */
1269
1270 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1271
1272 /* check fast clock is available (if core is not in reset) */
1273 if (wlc_hw->forcefastclk && wlc_hw->clk)
1274 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1275 SISF_FCLKA));
1276
1277 /*
1278 * keep the ucode wake bit on if forcefastclk is on since we
1279 * do not want ucode to put us back to slow clock when it dozes
1280 * for PM mode. Code below matches the wake override bit with
1281 * current forcefastclk state. Only setting bit in wake_override
1282 * instead of waking ucode immediately since old code had this
1283 * behavior. Older code set wlc->forcefastclk but only had the
1284 * wake happen if the wakup_ucode work (protected by an up
1285 * check) was executed just below.
1286 */
1287 if (wlc_hw->forcefastclk)
1288 mboolset(wlc_hw->wake_override,
1289 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1290 else
1291 mboolclr(wlc_hw->wake_override,
1292 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1293 }
1294 }
1295
1296 /* set or clear ucode host flag bits
1297 * it has an optimization for no-change write
1298 * it only writes through shared memory when the core has clock;
1299 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1300 *
1301 *
1302 * bands values are: BRCM_BAND_AUTO <--- Current band only
1303 * BRCM_BAND_5G <--- 5G band only
1304 * BRCM_BAND_2G <--- 2G band only
1305 * BRCM_BAND_ALL <--- All bands
1306 */
1307 void
1308 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1309 int bands)
1310 {
1311 u16 save;
1312 u16 addr[MHFMAX] = {
1313 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1314 M_HOST_FLAGS5
1315 };
1316 struct brcms_hw_band *band;
1317
1318 if ((val & ~mask) || idx >= MHFMAX)
1319 return; /* error condition */
1320
1321 switch (bands) {
1322 /* Current band only or all bands,
1323 * then set the band to current band
1324 */
1325 case BRCM_BAND_AUTO:
1326 case BRCM_BAND_ALL:
1327 band = wlc_hw->band;
1328 break;
1329 case BRCM_BAND_5G:
1330 band = wlc_hw->bandstate[BAND_5G_INDEX];
1331 break;
1332 case BRCM_BAND_2G:
1333 band = wlc_hw->bandstate[BAND_2G_INDEX];
1334 break;
1335 default:
1336 band = NULL; /* error condition */
1337 }
1338
1339 if (band) {
1340 save = band->mhfs[idx];
1341 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1342
1343 /* optimization: only write through if changed, and
1344 * changed band is the current band
1345 */
1346 if (wlc_hw->clk && (band->mhfs[idx] != save)
1347 && (band == wlc_hw->band))
1348 brcms_b_write_shm(wlc_hw, addr[idx],
1349 (u16) band->mhfs[idx]);
1350 }
1351
1352 if (bands == BRCM_BAND_ALL) {
1353 wlc_hw->bandstate[0]->mhfs[idx] =
1354 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1355 wlc_hw->bandstate[1]->mhfs[idx] =
1356 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1357 }
1358 }
1359
1360 /* set the maccontrol register to desired reset state and
1361 * initialize the sw cache of the register
1362 */
1363 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1364 {
1365 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1366 wlc_hw->maccontrol = 0;
1367 wlc_hw->suspended_fifos = 0;
1368 wlc_hw->wake_override = 0;
1369 wlc_hw->mute_override = 0;
1370 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1371 }
1372
1373 /*
1374 * write the software state of maccontrol and
1375 * overrides to the maccontrol register
1376 */
1377 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1378 {
1379 u32 maccontrol = wlc_hw->maccontrol;
1380
1381 /* OR in the wake bit if overridden */
1382 if (wlc_hw->wake_override)
1383 maccontrol |= MCTL_WAKE;
1384
1385 /* set AP and INFRA bits for mute if needed */
1386 if (wlc_hw->mute_override) {
1387 maccontrol &= ~(MCTL_AP);
1388 maccontrol |= MCTL_INFRA;
1389 }
1390
1391 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1392 maccontrol);
1393 }
1394
1395 /* set or clear maccontrol bits */
1396 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1397 {
1398 u32 maccontrol;
1399 u32 new_maccontrol;
1400
1401 if (val & ~mask)
1402 return; /* error condition */
1403 maccontrol = wlc_hw->maccontrol;
1404 new_maccontrol = (maccontrol & ~mask) | val;
1405
1406 /* if the new maccontrol value is the same as the old, nothing to do */
1407 if (new_maccontrol == maccontrol)
1408 return;
1409
1410 /* something changed, cache the new value */
1411 wlc_hw->maccontrol = new_maccontrol;
1412
1413 /* write the new values with overrides applied */
1414 brcms_c_mctrl_write(wlc_hw);
1415 }
1416
1417 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1418 u32 override_bit)
1419 {
1420 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1421 mboolset(wlc_hw->wake_override, override_bit);
1422 return;
1423 }
1424
1425 mboolset(wlc_hw->wake_override, override_bit);
1426
1427 brcms_c_mctrl_write(wlc_hw);
1428 brcms_b_wait_for_wake(wlc_hw);
1429 }
1430
1431 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1432 u32 override_bit)
1433 {
1434 mboolclr(wlc_hw->wake_override, override_bit);
1435
1436 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1437 return;
1438
1439 brcms_c_mctrl_write(wlc_hw);
1440 }
1441
1442 /* When driver needs ucode to stop beaconing, it has to make sure that
1443 * MCTL_AP is clear and MCTL_INFRA is set
1444 * Mode MCTL_AP MCTL_INFRA
1445 * AP 1 1
1446 * STA 0 1 <--- This will ensure no beacons
1447 * IBSS 0 0
1448 */
1449 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1450 {
1451 wlc_hw->mute_override = 1;
1452
1453 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1454 * override, then there is no change to write
1455 */
1456 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1457 return;
1458
1459 brcms_c_mctrl_write(wlc_hw);
1460 }
1461
1462 /* Clear the override on AP and INFRA bits */
1463 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1464 {
1465 if (wlc_hw->mute_override == 0)
1466 return;
1467
1468 wlc_hw->mute_override = 0;
1469
1470 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1471 * override, then there is no change to write
1472 */
1473 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1474 return;
1475
1476 brcms_c_mctrl_write(wlc_hw);
1477 }
1478
1479 /*
1480 * Write a MAC address to the given match reg offset in the RXE match engine.
1481 */
1482 static void
1483 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1484 const u8 *addr)
1485 {
1486 struct bcma_device *core = wlc_hw->d11core;
1487 u16 mac_l;
1488 u16 mac_m;
1489 u16 mac_h;
1490
1491 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1492 wlc_hw->unit);
1493
1494 mac_l = addr[0] | (addr[1] << 8);
1495 mac_m = addr[2] | (addr[3] << 8);
1496 mac_h = addr[4] | (addr[5] << 8);
1497
1498 /* enter the MAC addr into the RXE match registers */
1499 bcma_write16(core, D11REGOFFS(rcm_ctl),
1500 RCM_INC_DATA | match_reg_offset);
1501 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1502 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1503 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1504 }
1505
1506 void
1507 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1508 void *buf)
1509 {
1510 struct bcma_device *core = wlc_hw->d11core;
1511 u32 word;
1512 __le32 word_le;
1513 __be32 word_be;
1514 bool be_bit;
1515 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1516
1517 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1518
1519 /* if MCTL_BIGEND bit set in mac control register,
1520 * the chip swaps data in fifo, as well as data in
1521 * template ram
1522 */
1523 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1524
1525 while (len > 0) {
1526 memcpy(&word, buf, sizeof(u32));
1527
1528 if (be_bit) {
1529 word_be = cpu_to_be32(word);
1530 word = *(u32 *)&word_be;
1531 } else {
1532 word_le = cpu_to_le32(word);
1533 word = *(u32 *)&word_le;
1534 }
1535
1536 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1537
1538 buf = (u8 *) buf + sizeof(u32);
1539 len -= sizeof(u32);
1540 }
1541 }
1542
1543 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1544 {
1545 wlc_hw->band->CWmin = newmin;
1546
1547 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1548 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1549 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1550 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1551 }
1552
1553 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1554 {
1555 wlc_hw->band->CWmax = newmax;
1556
1557 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1558 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1559 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1560 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1561 }
1562
1563 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1564 {
1565 bool fastclk;
1566
1567 /* request FAST clock if not on */
1568 fastclk = wlc_hw->forcefastclk;
1569 if (!fastclk)
1570 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1571
1572 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1573
1574 brcms_b_phy_reset(wlc_hw);
1575 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1576
1577 /* restore the clk */
1578 if (!fastclk)
1579 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1580 }
1581
1582 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1583 {
1584 u16 v;
1585 struct brcms_c_info *wlc = wlc_hw->wlc;
1586 /* update SYNTHPU_DLY */
1587
1588 if (BRCMS_ISLCNPHY(wlc->band))
1589 v = SYNTHPU_DLY_LPPHY_US;
1590 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1591 v = SYNTHPU_DLY_NPHY_US;
1592 else
1593 v = SYNTHPU_DLY_BPHY_US;
1594
1595 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1596 }
1597
1598 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1599 {
1600 u16 phyctl;
1601 u16 phytxant = wlc_hw->bmac_phytxant;
1602 u16 mask = PHY_TXC_ANT_MASK;
1603
1604 /* set the Probe Response frame phy control word */
1605 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1606 phyctl = (phyctl & ~mask) | phytxant;
1607 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1608
1609 /* set the Response (ACK/CTS) frame phy control word */
1610 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1611 phyctl = (phyctl & ~mask) | phytxant;
1612 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1613 }
1614
1615 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1616 u8 rate)
1617 {
1618 uint i;
1619 u8 plcp_rate = 0;
1620 struct plcp_signal_rate_lookup {
1621 u8 rate;
1622 u8 signal_rate;
1623 };
1624 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1625 const struct plcp_signal_rate_lookup rate_lookup[] = {
1626 {BRCM_RATE_6M, 0xB},
1627 {BRCM_RATE_9M, 0xF},
1628 {BRCM_RATE_12M, 0xA},
1629 {BRCM_RATE_18M, 0xE},
1630 {BRCM_RATE_24M, 0x9},
1631 {BRCM_RATE_36M, 0xD},
1632 {BRCM_RATE_48M, 0x8},
1633 {BRCM_RATE_54M, 0xC}
1634 };
1635
1636 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1637 if (rate == rate_lookup[i].rate) {
1638 plcp_rate = rate_lookup[i].signal_rate;
1639 break;
1640 }
1641 }
1642
1643 /* Find the SHM pointer to the rate table entry by looking in the
1644 * Direct-map Table
1645 */
1646 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1647 }
1648
1649 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1650 {
1651 u8 rate;
1652 u8 rates[8] = {
1653 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1654 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1655 };
1656 u16 entry_ptr;
1657 u16 pctl1;
1658 uint i;
1659
1660 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1661 return;
1662
1663 /* walk the phy rate table and update the entries */
1664 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1665 rate = rates[i];
1666
1667 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1668
1669 /* read the SHM Rate Table entry OFDM PCTL1 values */
1670 pctl1 =
1671 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1672
1673 /* modify the value */
1674 pctl1 &= ~PHY_TXC1_MODE_MASK;
1675 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1676
1677 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1678 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1679 pctl1);
1680 }
1681 }
1682
1683 /* band-specific init */
1684 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1685 {
1686 struct brcms_hardware *wlc_hw = wlc->hw;
1687
1688 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1689 wlc_hw->band->bandunit);
1690
1691 brcms_c_ucode_bsinit(wlc_hw);
1692
1693 wlc_phy_init(wlc_hw->band->pi, chanspec);
1694
1695 brcms_c_ucode_txant_set(wlc_hw);
1696
1697 /*
1698 * cwmin is band-specific, update hardware
1699 * with value for current band
1700 */
1701 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1702 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1703
1704 brcms_b_update_slot_timing(wlc_hw,
1705 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1706 true : wlc_hw->shortslot);
1707
1708 /* write phytype and phyvers */
1709 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1710 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1711
1712 /*
1713 * initialize the txphyctl1 rate table since
1714 * shmem is shared between bands
1715 */
1716 brcms_upd_ofdm_pctl1_table(wlc_hw);
1717
1718 brcms_b_upd_synthpu(wlc_hw);
1719 }
1720
1721 /* Perform a soft reset of the PHY PLL */
1722 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1723 {
1724 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1725
1726 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1727 ~0, 0);
1728 udelay(1);
1729 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1730 0x4, 0);
1731 udelay(1);
1732 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1733 0x4, 4);
1734 udelay(1);
1735 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1736 0x4, 0);
1737 udelay(1);
1738 }
1739
1740 /* light way to turn on phy clock without reset for NPHY only
1741 * refer to brcms_b_core_phy_clk for full version
1742 */
1743 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1744 {
1745 /* support(necessary for NPHY and HYPHY) only */
1746 if (!BRCMS_ISNPHY(wlc_hw->band))
1747 return;
1748
1749 if (ON == clk)
1750 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1751 else
1752 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1753
1754 }
1755
1756 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1757 {
1758 if (ON == clk)
1759 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1760 else
1761 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1762 }
1763
1764 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1765 {
1766 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1767 u32 phy_bw_clkbits;
1768 bool phy_in_reset = false;
1769
1770 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1771
1772 if (pih == NULL)
1773 return;
1774
1775 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1776
1777 /* Specific reset sequence required for NPHY rev 3 and 4 */
1778 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1779 NREV_LE(wlc_hw->band->phyrev, 4)) {
1780 /* Set the PHY bandwidth */
1781 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1782
1783 udelay(1);
1784
1785 /* Perform a soft reset of the PHY PLL */
1786 brcms_b_core_phypll_reset(wlc_hw);
1787
1788 /* reset the PHY */
1789 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1790 (SICF_PRST | SICF_PCLKE));
1791 phy_in_reset = true;
1792 } else {
1793 brcms_b_core_ioctl(wlc_hw,
1794 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1795 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1796 }
1797
1798 udelay(2);
1799 brcms_b_core_phy_clk(wlc_hw, ON);
1800
1801 if (pih)
1802 wlc_phy_anacore(pih, ON);
1803 }
1804
1805 /* switch to and initialize new band */
1806 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1807 u16 chanspec) {
1808 struct brcms_c_info *wlc = wlc_hw->wlc;
1809 u32 macintmask;
1810
1811 /* Enable the d11 core before accessing it */
1812 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1813 bcma_core_enable(wlc_hw->d11core, 0);
1814 brcms_c_mctrl_reset(wlc_hw);
1815 }
1816
1817 macintmask = brcms_c_setband_inact(wlc, bandunit);
1818
1819 if (!wlc_hw->up)
1820 return;
1821
1822 brcms_b_core_phy_clk(wlc_hw, ON);
1823
1824 /* band-specific initializations */
1825 brcms_b_bsinit(wlc, chanspec);
1826
1827 /*
1828 * If there are any pending software interrupt bits,
1829 * then replace these with a harmless nonzero value
1830 * so brcms_c_dpc() will re-enable interrupts when done.
1831 */
1832 if (wlc->macintstatus)
1833 wlc->macintstatus = MI_DMAINT;
1834
1835 /* restore macintmask */
1836 brcms_intrsrestore(wlc->wl, macintmask);
1837
1838 /* ucode should still be suspended.. */
1839 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1840 MCTL_EN_MAC) != 0);
1841 }
1842
1843 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1844 {
1845
1846 /* reject unsupported corerev */
1847 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1848 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1849 wlc_hw->corerev);
1850 return false;
1851 }
1852
1853 return true;
1854 }
1855
1856 /* Validate some board info parameters */
1857 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1858 {
1859 uint boardrev = wlc_hw->boardrev;
1860
1861 /* 4 bits each for board type, major, minor, and tiny version */
1862 uint brt = (boardrev & 0xf000) >> 12;
1863 uint b0 = (boardrev & 0xf00) >> 8;
1864 uint b1 = (boardrev & 0xf0) >> 4;
1865 uint b2 = boardrev & 0xf;
1866
1867 /* voards from other vendors are always considered valid */
1868 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1869 return true;
1870
1871 /* do some boardrev sanity checks when boardvendor is Broadcom */
1872 if (boardrev == 0)
1873 return false;
1874
1875 if (boardrev <= 0xff)
1876 return true;
1877
1878 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1879 || (b2 > 9))
1880 return false;
1881
1882 return true;
1883 }
1884
1885 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1886 {
1887 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1888
1889 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1890 if (!is_zero_ether_addr(sprom->il0mac)) {
1891 memcpy(etheraddr, sprom->il0mac, 6);
1892 return;
1893 }
1894
1895 if (wlc_hw->_nbands > 1)
1896 memcpy(etheraddr, sprom->et1mac, 6);
1897 else
1898 memcpy(etheraddr, sprom->il0mac, 6);
1899 }
1900
1901 /* power both the pll and external oscillator on/off */
1902 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1903 {
1904 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
1905
1906 /*
1907 * dont power down if plldown is false or
1908 * we must poll hw radio disable
1909 */
1910 if (!want && wlc_hw->pllreq)
1911 return;
1912
1913 if (wlc_hw->sih)
1914 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
1915
1916 wlc_hw->sbclk = want;
1917 if (!wlc_hw->sbclk) {
1918 wlc_hw->clk = false;
1919 if (wlc_hw->band && wlc_hw->band->pi)
1920 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1921 }
1922 }
1923
1924 /*
1925 * Return true if radio is disabled, otherwise false.
1926 * hw radio disable signal is an external pin, users activate it asynchronously
1927 * this function could be called when driver is down and w/o clock
1928 * it operates on different registers depending on corerev and boardflag.
1929 */
1930 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1931 {
1932 bool v, clk, xtal;
1933 u32 flags = 0;
1934
1935 xtal = wlc_hw->sbclk;
1936 if (!xtal)
1937 brcms_b_xtal(wlc_hw, ON);
1938
1939 /* may need to take core out of reset first */
1940 clk = wlc_hw->clk;
1941 if (!clk) {
1942 /*
1943 * mac no longer enables phyclk automatically when driver
1944 * accesses phyreg throughput mac. This can be skipped since
1945 * only mac reg is accessed below
1946 */
1947 flags |= SICF_PCLKE;
1948
1949 /*
1950 * TODO: test suspend/resume
1951 *
1952 * AI chip doesn't restore bar0win2 on
1953 * hibernation/resume, need sw fixup
1954 */
1955
1956 bcma_core_enable(wlc_hw->d11core, flags);
1957 brcms_c_mctrl_reset(wlc_hw);
1958 }
1959
1960 v = ((bcma_read32(wlc_hw->d11core,
1961 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1962
1963 /* put core back into reset */
1964 if (!clk)
1965 bcma_core_disable(wlc_hw->d11core, 0);
1966
1967 if (!xtal)
1968 brcms_b_xtal(wlc_hw, OFF);
1969
1970 return v;
1971 }
1972
1973 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1974 {
1975 struct dma_pub *di = wlc_hw->di[fifo];
1976 return dma_rxreset(di);
1977 }
1978
1979 /* d11 core reset
1980 * ensure fask clock during reset
1981 * reset dma
1982 * reset d11(out of reset)
1983 * reset phy(out of reset)
1984 * clear software macintstatus for fresh new start
1985 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1986 */
1987 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1988 {
1989 uint i;
1990 bool fastclk;
1991
1992 if (flags == BRCMS_USE_COREFLAGS)
1993 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1994
1995 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1996
1997 /* request FAST clock if not on */
1998 fastclk = wlc_hw->forcefastclk;
1999 if (!fastclk)
2000 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2001
2002 /* reset the dma engines except first time thru */
2003 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2004 for (i = 0; i < NFIFO; i++)
2005 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2006 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2007 "dma_txreset[%d]: cannot stop dma\n",
2008 wlc_hw->unit, __func__, i);
2009
2010 if ((wlc_hw->di[RX_FIFO])
2011 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2012 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2013 "[%d]: cannot stop dma\n",
2014 wlc_hw->unit, __func__, RX_FIFO);
2015 }
2016 /* if noreset, just stop the psm and return */
2017 if (wlc_hw->noreset) {
2018 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2019 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2020 return;
2021 }
2022
2023 /*
2024 * mac no longer enables phyclk automatically when driver accesses
2025 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2026 * band->pi is invalid. need to enable PHY CLK
2027 */
2028 flags |= SICF_PCLKE;
2029
2030 /*
2031 * reset the core
2032 * In chips with PMU, the fastclk request goes through d11 core
2033 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2034 *
2035 * This adds some delay and we can optimize it by also requesting
2036 * fastclk through chipcommon during this period if necessary. But
2037 * that has to work coordinate with other driver like mips/arm since
2038 * they may touch chipcommon as well.
2039 */
2040 wlc_hw->clk = false;
2041 bcma_core_enable(wlc_hw->d11core, flags);
2042 wlc_hw->clk = true;
2043 if (wlc_hw->band && wlc_hw->band->pi)
2044 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2045
2046 brcms_c_mctrl_reset(wlc_hw);
2047
2048 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2049 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2050
2051 brcms_b_phy_reset(wlc_hw);
2052
2053 /* turn on PHY_PLL */
2054 brcms_b_core_phypll_ctl(wlc_hw, true);
2055
2056 /* clear sw intstatus */
2057 wlc_hw->wlc->macintstatus = 0;
2058
2059 /* restore the clk setting */
2060 if (!fastclk)
2061 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2062 }
2063
2064 /* txfifo sizes needs to be modified(increased) since the newer cores
2065 * have more memory.
2066 */
2067 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2068 {
2069 struct bcma_device *core = wlc_hw->d11core;
2070 u16 fifo_nu;
2071 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2072 u16 txfifo_def, txfifo_def1;
2073 u16 txfifo_cmd;
2074
2075 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2076 txfifo_startblk = TXFIFO_START_BLK;
2077
2078 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2079 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2080
2081 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2082 txfifo_def = (txfifo_startblk & 0xff) |
2083 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2084 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2085 ((((txfifo_endblk -
2086 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2087 txfifo_cmd =
2088 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2089
2090 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2091 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2092 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2093
2094 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2095
2096 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2097 }
2098 /*
2099 * need to propagate to shm location to be in sync since ucode/hw won't
2100 * do this
2101 */
2102 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2103 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2104 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2105 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2106 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2107 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2108 xmtfifo_sz[TX_AC_BK_FIFO]));
2109 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2110 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2111 xmtfifo_sz[TX_BCMC_FIFO]));
2112 }
2113
2114 /* This function is used for changing the tsf frac register
2115 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2116 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2117 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2118 * HTPHY Formula is 2^26/freq(MHz) e.g.
2119 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2120 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2121 * For spuron: 123MHz -> 2^26/123 = 545600.5
2122 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2123 * For spur off: 120MHz -> 2^26/120 = 559240.5
2124 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2125 */
2126
2127 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2128 {
2129 struct bcma_device *core = wlc_hw->d11core;
2130
2131 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
2132 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
2133 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2134 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2135 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2136 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2137 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2138 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2139 } else { /* 120Mhz */
2140 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2141 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2142 }
2143 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2144 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2147 } else { /* 80Mhz */
2148 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2149 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2150 }
2151 }
2152 }
2153
2154 /* Initialize GPIOs that are controlled by D11 core */
2155 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2156 {
2157 struct brcms_hardware *wlc_hw = wlc->hw;
2158 u32 gc, gm;
2159
2160 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2161 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2162
2163 /*
2164 * Common GPIO setup:
2165 * G0 = LED 0 = WLAN Activity
2166 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2167 * G2 = LED 2 = WLAN 5 GHz Radio State
2168 * G4 = radio disable input (HI enabled, LO disabled)
2169 */
2170
2171 gc = gm = 0;
2172
2173 /* Allocate GPIOs for mimo antenna diversity feature */
2174 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2175 /* Enable antenna diversity, use 2x3 mode */
2176 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2177 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2178 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2179 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2180
2181 /* init superswitch control */
2182 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2183
2184 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2185 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2186 /*
2187 * The board itself is powered by these GPIOs
2188 * (when not sending pattern) so set them high
2189 */
2190 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2191 (BOARD_GPIO_12 | BOARD_GPIO_13));
2192 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2193 (BOARD_GPIO_12 | BOARD_GPIO_13));
2194
2195 /* Enable antenna diversity, use 2x4 mode */
2196 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2197 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2198 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2199 BRCM_BAND_ALL);
2200
2201 /* Configure the desired clock to be 4Mhz */
2202 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2203 ANTSEL_CLKDIV_4MHZ);
2204 }
2205
2206 /*
2207 * gpio 9 controls the PA. ucode is responsible
2208 * for wiggling out and oe
2209 */
2210 if (wlc_hw->boardflags & BFL_PACTRL)
2211 gm |= gc |= BOARD_GPIO_PACTRL;
2212
2213 /* apply to gpiocontrol register */
2214 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2215 }
2216
2217 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2218 const __le32 ucode[], const size_t nbytes)
2219 {
2220 struct bcma_device *core = wlc_hw->d11core;
2221 uint i;
2222 uint count;
2223
2224 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2225
2226 count = (nbytes / sizeof(u32));
2227
2228 bcma_write32(core, D11REGOFFS(objaddr),
2229 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2230 (void)bcma_read32(core, D11REGOFFS(objaddr));
2231 for (i = 0; i < count; i++)
2232 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2233
2234 }
2235
2236 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2237 {
2238 struct brcms_c_info *wlc;
2239 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2240
2241 wlc = wlc_hw->wlc;
2242
2243 if (wlc_hw->ucode_loaded)
2244 return;
2245
2246 if (D11REV_IS(wlc_hw->corerev, 23)) {
2247 if (BRCMS_ISNPHY(wlc_hw->band)) {
2248 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2249 ucode->bcm43xx_16_mimosz);
2250 wlc_hw->ucode_loaded = true;
2251 } else
2252 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2253 "corerev %d\n",
2254 __func__, wlc_hw->unit, wlc_hw->corerev);
2255 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2256 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2257 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2258 ucode->bcm43xx_24_lcnsz);
2259 wlc_hw->ucode_loaded = true;
2260 } else {
2261 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2262 "corerev %d\n",
2263 __func__, wlc_hw->unit, wlc_hw->corerev);
2264 }
2265 }
2266 }
2267
2268 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2269 {
2270 /* update sw state */
2271 wlc_hw->bmac_phytxant = phytxant;
2272
2273 /* push to ucode if up */
2274 if (!wlc_hw->up)
2275 return;
2276 brcms_c_ucode_txant_set(wlc_hw);
2277
2278 }
2279
2280 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2281 {
2282 return (u16) wlc_hw->wlc->stf->txant;
2283 }
2284
2285 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2286 {
2287 wlc_hw->antsel_type = antsel_type;
2288
2289 /* Update the antsel type for phy module to use */
2290 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2291 }
2292
2293 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2294 {
2295 bool fatal = false;
2296 uint unit;
2297 uint intstatus, idx;
2298 struct bcma_device *core = wlc_hw->d11core;
2299 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2300
2301 unit = wlc_hw->unit;
2302
2303 for (idx = 0; idx < NFIFO; idx++) {
2304 /* read intstatus register and ignore any non-error bits */
2305 intstatus =
2306 bcma_read32(core,
2307 D11REGOFFS(intctrlregs[idx].intstatus)) &
2308 I_ERRORS;
2309 if (!intstatus)
2310 continue;
2311
2312 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2313 unit, idx, intstatus);
2314
2315 if (intstatus & I_RO) {
2316 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2317 "overflow\n", unit, idx);
2318 fatal = true;
2319 }
2320
2321 if (intstatus & I_PC) {
2322 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2323 unit, idx);
2324 fatal = true;
2325 }
2326
2327 if (intstatus & I_PD) {
2328 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2329 idx);
2330 fatal = true;
2331 }
2332
2333 if (intstatus & I_DE) {
2334 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2335 "error\n", unit, idx);
2336 fatal = true;
2337 }
2338
2339 if (intstatus & I_RU)
2340 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2341 "underflow\n", idx, unit);
2342
2343 if (intstatus & I_XU) {
2344 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2345 "underflow\n", idx, unit);
2346 fatal = true;
2347 }
2348
2349 if (fatal) {
2350 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2351 break;
2352 } else
2353 bcma_write32(core,
2354 D11REGOFFS(intctrlregs[idx].intstatus),
2355 intstatus);
2356 }
2357 }
2358
2359 void brcms_c_intrson(struct brcms_c_info *wlc)
2360 {
2361 struct brcms_hardware *wlc_hw = wlc->hw;
2362 wlc->macintmask = wlc->defmacintmask;
2363 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2364 }
2365
2366 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2367 {
2368 struct brcms_hardware *wlc_hw = wlc->hw;
2369 u32 macintmask;
2370
2371 if (!wlc_hw->clk)
2372 return 0;
2373
2374 macintmask = wlc->macintmask; /* isr can still happen */
2375
2376 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2377 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2378 udelay(1); /* ensure int line is no longer driven */
2379 wlc->macintmask = 0;
2380
2381 /* return previous macintmask; resolve race between us and our isr */
2382 return wlc->macintstatus ? 0 : macintmask;
2383 }
2384
2385 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2386 {
2387 struct brcms_hardware *wlc_hw = wlc->hw;
2388 if (!wlc_hw->clk)
2389 return;
2390
2391 wlc->macintmask = macintmask;
2392 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2393 }
2394
2395 /* assumes that the d11 MAC is enabled */
2396 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2397 uint tx_fifo)
2398 {
2399 u8 fifo = 1 << tx_fifo;
2400
2401 /* Two clients of this code, 11h Quiet period and scanning. */
2402
2403 /* only suspend if not already suspended */
2404 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2405 return;
2406
2407 /* force the core awake only if not already */
2408 if (wlc_hw->suspended_fifos == 0)
2409 brcms_c_ucode_wake_override_set(wlc_hw,
2410 BRCMS_WAKE_OVERRIDE_TXFIFO);
2411
2412 wlc_hw->suspended_fifos |= fifo;
2413
2414 if (wlc_hw->di[tx_fifo]) {
2415 /*
2416 * Suspending AMPDU transmissions in the middle can cause
2417 * underflow which may result in mismatch between ucode and
2418 * driver so suspend the mac before suspending the FIFO
2419 */
2420 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2421 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2422
2423 dma_txsuspend(wlc_hw->di[tx_fifo]);
2424
2425 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2426 brcms_c_enable_mac(wlc_hw->wlc);
2427 }
2428 }
2429
2430 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2431 uint tx_fifo)
2432 {
2433 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2434 * but need to be done here for PIO otherwise the watchdog will catch
2435 * the inconsistency and fire
2436 */
2437 /* Two clients of this code, 11h Quiet period and scanning. */
2438 if (wlc_hw->di[tx_fifo])
2439 dma_txresume(wlc_hw->di[tx_fifo]);
2440
2441 /* allow core to sleep again */
2442 if (wlc_hw->suspended_fifos == 0)
2443 return;
2444 else {
2445 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2446 if (wlc_hw->suspended_fifos == 0)
2447 brcms_c_ucode_wake_override_clear(wlc_hw,
2448 BRCMS_WAKE_OVERRIDE_TXFIFO);
2449 }
2450 }
2451
2452 /* precondition: requires the mac core to be enabled */
2453 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2454 {
2455 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2456
2457 if (mute_tx) {
2458 /* suspend tx fifos */
2459 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2460 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2461 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2462 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2463
2464 /* zero the address match register so we do not send ACKs */
2465 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2466 null_ether_addr);
2467 } else {
2468 /* resume tx fifos */
2469 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2470 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2471 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2472 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2473
2474 /* Restore address */
2475 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2476 wlc_hw->etheraddr);
2477 }
2478
2479 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2480
2481 if (mute_tx)
2482 brcms_c_ucode_mute_override_set(wlc_hw);
2483 else
2484 brcms_c_ucode_mute_override_clear(wlc_hw);
2485 }
2486
2487 void
2488 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2489 {
2490 brcms_b_mute(wlc->hw, mute_tx);
2491 }
2492
2493 /*
2494 * Read and clear macintmask and macintstatus and intstatus registers.
2495 * This routine should be called with interrupts off
2496 * Return:
2497 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2498 * 0 if the interrupt is not for us, or we are in some special cases;
2499 * device interrupt status bits otherwise.
2500 */
2501 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2502 {
2503 struct brcms_hardware *wlc_hw = wlc->hw;
2504 struct bcma_device *core = wlc_hw->d11core;
2505 u32 macintstatus;
2506
2507 /* macintstatus includes a DMA interrupt summary bit */
2508 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2509
2510 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2511 macintstatus);
2512
2513 /* detect cardbus removed, in power down(suspend) and in reset */
2514 if (brcms_deviceremoved(wlc))
2515 return -1;
2516
2517 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2518 * handle that case here.
2519 */
2520 if (macintstatus == 0xffffffff)
2521 return 0;
2522
2523 /* defer unsolicited interrupts */
2524 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2525
2526 /* if not for us */
2527 if (macintstatus == 0)
2528 return 0;
2529
2530 /* interrupts are already turned off for CFE build
2531 * Caution: For CFE Turning off the interrupts again has some undesired
2532 * consequences
2533 */
2534 /* turn off the interrupts */
2535 bcma_write32(core, D11REGOFFS(macintmask), 0);
2536 (void)bcma_read32(core, D11REGOFFS(macintmask));
2537 wlc->macintmask = 0;
2538
2539 /* clear device interrupts */
2540 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2541
2542 /* MI_DMAINT is indication of non-zero intstatus */
2543 if (macintstatus & MI_DMAINT)
2544 /*
2545 * only fifo interrupt enabled is I_RI in
2546 * RX_FIFO. If MI_DMAINT is set, assume it
2547 * is set and clear the interrupt.
2548 */
2549 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2550 DEF_RXINTMASK);
2551
2552 return macintstatus;
2553 }
2554
2555 /* Update wlc->macintstatus and wlc->intstatus[]. */
2556 /* Return true if they are updated successfully. false otherwise */
2557 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2558 {
2559 u32 macintstatus;
2560
2561 /* read and clear macintstatus and intstatus registers */
2562 macintstatus = wlc_intstatus(wlc, false);
2563
2564 /* device is removed */
2565 if (macintstatus == 0xffffffff)
2566 return false;
2567
2568 /* update interrupt status in software */
2569 wlc->macintstatus |= macintstatus;
2570
2571 return true;
2572 }
2573
2574 /*
2575 * First-level interrupt processing.
2576 * Return true if this was our interrupt, false otherwise.
2577 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2578 * false otherwise.
2579 */
2580 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2581 {
2582 struct brcms_hardware *wlc_hw = wlc->hw;
2583 u32 macintstatus;
2584
2585 *wantdpc = false;
2586
2587 if (!wlc_hw->up || !wlc->macintmask)
2588 return false;
2589
2590 /* read and clear macintstatus and intstatus registers */
2591 macintstatus = wlc_intstatus(wlc, true);
2592
2593 if (macintstatus == 0xffffffff)
2594 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2595 " path\n");
2596
2597 /* it is not for us */
2598 if (macintstatus == 0)
2599 return false;
2600
2601 *wantdpc = true;
2602
2603 /* save interrupt status bits */
2604 wlc->macintstatus = macintstatus;
2605
2606 return true;
2607
2608 }
2609
2610 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2611 {
2612 struct brcms_hardware *wlc_hw = wlc->hw;
2613 struct bcma_device *core = wlc_hw->d11core;
2614 u32 mc, mi;
2615 struct wiphy *wiphy = wlc->wiphy;
2616
2617 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2618 wlc_hw->band->bandunit);
2619
2620 /*
2621 * Track overlapping suspend requests
2622 */
2623 wlc_hw->mac_suspend_depth++;
2624 if (wlc_hw->mac_suspend_depth > 1)
2625 return;
2626
2627 /* force the core awake */
2628 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2629
2630 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2631
2632 if (mc == 0xffffffff) {
2633 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2634 __func__);
2635 brcms_down(wlc->wl);
2636 return;
2637 }
2638 WARN_ON(mc & MCTL_PSM_JMP_0);
2639 WARN_ON(!(mc & MCTL_PSM_RUN));
2640 WARN_ON(!(mc & MCTL_EN_MAC));
2641
2642 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2643 if (mi == 0xffffffff) {
2644 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2645 __func__);
2646 brcms_down(wlc->wl);
2647 return;
2648 }
2649 WARN_ON(mi & MI_MACSSPNDD);
2650
2651 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2652
2653 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2654 BRCMS_MAX_MAC_SUSPEND);
2655
2656 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2657 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2658 " and MI_MACSSPNDD is still not on.\n",
2659 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2660 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2661 "psm_brc 0x%04x\n", wlc_hw->unit,
2662 bcma_read32(core, D11REGOFFS(psmdebug)),
2663 bcma_read32(core, D11REGOFFS(phydebug)),
2664 bcma_read16(core, D11REGOFFS(psm_brc)));
2665 }
2666
2667 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2668 if (mc == 0xffffffff) {
2669 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2670 __func__);
2671 brcms_down(wlc->wl);
2672 return;
2673 }
2674 WARN_ON(mc & MCTL_PSM_JMP_0);
2675 WARN_ON(!(mc & MCTL_PSM_RUN));
2676 WARN_ON(mc & MCTL_EN_MAC);
2677 }
2678
2679 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2680 {
2681 struct brcms_hardware *wlc_hw = wlc->hw;
2682 struct bcma_device *core = wlc_hw->d11core;
2683 u32 mc, mi;
2684
2685 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2686 wlc->band->bandunit);
2687
2688 /*
2689 * Track overlapping suspend requests
2690 */
2691 wlc_hw->mac_suspend_depth--;
2692 if (wlc_hw->mac_suspend_depth > 0)
2693 return;
2694
2695 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2696 WARN_ON(mc & MCTL_PSM_JMP_0);
2697 WARN_ON(mc & MCTL_EN_MAC);
2698 WARN_ON(!(mc & MCTL_PSM_RUN));
2699
2700 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2701 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2702
2703 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2704 WARN_ON(mc & MCTL_PSM_JMP_0);
2705 WARN_ON(!(mc & MCTL_EN_MAC));
2706 WARN_ON(!(mc & MCTL_PSM_RUN));
2707
2708 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2709 WARN_ON(mi & MI_MACSSPNDD);
2710
2711 brcms_c_ucode_wake_override_clear(wlc_hw,
2712 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2713 }
2714
2715 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2716 {
2717 wlc_hw->hw_stf_ss_opmode = stf_mode;
2718
2719 if (wlc_hw->clk)
2720 brcms_upd_ofdm_pctl1_table(wlc_hw);
2721 }
2722
2723 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2724 {
2725 struct bcma_device *core = wlc_hw->d11core;
2726 u32 w, val;
2727 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2728
2729 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2730
2731 /* Validate dchip register access */
2732
2733 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2734 (void)bcma_read32(core, D11REGOFFS(objaddr));
2735 w = bcma_read32(core, D11REGOFFS(objdata));
2736
2737 /* Can we write and read back a 32bit register? */
2738 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2739 (void)bcma_read32(core, D11REGOFFS(objaddr));
2740 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2741
2742 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2743 (void)bcma_read32(core, D11REGOFFS(objaddr));
2744 val = bcma_read32(core, D11REGOFFS(objdata));
2745 if (val != (u32) 0xaa5555aa) {
2746 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2747 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2748 return false;
2749 }
2750
2751 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2752 (void)bcma_read32(core, D11REGOFFS(objaddr));
2753 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2754
2755 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2756 (void)bcma_read32(core, D11REGOFFS(objaddr));
2757 val = bcma_read32(core, D11REGOFFS(objdata));
2758 if (val != (u32) 0x55aaaa55) {
2759 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2760 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2761 return false;
2762 }
2763
2764 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2765 (void)bcma_read32(core, D11REGOFFS(objaddr));
2766 bcma_write32(core, D11REGOFFS(objdata), w);
2767
2768 /* clear CFPStart */
2769 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2770
2771 w = bcma_read32(core, D11REGOFFS(maccontrol));
2772 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2773 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2774 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2775 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2776 (MCTL_IHR_EN | MCTL_WAKE),
2777 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2778 return false;
2779 }
2780
2781 return true;
2782 }
2783
2784 #define PHYPLL_WAIT_US 100000
2785
2786 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2787 {
2788 struct bcma_device *core = wlc_hw->d11core;
2789 u32 tmp;
2790
2791 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2792
2793 tmp = 0;
2794
2795 if (on) {
2796 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
2797 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2798 CCS_ERSRC_REQ_HT |
2799 CCS_ERSRC_REQ_D11PLL |
2800 CCS_ERSRC_REQ_PHYPLL);
2801 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2802 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2803 PHYPLL_WAIT_US);
2804
2805 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2806 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2807 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2808 " PLL failed\n", __func__);
2809 } else {
2810 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2811 tmp | CCS_ERSRC_REQ_D11PLL |
2812 CCS_ERSRC_REQ_PHYPLL);
2813 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2814 (CCS_ERSRC_AVAIL_D11PLL |
2815 CCS_ERSRC_AVAIL_PHYPLL)) !=
2816 (CCS_ERSRC_AVAIL_D11PLL |
2817 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2818
2819 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2820 if ((tmp &
2821 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2822 !=
2823 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2824 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2825 "PHY PLL failed\n", __func__);
2826 }
2827 } else {
2828 /*
2829 * Since the PLL may be shared, other cores can still
2830 * be requesting it; so we'll deassert the request but
2831 * not wait for status to comply.
2832 */
2833 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2834 ~CCS_ERSRC_REQ_PHYPLL);
2835 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2836 }
2837 }
2838
2839 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2840 {
2841 bool dev_gone;
2842
2843 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2844
2845 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2846
2847 if (dev_gone)
2848 return;
2849
2850 if (wlc_hw->noreset)
2851 return;
2852
2853 /* radio off */
2854 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2855
2856 /* turn off analog core */
2857 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2858
2859 /* turn off PHYPLL to save power */
2860 brcms_b_core_phypll_ctl(wlc_hw, false);
2861
2862 wlc_hw->clk = false;
2863 bcma_core_disable(wlc_hw->d11core, 0);
2864 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2865 }
2866
2867 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2868 {
2869 struct brcms_hardware *wlc_hw = wlc->hw;
2870 uint i;
2871
2872 /* free any posted tx packets */
2873 for (i = 0; i < NFIFO; i++)
2874 if (wlc_hw->di[i]) {
2875 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2876 wlc->core->txpktpend[i] = 0;
2877 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
2878 }
2879
2880 /* free any posted rx packets */
2881 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2882 }
2883
2884 static u16
2885 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2886 {
2887 struct bcma_device *core = wlc_hw->d11core;
2888 u16 objoff = D11REGOFFS(objdata);
2889
2890 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2891 (void)bcma_read32(core, D11REGOFFS(objaddr));
2892 if (offset & 2)
2893 objoff += 2;
2894
2895 return bcma_read16(core, objoff);
2896 }
2897
2898 static void
2899 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2900 u32 sel)
2901 {
2902 struct bcma_device *core = wlc_hw->d11core;
2903 u16 objoff = D11REGOFFS(objdata);
2904
2905 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2906 (void)bcma_read32(core, D11REGOFFS(objaddr));
2907 if (offset & 2)
2908 objoff += 2;
2909
2910 bcma_write16(core, objoff, v);
2911 }
2912
2913 /*
2914 * Read a single u16 from shared memory.
2915 * SHM 'offset' needs to be an even address
2916 */
2917 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2918 {
2919 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2920 }
2921
2922 /*
2923 * Write a single u16 to shared memory.
2924 * SHM 'offset' needs to be an even address
2925 */
2926 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2927 {
2928 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2929 }
2930
2931 /*
2932 * Copy a buffer to shared memory of specified type .
2933 * SHM 'offset' needs to be an even address and
2934 * Buffer length 'len' must be an even number of bytes
2935 * 'sel' selects the type of memory
2936 */
2937 void
2938 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2939 const void *buf, int len, u32 sel)
2940 {
2941 u16 v;
2942 const u8 *p = (const u8 *)buf;
2943 int i;
2944
2945 if (len <= 0 || (offset & 1) || (len & 1))
2946 return;
2947
2948 for (i = 0; i < len; i += 2) {
2949 v = p[i] | (p[i + 1] << 8);
2950 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2951 }
2952 }
2953
2954 /*
2955 * Copy a piece of shared memory of specified type to a buffer .
2956 * SHM 'offset' needs to be an even address and
2957 * Buffer length 'len' must be an even number of bytes
2958 * 'sel' selects the type of memory
2959 */
2960 void
2961 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2962 int len, u32 sel)
2963 {
2964 u16 v;
2965 u8 *p = (u8 *) buf;
2966 int i;
2967
2968 if (len <= 0 || (offset & 1) || (len & 1))
2969 return;
2970
2971 for (i = 0; i < len; i += 2) {
2972 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2973 p[i] = v & 0xFF;
2974 p[i + 1] = (v >> 8) & 0xFF;
2975 }
2976 }
2977
2978 /* Copy a buffer to shared memory.
2979 * SHM 'offset' needs to be an even address and
2980 * Buffer length 'len' must be an even number of bytes
2981 */
2982 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2983 const void *buf, int len)
2984 {
2985 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2986 }
2987
2988 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2989 u16 SRL, u16 LRL)
2990 {
2991 wlc_hw->SRL = SRL;
2992 wlc_hw->LRL = LRL;
2993
2994 /* write retry limit to SCR, shouldn't need to suspend */
2995 if (wlc_hw->up) {
2996 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
2997 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2998 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
2999 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3000 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3001 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3002 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3003 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3004 }
3005 }
3006
3007 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3008 {
3009 if (set) {
3010 if (mboolisset(wlc_hw->pllreq, req_bit))
3011 return;
3012
3013 mboolset(wlc_hw->pllreq, req_bit);
3014
3015 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3016 if (!wlc_hw->sbclk)
3017 brcms_b_xtal(wlc_hw, ON);
3018 }
3019 } else {
3020 if (!mboolisset(wlc_hw->pllreq, req_bit))
3021 return;
3022
3023 mboolclr(wlc_hw->pllreq, req_bit);
3024
3025 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3026 if (wlc_hw->sbclk)
3027 brcms_b_xtal(wlc_hw, OFF);
3028 }
3029 }
3030 }
3031
3032 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3033 {
3034 wlc_hw->antsel_avail = antsel_avail;
3035 }
3036
3037 /*
3038 * conditions under which the PM bit should be set in outgoing frames
3039 * and STAY_AWAKE is meaningful
3040 */
3041 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3042 {
3043 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3044
3045 /* disallow PS when one of the following global conditions meets */
3046 if (!wlc->pub->associated)
3047 return false;
3048
3049 /* disallow PS when one of these meets when not scanning */
3050 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3051 return false;
3052
3053 if (cfg->associated) {
3054 /*
3055 * disallow PS when one of the following
3056 * bsscfg specific conditions meets
3057 */
3058 if (!cfg->BSS)
3059 return false;
3060
3061 return false;
3062 }
3063
3064 return true;
3065 }
3066
3067 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3068 {
3069 int i;
3070 struct macstat macstats;
3071 #ifdef DEBUG
3072 u16 delta;
3073 u16 rxf0ovfl;
3074 u16 txfunfl[NFIFO];
3075 #endif /* DEBUG */
3076
3077 /* if driver down, make no sense to update stats */
3078 if (!wlc->pub->up)
3079 return;
3080
3081 #ifdef DEBUG
3082 /* save last rx fifo 0 overflow count */
3083 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3084
3085 /* save last tx fifo underflow count */
3086 for (i = 0; i < NFIFO; i++)
3087 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3088 #endif /* DEBUG */
3089
3090 /* Read mac stats from contiguous shared memory */
3091 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3092 sizeof(struct macstat), OBJADDR_SHM_SEL);
3093
3094 #ifdef DEBUG
3095 /* check for rx fifo 0 overflow */
3096 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3097 if (delta)
3098 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
3099 wlc->pub->unit, delta);
3100
3101 /* check for tx fifo underflows */
3102 for (i = 0; i < NFIFO; i++) {
3103 delta =
3104 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3105 txfunfl[i]);
3106 if (delta)
3107 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
3108 "\n", wlc->pub->unit, delta, i);
3109 }
3110 #endif /* DEBUG */
3111
3112 /* merge counters from dma module */
3113 for (i = 0; i < NFIFO; i++) {
3114 if (wlc->hw->di[i])
3115 dma_counterreset(wlc->hw->di[i]);
3116 }
3117 }
3118
3119 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3120 {
3121 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3122
3123 /* reset the core */
3124 if (!brcms_deviceremoved(wlc_hw->wlc))
3125 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3126
3127 /* purge the dma rings */
3128 brcms_c_flushqueues(wlc_hw->wlc);
3129 }
3130
3131 void brcms_c_reset(struct brcms_c_info *wlc)
3132 {
3133 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3134
3135 /* slurp up hw mac counters before core reset */
3136 brcms_c_statsupd(wlc);
3137
3138 /* reset our snapshot of macstat counters */
3139 memset((char *)wlc->core->macstat_snapshot, 0,
3140 sizeof(struct macstat));
3141
3142 brcms_b_reset(wlc->hw);
3143 }
3144
3145 /* Return the channel the driver should initialize during brcms_c_init.
3146 * the channel may have to be changed from the currently configured channel
3147 * if other configurations are in conflict (bandlocked, 11n mode disabled,
3148 * invalid channel for current country, etc.)
3149 */
3150 static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
3151 {
3152 u16 chanspec =
3153 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
3154 WL_CHANSPEC_BAND_2G;
3155
3156 return chanspec;
3157 }
3158
3159 void brcms_c_init_scb(struct scb *scb)
3160 {
3161 int i;
3162
3163 memset(scb, 0, sizeof(struct scb));
3164 scb->flags = SCB_WMECAP | SCB_HTCAP;
3165 for (i = 0; i < NUMPRIO; i++) {
3166 scb->seqnum[i] = 0;
3167 scb->seqctl[i] = 0xFFFF;
3168 }
3169
3170 scb->seqctl_nonqos = 0xFFFF;
3171 scb->magic = SCB_MAGIC;
3172 }
3173
3174 /* d11 core init
3175 * reset PSM
3176 * download ucode/PCM
3177 * let ucode run to suspended
3178 * download ucode inits
3179 * config other core registers
3180 * init dma
3181 */
3182 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3183 {
3184 struct brcms_hardware *wlc_hw = wlc->hw;
3185 struct bcma_device *core = wlc_hw->d11core;
3186 u32 sflags;
3187 u32 bcnint_us;
3188 uint i = 0;
3189 bool fifosz_fixup = false;
3190 int err = 0;
3191 u16 buf[NFIFO];
3192 struct wiphy *wiphy = wlc->wiphy;
3193 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3194
3195 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3196
3197 /* reset PSM */
3198 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3199
3200 brcms_ucode_download(wlc_hw);
3201 /*
3202 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3203 */
3204 fifosz_fixup = true;
3205
3206 /* let the PSM run to the suspended state, set mode to BSS STA */
3207 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3208 brcms_b_mctrl(wlc_hw, ~0,
3209 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3210
3211 /* wait for ucode to self-suspend after auto-init */
3212 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3213 MI_MACSSPNDD) == 0), 1000 * 1000);
3214 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3215 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3216 "suspend!\n", wlc_hw->unit);
3217
3218 brcms_c_gpio_init(wlc);
3219
3220 sflags = bcma_aread32(core, BCMA_IOST);
3221
3222 if (D11REV_IS(wlc_hw->corerev, 23)) {
3223 if (BRCMS_ISNPHY(wlc_hw->band))
3224 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3225 else
3226 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3227 " %d\n", __func__, wlc_hw->unit,
3228 wlc_hw->corerev);
3229 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3230 if (BRCMS_ISLCNPHY(wlc_hw->band))
3231 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3232 else
3233 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3234 " %d\n", __func__, wlc_hw->unit,
3235 wlc_hw->corerev);
3236 } else {
3237 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3238 __func__, wlc_hw->unit, wlc_hw->corerev);
3239 }
3240
3241 /* For old ucode, txfifo sizes needs to be modified(increased) */
3242 if (fifosz_fixup)
3243 brcms_b_corerev_fifofixup(wlc_hw);
3244
3245 /* check txfifo allocations match between ucode and driver */
3246 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3247 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3248 i = TX_AC_BE_FIFO;
3249 err = -1;
3250 }
3251 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3252 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3253 i = TX_AC_VI_FIFO;
3254 err = -1;
3255 }
3256 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3257 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3258 buf[TX_AC_BK_FIFO] &= 0xff;
3259 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3260 i = TX_AC_BK_FIFO;
3261 err = -1;
3262 }
3263 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3264 i = TX_AC_VO_FIFO;
3265 err = -1;
3266 }
3267 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3268 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3269 buf[TX_BCMC_FIFO] &= 0xff;
3270 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3271 i = TX_BCMC_FIFO;
3272 err = -1;
3273 }
3274 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3275 i = TX_ATIM_FIFO;
3276 err = -1;
3277 }
3278 if (err != 0)
3279 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3280 " driver size %d index %d\n", buf[i],
3281 wlc_hw->xmtfifo_sz[i], i);
3282
3283 /* make sure we can still talk to the mac */
3284 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3285
3286 /* band-specific inits done by wlc_bsinit() */
3287
3288 /* Set up frame burst size and antenna swap threshold init values */
3289 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3290 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3291
3292 /* enable one rx interrupt per received frame */
3293 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3294
3295 /* set the station mode (BSS STA) */
3296 brcms_b_mctrl(wlc_hw,
3297 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3298 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3299
3300 /* set up Beacon interval */
3301 bcnint_us = 0x8000 << 10;
3302 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3303 (bcnint_us << CFPREP_CBI_SHIFT));
3304 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3305 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3306
3307 /* write interrupt mask */
3308 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3309 DEF_RXINTMASK);
3310
3311 /* allow the MAC to control the PHY clock (dynamic on/off) */
3312 brcms_b_macphyclk_set(wlc_hw, ON);
3313
3314 /* program dynamic clock control fast powerup delay register */
3315 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3316 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3317
3318 /* tell the ucode the corerev */
3319 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3320
3321 /* tell the ucode MAC capabilities */
3322 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3323 (u16) (wlc_hw->machwcap & 0xffff));
3324 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3325 (u16) ((wlc_hw->
3326 machwcap >> 16) & 0xffff));
3327
3328 /* write retry limits to SCR, this done after PSM init */
3329 bcma_write32(core, D11REGOFFS(objaddr),
3330 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3331 (void)bcma_read32(core, D11REGOFFS(objaddr));
3332 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3333 bcma_write32(core, D11REGOFFS(objaddr),
3334 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3335 (void)bcma_read32(core, D11REGOFFS(objaddr));
3336 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3337
3338 /* write rate fallback retry limits */
3339 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3340 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3341
3342 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3343 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3344
3345 /* init the tx dma engines */
3346 for (i = 0; i < NFIFO; i++) {
3347 if (wlc_hw->di[i])
3348 dma_txinit(wlc_hw->di[i]);
3349 }
3350
3351 /* init the rx dma engine(s) and post receive buffers */
3352 dma_rxinit(wlc_hw->di[RX_FIFO]);
3353 dma_rxfill(wlc_hw->di[RX_FIFO]);
3354 }
3355
3356 void
3357 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3358 u32 macintmask;
3359 bool fastclk;
3360 struct brcms_c_info *wlc = wlc_hw->wlc;
3361
3362 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3363
3364 /* request FAST clock if not on */
3365 fastclk = wlc_hw->forcefastclk;
3366 if (!fastclk)
3367 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
3368
3369 /* disable interrupts */
3370 macintmask = brcms_intrsoff(wlc->wl);
3371
3372 /* set up the specified band and chanspec */
3373 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3374 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3375
3376 /* do one-time phy inits and calibration */
3377 wlc_phy_cal_init(wlc_hw->band->pi);
3378
3379 /* core-specific initialization */
3380 brcms_b_coreinit(wlc);
3381
3382 /* band-specific inits */
3383 brcms_b_bsinit(wlc, chanspec);
3384
3385 /* restore macintmask */
3386 brcms_intrsrestore(wlc->wl, macintmask);
3387
3388 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3389 * is suspended and brcms_c_enable_mac() will clear this override bit.
3390 */
3391 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3392
3393 /*
3394 * initialize mac_suspend_depth to 1 to match ucode
3395 * initial suspended state
3396 */
3397 wlc_hw->mac_suspend_depth = 1;
3398
3399 /* restore the clk */
3400 if (!fastclk)
3401 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
3402 }
3403
3404 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3405 u16 chanspec)
3406 {
3407 /* Save our copy of the chanspec */
3408 wlc->chanspec = chanspec;
3409
3410 /* Set the chanspec and power limits for this locale */
3411 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3412
3413 if (wlc->stf->ss_algosel_auto)
3414 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3415 chanspec);
3416
3417 brcms_c_stf_ss_update(wlc, wlc->band);
3418 }
3419
3420 static void
3421 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3422 {
3423 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3424 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3425 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3426 brcms_chspec_bw(wlc->default_bss->chanspec),
3427 wlc->stf->txstreams);
3428 }
3429
3430 /* derive wlc->band->basic_rate[] table from 'rateset' */
3431 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3432 struct brcms_c_rateset *rateset)
3433 {
3434 u8 rate;
3435 u8 mandatory;
3436 u8 cck_basic = 0;
3437 u8 ofdm_basic = 0;
3438 u8 *br = wlc->band->basic_rate;
3439 uint i;
3440
3441 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3442 memset(br, 0, BRCM_MAXRATE + 1);
3443
3444 /* For each basic rate in the rates list, make an entry in the
3445 * best basic lookup.
3446 */
3447 for (i = 0; i < rateset->count; i++) {
3448 /* only make an entry for a basic rate */
3449 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3450 continue;
3451
3452 /* mask off basic bit */
3453 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3454
3455 if (rate > BRCM_MAXRATE) {
3456 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
3457 "invalid rate 0x%X in rate set\n",
3458 rateset->rates[i]);
3459 continue;
3460 }
3461
3462 br[rate] = rate;
3463 }
3464
3465 /* The rate lookup table now has non-zero entries for each
3466 * basic rate, equal to the basic rate: br[basicN] = basicN
3467 *
3468 * To look up the best basic rate corresponding to any
3469 * particular rate, code can use the basic_rate table
3470 * like this
3471 *
3472 * basic_rate = wlc->band->basic_rate[tx_rate]
3473 *
3474 * Make sure there is a best basic rate entry for
3475 * every rate by walking up the table from low rates
3476 * to high, filling in holes in the lookup table
3477 */
3478
3479 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3480 rate = wlc->band->hw_rateset.rates[i];
3481
3482 if (br[rate] != 0) {
3483 /* This rate is a basic rate.
3484 * Keep track of the best basic rate so far by
3485 * modulation type.
3486 */
3487 if (is_ofdm_rate(rate))
3488 ofdm_basic = rate;
3489 else
3490 cck_basic = rate;
3491
3492 continue;
3493 }
3494
3495 /* This rate is not a basic rate so figure out the
3496 * best basic rate less than this rate and fill in
3497 * the hole in the table
3498 */
3499
3500 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3501
3502 if (br[rate] != 0)
3503 continue;
3504
3505 if (is_ofdm_rate(rate)) {
3506 /*
3507 * In 11g and 11a, the OFDM mandatory rates
3508 * are 6, 12, and 24 Mbps
3509 */
3510 if (rate >= BRCM_RATE_24M)
3511 mandatory = BRCM_RATE_24M;
3512 else if (rate >= BRCM_RATE_12M)
3513 mandatory = BRCM_RATE_12M;
3514 else
3515 mandatory = BRCM_RATE_6M;
3516 } else {
3517 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3518 mandatory = rate;
3519 }
3520
3521 br[rate] = mandatory;
3522 }
3523 }
3524
3525 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3526 u16 chanspec)
3527 {
3528 struct brcms_c_rateset default_rateset;
3529 uint parkband;
3530 uint i, band_order[2];
3531
3532 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3533 /*
3534 * We might have been bandlocked during down and the chip
3535 * power-cycled (hibernate). Figure out the right band to park on
3536 */
3537 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3538 /* updated in brcms_c_bandlock() */
3539 parkband = wlc->band->bandunit;
3540 band_order[0] = band_order[1] = parkband;
3541 } else {
3542 /* park on the band of the specified chanspec */
3543 parkband = chspec_bandunit(chanspec);
3544
3545 /* order so that parkband initialize last */
3546 band_order[0] = parkband ^ 1;
3547 band_order[1] = parkband;
3548 }
3549
3550 /* make each band operational, software state init */
3551 for (i = 0; i < wlc->pub->_nbands; i++) {
3552 uint j = band_order[i];
3553
3554 wlc->band = wlc->bandstate[j];
3555
3556 brcms_default_rateset(wlc, &default_rateset);
3557
3558 /* fill in hw_rate */
3559 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3560 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3561 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3562
3563 /* init basic rate lookup */
3564 brcms_c_rate_lookup_init(wlc, &default_rateset);
3565 }
3566
3567 /* sync up phy/radio chanspec */
3568 brcms_c_set_phy_chanspec(wlc, chanspec);
3569 }
3570
3571 /*
3572 * Set or clear filtering related maccontrol bits based on
3573 * specified filter flags
3574 */
3575 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3576 {
3577 u32 promisc_bits = 0;
3578
3579 wlc->filter_flags = filter_flags;
3580
3581 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3582 promisc_bits |= MCTL_PROMISC;
3583
3584 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3585 promisc_bits |= MCTL_BCNS_PROMISC;
3586
3587 if (filter_flags & FIF_FCSFAIL)
3588 promisc_bits |= MCTL_KEEPBADFCS;
3589
3590 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3591 promisc_bits |= MCTL_KEEPCONTROL;
3592
3593 brcms_b_mctrl(wlc->hw,
3594 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3595 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3596 promisc_bits);
3597 }
3598
3599 /*
3600 * ucode, hwmac update
3601 * Channel dependent updates for ucode and hw
3602 */
3603 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3604 {
3605 /* enable or disable any active IBSSs depending on whether or not
3606 * we are on the home channel
3607 */
3608 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3609 if (wlc->pub->associated) {
3610 /*
3611 * BMAC_NOTE: This is something that should be fixed
3612 * in ucode inits. I think that the ucode inits set
3613 * up the bcn templates and shm values with a bogus
3614 * beacon. This should not be done in the inits. If
3615 * ucode needs to set up a beacon for testing, the
3616 * test routines should write it down, not expect the
3617 * inits to populate a bogus beacon.
3618 */
3619 if (BRCMS_PHY_11N_CAP(wlc->band))
3620 brcms_b_write_shm(wlc->hw,
3621 M_BCN_TXTSF_OFFSET, 0);
3622 }
3623 } else {
3624 /* disable an active IBSS if we are not on the home channel */
3625 }
3626 }
3627
3628 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3629 u8 basic_rate)
3630 {
3631 u8 phy_rate, index;
3632 u8 basic_phy_rate, basic_index;
3633 u16 dir_table, basic_table;
3634 u16 basic_ptr;
3635
3636 /* Shared memory address for the table we are reading */
3637 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3638
3639 /* Shared memory address for the table we are writing */
3640 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3641
3642 /*
3643 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3644 * the index into the rate table.
3645 */
3646 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3647 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3648 index = phy_rate & 0xf;
3649 basic_index = basic_phy_rate & 0xf;
3650
3651 /* Find the SHM pointer to the ACK rate entry by looking in the
3652 * Direct-map Table
3653 */
3654 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3655
3656 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3657 * to the correct basic rate for the given incoming rate
3658 */
3659 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3660 }
3661
3662 static const struct brcms_c_rateset *
3663 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3664 {
3665 const struct brcms_c_rateset *rs_dflt;
3666
3667 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3668 if (wlc->band->bandtype == BRCM_BAND_5G)
3669 rs_dflt = &ofdm_mimo_rates;
3670 else
3671 rs_dflt = &cck_ofdm_mimo_rates;
3672 } else if (wlc->band->gmode)
3673 rs_dflt = &cck_ofdm_rates;
3674 else
3675 rs_dflt = &cck_rates;
3676
3677 return rs_dflt;
3678 }
3679
3680 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3681 {
3682 const struct brcms_c_rateset *rs_dflt;
3683 struct brcms_c_rateset rs;
3684 u8 rate, basic_rate;
3685 uint i;
3686
3687 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3688
3689 brcms_c_rateset_copy(rs_dflt, &rs);
3690 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3691
3692 /* walk the phy rate table and update SHM basic rate lookup table */
3693 for (i = 0; i < rs.count; i++) {
3694 rate = rs.rates[i] & BRCMS_RATE_MASK;
3695
3696 /* for a given rate brcms_basic_rate returns the rate at
3697 * which a response ACK/CTS should be sent.
3698 */
3699 basic_rate = brcms_basic_rate(wlc, rate);
3700 if (basic_rate == 0)
3701 /* This should only happen if we are using a
3702 * restricted rateset.
3703 */
3704 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3705
3706 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3707 }
3708 }
3709
3710 /* band-specific init */
3711 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3712 {
3713 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3714 wlc->pub->unit, wlc->band->bandunit);
3715
3716 /* write ucode ACK/CTS rate table */
3717 brcms_c_set_ratetable(wlc);
3718
3719 /* update some band specific mac configuration */
3720 brcms_c_ucode_mac_upd(wlc);
3721
3722 /* init antenna selection */
3723 brcms_c_antsel_init(wlc->asi);
3724
3725 }
3726
3727 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3728 static int
3729 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3730 bool writeToShm)
3731 {
3732 int idle_busy_ratio_x_16 = 0;
3733 uint offset =
3734 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3735 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3736 if (duty_cycle > 100 || duty_cycle < 0) {
3737 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
3738 wlc->pub->unit);
3739 return -EINVAL;
3740 }
3741 if (duty_cycle)
3742 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3743 /* Only write to shared memory when wl is up */
3744 if (writeToShm)
3745 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3746
3747 if (isOFDM)
3748 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3749 else
3750 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3751
3752 return 0;
3753 }
3754
3755 /*
3756 * Initialize the base precedence map for dequeueing
3757 * from txq based on WME settings
3758 */
3759 static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
3760 {
3761 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
3762 memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
3763
3764 wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
3765 wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
3766 wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
3767 wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
3768 }
3769
3770 static void
3771 brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
3772 struct brcms_txq_info *qi, bool on, int prio)
3773 {
3774 /* transmit flowcontrol is not yet implemented */
3775 }
3776
3777 static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
3778 {
3779 struct brcms_txq_info *qi;
3780
3781 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
3782 if (qi->stopped) {
3783 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
3784 qi->stopped = 0;
3785 }
3786 }
3787 }
3788
3789 /* push sw hps and wake state through hardware */
3790 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3791 {
3792 u32 v1, v2;
3793 bool hps;
3794 bool awake_before;
3795
3796 hps = brcms_c_ps_allowed(wlc);
3797
3798 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3799
3800 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3801 v2 = MCTL_WAKE;
3802 if (hps)
3803 v2 |= MCTL_HPS;
3804
3805 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3806
3807 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3808
3809 if (!awake_before)
3810 brcms_b_wait_for_wake(wlc->hw);
3811 }
3812
3813 /*
3814 * Write this BSS config's MAC address to core.
3815 * Updates RXE match engine.
3816 */
3817 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3818 {
3819 int err = 0;
3820 struct brcms_c_info *wlc = bsscfg->wlc;
3821
3822 /* enter the MAC addr into the RXE match registers */
3823 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3824
3825 brcms_c_ampdu_macaddr_upd(wlc);
3826
3827 return err;
3828 }
3829
3830 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3831 * Updates RXE match engine.
3832 */
3833 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3834 {
3835 /* we need to update BSSID in RXE match registers */
3836 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3837 }
3838
3839 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3840 {
3841 wlc_hw->shortslot = shortslot;
3842
3843 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3844 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3845 brcms_b_update_slot_timing(wlc_hw, shortslot);
3846 brcms_c_enable_mac(wlc_hw->wlc);
3847 }
3848 }
3849
3850 /*
3851 * Suspend the the MAC and update the slot timing
3852 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3853 */
3854 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3855 {
3856 /* use the override if it is set */
3857 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3858 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3859
3860 if (wlc->shortslot == shortslot)
3861 return;
3862
3863 wlc->shortslot = shortslot;
3864
3865 brcms_b_set_shortslot(wlc->hw, shortslot);
3866 }
3867
3868 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3869 {
3870 if (wlc->home_chanspec != chanspec) {
3871 wlc->home_chanspec = chanspec;
3872
3873 if (wlc->bsscfg->associated)
3874 wlc->bsscfg->current_bss->chanspec = chanspec;
3875 }
3876 }
3877
3878 void
3879 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3880 bool mute_tx, struct txpwr_limits *txpwr)
3881 {
3882 uint bandunit;
3883
3884 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3885
3886 wlc_hw->chanspec = chanspec;
3887
3888 /* Switch bands if necessary */
3889 if (wlc_hw->_nbands > 1) {
3890 bandunit = chspec_bandunit(chanspec);
3891 if (wlc_hw->band->bandunit != bandunit) {
3892 /* brcms_b_setband disables other bandunit,
3893 * use light band switch if not up yet
3894 */
3895 if (wlc_hw->up) {
3896 wlc_phy_chanspec_radio_set(wlc_hw->
3897 bandstate[bandunit]->
3898 pi, chanspec);
3899 brcms_b_setband(wlc_hw, bandunit, chanspec);
3900 } else {
3901 brcms_c_setxband(wlc_hw, bandunit);
3902 }
3903 }
3904 }
3905
3906 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3907
3908 if (!wlc_hw->up) {
3909 if (wlc_hw->clk)
3910 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3911 chanspec);
3912 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3913 } else {
3914 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3915 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3916
3917 /* Update muting of the channel */
3918 brcms_b_mute(wlc_hw, mute_tx);
3919 }
3920 }
3921
3922 /* switch to and initialize new band */
3923 static void brcms_c_setband(struct brcms_c_info *wlc,
3924 uint bandunit)
3925 {
3926 wlc->band = wlc->bandstate[bandunit];
3927
3928 if (!wlc->pub->up)
3929 return;
3930
3931 /* wait for at least one beacon before entering sleeping state */
3932 brcms_c_set_ps_ctrl(wlc);
3933
3934 /* band-specific initializations */
3935 brcms_c_bsinit(wlc);
3936 }
3937
3938 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3939 {
3940 uint bandunit;
3941 bool switchband = false;
3942 u16 old_chanspec = wlc->chanspec;
3943
3944 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3945 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3946 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3947 return;
3948 }
3949
3950 /* Switch bands if necessary */
3951 if (wlc->pub->_nbands > 1) {
3952 bandunit = chspec_bandunit(chanspec);
3953 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3954 switchband = true;
3955 if (wlc->bandlocked) {
3956 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3957 "band is locked!\n",
3958 wlc->pub->unit, __func__,
3959 CHSPEC_CHANNEL(chanspec));
3960 return;
3961 }
3962 /*
3963 * should the setband call come after the
3964 * brcms_b_chanspec() ? if the setband updates
3965 * (brcms_c_bsinit) use low level calls to inspect and
3966 * set state, the state inspected may be from the wrong
3967 * band, or the following brcms_b_set_chanspec() may
3968 * undo the work.
3969 */
3970 brcms_c_setband(wlc, bandunit);
3971 }
3972 }
3973
3974 /* sync up phy/radio chanspec */
3975 brcms_c_set_phy_chanspec(wlc, chanspec);
3976
3977 /* init antenna selection */
3978 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3979 brcms_c_antsel_init(wlc->asi);
3980
3981 /* Fix the hardware rateset based on bw.
3982 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3983 */
3984 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3985 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3986 }
3987
3988 /* update some mac configuration since chanspec changed */
3989 brcms_c_ucode_mac_upd(wlc);
3990 }
3991
3992 /*
3993 * This function changes the phytxctl for beacon based on current
3994 * beacon ratespec AND txant setting as per this table:
3995 * ratespec CCK ant = wlc->stf->txant
3996 * OFDM ant = 3
3997 */
3998 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3999 u32 bcn_rspec)
4000 {
4001 u16 phyctl;
4002 u16 phytxant = wlc->stf->phytxant;
4003 u16 mask = PHY_TXC_ANT_MASK;
4004
4005 /* for non-siso rates or default setting, use the available chains */
4006 if (BRCMS_PHY_11N_CAP(wlc->band))
4007 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
4008
4009 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
4010 phyctl = (phyctl & ~mask) | phytxant;
4011 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
4012 }
4013
4014 /*
4015 * centralized protection config change function to simplify debugging, no
4016 * consistency checking this should be called only on changes to avoid overhead
4017 * in periodic function
4018 */
4019 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4020 {
4021 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4022
4023 switch (idx) {
4024 case BRCMS_PROT_G_SPEC:
4025 wlc->protection->_g = (bool) val;
4026 break;
4027 case BRCMS_PROT_G_OVR:
4028 wlc->protection->g_override = (s8) val;
4029 break;
4030 case BRCMS_PROT_G_USER:
4031 wlc->protection->gmode_user = (u8) val;
4032 break;
4033 case BRCMS_PROT_OVERLAP:
4034 wlc->protection->overlap = (s8) val;
4035 break;
4036 case BRCMS_PROT_N_USER:
4037 wlc->protection->nmode_user = (s8) val;
4038 break;
4039 case BRCMS_PROT_N_CFG:
4040 wlc->protection->n_cfg = (s8) val;
4041 break;
4042 case BRCMS_PROT_N_CFG_OVR:
4043 wlc->protection->n_cfg_override = (s8) val;
4044 break;
4045 case BRCMS_PROT_N_NONGF:
4046 wlc->protection->nongf = (bool) val;
4047 break;
4048 case BRCMS_PROT_N_NONGF_OVR:
4049 wlc->protection->nongf_override = (s8) val;
4050 break;
4051 case BRCMS_PROT_N_PAM_OVR:
4052 wlc->protection->n_pam_override = (s8) val;
4053 break;
4054 case BRCMS_PROT_N_OBSS:
4055 wlc->protection->n_obss = (bool) val;
4056 break;
4057
4058 default:
4059 break;
4060 }
4061
4062 }
4063
4064 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4065 {
4066 if (wlc->pub->up) {
4067 brcms_c_update_beacon(wlc);
4068 brcms_c_update_probe_resp(wlc, true);
4069 }
4070 }
4071
4072 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4073 {
4074 wlc->stf->ldpc = val;
4075
4076 if (wlc->pub->up) {
4077 brcms_c_update_beacon(wlc);
4078 brcms_c_update_probe_resp(wlc, true);
4079 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4080 }
4081 }
4082
4083 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4084 const struct ieee80211_tx_queue_params *params,
4085 bool suspend)
4086 {
4087 int i;
4088 struct shm_acparams acp_shm;
4089 u16 *shm_entry;
4090
4091 /* Only apply params if the core is out of reset and has clocks */
4092 if (!wlc->clk) {
4093 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4094 __func__);
4095 return;
4096 }
4097
4098 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4099 /* fill in shm ac params struct */
4100 acp_shm.txop = params->txop;
4101 /* convert from units of 32us to us for ucode */
4102 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4103 EDCF_TXOP2USEC(acp_shm.txop);
4104 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4105
4106 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4107 && acp_shm.aifs < EDCF_AIFSN_MAX)
4108 acp_shm.aifs++;
4109
4110 if (acp_shm.aifs < EDCF_AIFSN_MIN
4111 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4112 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4113 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4114 } else {
4115 acp_shm.cwmin = params->cw_min;
4116 acp_shm.cwmax = params->cw_max;
4117 acp_shm.cwcur = acp_shm.cwmin;
4118 acp_shm.bslots =
4119 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4120 acp_shm.cwcur;
4121 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4122 /* Indicate the new params to the ucode */
4123 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4124 wme_ac2fifo[aci] *
4125 M_EDCF_QLEN +
4126 M_EDCF_STATUS_OFF));
4127 acp_shm.status |= WME_STATUS_NEWAC;
4128
4129 /* Fill in shm acparam table */
4130 shm_entry = (u16 *) &acp_shm;
4131 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4132 brcms_b_write_shm(wlc->hw,
4133 M_EDCF_QINFO +
4134 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4135 *shm_entry++);
4136 }
4137
4138 if (suspend) {
4139 brcms_c_suspend_mac_and_wait(wlc);
4140 brcms_c_enable_mac(wlc);
4141 }
4142 }
4143
4144 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4145 {
4146 u16 aci;
4147 int i_ac;
4148 struct ieee80211_tx_queue_params txq_pars;
4149 static const struct edcf_acparam default_edcf_acparams[] = {
4150 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4151 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4152 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4153 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4154 }; /* ucode needs these parameters during its initialization */
4155 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4156
4157 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4158 /* find out which ac this set of params applies to */
4159 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4160
4161 /* fill in shm ac params struct */
4162 txq_pars.txop = edcf_acp->TXOP;
4163 txq_pars.aifs = edcf_acp->ACI;
4164
4165 /* CWmin = 2^(ECWmin) - 1 */
4166 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4167 /* CWmax = 2^(ECWmax) - 1 */
4168 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4169 >> EDCF_ECWMAX_SHIFT);
4170 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4171 }
4172
4173 if (suspend) {
4174 brcms_c_suspend_mac_and_wait(wlc);
4175 brcms_c_enable_mac(wlc);
4176 }
4177 }
4178
4179 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4180 {
4181 /* Don't start the timer if HWRADIO feature is disabled */
4182 if (wlc->radio_monitor)
4183 return;
4184
4185 wlc->radio_monitor = true;
4186 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4187 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4188 }
4189
4190 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4191 {
4192 if (!wlc->radio_monitor)
4193 return true;
4194
4195 wlc->radio_monitor = false;
4196 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4197 return brcms_del_timer(wlc->radio_timer);
4198 }
4199
4200 /* read hwdisable state and propagate to wlc flag */
4201 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4202 {
4203 if (wlc->pub->hw_off)
4204 return;
4205
4206 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4207 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4208 else
4209 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4210 }
4211
4212 /* update hwradio status and return it */
4213 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4214 {
4215 brcms_c_radio_hwdisable_upd(wlc);
4216
4217 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4218 true : false;
4219 }
4220
4221 /* periodical query hw radio button while driver is "down" */
4222 static void brcms_c_radio_timer(void *arg)
4223 {
4224 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4225
4226 if (brcms_deviceremoved(wlc)) {
4227 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4228 __func__);
4229 brcms_down(wlc->wl);
4230 return;
4231 }
4232
4233 brcms_c_radio_hwdisable_upd(wlc);
4234 }
4235
4236 /* common low-level watchdog code */
4237 static void brcms_b_watchdog(void *arg)
4238 {
4239 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4240 struct brcms_hardware *wlc_hw = wlc->hw;
4241
4242 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4243
4244 if (!wlc_hw->up)
4245 return;
4246
4247 /* increment second count */
4248 wlc_hw->now++;
4249
4250 /* Check for FIFO error interrupts */
4251 brcms_b_fifoerrors(wlc_hw);
4252
4253 /* make sure RX dma has buffers */
4254 dma_rxfill(wlc->hw->di[RX_FIFO]);
4255
4256 wlc_phy_watchdog(wlc_hw->band->pi);
4257 }
4258
4259 /* common watchdog code */
4260 static void brcms_c_watchdog(void *arg)
4261 {
4262 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4263
4264 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4265
4266 if (!wlc->pub->up)
4267 return;
4268
4269 if (brcms_deviceremoved(wlc)) {
4270 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4271 __func__);
4272 brcms_down(wlc->wl);
4273 return;
4274 }
4275
4276 /* increment second count */
4277 wlc->pub->now++;
4278
4279 brcms_c_radio_hwdisable_upd(wlc);
4280 /* if radio is disable, driver may be down, quit here */
4281 if (wlc->pub->radio_disabled)
4282 return;
4283
4284 brcms_b_watchdog(wlc);
4285
4286 /*
4287 * occasionally sample mac stat counters to
4288 * detect 16-bit counter wrap
4289 */
4290 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4291 brcms_c_statsupd(wlc);
4292
4293 if (BRCMS_ISNPHY(wlc->band) &&
4294 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4295 BRCMS_TEMPSENSE_PERIOD)) {
4296 wlc->tempsense_lasttime = wlc->pub->now;
4297 brcms_c_tempsense_upd(wlc);
4298 }
4299 }
4300
4301 static void brcms_c_watchdog_by_timer(void *arg)
4302 {
4303 brcms_c_watchdog(arg);
4304 }
4305
4306 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4307 {
4308 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4309 wlc, "watchdog");
4310 if (!wlc->wdtimer) {
4311 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4312 "failed\n", unit);
4313 goto fail;
4314 }
4315
4316 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4317 wlc, "radio");
4318 if (!wlc->radio_timer) {
4319 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4320 "failed\n", unit);
4321 goto fail;
4322 }
4323
4324 return true;
4325
4326 fail:
4327 return false;
4328 }
4329
4330 /*
4331 * Initialize brcms_c_info default values ...
4332 * may get overrides later in this function
4333 */
4334 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4335 {
4336 int i;
4337
4338 /* Save our copy of the chanspec */
4339 wlc->chanspec = ch20mhz_chspec(1);
4340
4341 /* various 802.11g modes */
4342 wlc->shortslot = false;
4343 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4344
4345 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4346 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4347
4348 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4349 BRCMS_PROTECTION_AUTO);
4350 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4351 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4352 BRCMS_PROTECTION_AUTO);
4353 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4354 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4355
4356 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4357 BRCMS_PROTECTION_CTL_OVERLAP);
4358
4359 /* 802.11g draft 4.0 NonERP elt advertisement */
4360 wlc->include_legacy_erp = true;
4361
4362 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4363 wlc->stf->txant = ANT_TX_DEF;
4364
4365 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4366
4367 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4368 for (i = 0; i < NFIFO; i++)
4369 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4370 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4371
4372 /* default rate fallback retry limits */
4373 wlc->SFBL = RETRY_SHORT_FB;
4374 wlc->LFBL = RETRY_LONG_FB;
4375
4376 /* default mac retry limits */
4377 wlc->SRL = RETRY_SHORT_DEF;
4378 wlc->LRL = RETRY_LONG_DEF;
4379
4380 /* WME QoS mode is Auto by default */
4381 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4382 wlc->pub->bcmerror = 0;
4383 }
4384
4385 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4386 {
4387 uint err = 0;
4388 uint unit;
4389 unit = wlc->pub->unit;
4390
4391 wlc->asi = brcms_c_antsel_attach(wlc);
4392 if (wlc->asi == NULL) {
4393 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4394 "failed\n", unit);
4395 err = 44;
4396 goto fail;
4397 }
4398
4399 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4400 if (wlc->ampdu == NULL) {
4401 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4402 "failed\n", unit);
4403 err = 50;
4404 goto fail;
4405 }
4406
4407 if ((brcms_c_stf_attach(wlc) != 0)) {
4408 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4409 "failed\n", unit);
4410 err = 68;
4411 goto fail;
4412 }
4413 fail:
4414 return err;
4415 }
4416
4417 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4418 {
4419 return wlc->pub;
4420 }
4421
4422 /* low level attach
4423 * run backplane attach, init nvram
4424 * run phy attach
4425 * initialize software state for each core and band
4426 * put the whole chip in reset(driver down state), no clock
4427 */
4428 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4429 uint unit, bool piomode)
4430 {
4431 struct brcms_hardware *wlc_hw;
4432 uint err = 0;
4433 uint j;
4434 bool wme = false;
4435 struct shared_phy_params sha_params;
4436 struct wiphy *wiphy = wlc->wiphy;
4437 struct pci_dev *pcidev = core->bus->host_pci;
4438 struct ssb_sprom *sprom = &core->bus->sprom;
4439
4440 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4441 pcidev->vendor,
4442 pcidev->device);
4443
4444 wme = true;
4445
4446 wlc_hw = wlc->hw;
4447 wlc_hw->wlc = wlc;
4448 wlc_hw->unit = unit;
4449 wlc_hw->band = wlc_hw->bandstate[0];
4450 wlc_hw->_piomode = piomode;
4451
4452 /* populate struct brcms_hardware with default values */
4453 brcms_b_info_init(wlc_hw);
4454
4455 /*
4456 * Do the hardware portion of the attach. Also initialize software
4457 * state that depends on the particular hardware we are running.
4458 */
4459 wlc_hw->sih = ai_attach(core->bus);
4460 if (wlc_hw->sih == NULL) {
4461 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4462 unit);
4463 err = 11;
4464 goto fail;
4465 }
4466
4467 /* verify again the device is supported */
4468 if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
4469 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
4470 "vendor/device (0x%x/0x%x)\n",
4471 unit, pcidev->vendor, pcidev->device);
4472 err = 12;
4473 goto fail;
4474 }
4475
4476 wlc_hw->vendorid = pcidev->vendor;
4477 wlc_hw->deviceid = pcidev->device;
4478
4479 wlc_hw->d11core = core;
4480 wlc_hw->corerev = core->id.rev;
4481
4482 /* validate chip, chiprev and corerev */
4483 if (!brcms_c_isgoodchip(wlc_hw)) {
4484 err = 13;
4485 goto fail;
4486 }
4487
4488 /* initialize power control registers */
4489 ai_clkctl_init(wlc_hw->sih);
4490
4491 /* request fastclock and force fastclock for the rest of attach
4492 * bring the d11 core out of reset.
4493 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4494 * is still false; But it will be called again inside wlc_corereset,
4495 * after d11 is out of reset.
4496 */
4497 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
4498 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4499
4500 if (!brcms_b_validate_chip_access(wlc_hw)) {
4501 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4502 "failed\n", unit);
4503 err = 14;
4504 goto fail;
4505 }
4506
4507 /* get the board rev, used just below */
4508 j = sprom->board_rev;
4509 /* promote srom boardrev of 0xFF to 1 */
4510 if (j == BOARDREV_PROMOTABLE)
4511 j = BOARDREV_PROMOTED;
4512 wlc_hw->boardrev = (u16) j;
4513 if (!brcms_c_validboardtype(wlc_hw)) {
4514 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4515 "board type (0x%x)" " or revision level (0x%x)\n",
4516 unit, ai_get_boardtype(wlc_hw->sih),
4517 wlc_hw->boardrev);
4518 err = 15;
4519 goto fail;
4520 }
4521 wlc_hw->sromrev = sprom->revision;
4522 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4523 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4524
4525 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4526 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4527
4528 /* check device id(srom, nvram etc.) to set bands */
4529 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4530 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4531 /* Dualband boards */
4532 wlc_hw->_nbands = 2;
4533 else
4534 wlc_hw->_nbands = 1;
4535
4536 if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
4537 wlc_hw->_nbands = 1;
4538
4539 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4540 * unconditionally does the init of these values
4541 */
4542 wlc->vendorid = wlc_hw->vendorid;
4543 wlc->deviceid = wlc_hw->deviceid;
4544 wlc->pub->sih = wlc_hw->sih;
4545 wlc->pub->corerev = wlc_hw->corerev;
4546 wlc->pub->sromrev = wlc_hw->sromrev;
4547 wlc->pub->boardrev = wlc_hw->boardrev;
4548 wlc->pub->boardflags = wlc_hw->boardflags;
4549 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4550 wlc->pub->_nbands = wlc_hw->_nbands;
4551
4552 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4553
4554 if (wlc_hw->physhim == NULL) {
4555 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4556 "failed\n", unit);
4557 err = 25;
4558 goto fail;
4559 }
4560
4561 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4562 sha_params.sih = wlc_hw->sih;
4563 sha_params.physhim = wlc_hw->physhim;
4564 sha_params.unit = unit;
4565 sha_params.corerev = wlc_hw->corerev;
4566 sha_params.vid = wlc_hw->vendorid;
4567 sha_params.did = wlc_hw->deviceid;
4568 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4569 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4570 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4571 sha_params.sromrev = wlc_hw->sromrev;
4572 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4573 sha_params.boardrev = wlc_hw->boardrev;
4574 sha_params.boardflags = wlc_hw->boardflags;
4575 sha_params.boardflags2 = wlc_hw->boardflags2;
4576
4577 /* alloc and save pointer to shared phy state area */
4578 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4579 if (!wlc_hw->phy_sh) {
4580 err = 16;
4581 goto fail;
4582 }
4583
4584 /* initialize software state for each core and band */
4585 for (j = 0; j < wlc_hw->_nbands; j++) {
4586 /*
4587 * band0 is always 2.4Ghz
4588 * band1, if present, is 5Ghz
4589 */
4590
4591 brcms_c_setxband(wlc_hw, j);
4592
4593 wlc_hw->band->bandunit = j;
4594 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4595 wlc->band->bandunit = j;
4596 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4597 wlc->core->coreidx = core->core_index;
4598
4599 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4600 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4601
4602 /* init tx fifo size */
4603 wlc_hw->xmtfifo_sz =
4604 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4605
4606 /* Get a phy for this band */
4607 wlc_hw->band->pi =
4608 wlc_phy_attach(wlc_hw->phy_sh, core,
4609 wlc_hw->band->bandtype,
4610 wlc->wiphy);
4611 if (wlc_hw->band->pi == NULL) {
4612 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4613 "attach failed\n", unit);
4614 err = 17;
4615 goto fail;
4616 }
4617
4618 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4619
4620 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4621 &wlc_hw->band->phyrev,
4622 &wlc_hw->band->radioid,
4623 &wlc_hw->band->radiorev);
4624 wlc_hw->band->abgphy_encore =
4625 wlc_phy_get_encore(wlc_hw->band->pi);
4626 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4627 wlc_hw->band->core_flags =
4628 wlc_phy_get_coreflags(wlc_hw->band->pi);
4629
4630 /* verify good phy_type & supported phy revision */
4631 if (BRCMS_ISNPHY(wlc_hw->band)) {
4632 if (NCONF_HAS(wlc_hw->band->phyrev))
4633 goto good_phy;
4634 else
4635 goto bad_phy;
4636 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4637 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4638 goto good_phy;
4639 else
4640 goto bad_phy;
4641 } else {
4642 bad_phy:
4643 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4644 "phy type/rev (%d/%d)\n", unit,
4645 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4646 err = 18;
4647 goto fail;
4648 }
4649
4650 good_phy:
4651 /*
4652 * BMAC_NOTE: wlc->band->pi should not be set below and should
4653 * be done in the high level attach. However we can not make
4654 * that change until all low level access is changed to
4655 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4656 * keeping wlc_hw->band->pi as well for incremental update of
4657 * low level fns, and cut over low only init when all fns
4658 * updated.
4659 */
4660 wlc->band->pi = wlc_hw->band->pi;
4661 wlc->band->phytype = wlc_hw->band->phytype;
4662 wlc->band->phyrev = wlc_hw->band->phyrev;
4663 wlc->band->radioid = wlc_hw->band->radioid;
4664 wlc->band->radiorev = wlc_hw->band->radiorev;
4665
4666 /* default contention windows size limits */
4667 wlc_hw->band->CWmin = APHY_CWMIN;
4668 wlc_hw->band->CWmax = PHY_CWMAX;
4669
4670 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4671 err = 19;
4672 goto fail;
4673 }
4674 }
4675
4676 /* disable core to match driver "down" state */
4677 brcms_c_coredisable(wlc_hw);
4678
4679 /* Match driver "down" state */
4680 ai_pci_down(wlc_hw->sih);
4681
4682 /* turn off pll and xtal to match driver "down" state */
4683 brcms_b_xtal(wlc_hw, OFF);
4684
4685 /* *******************************************************************
4686 * The hardware is in the DOWN state at this point. D11 core
4687 * or cores are in reset with clocks off, and the board PLLs
4688 * are off if possible.
4689 *
4690 * Beyond this point, wlc->sbclk == false and chip registers
4691 * should not be touched.
4692 *********************************************************************
4693 */
4694
4695 /* init etheraddr state variables */
4696 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4697
4698 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4699 is_zero_ether_addr(wlc_hw->etheraddr)) {
4700 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4701 unit);
4702 err = 22;
4703 goto fail;
4704 }
4705
4706 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4707 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4708
4709 return err;
4710
4711 fail:
4712 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4713 err);
4714 return err;
4715 }
4716
4717 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4718 {
4719 uint unit;
4720 unit = wlc->pub->unit;
4721
4722 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4723 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4724 wlc->band->antgain = 8;
4725 } else if (wlc->band->antgain == -1) {
4726 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4727 " srom, using 2dB\n", unit, __func__);
4728 wlc->band->antgain = 8;
4729 } else {
4730 s8 gain, fract;
4731 /* Older sroms specified gain in whole dbm only. In order
4732 * be able to specify qdbm granularity and remain backward
4733 * compatible the whole dbms are now encoded in only
4734 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4735 * 6 bit signed number ranges from -32 - 31.
4736 *
4737 * Examples:
4738 * 0x1 = 1 db,
4739 * 0xc1 = 1.75 db (1 + 3 quarters),
4740 * 0x3f = -1 (-1 + 0 quarters),
4741 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4742 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4743 */
4744 gain = wlc->band->antgain & 0x3f;
4745 gain <<= 2; /* Sign extend */
4746 gain >>= 2;
4747 fract = (wlc->band->antgain & 0xc0) >> 6;
4748 wlc->band->antgain = 4 * gain + fract;
4749 }
4750 }
4751
4752 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4753 {
4754 int aa;
4755 uint unit;
4756 int bandtype;
4757 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4758
4759 unit = wlc->pub->unit;
4760 bandtype = wlc->band->bandtype;
4761
4762 /* get antennas available */
4763 if (bandtype == BRCM_BAND_5G)
4764 aa = sprom->ant_available_a;
4765 else
4766 aa = sprom->ant_available_bg;
4767
4768 if ((aa < 1) || (aa > 15)) {
4769 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4770 " srom (0x%x), using 3\n", unit, __func__, aa);
4771 aa = 3;
4772 }
4773
4774 /* reset the defaults if we have a single antenna */
4775 if (aa == 1) {
4776 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4777 wlc->stf->txant = ANT_TX_FORCE_0;
4778 } else if (aa == 2) {
4779 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4780 wlc->stf->txant = ANT_TX_FORCE_1;
4781 } else {
4782 }
4783
4784 /* Compute Antenna Gain */
4785 if (bandtype == BRCM_BAND_5G)
4786 wlc->band->antgain = sprom->antenna_gain.a1;
4787 else
4788 wlc->band->antgain = sprom->antenna_gain.a0;
4789
4790 brcms_c_attach_antgain_init(wlc);
4791
4792 return true;
4793 }
4794
4795 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4796 {
4797 u16 chanspec;
4798 struct brcms_band *band;
4799 struct brcms_bss_info *bi = wlc->default_bss;
4800
4801 /* init default and target BSS with some sane initial values */
4802 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4803 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4804
4805 /* fill the default channel as the first valid channel
4806 * starting from the 2G channels
4807 */
4808 chanspec = ch20mhz_chspec(1);
4809 wlc->home_chanspec = bi->chanspec = chanspec;
4810
4811 /* find the band of our default channel */
4812 band = wlc->band;
4813 if (wlc->pub->_nbands > 1 &&
4814 band->bandunit != chspec_bandunit(chanspec))
4815 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4816
4817 /* init bss rates to the band specific default rate set */
4818 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4819 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4820 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4821 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4822
4823 if (wlc->pub->_n_enab & SUPPORT_11N)
4824 bi->flags |= BRCMS_BSS_HT;
4825 }
4826
4827 static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
4828 {
4829 struct brcms_txq_info *qi, *p;
4830
4831 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
4832 if (qi != NULL) {
4833 /*
4834 * Have enough room for control packets along with HI watermark
4835 * Also, add room to txq for total psq packets if all the SCBs
4836 * leave PS mode. The watermark for flowcontrol to OS packets
4837 * will remain the same
4838 */
4839 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
4840 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
4841
4842 /* add this queue to the the global list */
4843 p = wlc->tx_queues;
4844 if (p == NULL) {
4845 wlc->tx_queues = qi;
4846 } else {
4847 while (p->next != NULL)
4848 p = p->next;
4849 p->next = qi;
4850 }
4851 }
4852 return qi;
4853 }
4854
4855 static void brcms_c_txq_free(struct brcms_c_info *wlc,
4856 struct brcms_txq_info *qi)
4857 {
4858 struct brcms_txq_info *p;
4859
4860 if (qi == NULL)
4861 return;
4862
4863 /* remove the queue from the linked list */
4864 p = wlc->tx_queues;
4865 if (p == qi)
4866 wlc->tx_queues = p->next;
4867 else {
4868 while (p != NULL && p->next != qi)
4869 p = p->next;
4870 if (p != NULL)
4871 p->next = p->next->next;
4872 }
4873
4874 kfree(qi);
4875 }
4876
4877 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4878 {
4879 uint i;
4880 struct brcms_band *band;
4881
4882 for (i = 0; i < wlc->pub->_nbands; i++) {
4883 band = wlc->bandstate[i];
4884 if (band->bandtype == BRCM_BAND_5G) {
4885 if ((bwcap == BRCMS_N_BW_40ALL)
4886 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4887 band->mimo_cap_40 = true;
4888 else
4889 band->mimo_cap_40 = false;
4890 } else {
4891 if (bwcap == BRCMS_N_BW_40ALL)
4892 band->mimo_cap_40 = true;
4893 else
4894 band->mimo_cap_40 = false;
4895 }
4896 }
4897 }
4898
4899 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4900 {
4901 /* free timer state */
4902 if (wlc->wdtimer) {
4903 brcms_free_timer(wlc->wdtimer);
4904 wlc->wdtimer = NULL;
4905 }
4906 if (wlc->radio_timer) {
4907 brcms_free_timer(wlc->radio_timer);
4908 wlc->radio_timer = NULL;
4909 }
4910 }
4911
4912 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4913 {
4914 if (wlc->asi) {
4915 brcms_c_antsel_detach(wlc->asi);
4916 wlc->asi = NULL;
4917 }
4918
4919 if (wlc->ampdu) {
4920 brcms_c_ampdu_detach(wlc->ampdu);
4921 wlc->ampdu = NULL;
4922 }
4923
4924 brcms_c_stf_detach(wlc);
4925 }
4926
4927 /*
4928 * low level detach
4929 */
4930 static int brcms_b_detach(struct brcms_c_info *wlc)
4931 {
4932 uint i;
4933 struct brcms_hw_band *band;
4934 struct brcms_hardware *wlc_hw = wlc->hw;
4935 int callbacks;
4936
4937 callbacks = 0;
4938
4939 if (wlc_hw->sih) {
4940 /*
4941 * detach interrupt sync mechanism since interrupt is disabled
4942 * and per-port interrupt object may has been freed. this must
4943 * be done before sb core switch
4944 */
4945 ai_pci_sleep(wlc_hw->sih);
4946 }
4947
4948 brcms_b_detach_dmapio(wlc_hw);
4949
4950 band = wlc_hw->band;
4951 for (i = 0; i < wlc_hw->_nbands; i++) {
4952 if (band->pi) {
4953 /* Detach this band's phy */
4954 wlc_phy_detach(band->pi);
4955 band->pi = NULL;
4956 }
4957 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4958 }
4959
4960 /* Free shared phy state */
4961 kfree(wlc_hw->phy_sh);
4962
4963 wlc_phy_shim_detach(wlc_hw->physhim);
4964
4965 if (wlc_hw->sih) {
4966 ai_detach(wlc_hw->sih);
4967 wlc_hw->sih = NULL;
4968 }
4969
4970 return callbacks;
4971
4972 }
4973
4974 /*
4975 * Return a count of the number of driver callbacks still pending.
4976 *
4977 * General policy is that brcms_c_detach can only dealloc/free software states.
4978 * It can NOT touch hardware registers since the d11core may be in reset and
4979 * clock may not be available.
4980 * One exception is sb register access, which is possible if crystal is turned
4981 * on after "down" state, driver should avoid software timer with the exception
4982 * of radio_monitor.
4983 */
4984 uint brcms_c_detach(struct brcms_c_info *wlc)
4985 {
4986 uint callbacks = 0;
4987
4988 if (wlc == NULL)
4989 return 0;
4990
4991 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4992
4993 callbacks += brcms_b_detach(wlc);
4994
4995 /* delete software timers */
4996 if (!brcms_c_radio_monitor_stop(wlc))
4997 callbacks++;
4998
4999 brcms_c_channel_mgr_detach(wlc->cmi);
5000
5001 brcms_c_timers_deinit(wlc);
5002
5003 brcms_c_detach_module(wlc);
5004
5005
5006 while (wlc->tx_queues != NULL)
5007 brcms_c_txq_free(wlc, wlc->tx_queues);
5008
5009 brcms_c_detach_mfree(wlc);
5010 return callbacks;
5011 }
5012
5013 /* update state that depends on the current value of "ap" */
5014 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
5015 {
5016 /* STA-BSS; short capable */
5017 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
5018 }
5019
5020 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
5021 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5022 {
5023 if (wlc_hw->wlc->pub->hw_up)
5024 return;
5025
5026 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5027
5028 /*
5029 * Enable pll and xtal, initialize the power control registers,
5030 * and force fastclock for the remainder of brcms_c_up().
5031 */
5032 brcms_b_xtal(wlc_hw, ON);
5033 ai_clkctl_init(wlc_hw->sih);
5034 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5035
5036 ai_pci_fixcfg(wlc_hw->sih);
5037
5038 /*
5039 * TODO: test suspend/resume
5040 *
5041 * AI chip doesn't restore bar0win2 on
5042 * hibernation/resume, need sw fixup
5043 */
5044
5045 /*
5046 * Inform phy that a POR reset has occurred so
5047 * it does a complete phy init
5048 */
5049 wlc_phy_por_inform(wlc_hw->band->pi);
5050
5051 wlc_hw->ucode_loaded = false;
5052 wlc_hw->wlc->pub->hw_up = true;
5053
5054 if ((wlc_hw->boardflags & BFL_FEM)
5055 && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
5056 if (!
5057 (wlc_hw->boardrev >= 0x1250
5058 && (wlc_hw->boardflags & BFL_FEM_BT)))
5059 ai_epa_4313war(wlc_hw->sih);
5060 }
5061 }
5062
5063 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5064 {
5065 uint coremask;
5066
5067 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5068
5069 /*
5070 * Enable pll and xtal, initialize the power control registers,
5071 * and force fastclock for the remainder of brcms_c_up().
5072 */
5073 brcms_b_xtal(wlc_hw, ON);
5074 ai_clkctl_init(wlc_hw->sih);
5075 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5076
5077 /*
5078 * Configure pci/pcmcia here instead of in brcms_c_attach()
5079 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5080 */
5081 coremask = (1 << wlc_hw->wlc->core->coreidx);
5082
5083 ai_pci_setup(wlc_hw->sih, coremask);
5084
5085 /*
5086 * Need to read the hwradio status here to cover the case where the
5087 * system is loaded with the hw radio disabled. We do not want to
5088 * bring the driver up in this case.
5089 */
5090 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5091 /* put SB PCI in down state again */
5092 ai_pci_down(wlc_hw->sih);
5093 brcms_b_xtal(wlc_hw, OFF);
5094 return -ENOMEDIUM;
5095 }
5096
5097 ai_pci_up(wlc_hw->sih);
5098
5099 /* reset the d11 core */
5100 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5101
5102 return 0;
5103 }
5104
5105 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5106 {
5107 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5108
5109 wlc_hw->up = true;
5110 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5111
5112 /* FULLY enable dynamic power control and d11 core interrupt */
5113 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
5114 brcms_intrson(wlc_hw->wlc->wl);
5115 return 0;
5116 }
5117
5118 /*
5119 * Write WME tunable parameters for retransmit/max rate
5120 * from wlc struct to ucode
5121 */
5122 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5123 {
5124 int ac;
5125
5126 /* Need clock to do this */
5127 if (!wlc->clk)
5128 return;
5129
5130 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5131 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5132 wlc->wme_retries[ac]);
5133 }
5134
5135 /* make interface operational */
5136 int brcms_c_up(struct brcms_c_info *wlc)
5137 {
5138 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5139
5140 /* HW is turned off so don't try to access it */
5141 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5142 return -ENOMEDIUM;
5143
5144 if (!wlc->pub->hw_up) {
5145 brcms_b_hw_up(wlc->hw);
5146 wlc->pub->hw_up = true;
5147 }
5148
5149 if ((wlc->pub->boardflags & BFL_FEM)
5150 && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
5151 if (wlc->pub->boardrev >= 0x1250
5152 && (wlc->pub->boardflags & BFL_FEM_BT))
5153 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5154 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5155 else
5156 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5157 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5158 }
5159
5160 /*
5161 * Need to read the hwradio status here to cover the case where the
5162 * system is loaded with the hw radio disabled. We do not want to bring
5163 * the driver up in this case. If radio is disabled, abort up, lower
5164 * power, start radio timer and return 0(for NDIS) don't call
5165 * radio_update to avoid looping brcms_c_up.
5166 *
5167 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5168 */
5169 if (!wlc->pub->radio_disabled) {
5170 int status = brcms_b_up_prep(wlc->hw);
5171 if (status == -ENOMEDIUM) {
5172 if (!mboolisset
5173 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5174 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5175 mboolset(wlc->pub->radio_disabled,
5176 WL_RADIO_HW_DISABLE);
5177
5178 if (bsscfg->enable && bsscfg->BSS)
5179 wiphy_err(wlc->wiphy, "wl%d: up"
5180 ": rfdisable -> "
5181 "bsscfg_disable()\n",
5182 wlc->pub->unit);
5183 }
5184 }
5185 }
5186
5187 if (wlc->pub->radio_disabled) {
5188 brcms_c_radio_monitor_start(wlc);
5189 return 0;
5190 }
5191
5192 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5193 wlc->clk = true;
5194
5195 brcms_c_radio_monitor_stop(wlc);
5196
5197 /* Set EDCF hostflags */
5198 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5199
5200 brcms_init(wlc->wl);
5201 wlc->pub->up = true;
5202
5203 if (wlc->bandinit_pending) {
5204 brcms_c_suspend_mac_and_wait(wlc);
5205 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec);
5206 wlc->bandinit_pending = false;
5207 brcms_c_enable_mac(wlc);
5208 }
5209
5210 brcms_b_up_finish(wlc->hw);
5211
5212 /* Program the TX wme params with the current settings */
5213 brcms_c_wme_retries_write(wlc);
5214
5215 /* start one second watchdog timer */
5216 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5217 wlc->WDarmed = true;
5218
5219 /* ensure antenna config is up to date */
5220 brcms_c_stf_phy_txant_upd(wlc);
5221 /* ensure LDPC config is in sync */
5222 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5223
5224 return 0;
5225 }
5226
5227 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5228 {
5229 uint callbacks = 0;
5230
5231 return callbacks;
5232 }
5233
5234 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5235 {
5236 bool dev_gone;
5237 uint callbacks = 0;
5238
5239 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5240
5241 if (!wlc_hw->up)
5242 return callbacks;
5243
5244 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5245
5246 /* disable interrupts */
5247 if (dev_gone)
5248 wlc_hw->wlc->macintmask = 0;
5249 else {
5250 /* now disable interrupts */
5251 brcms_intrsoff(wlc_hw->wlc->wl);
5252
5253 /* ensure we're running on the pll clock again */
5254 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5255 }
5256 /* down phy at the last of this stage */
5257 callbacks += wlc_phy_down(wlc_hw->band->pi);
5258
5259 return callbacks;
5260 }
5261
5262 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5263 {
5264 uint callbacks = 0;
5265 bool dev_gone;
5266
5267 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5268
5269 if (!wlc_hw->up)
5270 return callbacks;
5271
5272 wlc_hw->up = false;
5273 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5274
5275 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5276
5277 if (dev_gone) {
5278 wlc_hw->sbclk = false;
5279 wlc_hw->clk = false;
5280 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5281
5282 /* reclaim any posted packets */
5283 brcms_c_flushqueues(wlc_hw->wlc);
5284 } else {
5285
5286 /* Reset and disable the core */
5287 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5288 if (bcma_read32(wlc_hw->d11core,
5289 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5290 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5291 callbacks += brcms_reset(wlc_hw->wlc->wl);
5292 brcms_c_coredisable(wlc_hw);
5293 }
5294
5295 /* turn off primary xtal and pll */
5296 if (!wlc_hw->noreset) {
5297 ai_pci_down(wlc_hw->sih);
5298 brcms_b_xtal(wlc_hw, OFF);
5299 }
5300 }
5301
5302 return callbacks;
5303 }
5304
5305 /*
5306 * Mark the interface nonoperational, stop the software mechanisms,
5307 * disable the hardware, free any transient buffer state.
5308 * Return a count of the number of driver callbacks still pending.
5309 */
5310 uint brcms_c_down(struct brcms_c_info *wlc)
5311 {
5312
5313 uint callbacks = 0;
5314 int i;
5315 bool dev_gone = false;
5316 struct brcms_txq_info *qi;
5317
5318 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5319
5320 /* check if we are already in the going down path */
5321 if (wlc->going_down) {
5322 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5323 "\n", wlc->pub->unit, __func__);
5324 return 0;
5325 }
5326 if (!wlc->pub->up)
5327 return callbacks;
5328
5329 wlc->going_down = true;
5330
5331 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5332
5333 dev_gone = brcms_deviceremoved(wlc);
5334
5335 /* Call any registered down handlers */
5336 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5337 if (wlc->modulecb[i].down_fn)
5338 callbacks +=
5339 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5340 }
5341
5342 /* cancel the watchdog timer */
5343 if (wlc->WDarmed) {
5344 if (!brcms_del_timer(wlc->wdtimer))
5345 callbacks++;
5346 wlc->WDarmed = false;
5347 }
5348 /* cancel all other timers */
5349 callbacks += brcms_c_down_del_timer(wlc);
5350
5351 wlc->pub->up = false;
5352
5353 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5354
5355 /* clear txq flow control */
5356 brcms_c_txflowcontrol_reset(wlc);
5357
5358 /* flush tx queues */
5359 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
5360 brcmu_pktq_flush(&qi->q, true, NULL, NULL);
5361
5362 callbacks += brcms_b_down_finish(wlc->hw);
5363
5364 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5365 wlc->clk = false;
5366
5367 wlc->going_down = false;
5368 return callbacks;
5369 }
5370
5371 /* Set the current gmode configuration */
5372 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5373 {
5374 int ret = 0;
5375 uint i;
5376 struct brcms_c_rateset rs;
5377 /* Default to 54g Auto */
5378 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5379 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5380 bool shortslot_restrict = false; /* Restrict association to stations
5381 * that support shortslot
5382 */
5383 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5384 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5385 int preamble = BRCMS_PLCP_LONG;
5386 bool preamble_restrict = false; /* Restrict association to stations
5387 * that support short preambles
5388 */
5389 struct brcms_band *band;
5390
5391 /* if N-support is enabled, allow Gmode set as long as requested
5392 * Gmode is not GMODE_LEGACY_B
5393 */
5394 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5395 return -ENOTSUPP;
5396
5397 /* verify that we are dealing with 2G band and grab the band pointer */
5398 if (wlc->band->bandtype == BRCM_BAND_2G)
5399 band = wlc->band;
5400 else if ((wlc->pub->_nbands > 1) &&
5401 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5402 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5403 else
5404 return -EINVAL;
5405
5406 /* Legacy or bust when no OFDM is supported by regulatory */
5407 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
5408 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
5409 return -EINVAL;
5410
5411 /* update configuration value */
5412 if (config)
5413 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5414
5415 /* Clear rateset override */
5416 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5417
5418 switch (gmode) {
5419 case GMODE_LEGACY_B:
5420 shortslot = BRCMS_SHORTSLOT_OFF;
5421 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5422
5423 break;
5424
5425 case GMODE_LRS:
5426 break;
5427
5428 case GMODE_AUTO:
5429 /* Accept defaults */
5430 break;
5431
5432 case GMODE_ONLY:
5433 ofdm_basic = true;
5434 preamble = BRCMS_PLCP_SHORT;
5435 preamble_restrict = true;
5436 break;
5437
5438 case GMODE_PERFORMANCE:
5439 shortslot = BRCMS_SHORTSLOT_ON;
5440 shortslot_restrict = true;
5441 ofdm_basic = true;
5442 preamble = BRCMS_PLCP_SHORT;
5443 preamble_restrict = true;
5444 break;
5445
5446 default:
5447 /* Error */
5448 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5449 wlc->pub->unit, __func__, gmode);
5450 return -ENOTSUPP;
5451 }
5452
5453 band->gmode = gmode;
5454
5455 wlc->shortslot_override = shortslot;
5456
5457 /* Use the default 11g rateset */
5458 if (!rs.count)
5459 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5460
5461 if (ofdm_basic) {
5462 for (i = 0; i < rs.count; i++) {
5463 if (rs.rates[i] == BRCM_RATE_6M
5464 || rs.rates[i] == BRCM_RATE_12M
5465 || rs.rates[i] == BRCM_RATE_24M)
5466 rs.rates[i] |= BRCMS_RATE_FLAG;
5467 }
5468 }
5469
5470 /* Set default bss rateset */
5471 wlc->default_bss->rateset.count = rs.count;
5472 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5473 sizeof(wlc->default_bss->rateset.rates));
5474
5475 return ret;
5476 }
5477
5478 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5479 {
5480 uint i;
5481 s32 nmode = AUTO;
5482
5483 if (wlc->stf->txstreams == WL_11N_3x3)
5484 nmode = WL_11N_3x3;
5485 else
5486 nmode = WL_11N_2x2;
5487
5488 /* force GMODE_AUTO if NMODE is ON */
5489 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5490 if (nmode == WL_11N_3x3)
5491 wlc->pub->_n_enab = SUPPORT_HT;
5492 else
5493 wlc->pub->_n_enab = SUPPORT_11N;
5494 wlc->default_bss->flags |= BRCMS_BSS_HT;
5495 /* add the mcs rates to the default and hw ratesets */
5496 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5497 wlc->stf->txstreams);
5498 for (i = 0; i < wlc->pub->_nbands; i++)
5499 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5500 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5501
5502 return 0;
5503 }
5504
5505 static int
5506 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5507 struct brcms_c_rateset *rs_arg)
5508 {
5509 struct brcms_c_rateset rs, new;
5510 uint bandunit;
5511
5512 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5513
5514 /* check for bad count value */
5515 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5516 return -EINVAL;
5517
5518 /* try the current band */
5519 bandunit = wlc->band->bandunit;
5520 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5521 if (brcms_c_rate_hwrs_filter_sort_validate
5522 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5523 wlc->stf->txstreams))
5524 goto good;
5525
5526 /* try the other band */
5527 if (brcms_is_mband_unlocked(wlc)) {
5528 bandunit = OTHERBANDUNIT(wlc);
5529 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5530 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5531 &wlc->
5532 bandstate[bandunit]->
5533 hw_rateset, true,
5534 wlc->stf->txstreams))
5535 goto good;
5536 }
5537
5538 return -EBADE;
5539
5540 good:
5541 /* apply new rateset */
5542 memcpy(&wlc->default_bss->rateset, &new,
5543 sizeof(struct brcms_c_rateset));
5544 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5545 sizeof(struct brcms_c_rateset));
5546 return 0;
5547 }
5548
5549 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5550 {
5551 u8 r;
5552 bool war = false;
5553
5554 if (wlc->bsscfg->associated)
5555 r = wlc->bsscfg->current_bss->rateset.rates[0];
5556 else
5557 r = wlc->default_bss->rateset.rates[0];
5558
5559 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5560 }
5561
5562 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5563 {
5564 u16 chspec = ch20mhz_chspec(channel);
5565
5566 if (channel < 0 || channel > MAXCHANNEL)
5567 return -EINVAL;
5568
5569 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5570 return -EINVAL;
5571
5572
5573 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5574 if (wlc->band->bandunit != chspec_bandunit(chspec))
5575 wlc->bandinit_pending = true;
5576 else
5577 wlc->bandinit_pending = false;
5578 }
5579
5580 wlc->default_bss->chanspec = chspec;
5581 /* brcms_c_BSSinit() will sanitize the rateset before
5582 * using it.. */
5583 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5584 brcms_c_set_home_chanspec(wlc, chspec);
5585 brcms_c_suspend_mac_and_wait(wlc);
5586 brcms_c_set_chanspec(wlc, chspec);
5587 brcms_c_enable_mac(wlc);
5588 }
5589 return 0;
5590 }
5591
5592 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5593 {
5594 int ac;
5595
5596 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5597 lrl < 1 || lrl > RETRY_SHORT_MAX)
5598 return -EINVAL;
5599
5600 wlc->SRL = srl;
5601 wlc->LRL = lrl;
5602
5603 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5604
5605 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5606 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5607 EDCF_SHORT, wlc->SRL);
5608 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5609 EDCF_LONG, wlc->LRL);
5610 }
5611 brcms_c_wme_retries_write(wlc);
5612
5613 return 0;
5614 }
5615
5616 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5617 struct brcm_rateset *currs)
5618 {
5619 struct brcms_c_rateset *rs;
5620
5621 if (wlc->pub->associated)
5622 rs = &wlc->bsscfg->current_bss->rateset;
5623 else
5624 rs = &wlc->default_bss->rateset;
5625
5626 /* Copy only legacy rateset section */
5627 currs->count = rs->count;
5628 memcpy(&currs->rates, &rs->rates, rs->count);
5629 }
5630
5631 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5632 {
5633 struct brcms_c_rateset internal_rs;
5634 int bcmerror;
5635
5636 if (rs->count > BRCMS_NUMRATES)
5637 return -ENOBUFS;
5638
5639 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5640
5641 /* Copy only legacy rateset section */
5642 internal_rs.count = rs->count;
5643 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5644
5645 /* merge rateset coming in with the current mcsset */
5646 if (wlc->pub->_n_enab & SUPPORT_11N) {
5647 struct brcms_bss_info *mcsset_bss;
5648 if (wlc->bsscfg->associated)
5649 mcsset_bss = wlc->bsscfg->current_bss;
5650 else
5651 mcsset_bss = wlc->default_bss;
5652 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5653 MCSSET_LEN);
5654 }
5655
5656 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5657 if (!bcmerror)
5658 brcms_c_ofdm_rateset_war(wlc);
5659
5660 return bcmerror;
5661 }
5662
5663 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5664 {
5665 if (period < DOT11_MIN_BEACON_PERIOD ||
5666 period > DOT11_MAX_BEACON_PERIOD)
5667 return -EINVAL;
5668
5669 wlc->default_bss->beacon_period = period;
5670 return 0;
5671 }
5672
5673 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5674 {
5675 return wlc->band->phytype;
5676 }
5677
5678 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5679 {
5680 wlc->shortslot_override = sslot_override;
5681
5682 /*
5683 * shortslot is an 11g feature, so no more work if we are
5684 * currently on the 5G band
5685 */
5686 if (wlc->band->bandtype == BRCM_BAND_5G)
5687 return;
5688
5689 if (wlc->pub->up && wlc->pub->associated) {
5690 /* let watchdog or beacon processing update shortslot */
5691 } else if (wlc->pub->up) {
5692 /* unassociated shortslot is off */
5693 brcms_c_switch_shortslot(wlc, false);
5694 } else {
5695 /* driver is down, so just update the brcms_c_info
5696 * value */
5697 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5698 wlc->shortslot = false;
5699 else
5700 wlc->shortslot =
5701 (wlc->shortslot_override ==
5702 BRCMS_SHORTSLOT_ON);
5703 }
5704 }
5705
5706 /*
5707 * register watchdog and down handlers.
5708 */
5709 int brcms_c_module_register(struct brcms_pub *pub,
5710 const char *name, struct brcms_info *hdl,
5711 int (*d_fn)(void *handle))
5712 {
5713 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5714 int i;
5715
5716 /* find an empty entry and just add, no duplication check! */
5717 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5718 if (wlc->modulecb[i].name[0] == '\0') {
5719 strncpy(wlc->modulecb[i].name, name,
5720 sizeof(wlc->modulecb[i].name) - 1);
5721 wlc->modulecb[i].hdl = hdl;
5722 wlc->modulecb[i].down_fn = d_fn;
5723 return 0;
5724 }
5725 }
5726
5727 return -ENOSR;
5728 }
5729
5730 /* unregister module callbacks */
5731 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5732 struct brcms_info *hdl)
5733 {
5734 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5735 int i;
5736
5737 if (wlc == NULL)
5738 return -ENODATA;
5739
5740 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5741 if (!strcmp(wlc->modulecb[i].name, name) &&
5742 (wlc->modulecb[i].hdl == hdl)) {
5743 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5744 return 0;
5745 }
5746 }
5747
5748 /* table not found! */
5749 return -ENODATA;
5750 }
5751
5752 void brcms_c_print_txstatus(struct tx_status *txs)
5753 {
5754 pr_debug("\ntxpkt (MPDU) Complete\n");
5755
5756 pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status);
5757
5758 pr_debug("[15:12] %d frame attempts\n",
5759 (txs->status & TX_STATUS_FRM_RTX_MASK) >>
5760 TX_STATUS_FRM_RTX_SHIFT);
5761 pr_debug(" [11:8] %d rts attempts\n",
5762 (txs->status & TX_STATUS_RTS_RTX_MASK) >>
5763 TX_STATUS_RTS_RTX_SHIFT);
5764 pr_debug(" [7] %d PM mode indicated\n",
5765 txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
5766 pr_debug(" [6] %d intermediate status\n",
5767 txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
5768 pr_debug(" [5] %d AMPDU\n",
5769 txs->status & TX_STATUS_AMPDU ? 1 : 0);
5770 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
5771 (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
5772 (const char *[]) {
5773 "None",
5774 "PMQ Entry",
5775 "Flush request",
5776 "Previous frag failure",
5777 "Channel mismatch",
5778 "Lifetime Expiry",
5779 "Underflow"
5780 } [(txs->status & TX_STATUS_SUPR_MASK) >>
5781 TX_STATUS_SUPR_SHIFT]);
5782 pr_debug(" [1] %d acked\n",
5783 txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
5784
5785 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5786 txs->lasttxtime, txs->sequence, txs->phyerr,
5787 (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
5788 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
5789 }
5790
5791 bool brcms_c_chipmatch(u16 vendor, u16 device)
5792 {
5793 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5794 pr_err("unknown vendor id %04x\n", vendor);
5795 return false;
5796 }
5797
5798 if (device == BCM43224_D11N_ID_VEN1)
5799 return true;
5800 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5801 return true;
5802 if (device == BCM4313_D11N2G_ID)
5803 return true;
5804 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5805 return true;
5806
5807 pr_err("unknown device id %04x\n", device);
5808 return false;
5809 }
5810
5811 #if defined(DEBUG)
5812 void brcms_c_print_txdesc(struct d11txh *txh)
5813 {
5814 u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
5815 u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
5816 u16 mfc = le16_to_cpu(txh->MacFrameControl);
5817 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
5818 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
5819 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
5820 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
5821 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
5822 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
5823 u16 mainrates = le16_to_cpu(txh->MainRates);
5824 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
5825 u8 *iv = txh->IV;
5826 u8 *ra = txh->TxFrameRA;
5827 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
5828 u8 *rtspfb = txh->RTSPLCPFallback;
5829 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
5830 u8 *fragpfb = txh->FragPLCPFallback;
5831 u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
5832 u16 mmodelen = le16_to_cpu(txh->MModeLen);
5833 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
5834 u16 tfid = le16_to_cpu(txh->TxFrameID);
5835 u16 txs = le16_to_cpu(txh->TxStatus);
5836 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
5837 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
5838 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
5839 u16 mmbyte = le16_to_cpu(txh->MinMBytes);
5840
5841 u8 *rtsph = txh->RTSPhyHeader;
5842 struct ieee80211_rts rts = txh->rts_frame;
5843
5844 /* add plcp header along with txh descriptor */
5845 brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
5846 "Raw TxDesc + plcp header:\n");
5847
5848 pr_debug("TxCtlLow: %04x ", mtcl);
5849 pr_debug("TxCtlHigh: %04x ", mtch);
5850 pr_debug("FC: %04x ", mfc);
5851 pr_debug("FES Time: %04x\n", tfest);
5852 pr_debug("PhyCtl: %04x%s ", ptcw,
5853 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
5854 pr_debug("PhyCtl_1: %04x ", ptcw_1);
5855 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
5856 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
5857 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
5858 pr_debug("MainRates: %04x ", mainrates);
5859 pr_debug("XtraFrameTypes: %04x ", xtraft);
5860 pr_debug("\n");
5861
5862 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
5863 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
5864 ra, sizeof(txh->TxFrameRA));
5865
5866 pr_debug("Fb FES Time: %04x ", tfestfb);
5867 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
5868 rtspfb, sizeof(txh->RTSPLCPFallback));
5869 pr_debug("RTS DUR: %04x ", rtsdfb);
5870 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
5871 fragpfb, sizeof(txh->FragPLCPFallback));
5872 pr_debug("DUR: %04x", fragdfb);
5873 pr_debug("\n");
5874
5875 pr_debug("MModeLen: %04x ", mmodelen);
5876 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
5877
5878 pr_debug("FrameID: %04x\n", tfid);
5879 pr_debug("TxStatus: %04x\n", txs);
5880
5881 pr_debug("MaxNumMpdu: %04x\n", mnmpdu);
5882 pr_debug("MaxAggbyte: %04x\n", mabyte);
5883 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f);
5884 pr_debug("MinByte: %04x\n", mmbyte);
5885
5886 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
5887 rtsph, sizeof(txh->RTSPhyHeader));
5888 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
5889 (u8 *)&rts, sizeof(txh->rts_frame));
5890 pr_debug("\n");
5891 }
5892 #endif /* defined(DEBUG) */
5893
5894 #if defined(DEBUG)
5895 static int
5896 brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
5897 int len)
5898 {
5899 int i;
5900 char *p = buf;
5901 char hexstr[16];
5902 int slen = 0, nlen = 0;
5903 u32 bit;
5904 const char *name;
5905
5906 if (len < 2 || !buf)
5907 return 0;
5908
5909 buf[0] = '\0';
5910
5911 for (i = 0; flags != 0; i++) {
5912 bit = bd[i].bit;
5913 name = bd[i].name;
5914 if (bit == 0 && flags != 0) {
5915 /* print any unnamed bits */
5916 snprintf(hexstr, 16, "0x%X", flags);
5917 name = hexstr;
5918 flags = 0; /* exit loop */
5919 } else if ((flags & bit) == 0)
5920 continue;
5921 flags &= ~bit;
5922 nlen = strlen(name);
5923 slen += nlen;
5924 /* count btwn flag space */
5925 if (flags != 0)
5926 slen += 1;
5927 /* need NULL char as well */
5928 if (len <= slen)
5929 break;
5930 /* copy NULL char but don't count it */
5931 strncpy(p, name, nlen + 1);
5932 p += nlen;
5933 /* copy btwn flag space and NULL char */
5934 if (flags != 0)
5935 p += snprintf(p, 2, " ");
5936 len -= slen;
5937 }
5938
5939 /* indicate the str was too short */
5940 if (flags != 0) {
5941 if (len < 2)
5942 p -= 2 - len; /* overwrite last char */
5943 p += snprintf(p, 2, ">");
5944 }
5945
5946 return (int)(p - buf);
5947 }
5948 #endif /* defined(DEBUG) */
5949
5950 #if defined(DEBUG)
5951 void brcms_c_print_rxh(struct d11rxhdr *rxh)
5952 {
5953 u16 len = rxh->RxFrameSize;
5954 u16 phystatus_0 = rxh->PhyRxStatus_0;
5955 u16 phystatus_1 = rxh->PhyRxStatus_1;
5956 u16 phystatus_2 = rxh->PhyRxStatus_2;
5957 u16 phystatus_3 = rxh->PhyRxStatus_3;
5958 u16 macstatus1 = rxh->RxStatus1;
5959 u16 macstatus2 = rxh->RxStatus2;
5960 char flagstr[64];
5961 char lenbuf[20];
5962 static const struct brcms_c_bit_desc macstat_flags[] = {
5963 {RXS_FCSERR, "FCSErr"},
5964 {RXS_RESPFRAMETX, "Reply"},
5965 {RXS_PBPRES, "PADDING"},
5966 {RXS_DECATMPT, "DeCr"},
5967 {RXS_DECERR, "DeCrErr"},
5968 {RXS_BCNSENT, "Bcn"},
5969 {0, NULL}
5970 };
5971
5972 brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
5973
5974 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
5975
5976 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
5977
5978 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len,
5979 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
5980 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
5981 phystatus_0, phystatus_1, phystatus_2, phystatus_3);
5982 pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr);
5983 pr_debug("RXMACaggtype: %x\n",
5984 (macstatus2 & RXS_AGGTYPE_MASK));
5985 pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime);
5986 }
5987 #endif /* defined(DEBUG) */
5988
5989 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5990 {
5991 u16 table_ptr;
5992 u8 phy_rate, index;
5993
5994 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5995 if (is_ofdm_rate(rate))
5996 table_ptr = M_RT_DIRMAP_A;
5997 else
5998 table_ptr = M_RT_DIRMAP_B;
5999
6000 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
6001 * the index into the rate table.
6002 */
6003 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
6004 index = phy_rate & 0xf;
6005
6006 /* Find the SHM pointer to the rate table entry by looking in the
6007 * Direct-map Table
6008 */
6009 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
6010 }
6011
6012 static bool
6013 brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
6014 struct sk_buff *pkt, int prec, bool head)
6015 {
6016 struct sk_buff *p;
6017 int eprec = -1; /* precedence to evict from */
6018
6019 /* Determine precedence from which to evict packet, if any */
6020 if (pktq_pfull(q, prec))
6021 eprec = prec;
6022 else if (pktq_full(q)) {
6023 p = brcmu_pktq_peek_tail(q, &eprec);
6024 if (eprec > prec) {
6025 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
6026 "\n", __func__, eprec, prec);
6027 return false;
6028 }
6029 }
6030
6031 /* Evict if needed */
6032 if (eprec >= 0) {
6033 bool discard_oldest;
6034
6035 discard_oldest = ac_bitmap_tst(0, eprec);
6036
6037 /* Refuse newer packet unless configured to discard oldest */
6038 if (eprec == prec && !discard_oldest) {
6039 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
6040 "\n", __func__, prec);
6041 return false;
6042 }
6043
6044 /* Evict packet according to discard policy */
6045 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
6046 brcmu_pktq_pdeq_tail(q, eprec);
6047 brcmu_pkt_buf_free_skb(p);
6048 }
6049
6050 /* Enqueue */
6051 if (head)
6052 p = brcmu_pktq_penq_head(q, prec, pkt);
6053 else
6054 p = brcmu_pktq_penq(q, prec, pkt);
6055
6056 return true;
6057 }
6058
6059 /*
6060 * Attempts to queue a packet onto a multiple-precedence queue,
6061 * if necessary evicting a lower precedence packet from the queue.
6062 *
6063 * 'prec' is the precedence number that has already been mapped
6064 * from the packet priority.
6065 *
6066 * Returns true if packet consumed (queued), false if not.
6067 */
6068 static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
6069 struct sk_buff *pkt, int prec)
6070 {
6071 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
6072 }
6073
6074 void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
6075 struct sk_buff *sdu, uint prec)
6076 {
6077 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
6078 struct pktq *q = &qi->q;
6079 int prio;
6080
6081 prio = sdu->priority;
6082
6083 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
6084 /*
6085 * we might hit this condtion in case
6086 * packet flooding from mac80211 stack
6087 */
6088 brcmu_pkt_buf_free_skb(sdu);
6089 }
6090 }
6091
6092 /*
6093 * bcmc_fid_generate:
6094 * Generate frame ID for a BCMC packet. The frag field is not used
6095 * for MC frames so is used as part of the sequence number.
6096 */
6097 static inline u16
6098 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
6099 struct d11txh *txh)
6100 {
6101 u16 frameid;
6102
6103 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
6104 TXFID_QUEUE_MASK);
6105 frameid |=
6106 (((wlc->
6107 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6108 TX_BCMC_FIFO;
6109
6110 return frameid;
6111 }
6112
6113 static uint
6114 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
6115 u8 preamble_type)
6116 {
6117 uint dur = 0;
6118
6119 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
6120 wlc->pub->unit, rspec, preamble_type);
6121 /*
6122 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6123 * is less than or equal to the rate of the immediately previous
6124 * frame in the FES
6125 */
6126 rspec = brcms_basic_rate(wlc, rspec);
6127 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
6128 dur =
6129 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6130 (DOT11_ACK_LEN + FCS_LEN));
6131 return dur;
6132 }
6133
6134 static uint
6135 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
6136 u8 preamble_type)
6137 {
6138 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
6139 wlc->pub->unit, rspec, preamble_type);
6140 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
6141 }
6142
6143 static uint
6144 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
6145 u8 preamble_type)
6146 {
6147 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
6148 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
6149 /*
6150 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6151 * is less than or equal to the rate of the immediately previous
6152 * frame in the FES
6153 */
6154 rspec = brcms_basic_rate(wlc, rspec);
6155 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6156 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6157 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
6158 FCS_LEN));
6159 }
6160
6161 /* brcms_c_compute_frame_dur()
6162 *
6163 * Calculate the 802.11 MAC header DUR field for MPDU
6164 * DUR for a single frame = 1 SIFS + 1 ACK
6165 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6166 *
6167 * rate MPDU rate in unit of 500kbps
6168 * next_frag_len next MPDU length in bytes
6169 * preamble_type use short/GF or long/MM PLCP header
6170 */
6171 static u16
6172 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
6173 u8 preamble_type, uint next_frag_len)
6174 {
6175 u16 dur, sifs;
6176
6177 sifs = get_sifs(wlc->band);
6178
6179 dur = sifs;
6180 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
6181
6182 if (next_frag_len) {
6183 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6184 dur *= 2;
6185 /* add another SIFS and the frag time */
6186 dur += sifs;
6187 dur +=
6188 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
6189 next_frag_len);
6190 }
6191 return dur;
6192 }
6193
6194 /* The opposite of brcms_c_calc_frame_time */
6195 static uint
6196 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
6197 u8 preamble_type, uint dur)
6198 {
6199 uint nsyms, mac_len, Ndps, kNdps;
6200 uint rate = rspec2rate(ratespec);
6201
6202 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6203 wlc->pub->unit, ratespec, preamble_type, dur);
6204
6205 if (is_mcs_rate(ratespec)) {
6206 uint mcs = ratespec & RSPEC_RATE_MASK;
6207 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
6208 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
6209 /* payload calculation matches that of regular ofdm */
6210 if (wlc->band->bandtype == BRCM_BAND_2G)
6211 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
6212 /* kNdbps = kbps * 4 */
6213 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
6214 rspec_issgi(ratespec)) * 4;
6215 nsyms = dur / APHY_SYMBOL_TIME;
6216 mac_len =
6217 ((nsyms * kNdps) -
6218 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
6219 } else if (is_ofdm_rate(ratespec)) {
6220 dur -= APHY_PREAMBLE_TIME;
6221 dur -= APHY_SIGNAL_TIME;
6222 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6223 Ndps = rate * 2;
6224 nsyms = dur / APHY_SYMBOL_TIME;
6225 mac_len =
6226 ((nsyms * Ndps) -
6227 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
6228 } else {
6229 if (preamble_type & BRCMS_SHORT_PREAMBLE)
6230 dur -= BPHY_PLCP_SHORT_TIME;
6231 else
6232 dur -= BPHY_PLCP_TIME;
6233 mac_len = dur * rate;
6234 /* divide out factor of 2 in rate (1/2 mbps) */
6235 mac_len = mac_len / 8 / 2;
6236 }
6237 return mac_len;
6238 }
6239
6240 /*
6241 * Return true if the specified rate is supported by the specified band.
6242 * BRCM_BAND_AUTO indicates the current band.
6243 */
6244 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
6245 bool verbose)
6246 {
6247 struct brcms_c_rateset *hw_rateset;
6248 uint i;
6249
6250 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
6251 hw_rateset = &wlc->band->hw_rateset;
6252 else if (wlc->pub->_nbands > 1)
6253 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
6254 else
6255 /* other band specified and we are a single band device */
6256 return false;
6257
6258 /* check if this is a mimo rate */
6259 if (is_mcs_rate(rspec)) {
6260 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
6261 goto error;
6262
6263 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
6264 }
6265
6266 for (i = 0; i < hw_rateset->count; i++)
6267 if (hw_rateset->rates[i] == rspec2rate(rspec))
6268 return true;
6269 error:
6270 if (verbose)
6271 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
6272 "not in hw_rateset\n", wlc->pub->unit, rspec);
6273
6274 return false;
6275 }
6276
6277 static u32
6278 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
6279 u32 int_val)
6280 {
6281 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
6282 u8 rate = int_val & NRATE_RATE_MASK;
6283 u32 rspec;
6284 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
6285 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
6286 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
6287 == NRATE_OVERRIDE_MCS_ONLY);
6288 int bcmerror = 0;
6289
6290 if (!ismcs)
6291 return (u32) rate;
6292
6293 /* validate the combination of rate/mcs/stf is allowed */
6294 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
6295 /* mcs only allowed when nmode */
6296 if (stf > PHY_TXC1_MODE_SDM) {
6297 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
6298 wlc->pub->unit, __func__);
6299 bcmerror = -EINVAL;
6300 goto done;
6301 }
6302
6303 /* mcs 32 is a special case, DUP mode 40 only */
6304 if (rate == 32) {
6305 if (!CHSPEC_IS40(wlc->home_chanspec) ||
6306 ((stf != PHY_TXC1_MODE_SISO)
6307 && (stf != PHY_TXC1_MODE_CDD))) {
6308 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
6309 "32\n", wlc->pub->unit, __func__);
6310 bcmerror = -EINVAL;
6311 goto done;
6312 }
6313 /* mcs > 7 must use stf SDM */
6314 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
6315 /* mcs > 7 must use stf SDM */
6316 if (stf != PHY_TXC1_MODE_SDM) {
6317 BCMMSG(wlc->wiphy, "wl%d: enabling "
6318 "SDM mode for mcs %d\n",
6319 wlc->pub->unit, rate);
6320 stf = PHY_TXC1_MODE_SDM;
6321 }
6322 } else {
6323 /*
6324 * MCS 0-7 may use SISO, CDD, and for
6325 * phy_rev >= 3 STBC
6326 */
6327 if ((stf > PHY_TXC1_MODE_STBC) ||
6328 (!BRCMS_STBC_CAP_PHY(wlc)
6329 && (stf == PHY_TXC1_MODE_STBC))) {
6330 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
6331 "\n", wlc->pub->unit, __func__);
6332 bcmerror = -EINVAL;
6333 goto done;
6334 }
6335 }
6336 } else if (is_ofdm_rate(rate)) {
6337 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6338 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
6339 wlc->pub->unit, __func__);
6340 bcmerror = -EINVAL;
6341 goto done;
6342 }
6343 } else if (is_cck_rate(rate)) {
6344 if ((cur_band->bandtype != BRCM_BAND_2G)
6345 || (stf != PHY_TXC1_MODE_SISO)) {
6346 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
6347 wlc->pub->unit, __func__);
6348 bcmerror = -EINVAL;
6349 goto done;
6350 }
6351 } else {
6352 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
6353 wlc->pub->unit, __func__);
6354 bcmerror = -EINVAL;
6355 goto done;
6356 }
6357 /* make sure multiple antennae are available for non-siso rates */
6358 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6359 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
6360 "request\n", wlc->pub->unit, __func__);
6361 bcmerror = -EINVAL;
6362 goto done;
6363 }
6364
6365 rspec = rate;
6366 if (ismcs) {
6367 rspec |= RSPEC_MIMORATE;
6368 /* For STBC populate the STC field of the ratespec */
6369 if (stf == PHY_TXC1_MODE_STBC) {
6370 u8 stc;
6371 stc = 1; /* Nss for single stream is always 1 */
6372 rspec |= (stc << RSPEC_STC_SHIFT);
6373 }
6374 }
6375
6376 rspec |= (stf << RSPEC_STF_SHIFT);
6377
6378 if (override_mcs_only)
6379 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6380
6381 if (issgi)
6382 rspec |= RSPEC_SHORT_GI;
6383
6384 if ((rate != 0)
6385 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6386 return rate;
6387
6388 return rspec;
6389 done:
6390 return rate;
6391 }
6392
6393 /*
6394 * Compute PLCP, but only requires actual rate and length of pkt.
6395 * Rate is given in the driver standard multiple of 500 kbps.
6396 * le is set for 11 Mbps rate if necessary.
6397 * Broken out for PRQ.
6398 */
6399
6400 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6401 uint length, u8 *plcp)
6402 {
6403 u16 usec = 0;
6404 u8 le = 0;
6405
6406 switch (rate_500) {
6407 case BRCM_RATE_1M:
6408 usec = length << 3;
6409 break;
6410 case BRCM_RATE_2M:
6411 usec = length << 2;
6412 break;
6413 case BRCM_RATE_5M5:
6414 usec = (length << 4) / 11;
6415 if ((length << 4) - (usec * 11) > 0)
6416 usec++;
6417 break;
6418 case BRCM_RATE_11M:
6419 usec = (length << 3) / 11;
6420 if ((length << 3) - (usec * 11) > 0) {
6421 usec++;
6422 if ((usec * 11) - (length << 3) >= 8)
6423 le = D11B_PLCP_SIGNAL_LE;
6424 }
6425 break;
6426
6427 default:
6428 wiphy_err(wlc->wiphy,
6429 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6430 rate_500);
6431 rate_500 = BRCM_RATE_1M;
6432 usec = length << 3;
6433 break;
6434 }
6435 /* PLCP signal byte */
6436 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6437 /* PLCP service byte */
6438 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6439 /* PLCP length u16, little endian */
6440 plcp[2] = usec & 0xff;
6441 plcp[3] = (usec >> 8) & 0xff;
6442 /* PLCP CRC16 */
6443 plcp[4] = 0;
6444 plcp[5] = 0;
6445 }
6446
6447 /* Rate: 802.11 rate code, length: PSDU length in octets */
6448 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6449 {
6450 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6451 plcp[0] = mcs;
6452 if (rspec_is40mhz(rspec) || (mcs == 32))
6453 plcp[0] |= MIMO_PLCP_40MHZ;
6454 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6455 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6456 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6457 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6458 plcp[5] = 0;
6459 }
6460
6461 /* Rate: 802.11 rate code, length: PSDU length in octets */
6462 static void
6463 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6464 {
6465 u8 rate_signal;
6466 u32 tmp = 0;
6467 int rate = rspec2rate(rspec);
6468
6469 /*
6470 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6471 * transmitted first
6472 */
6473 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6474 memset(plcp, 0, D11_PHY_HDR_LEN);
6475 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6476
6477 tmp = (length & 0xfff) << 5;
6478 plcp[2] |= (tmp >> 16) & 0xff;
6479 plcp[1] |= (tmp >> 8) & 0xff;
6480 plcp[0] |= tmp & 0xff;
6481 }
6482
6483 /* Rate: 802.11 rate code, length: PSDU length in octets */
6484 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6485 uint length, u8 *plcp)
6486 {
6487 int rate = rspec2rate(rspec);
6488
6489 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6490 }
6491
6492 static void
6493 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6494 uint length, u8 *plcp)
6495 {
6496 if (is_mcs_rate(rspec))
6497 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6498 else if (is_ofdm_rate(rspec))
6499 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6500 else
6501 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6502 }
6503
6504 /* brcms_c_compute_rtscts_dur()
6505 *
6506 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6507 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6508 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6509 *
6510 * cts cts-to-self or rts/cts
6511 * rts_rate rts or cts rate in unit of 500kbps
6512 * rate next MPDU rate in unit of 500kbps
6513 * frame_len next MPDU frame length in bytes
6514 */
6515 u16
6516 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6517 u32 rts_rate,
6518 u32 frame_rate, u8 rts_preamble_type,
6519 u8 frame_preamble_type, uint frame_len, bool ba)
6520 {
6521 u16 dur, sifs;
6522
6523 sifs = get_sifs(wlc->band);
6524
6525 if (!cts_only) {
6526 /* RTS/CTS */
6527 dur = 3 * sifs;
6528 dur +=
6529 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6530 rts_preamble_type);
6531 } else {
6532 /* CTS-TO-SELF */
6533 dur = 2 * sifs;
6534 }
6535
6536 dur +=
6537 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6538 frame_len);
6539 if (ba)
6540 dur +=
6541 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6542 BRCMS_SHORT_PREAMBLE);
6543 else
6544 dur +=
6545 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6546 frame_preamble_type);
6547 return dur;
6548 }
6549
6550 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6551 {
6552 u16 phyctl1 = 0;
6553 u16 bw;
6554
6555 if (BRCMS_ISLCNPHY(wlc->band)) {
6556 bw = PHY_TXC1_BW_20MHZ;
6557 } else {
6558 bw = rspec_get_bw(rspec);
6559 /* 10Mhz is not supported yet */
6560 if (bw < PHY_TXC1_BW_20MHZ) {
6561 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
6562 "not supported yet, set to 20L\n", bw);
6563 bw = PHY_TXC1_BW_20MHZ;
6564 }
6565 }
6566
6567 if (is_mcs_rate(rspec)) {
6568 uint mcs = rspec & RSPEC_RATE_MASK;
6569
6570 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6571 phyctl1 = rspec_phytxbyte2(rspec);
6572 /* set the upper byte of phyctl1 */
6573 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6574 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6575 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6576 /*
6577 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6578 * Data Rate. Eventually MIMOPHY would also be converted to
6579 * this format
6580 */
6581 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6582 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6583 } else { /* legacy OFDM/CCK */
6584 s16 phycfg;
6585 /* get the phyctl byte from rate phycfg table */
6586 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6587 if (phycfg == -1) {
6588 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
6589 "legacy OFDM/CCK rate\n");
6590 phycfg = 0;
6591 }
6592 /* set the upper byte of phyctl1 */
6593 phyctl1 =
6594 (bw | (phycfg << 8) |
6595 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6596 }
6597 return phyctl1;
6598 }
6599
6600 /*
6601 * Add struct d11txh, struct cck_phy_hdr.
6602 *
6603 * 'p' data must start with 802.11 MAC header
6604 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6605 *
6606 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6607 *
6608 */
6609 static u16
6610 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6611 struct sk_buff *p, struct scb *scb, uint frag,
6612 uint nfrags, uint queue, uint next_frag_len)
6613 {
6614 struct ieee80211_hdr *h;
6615 struct d11txh *txh;
6616 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6617 int len, phylen, rts_phylen;
6618 u16 mch, phyctl, xfts, mainrates;
6619 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6620 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6621 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6622 bool use_rts = false;
6623 bool use_cts = false;
6624 bool use_rifs = false;
6625 bool short_preamble[2] = { false, false };
6626 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6627 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6628 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6629 struct ieee80211_rts *rts = NULL;
6630 bool qos;
6631 uint ac;
6632 bool hwtkmic = false;
6633 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6634 #define ANTCFG_NONE 0xFF
6635 u8 antcfg = ANTCFG_NONE;
6636 u8 fbantcfg = ANTCFG_NONE;
6637 uint phyctl1_stf = 0;
6638 u16 durid = 0;
6639 struct ieee80211_tx_rate *txrate[2];
6640 int k;
6641 struct ieee80211_tx_info *tx_info;
6642 bool is_mcs;
6643 u16 mimo_txbw;
6644 u8 mimo_preamble_type;
6645
6646 /* locate 802.11 MAC header */
6647 h = (struct ieee80211_hdr *)(p->data);
6648 qos = ieee80211_is_data_qos(h->frame_control);
6649
6650 /* compute length of frame in bytes for use in PLCP computations */
6651 len = p->len;
6652 phylen = len + FCS_LEN;
6653
6654 /* Get tx_info */
6655 tx_info = IEEE80211_SKB_CB(p);
6656
6657 /* add PLCP */
6658 plcp = skb_push(p, D11_PHY_HDR_LEN);
6659
6660 /* add Broadcom tx descriptor header */
6661 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6662 memset(txh, 0, D11_TXH_LEN);
6663
6664 /* setup frameid */
6665 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6666 /* non-AP STA should never use BCMC queue */
6667 if (queue == TX_BCMC_FIFO) {
6668 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
6669 "TX_BCMC!\n", wlc->pub->unit, __func__);
6670 frameid = bcmc_fid_generate(wlc, NULL, txh);
6671 } else {
6672 /* Increment the counter for first fragment */
6673 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6674 scb->seqnum[p->priority]++;
6675
6676 /* extract fragment number from frame first */
6677 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6678 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6679 h->seq_ctrl = cpu_to_le16(seq);
6680
6681 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6682 (queue & TXFID_QUEUE_MASK);
6683 }
6684 }
6685 frameid |= queue & TXFID_QUEUE_MASK;
6686
6687 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6688 if (ieee80211_is_beacon(h->frame_control))
6689 mcl |= TXC_IGNOREPMQ;
6690
6691 txrate[0] = tx_info->control.rates;
6692 txrate[1] = txrate[0] + 1;
6693
6694 /*
6695 * if rate control algorithm didn't give us a fallback
6696 * rate, use the primary rate
6697 */
6698 if (txrate[1]->idx < 0)
6699 txrate[1] = txrate[0];
6700
6701 for (k = 0; k < hw->max_rates; k++) {
6702 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6703 if (!is_mcs) {
6704 if ((txrate[k]->idx >= 0)
6705 && (txrate[k]->idx <
6706 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6707 rspec[k] =
6708 hw->wiphy->bands[tx_info->band]->
6709 bitrates[txrate[k]->idx].hw_value;
6710 short_preamble[k] =
6711 txrate[k]->
6712 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6713 true : false;
6714 } else {
6715 rspec[k] = BRCM_RATE_1M;
6716 }
6717 } else {
6718 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6719 NRATE_MCS_INUSE | txrate[k]->idx);
6720 }
6721
6722 /*
6723 * Currently only support same setting for primay and
6724 * fallback rates. Unify flags for each rate into a
6725 * single value for the frame
6726 */
6727 use_rts |=
6728 txrate[k]->
6729 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6730 use_cts |=
6731 txrate[k]->
6732 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6733
6734
6735 /*
6736 * (1) RATE:
6737 * determine and validate primary rate
6738 * and fallback rates
6739 */
6740 if (!rspec_active(rspec[k])) {
6741 rspec[k] = BRCM_RATE_1M;
6742 } else {
6743 if (!is_multicast_ether_addr(h->addr1)) {
6744 /* set tx antenna config */
6745 brcms_c_antsel_antcfg_get(wlc->asi, false,
6746 false, 0, 0, &antcfg, &fbantcfg);
6747 }
6748 }
6749 }
6750
6751 phyctl1_stf = wlc->stf->ss_opmode;
6752
6753 if (wlc->pub->_n_enab & SUPPORT_11N) {
6754 for (k = 0; k < hw->max_rates; k++) {
6755 /*
6756 * apply siso/cdd to single stream mcs's or ofdm
6757 * if rspec is auto selected
6758 */
6759 if (((is_mcs_rate(rspec[k]) &&
6760 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6761 is_ofdm_rate(rspec[k]))
6762 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6763 || !(rspec[k] & RSPEC_OVERRIDE))) {
6764 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6765
6766 /* For SISO MCS use STBC if possible */
6767 if (is_mcs_rate(rspec[k])
6768 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6769 u8 stc;
6770
6771 /* Nss for single stream is always 1 */
6772 stc = 1;
6773 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6774 RSPEC_STF_SHIFT) |
6775 (stc << RSPEC_STC_SHIFT);
6776 } else
6777 rspec[k] |=
6778 (phyctl1_stf << RSPEC_STF_SHIFT);
6779 }
6780
6781 /*
6782 * Is the phy configured to use 40MHZ frames? If
6783 * so then pick the desired txbw
6784 */
6785 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6786 /* default txbw is 20in40 SB */
6787 mimo_ctlchbw = mimo_txbw =
6788 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6789 wlc->band->pi))
6790 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6791
6792 if (is_mcs_rate(rspec[k])) {
6793 /* mcs 32 must be 40b/w DUP */
6794 if ((rspec[k] & RSPEC_RATE_MASK)
6795 == 32) {
6796 mimo_txbw =
6797 PHY_TXC1_BW_40MHZ_DUP;
6798 /* use override */
6799 } else if (wlc->mimo_40txbw != AUTO)
6800 mimo_txbw = wlc->mimo_40txbw;
6801 /* else check if dst is using 40 Mhz */
6802 else if (scb->flags & SCB_IS40)
6803 mimo_txbw = PHY_TXC1_BW_40MHZ;
6804 } else if (is_ofdm_rate(rspec[k])) {
6805 if (wlc->ofdm_40txbw != AUTO)
6806 mimo_txbw = wlc->ofdm_40txbw;
6807 } else if (wlc->cck_40txbw != AUTO) {
6808 mimo_txbw = wlc->cck_40txbw;
6809 }
6810 } else {
6811 /*
6812 * mcs32 is 40 b/w only.
6813 * This is possible for probe packets on
6814 * a STA during SCAN
6815 */
6816 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6817 /* mcs 0 */
6818 rspec[k] = RSPEC_MIMORATE;
6819
6820 mimo_txbw = PHY_TXC1_BW_20MHZ;
6821 }
6822
6823 /* Set channel width */
6824 rspec[k] &= ~RSPEC_BW_MASK;
6825 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6826 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6827 else
6828 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6829
6830 /* Disable short GI, not supported yet */
6831 rspec[k] &= ~RSPEC_SHORT_GI;
6832
6833 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6834 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6835 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6836
6837 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6838 && (!is_mcs_rate(rspec[k]))) {
6839 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
6840 "RC_MCS != is_mcs_rate(rspec)\n",
6841 wlc->pub->unit, __func__);
6842 }
6843
6844 if (is_mcs_rate(rspec[k])) {
6845 preamble_type[k] = mimo_preamble_type;
6846
6847 /*
6848 * if SGI is selected, then forced mm
6849 * for single stream
6850 */
6851 if ((rspec[k] & RSPEC_SHORT_GI)
6852 && is_single_stream(rspec[k] &
6853 RSPEC_RATE_MASK))
6854 preamble_type[k] = BRCMS_MM_PREAMBLE;
6855 }
6856
6857 /* should be better conditionalized */
6858 if (!is_mcs_rate(rspec[0])
6859 && (tx_info->control.rates[0].
6860 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6861 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6862 }
6863 } else {
6864 for (k = 0; k < hw->max_rates; k++) {
6865 /* Set ctrlchbw as 20Mhz */
6866 rspec[k] &= ~RSPEC_BW_MASK;
6867 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6868
6869 /* for nphy, stf of ofdm frames must follow policies */
6870 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6871 rspec[k] &= ~RSPEC_STF_MASK;
6872 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6873 }
6874 }
6875 }
6876
6877 /* Reset these for use with AMPDU's */
6878 txrate[0]->count = 0;
6879 txrate[1]->count = 0;
6880
6881 /* (2) PROTECTION, may change rspec */
6882 if ((ieee80211_is_data(h->frame_control) ||
6883 ieee80211_is_mgmt(h->frame_control)) &&
6884 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6885 use_rts = true;
6886
6887 /* (3) PLCP: determine PLCP header and MAC duration,
6888 * fill struct d11txh */
6889 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6890 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6891 memcpy(&txh->FragPLCPFallback,
6892 plcp_fallback, sizeof(txh->FragPLCPFallback));
6893
6894 /* Length field now put in CCK FBR CRC field */
6895 if (is_cck_rate(rspec[1])) {
6896 txh->FragPLCPFallback[4] = phylen & 0xff;
6897 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6898 }
6899
6900 /* MIMO-RATE: need validation ?? */
6901 mainrates = is_ofdm_rate(rspec[0]) ?
6902 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6903 plcp[0];
6904
6905 /* DUR field for main rate */
6906 if (!ieee80211_is_pspoll(h->frame_control) &&
6907 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6908 durid =
6909 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6910 next_frag_len);
6911 h->duration_id = cpu_to_le16(durid);
6912 } else if (use_rifs) {
6913 /* NAV protect to end of next max packet size */
6914 durid =
6915 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6916 preamble_type[0],
6917 DOT11_MAX_FRAG_LEN);
6918 durid += RIFS_11N_TIME;
6919 h->duration_id = cpu_to_le16(durid);
6920 }
6921
6922 /* DUR field for fallback rate */
6923 if (ieee80211_is_pspoll(h->frame_control))
6924 txh->FragDurFallback = h->duration_id;
6925 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6926 txh->FragDurFallback = 0;
6927 else {
6928 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6929 preamble_type[1], next_frag_len);
6930 txh->FragDurFallback = cpu_to_le16(durid);
6931 }
6932
6933 /* (4) MAC-HDR: MacTxControlLow */
6934 if (frag == 0)
6935 mcl |= TXC_STARTMSDU;
6936
6937 if (!is_multicast_ether_addr(h->addr1))
6938 mcl |= TXC_IMMEDACK;
6939
6940 if (wlc->band->bandtype == BRCM_BAND_5G)
6941 mcl |= TXC_FREQBAND_5G;
6942
6943 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6944 mcl |= TXC_BW_40;
6945
6946 /* set AMIC bit if using hardware TKIP MIC */
6947 if (hwtkmic)
6948 mcl |= TXC_AMIC;
6949
6950 txh->MacTxControlLow = cpu_to_le16(mcl);
6951
6952 /* MacTxControlHigh */
6953 mch = 0;
6954
6955 /* Set fallback rate preamble type */
6956 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6957 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6958 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6959 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6960 }
6961
6962 /* MacFrameControl */
6963 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6964 txh->TxFesTimeNormal = cpu_to_le16(0);
6965
6966 txh->TxFesTimeFallback = cpu_to_le16(0);
6967
6968 /* TxFrameRA */
6969 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6970
6971 /* TxFrameID */
6972 txh->TxFrameID = cpu_to_le16(frameid);
6973
6974 /*
6975 * TxStatus, Note the case of recreating the first frag of a suppressed
6976 * frame then we may need to reset the retry cnt's via the status reg
6977 */
6978 txh->TxStatus = cpu_to_le16(status);
6979
6980 /*
6981 * extra fields for ucode AMPDU aggregation, the new fields are added to
6982 * the END of previous structure so that it's compatible in driver.
6983 */
6984 txh->MaxNMpdus = cpu_to_le16(0);
6985 txh->MaxABytes_MRT = cpu_to_le16(0);
6986 txh->MaxABytes_FBR = cpu_to_le16(0);
6987 txh->MinMBytes = cpu_to_le16(0);
6988
6989 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6990 * furnish struct d11txh */
6991 /* RTS PLCP header and RTS frame */
6992 if (use_rts || use_cts) {
6993 if (use_rts && use_cts)
6994 use_cts = false;
6995
6996 for (k = 0; k < 2; k++) {
6997 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6998 false,
6999 mimo_ctlchbw);
7000 }
7001
7002 if (!is_ofdm_rate(rts_rspec[0]) &&
7003 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
7004 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
7005 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
7006 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
7007 }
7008
7009 if (!is_ofdm_rate(rts_rspec[1]) &&
7010 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
7011 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
7012 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
7013 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
7014 }
7015
7016 /* RTS/CTS additions to MacTxControlLow */
7017 if (use_cts) {
7018 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
7019 } else {
7020 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
7021 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
7022 }
7023
7024 /* RTS PLCP header */
7025 rts_plcp = txh->RTSPhyHeader;
7026 if (use_cts)
7027 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
7028 else
7029 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
7030
7031 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
7032
7033 /* fallback rate version of RTS PLCP header */
7034 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
7035 rts_plcp_fallback);
7036 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
7037 sizeof(txh->RTSPLCPFallback));
7038
7039 /* RTS frame fields... */
7040 rts = (struct ieee80211_rts *)&txh->rts_frame;
7041
7042 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
7043 rspec[0], rts_preamble_type[0],
7044 preamble_type[0], phylen, false);
7045 rts->duration = cpu_to_le16(durid);
7046 /* fallback rate version of RTS DUR field */
7047 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
7048 rts_rspec[1], rspec[1],
7049 rts_preamble_type[1],
7050 preamble_type[1], phylen, false);
7051 txh->RTSDurFallback = cpu_to_le16(durid);
7052
7053 if (use_cts) {
7054 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7055 IEEE80211_STYPE_CTS);
7056
7057 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
7058 } else {
7059 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7060 IEEE80211_STYPE_RTS);
7061
7062 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
7063 }
7064
7065 /* mainrate
7066 * low 8 bits: main frag rate/mcs,
7067 * high 8 bits: rts/cts rate/mcs
7068 */
7069 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
7070 D11A_PHY_HDR_GRATE(
7071 (struct ofdm_phy_hdr *) rts_plcp) :
7072 rts_plcp[0]) << 8;
7073 } else {
7074 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
7075 memset((char *)&txh->rts_frame, 0,
7076 sizeof(struct ieee80211_rts));
7077 memset((char *)txh->RTSPLCPFallback, 0,
7078 sizeof(txh->RTSPLCPFallback));
7079 txh->RTSDurFallback = 0;
7080 }
7081
7082 #ifdef SUPPORT_40MHZ
7083 /* add null delimiter count */
7084 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
7085 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
7086 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
7087
7088 #endif
7089
7090 /*
7091 * Now that RTS/RTS FB preamble types are updated, write
7092 * the final value
7093 */
7094 txh->MacTxControlHigh = cpu_to_le16(mch);
7095
7096 /*
7097 * MainRates (both the rts and frag plcp rates have
7098 * been calculated now)
7099 */
7100 txh->MainRates = cpu_to_le16(mainrates);
7101
7102 /* XtraFrameTypes */
7103 xfts = frametype(rspec[1], wlc->mimoft);
7104 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
7105 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
7106 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
7107 XFTS_CHANNEL_SHIFT;
7108 txh->XtraFrameTypes = cpu_to_le16(xfts);
7109
7110 /* PhyTxControlWord */
7111 phyctl = frametype(rspec[0], wlc->mimoft);
7112 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
7113 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
7114 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
7115 phyctl |= PHY_TXC_SHORT_HDR;
7116 }
7117
7118 /* phytxant is properly bit shifted */
7119 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
7120 txh->PhyTxControlWord = cpu_to_le16(phyctl);
7121
7122 /* PhyTxControlWord_1 */
7123 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7124 u16 phyctl1 = 0;
7125
7126 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
7127 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
7128 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
7129 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
7130
7131 if (use_rts || use_cts) {
7132 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
7133 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
7134 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
7135 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
7136 }
7137
7138 /*
7139 * For mcs frames, if mixedmode(overloaded with long preamble)
7140 * is going to be set, fill in non-zero MModeLen and/or
7141 * MModeFbrLen it will be unnecessary if they are separated
7142 */
7143 if (is_mcs_rate(rspec[0]) &&
7144 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
7145 u16 mmodelen =
7146 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
7147 txh->MModeLen = cpu_to_le16(mmodelen);
7148 }
7149
7150 if (is_mcs_rate(rspec[1]) &&
7151 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
7152 u16 mmodefbrlen =
7153 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
7154 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
7155 }
7156 }
7157
7158 ac = skb_get_queue_mapping(p);
7159 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
7160 uint frag_dur, dur, dur_fallback;
7161
7162 /* WME: Update TXOP threshold */
7163 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
7164 frag_dur =
7165 brcms_c_calc_frame_time(wlc, rspec[0],
7166 preamble_type[0], phylen);
7167
7168 if (rts) {
7169 /* 1 RTS or CTS-to-self frame */
7170 dur =
7171 brcms_c_calc_cts_time(wlc, rts_rspec[0],
7172 rts_preamble_type[0]);
7173 dur_fallback =
7174 brcms_c_calc_cts_time(wlc, rts_rspec[1],
7175 rts_preamble_type[1]);
7176 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7177 dur += le16_to_cpu(rts->duration);
7178 dur_fallback +=
7179 le16_to_cpu(txh->RTSDurFallback);
7180 } else if (use_rifs) {
7181 dur = frag_dur;
7182 dur_fallback = 0;
7183 } else {
7184 /* frame + SIFS + ACK */
7185 dur = frag_dur;
7186 dur +=
7187 brcms_c_compute_frame_dur(wlc, rspec[0],
7188 preamble_type[0], 0);
7189
7190 dur_fallback =
7191 brcms_c_calc_frame_time(wlc, rspec[1],
7192 preamble_type[1],
7193 phylen);
7194 dur_fallback +=
7195 brcms_c_compute_frame_dur(wlc, rspec[1],
7196 preamble_type[1], 0);
7197 }
7198 /* NEED to set TxFesTimeNormal (hard) */
7199 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
7200 /*
7201 * NEED to set fallback rate version of
7202 * TxFesTimeNormal (hard)
7203 */
7204 txh->TxFesTimeFallback =
7205 cpu_to_le16((u16) dur_fallback);
7206
7207 /*
7208 * update txop byte threshold (txop minus intraframe
7209 * overhead)
7210 */
7211 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
7212 uint newfragthresh;
7213
7214 newfragthresh =
7215 brcms_c_calc_frame_len(wlc,
7216 rspec[0], preamble_type[0],
7217 (wlc->edcf_txop[ac] -
7218 (dur - frag_dur)));
7219 /* range bound the fragthreshold */
7220 if (newfragthresh < DOT11_MIN_FRAG_LEN)
7221 newfragthresh =
7222 DOT11_MIN_FRAG_LEN;
7223 else if (newfragthresh >
7224 wlc->usr_fragthresh)
7225 newfragthresh =
7226 wlc->usr_fragthresh;
7227 /* update the fragthresh and do txc update */
7228 if (wlc->fragthresh[queue] !=
7229 (u16) newfragthresh)
7230 wlc->fragthresh[queue] =
7231 (u16) newfragthresh;
7232 } else {
7233 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
7234 "for rate %d\n",
7235 wlc->pub->unit, fifo_names[queue],
7236 rspec2rate(rspec[0]));
7237 }
7238
7239 if (dur > wlc->edcf_txop[ac])
7240 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
7241 "exceeded phylen %d/%d dur %d/%d\n",
7242 wlc->pub->unit, __func__,
7243 fifo_names[queue],
7244 phylen, wlc->fragthresh[queue],
7245 dur, wlc->edcf_txop[ac]);
7246 }
7247 }
7248
7249 return 0;
7250 }
7251
7252 void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
7253 struct ieee80211_hw *hw)
7254 {
7255 u8 prio;
7256 uint fifo;
7257 struct scb *scb = &wlc->pri_scb;
7258 struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
7259
7260 /*
7261 * 802.11 standard requires management traffic
7262 * to go at highest priority
7263 */
7264 prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
7265 MAXPRIO;
7266 fifo = prio2fifo[prio];
7267 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
7268 return;
7269 brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio));
7270 brcms_c_send_q(wlc);
7271 }
7272
7273 void brcms_c_send_q(struct brcms_c_info *wlc)
7274 {
7275 struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
7276 int prec;
7277 u16 prec_map;
7278 int err = 0, i, count;
7279 uint fifo;
7280 struct brcms_txq_info *qi = wlc->pkt_queue;
7281 struct pktq *q = &qi->q;
7282 struct ieee80211_tx_info *tx_info;
7283
7284 prec_map = wlc->tx_prec_map;
7285
7286 /* Send all the enq'd pkts that we can.
7287 * Dequeue packets with precedence with empty HW fifo only
7288 */
7289 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
7290 tx_info = IEEE80211_SKB_CB(pkt[0]);
7291 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
7292 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
7293 } else {
7294 count = 1;
7295 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
7296 if (!err) {
7297 for (i = 0; i < count; i++)
7298 brcms_c_txfifo(wlc, fifo, pkt[i], true,
7299 1);
7300 }
7301 }
7302
7303 if (err == -EBUSY) {
7304 brcmu_pktq_penq_head(q, prec, pkt[0]);
7305 /*
7306 * If send failed due to any other reason than a
7307 * change in HW FIFO condition, quit. Otherwise,
7308 * read the new prec_map!
7309 */
7310 if (prec_map == wlc->tx_prec_map)
7311 break;
7312 prec_map = wlc->tx_prec_map;
7313 }
7314 }
7315 }
7316
7317 void
7318 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
7319 bool commit, s8 txpktpend)
7320 {
7321 u16 frameid = INVALIDFID;
7322 struct d11txh *txh;
7323
7324 txh = (struct d11txh *) (p->data);
7325
7326 /* When a BC/MC frame is being committed to the BCMC fifo
7327 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7328 */
7329 if (fifo == TX_BCMC_FIFO)
7330 frameid = le16_to_cpu(txh->TxFrameID);
7331
7332 /*
7333 * Bump up pending count for if not using rpc. If rpc is
7334 * used, this will be handled in brcms_b_txfifo()
7335 */
7336 if (commit) {
7337 wlc->core->txpktpend[fifo] += txpktpend;
7338 BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
7339 txpktpend, wlc->core->txpktpend[fifo]);
7340 }
7341
7342 /* Commit BCMC sequence number in the SHM frame ID location */
7343 if (frameid != INVALIDFID) {
7344 /*
7345 * To inform the ucode of the last mcast frame posted
7346 * so that it can clear moredata bit
7347 */
7348 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
7349 }
7350
7351 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
7352 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
7353 }
7354
7355 u32
7356 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7357 bool use_rspec, u16 mimo_ctlchbw)
7358 {
7359 u32 rts_rspec = 0;
7360
7361 if (use_rspec)
7362 /* use frame rate as rts rate */
7363 rts_rspec = rspec;
7364 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7365 /* Use 11Mbps as the g protection RTS target rate and fallback.
7366 * Use the brcms_basic_rate() lookup to find the best basic rate
7367 * under the target in case 11 Mbps is not Basic.
7368 * 6 and 9 Mbps are not usually selected by rate selection, but
7369 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7370 * is more robust.
7371 */
7372 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7373 else
7374 /* calculate RTS rate and fallback rate based on the frame rate
7375 * RTS must be sent at a basic rate since it is a
7376 * control frame, sec 9.6 of 802.11 spec
7377 */
7378 rts_rspec = brcms_basic_rate(wlc, rspec);
7379
7380 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7381 /* set rts txbw to correct side band */
7382 rts_rspec &= ~RSPEC_BW_MASK;
7383
7384 /*
7385 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7386 * 20MHz channel (DUP), otherwise send RTS on control channel
7387 */
7388 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7389 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7390 else
7391 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7392
7393 /* pick siso/cdd as default for ofdm */
7394 if (is_ofdm_rate(rts_rspec)) {
7395 rts_rspec &= ~RSPEC_STF_MASK;
7396 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7397 }
7398 }
7399 return rts_rspec;
7400 }
7401
7402 void
7403 brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend)
7404 {
7405 wlc->core->txpktpend[fifo] -= txpktpend;
7406 BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
7407 wlc->core->txpktpend[fifo]);
7408
7409 /* There is more room; mark precedences related to this FIFO sendable */
7410 wlc->tx_prec_map |= wlc->fifo2prec_map[fifo];
7411
7412 /* figure out which bsscfg is being worked on... */
7413 }
7414
7415 /* Update beacon listen interval in shared memory */
7416 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7417 {
7418 /* wake up every DTIM is the default */
7419 if (wlc->bcn_li_dtim == 1)
7420 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7421 else
7422 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7423 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7424 }
7425
7426 static void
7427 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7428 u32 *tsf_h_ptr)
7429 {
7430 struct bcma_device *core = wlc_hw->d11core;
7431
7432 /* read the tsf timer low, then high to get an atomic read */
7433 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7434 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7435 }
7436
7437 /*
7438 * recover 64bit TSF value from the 16bit TSF value in the rx header
7439 * given the assumption that the TSF passed in header is within 65ms
7440 * of the current tsf.
7441 *
7442 * 6 5 4 4 3 2 1
7443 * 3.......6.......8.......0.......2.......4.......6.......8......0
7444 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7445 *
7446 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7447 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7448 * receive call sequence after rx interrupt. Only the higher 16 bits
7449 * are used. Finally, the tsf_h is read from the tsf register.
7450 */
7451 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7452 struct d11rxhdr *rxh)
7453 {
7454 u32 tsf_h, tsf_l;
7455 u16 rx_tsf_0_15, rx_tsf_16_31;
7456
7457 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7458
7459 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7460 rx_tsf_0_15 = rxh->RxTSFTime;
7461
7462 /*
7463 * a greater tsf time indicates the low 16 bits of
7464 * tsf_l wrapped, so decrement the high 16 bits.
7465 */
7466 if ((u16)tsf_l < rx_tsf_0_15) {
7467 rx_tsf_16_31 -= 1;
7468 if (rx_tsf_16_31 == 0xffff)
7469 tsf_h -= 1;
7470 }
7471
7472 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7473 }
7474
7475 static void
7476 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7477 struct sk_buff *p,
7478 struct ieee80211_rx_status *rx_status)
7479 {
7480 int preamble;
7481 int channel;
7482 u32 rspec;
7483 unsigned char *plcp;
7484
7485 /* fill in TSF and flag its presence */
7486 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7487 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
7488
7489 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7490
7491 if (channel > 14) {
7492 rx_status->band = IEEE80211_BAND_5GHZ;
7493 rx_status->freq = ieee80211_ofdm_chan_to_freq(
7494 WF_CHAN_FACTOR_5_G/2, channel);
7495
7496 } else {
7497 rx_status->band = IEEE80211_BAND_2GHZ;
7498 rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
7499 }
7500
7501 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7502
7503 /* noise */
7504 /* qual */
7505 rx_status->antenna =
7506 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7507
7508 plcp = p->data;
7509
7510 rspec = brcms_c_compute_rspec(rxh, plcp);
7511 if (is_mcs_rate(rspec)) {
7512 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7513 rx_status->flag |= RX_FLAG_HT;
7514 if (rspec_is40mhz(rspec))
7515 rx_status->flag |= RX_FLAG_40MHZ;
7516 } else {
7517 switch (rspec2rate(rspec)) {
7518 case BRCM_RATE_1M:
7519 rx_status->rate_idx = 0;
7520 break;
7521 case BRCM_RATE_2M:
7522 rx_status->rate_idx = 1;
7523 break;
7524 case BRCM_RATE_5M5:
7525 rx_status->rate_idx = 2;
7526 break;
7527 case BRCM_RATE_11M:
7528 rx_status->rate_idx = 3;
7529 break;
7530 case BRCM_RATE_6M:
7531 rx_status->rate_idx = 4;
7532 break;
7533 case BRCM_RATE_9M:
7534 rx_status->rate_idx = 5;
7535 break;
7536 case BRCM_RATE_12M:
7537 rx_status->rate_idx = 6;
7538 break;
7539 case BRCM_RATE_18M:
7540 rx_status->rate_idx = 7;
7541 break;
7542 case BRCM_RATE_24M:
7543 rx_status->rate_idx = 8;
7544 break;
7545 case BRCM_RATE_36M:
7546 rx_status->rate_idx = 9;
7547 break;
7548 case BRCM_RATE_48M:
7549 rx_status->rate_idx = 10;
7550 break;
7551 case BRCM_RATE_54M:
7552 rx_status->rate_idx = 11;
7553 break;
7554 default:
7555 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
7556 }
7557
7558 /*
7559 * For 5GHz, we should decrease the index as it is
7560 * a subset of the 2.4G rates. See bitrates field
7561 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7562 */
7563 if (rx_status->band == IEEE80211_BAND_5GHZ)
7564 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7565
7566 /* Determine short preamble and rate_idx */
7567 preamble = 0;
7568 if (is_cck_rate(rspec)) {
7569 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7570 rx_status->flag |= RX_FLAG_SHORTPRE;
7571 } else if (is_ofdm_rate(rspec)) {
7572 rx_status->flag |= RX_FLAG_SHORTPRE;
7573 } else {
7574 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
7575 __func__);
7576 }
7577 }
7578
7579 if (plcp3_issgi(plcp[3]))
7580 rx_status->flag |= RX_FLAG_SHORT_GI;
7581
7582 if (rxh->RxStatus1 & RXS_DECERR) {
7583 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7584 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7585 __func__);
7586 }
7587 if (rxh->RxStatus1 & RXS_FCSERR) {
7588 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7589 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7590 __func__);
7591 }
7592 }
7593
7594 static void
7595 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7596 struct sk_buff *p)
7597 {
7598 int len_mpdu;
7599 struct ieee80211_rx_status rx_status;
7600 struct ieee80211_hdr *hdr;
7601
7602 memset(&rx_status, 0, sizeof(rx_status));
7603 prep_mac80211_status(wlc, rxh, p, &rx_status);
7604
7605 /* mac header+body length, exclude CRC and plcp header */
7606 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7607 skb_pull(p, D11_PHY_HDR_LEN);
7608 __skb_trim(p, len_mpdu);
7609
7610 /* unmute transmit */
7611 if (wlc->hw->suspended_fifos) {
7612 hdr = (struct ieee80211_hdr *)p->data;
7613 if (ieee80211_is_beacon(hdr->frame_control))
7614 brcms_b_mute(wlc->hw, false);
7615 }
7616
7617 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7618 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7619 }
7620
7621 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7622 * number of bytes goes in the length field
7623 *
7624 * Formula given by HT PHY Spec v 1.13
7625 * len = 3(nsyms + nstream + 3) - 3
7626 */
7627 u16
7628 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7629 uint mac_len)
7630 {
7631 uint nsyms, len = 0, kNdps;
7632
7633 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
7634 wlc->pub->unit, rspec2rate(ratespec), mac_len);
7635
7636 if (is_mcs_rate(ratespec)) {
7637 uint mcs = ratespec & RSPEC_RATE_MASK;
7638 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7639 rspec_stc(ratespec);
7640
7641 /*
7642 * the payload duration calculation matches that
7643 * of regular ofdm
7644 */
7645 /* 1000Ndbps = kbps * 4 */
7646 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7647 rspec_issgi(ratespec)) * 4;
7648
7649 if (rspec_stc(ratespec) == 0)
7650 nsyms =
7651 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7652 APHY_TAIL_NBITS) * 1000, kNdps);
7653 else
7654 /* STBC needs to have even number of symbols */
7655 nsyms =
7656 2 *
7657 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7658 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7659
7660 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7661 nsyms += (tot_streams + 3);
7662 /*
7663 * 3 bytes/symbol @ legacy 6Mbps rate
7664 * (-3) excluding service bits and tail bits
7665 */
7666 len = (3 * nsyms) - 3;
7667 }
7668
7669 return (u16) len;
7670 }
7671
7672 static void
7673 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7674 {
7675 const struct brcms_c_rateset *rs_dflt;
7676 struct brcms_c_rateset rs;
7677 u8 rate;
7678 u16 entry_ptr;
7679 u8 plcp[D11_PHY_HDR_LEN];
7680 u16 dur, sifs;
7681 uint i;
7682
7683 sifs = get_sifs(wlc->band);
7684
7685 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7686
7687 brcms_c_rateset_copy(rs_dflt, &rs);
7688 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7689
7690 /*
7691 * walk the phy rate table and update MAC core SHM
7692 * basic rate table entries
7693 */
7694 for (i = 0; i < rs.count; i++) {
7695 rate = rs.rates[i] & BRCMS_RATE_MASK;
7696
7697 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7698
7699 /* Calculate the Probe Response PLCP for the given rate */
7700 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7701
7702 /*
7703 * Calculate the duration of the Probe Response
7704 * frame plus SIFS for the MAC
7705 */
7706 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7707 BRCMS_LONG_PREAMBLE, frame_len);
7708 dur += sifs;
7709
7710 /* Update the SHM Rate Table entry Probe Response values */
7711 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7712 (u16) (plcp[0] + (plcp[1] << 8)));
7713 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7714 (u16) (plcp[2] + (plcp[3] << 8)));
7715 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7716 }
7717 }
7718
7719 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7720 *
7721 * PLCP header is 6 bytes.
7722 * 802.11 A3 header is 24 bytes.
7723 * Max beacon frame body template length is 112 bytes.
7724 * Max probe resp frame body template length is 110 bytes.
7725 *
7726 * *len on input contains the max length of the packet available.
7727 *
7728 * The *len value is set to the number of bytes in buf used, and starts
7729 * with the PLCP and included up to, but not including, the 4 byte FCS.
7730 */
7731 static void
7732 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7733 u32 bcn_rspec,
7734 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7735 {
7736 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7737 struct cck_phy_hdr *plcp;
7738 struct ieee80211_mgmt *h;
7739 int hdr_len, body_len;
7740
7741 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7742
7743 /* calc buffer size provided for frame body */
7744 body_len = *len - hdr_len;
7745 /* return actual size */
7746 *len = hdr_len + body_len;
7747
7748 /* format PHY and MAC headers */
7749 memset((char *)buf, 0, hdr_len);
7750
7751 plcp = (struct cck_phy_hdr *) buf;
7752
7753 /*
7754 * PLCP for Probe Response frames are filled in from
7755 * core's rate table
7756 */
7757 if (type == IEEE80211_STYPE_BEACON)
7758 /* fill in PLCP */
7759 brcms_c_compute_plcp(wlc, bcn_rspec,
7760 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7761 (u8 *) plcp);
7762
7763 /* "Regular" and 16 MBSS but not for 4 MBSS */
7764 /* Update the phytxctl for the beacon based on the rspec */
7765 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7766
7767 h = (struct ieee80211_mgmt *)&plcp[1];
7768
7769 /* fill in 802.11 header */
7770 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7771
7772 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7773 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7774 if (type == IEEE80211_STYPE_BEACON)
7775 memcpy(&h->da, &ether_bcast, ETH_ALEN);
7776 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7777 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7778
7779 /* SEQ filled in by MAC */
7780 }
7781
7782 int brcms_c_get_header_len(void)
7783 {
7784 return TXOFF;
7785 }
7786
7787 /*
7788 * Update all beacons for the system.
7789 */
7790 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7791 {
7792 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7793
7794 if (bsscfg->up && !bsscfg->BSS)
7795 /* Clear the soft intmask */
7796 wlc->defmacintmask &= ~MI_BCNTPL;
7797 }
7798
7799 /* Write ssid into shared memory */
7800 static void
7801 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7802 {
7803 u8 *ssidptr = cfg->SSID;
7804 u16 base = M_SSID;
7805 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7806
7807 /* padding the ssid with zero and copy it into shm */
7808 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7809 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7810
7811 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7812 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7813 }
7814
7815 static void
7816 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7817 struct brcms_bss_cfg *cfg,
7818 bool suspend)
7819 {
7820 u16 prb_resp[BCN_TMPL_LEN / 2];
7821 int len = BCN_TMPL_LEN;
7822
7823 /*
7824 * write the probe response to hardware, or save in
7825 * the config structure
7826 */
7827
7828 /* create the probe response template */
7829 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7830 cfg, prb_resp, &len);
7831
7832 if (suspend)
7833 brcms_c_suspend_mac_and_wait(wlc);
7834
7835 /* write the probe response into the template region */
7836 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7837 (len + 3) & ~3, prb_resp);
7838
7839 /* write the length of the probe response frame (+PLCP/-FCS) */
7840 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7841
7842 /* write the SSID and SSID length */
7843 brcms_c_shm_ssid_upd(wlc, cfg);
7844
7845 /*
7846 * Write PLCP headers and durations for probe response frames
7847 * at all rates. Use the actual frame length covered by the
7848 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7849 * by subtracting the PLCP len and adding the FCS.
7850 */
7851 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7852 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7853
7854 if (suspend)
7855 brcms_c_enable_mac(wlc);
7856 }
7857
7858 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7859 {
7860 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7861
7862 /* update AP or IBSS probe responses */
7863 if (bsscfg->up && !bsscfg->BSS)
7864 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7865 }
7866
7867 /* prepares pdu for transmission. returns BCM error codes */
7868 int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
7869 {
7870 uint fifo;
7871 struct d11txh *txh;
7872 struct ieee80211_hdr *h;
7873 struct scb *scb;
7874
7875 txh = (struct d11txh *) (pdu->data);
7876 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
7877
7878 /* get the pkt queue info. This was put at brcms_c_sendctl or
7879 * brcms_c_send for PDU */
7880 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
7881
7882 scb = NULL;
7883
7884 *fifop = fifo;
7885
7886 /* return if insufficient dma resources */
7887 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
7888 /* Mark precedences related to this FIFO, unsendable */
7889 /* A fifo is full. Clear precedences related to that FIFO */
7890 wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]);
7891 return -EBUSY;
7892 }
7893 return 0;
7894 }
7895
7896 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7897 uint *blocks)
7898 {
7899 if (fifo >= NFIFO)
7900 return -EINVAL;
7901
7902 *blocks = wlc_hw->xmtfifo_sz[fifo];
7903
7904 return 0;
7905 }
7906
7907 void
7908 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7909 const u8 *addr)
7910 {
7911 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7912 if (match_reg_offset == RCM_BSSID_OFFSET)
7913 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7914 }
7915
7916 /*
7917 * Flag 'scan in progress' to withhold dynamic phy calibration
7918 */
7919 void brcms_c_scan_start(struct brcms_c_info *wlc)
7920 {
7921 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7922 }
7923
7924 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7925 {
7926 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7927 }
7928
7929 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7930 {
7931 wlc->pub->associated = state;
7932 wlc->bsscfg->associated = state;
7933 }
7934
7935 /*
7936 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7937 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7938 * when later on hardware releases them, they can be handled appropriately.
7939 */
7940 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7941 struct ieee80211_sta *sta,
7942 void (*dma_callback_fn))
7943 {
7944 struct dma_pub *dmah;
7945 int i;
7946 for (i = 0; i < NFIFO; i++) {
7947 dmah = hw->di[i];
7948 if (dmah != NULL)
7949 dma_walk_packets(dmah, dma_callback_fn, sta);
7950 }
7951 }
7952
7953 int brcms_c_get_curband(struct brcms_c_info *wlc)
7954 {
7955 return wlc->band->bandunit;
7956 }
7957
7958 void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7959 {
7960 int timeout = 20;
7961
7962 /* flush packet queue when requested */
7963 if (drop)
7964 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
7965
7966 /* wait for queue and DMA fifos to run dry */
7967 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0) {
7968 brcms_msleep(wlc->wl, 1);
7969
7970 if (--timeout == 0)
7971 break;
7972 }
7973
7974 WARN_ON_ONCE(timeout == 0);
7975 }
7976
7977 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7978 {
7979 wlc->bcn_li_bcn = interval;
7980 if (wlc->pub->up)
7981 brcms_c_bcn_li_upd(wlc);
7982 }
7983
7984 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7985 {
7986 uint qdbm;
7987
7988 /* Remove override bit and clip to max qdbm value */
7989 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7990 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7991 }
7992
7993 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7994 {
7995 uint qdbm;
7996 bool override;
7997
7998 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7999
8000 /* Return qdbm units */
8001 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
8002 }
8003
8004 /* Process received frames */
8005 /*
8006 * Return true if more frames need to be processed. false otherwise.
8007 * Param 'bound' indicates max. # frames to process before break out.
8008 */
8009 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
8010 {
8011 struct d11rxhdr *rxh;
8012 struct ieee80211_hdr *h;
8013 uint len;
8014 bool is_amsdu;
8015
8016 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8017
8018 /* frame starts with rxhdr */
8019 rxh = (struct d11rxhdr *) (p->data);
8020
8021 /* strip off rxhdr */
8022 skb_pull(p, BRCMS_HWRXOFF);
8023
8024 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
8025 if (rxh->RxStatus1 & RXS_PBPRES) {
8026 if (p->len < 2) {
8027 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
8028 "len %d\n", wlc->pub->unit, p->len);
8029 goto toss;
8030 }
8031 skb_pull(p, 2);
8032 }
8033
8034 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
8035 len = p->len;
8036
8037 if (rxh->RxStatus1 & RXS_FCSERR) {
8038 if (!(wlc->filter_flags & FIF_FCSFAIL))
8039 goto toss;
8040 }
8041
8042 /* check received pkt has at least frame control field */
8043 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
8044 goto toss;
8045
8046 /* not supporting A-MSDU */
8047 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
8048 if (is_amsdu)
8049 goto toss;
8050
8051 brcms_c_recvctl(wlc, rxh, p);
8052 return;
8053
8054 toss:
8055 brcmu_pkt_buf_free_skb(p);
8056 }
8057
8058 /* Process received frames */
8059 /*
8060 * Return true if more frames need to be processed. false otherwise.
8061 * Param 'bound' indicates max. # frames to process before break out.
8062 */
8063 static bool
8064 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
8065 {
8066 struct sk_buff *p;
8067 struct sk_buff *next = NULL;
8068 struct sk_buff_head recv_frames;
8069
8070 uint n = 0;
8071 uint bound_limit = bound ? RXBND : -1;
8072
8073 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
8074 skb_queue_head_init(&recv_frames);
8075
8076 /* gather received frames */
8077 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
8078
8079 /* !give others some time to run! */
8080 if (++n >= bound_limit)
8081 break;
8082 }
8083
8084 /* post more rbufs */
8085 dma_rxfill(wlc_hw->di[fifo]);
8086
8087 /* process each frame */
8088 skb_queue_walk_safe(&recv_frames, p, next) {
8089 struct d11rxhdr_le *rxh_le;
8090 struct d11rxhdr *rxh;
8091
8092 skb_unlink(p, &recv_frames);
8093 rxh_le = (struct d11rxhdr_le *)p->data;
8094 rxh = (struct d11rxhdr *)p->data;
8095
8096 /* fixup rx header endianness */
8097 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
8098 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
8099 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
8100 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
8101 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
8102 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
8103 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
8104 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
8105 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
8106 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
8107 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
8108
8109 brcms_c_recv(wlc_hw->wlc, p);
8110 }
8111
8112 return n >= bound_limit;
8113 }
8114
8115 /* second-level interrupt processing
8116 * Return true if another dpc needs to be re-scheduled. false otherwise.
8117 * Param 'bounded' indicates if applicable loops should be bounded.
8118 */
8119 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8120 {
8121 u32 macintstatus;
8122 struct brcms_hardware *wlc_hw = wlc->hw;
8123 struct bcma_device *core = wlc_hw->d11core;
8124 struct wiphy *wiphy = wlc->wiphy;
8125
8126 if (brcms_deviceremoved(wlc)) {
8127 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
8128 __func__);
8129 brcms_down(wlc->wl);
8130 return false;
8131 }
8132
8133 /* grab and clear the saved software intstatus bits */
8134 macintstatus = wlc->macintstatus;
8135 wlc->macintstatus = 0;
8136
8137 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
8138 wlc_hw->unit, macintstatus);
8139
8140 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
8141
8142 /* tx status */
8143 if (macintstatus & MI_TFS) {
8144 bool fatal;
8145 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
8146 wlc->macintstatus |= MI_TFS;
8147 if (fatal) {
8148 wiphy_err(wiphy, "MI_TFS: fatal\n");
8149 goto fatal;
8150 }
8151 }
8152
8153 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
8154 brcms_c_tbtt(wlc);
8155
8156 /* ATIM window end */
8157 if (macintstatus & MI_ATIMWINEND) {
8158 BCMMSG(wlc->wiphy, "end of ATIM window\n");
8159 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
8160 wlc->qvalid = 0;
8161 }
8162
8163 /*
8164 * received data or control frame, MI_DMAINT is
8165 * indication of RX_FIFO interrupt
8166 */
8167 if (macintstatus & MI_DMAINT)
8168 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
8169 wlc->macintstatus |= MI_DMAINT;
8170
8171 /* noise sample collected */
8172 if (macintstatus & MI_BG_NOISE)
8173 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
8174
8175 if (macintstatus & MI_GP0) {
8176 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
8177 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
8178
8179 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
8180 __func__, ai_get_chip_id(wlc_hw->sih),
8181 ai_get_chiprev(wlc_hw->sih));
8182 brcms_fatal_error(wlc_hw->wlc->wl);
8183 }
8184
8185 /* gptimer timeout */
8186 if (macintstatus & MI_TO)
8187 bcma_write32(core, D11REGOFFS(gptimer), 0);
8188
8189 if (macintstatus & MI_RFDISABLE) {
8190 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
8191 " RF Disable Input\n", wlc_hw->unit);
8192 brcms_rfkill_set_hw_state(wlc->wl);
8193 }
8194
8195 /* send any enq'd tx packets. Just makes sure to jump start tx */
8196 if (!pktq_empty(&wlc->pkt_queue->q))
8197 brcms_c_send_q(wlc);
8198
8199 /* it isn't done and needs to be resched if macintstatus is non-zero */
8200 return wlc->macintstatus != 0;
8201
8202 fatal:
8203 brcms_fatal_error(wlc_hw->wlc->wl);
8204 return wlc->macintstatus != 0;
8205 }
8206
8207 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8208 {
8209 struct bcma_device *core = wlc->hw->d11core;
8210 u16 chanspec;
8211
8212 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8213
8214 /*
8215 * This will happen if a big-hammer was executed. In
8216 * that case, we want to go back to the channel that
8217 * we were on and not new channel
8218 */
8219 if (wlc->pub->associated)
8220 chanspec = wlc->home_chanspec;
8221 else
8222 chanspec = brcms_c_init_chanspec(wlc);
8223
8224 brcms_b_init(wlc->hw, chanspec);
8225
8226 /* update beacon listen interval */
8227 brcms_c_bcn_li_upd(wlc);
8228
8229 /* write ethernet address to core */
8230 brcms_c_set_mac(wlc->bsscfg);
8231 brcms_c_set_bssid(wlc->bsscfg);
8232
8233 /* Update tsf_cfprep if associated and up */
8234 if (wlc->pub->associated && wlc->bsscfg->up) {
8235 u32 bi;
8236
8237 /* get beacon period and convert to uS */
8238 bi = wlc->bsscfg->current_bss->beacon_period << 10;
8239 /*
8240 * update since init path would reset
8241 * to default value
8242 */
8243 bcma_write32(core, D11REGOFFS(tsf_cfprep),
8244 bi << CFPREP_CBI_SHIFT);
8245
8246 /* Update maccontrol PM related bits */
8247 brcms_c_set_ps_ctrl(wlc);
8248 }
8249
8250 brcms_c_bandinit_ordered(wlc, chanspec);
8251
8252 /* init probe response timeout */
8253 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
8254
8255 /* init max burst txop (framebursting) */
8256 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
8257 (wlc->
8258 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
8259
8260 /* initialize maximum allowed duty cycle */
8261 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
8262 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
8263
8264 /*
8265 * Update some shared memory locations related to
8266 * max AMPDU size allowed to received
8267 */
8268 brcms_c_ampdu_shm_upd(wlc->ampdu);
8269
8270 /* band-specific inits */
8271 brcms_c_bsinit(wlc);
8272
8273 /* Enable EDCF mode (while the MAC is suspended) */
8274 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
8275 brcms_c_edcf_setparams(wlc, false);
8276
8277 /* Init precedence maps for empty FIFOs */
8278 brcms_c_tx_prec_map_init(wlc);
8279
8280 /* read the ucode version if we have not yet done so */
8281 if (wlc->ucode_rev == 0) {
8282 wlc->ucode_rev =
8283 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
8284 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
8285 }
8286
8287 /* ..now really unleash hell (allow the MAC out of suspend) */
8288 brcms_c_enable_mac(wlc);
8289
8290 /* suspend the tx fifos and mute the phy for preism cac time */
8291 if (mute_tx)
8292 brcms_b_mute(wlc->hw, true);
8293
8294 /* clear tx flow control */
8295 brcms_c_txflowcontrol_reset(wlc);
8296
8297 /* enable the RF Disable Delay timer */
8298 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8299
8300 /*
8301 * Initialize WME parameters; if they haven't been set by some other
8302 * mechanism (IOVar, etc) then read them from the hardware.
8303 */
8304 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8305 /* Uninitialized; read from HW */
8306 int ac;
8307
8308 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8309 wlc->wme_retries[ac] =
8310 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8311 }
8312 }
8313
8314 /*
8315 * The common driver entry routine. Error codes should be unique
8316 */
8317 struct brcms_c_info *
8318 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8319 bool piomode, uint *perr)
8320 {
8321 struct brcms_c_info *wlc;
8322 uint err = 0;
8323 uint i, j;
8324 struct brcms_pub *pub;
8325
8326 /* allocate struct brcms_c_info state and its substructures */
8327 wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, 0);
8328 if (wlc == NULL)
8329 goto fail;
8330 wlc->wiphy = wl->wiphy;
8331 pub = wlc->pub;
8332
8333 #if defined(DEBUG)
8334 wlc_info_dbg = wlc;
8335 #endif
8336
8337 wlc->band = wlc->bandstate[0];
8338 wlc->core = wlc->corestate;
8339 wlc->wl = wl;
8340 pub->unit = unit;
8341 pub->_piomode = piomode;
8342 wlc->bandinit_pending = false;
8343
8344 /* populate struct brcms_c_info with default values */
8345 brcms_c_info_init(wlc, unit);
8346
8347 /* update sta/ap related parameters */
8348 brcms_c_ap_upd(wlc);
8349
8350 /*
8351 * low level attach steps(all hw accesses go
8352 * inside, no more in rest of the attach)
8353 */
8354 err = brcms_b_attach(wlc, core, unit, piomode);
8355 if (err)
8356 goto fail;
8357
8358 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8359
8360 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8361
8362 /* disable allowed duty cycle */
8363 wlc->tx_duty_cycle_ofdm = 0;
8364 wlc->tx_duty_cycle_cck = 0;
8365
8366 brcms_c_stf_phy_chain_calc(wlc);
8367
8368 /* txchain 1: txant 0, txchain 2: txant 1 */
8369 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8370 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8371
8372 /* push to BMAC driver */
8373 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8374 wlc->stf->hw_rxchain);
8375
8376 /* pull up some info resulting from the low attach */
8377 for (i = 0; i < NFIFO; i++)
8378 wlc->core->txavail[i] = wlc->hw->txavail[i];
8379
8380 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8381 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8382
8383 for (j = 0; j < wlc->pub->_nbands; j++) {
8384 wlc->band = wlc->bandstate[j];
8385
8386 if (!brcms_c_attach_stf_ant_init(wlc)) {
8387 err = 24;
8388 goto fail;
8389 }
8390
8391 /* default contention windows size limits */
8392 wlc->band->CWmin = APHY_CWMIN;
8393 wlc->band->CWmax = PHY_CWMAX;
8394
8395 /* init gmode value */
8396 if (wlc->band->bandtype == BRCM_BAND_2G) {
8397 wlc->band->gmode = GMODE_AUTO;
8398 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8399 wlc->band->gmode);
8400 }
8401
8402 /* init _n_enab supported mode */
8403 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8404 pub->_n_enab = SUPPORT_11N;
8405 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8406 ((pub->_n_enab ==
8407 SUPPORT_11N) ? WL_11N_2x2 :
8408 WL_11N_3x3));
8409 }
8410
8411 /* init per-band default rateset, depend on band->gmode */
8412 brcms_default_rateset(wlc, &wlc->band->defrateset);
8413
8414 /* fill in hw_rateset */
8415 brcms_c_rateset_filter(&wlc->band->defrateset,
8416 &wlc->band->hw_rateset, false,
8417 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8418 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8419 }
8420
8421 /*
8422 * update antenna config due to
8423 * wlc->stf->txant/txchain/ant_rx_ovr change
8424 */
8425 brcms_c_stf_phy_txant_upd(wlc);
8426
8427 /* attach each modules */
8428 err = brcms_c_attach_module(wlc);
8429 if (err != 0)
8430 goto fail;
8431
8432 if (!brcms_c_timers_init(wlc, unit)) {
8433 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8434 __func__);
8435 err = 32;
8436 goto fail;
8437 }
8438
8439 /* depend on rateset, gmode */
8440 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8441 if (!wlc->cmi) {
8442 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8443 "\n", unit, __func__);
8444 err = 33;
8445 goto fail;
8446 }
8447
8448 /* init default when all parameters are ready, i.e. ->rateset */
8449 brcms_c_bss_default_init(wlc);
8450
8451 /*
8452 * Complete the wlc default state initializations..
8453 */
8454
8455 /* allocate our initial queue */
8456 wlc->pkt_queue = brcms_c_txq_alloc(wlc);
8457 if (wlc->pkt_queue == NULL) {
8458 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
8459 unit, __func__);
8460 err = 100;
8461 goto fail;
8462 }
8463
8464 wlc->bsscfg->wlc = wlc;
8465
8466 wlc->mimoft = FT_HT;
8467 wlc->mimo_40txbw = AUTO;
8468 wlc->ofdm_40txbw = AUTO;
8469 wlc->cck_40txbw = AUTO;
8470 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8471
8472 /* Set default values of SGI */
8473 if (BRCMS_SGI_CAP_PHY(wlc)) {
8474 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8475 BRCMS_N_SGI_40));
8476 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8477 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8478 BRCMS_N_SGI_40));
8479 } else {
8480 brcms_c_ht_update_sgi_rx(wlc, 0);
8481 }
8482
8483 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8484
8485 if (perr)
8486 *perr = 0;
8487
8488 return wlc;
8489
8490 fail:
8491 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8492 unit, __func__, err);
8493 if (wlc)
8494 brcms_c_detach(wlc);
8495
8496 if (perr)
8497 *perr = err;
8498 return NULL;
8499 }
Linux kernel - Deliverables
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