2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
39 #include "brcms_trace_events.h"
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG 1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK 800
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT 100
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52 * control it independently
58 #define EDCF_ACI_MASK 0x60
59 #define EDCF_ACI_SHIFT 5
60 #define EDCF_ECWMIN_MASK 0x0f
61 #define EDCF_ECWMAX_SHIFT 4
62 #define EDCF_AIFSN_MASK 0x0f
63 #define EDCF_AIFSN_MAX 15
64 #define EDCF_ECWMAX_MASK 0xf0
66 #define EDCF_AC_BE_TXOP_STA 0x0000
67 #define EDCF_AC_BK_TXOP_STA 0x0000
68 #define EDCF_AC_VO_ACI_STA 0x62
69 #define EDCF_AC_VO_ECW_STA 0x32
70 #define EDCF_AC_VI_ACI_STA 0x42
71 #define EDCF_AC_VI_ECW_STA 0x43
72 #define EDCF_AC_BK_ECW_STA 0xA4
73 #define EDCF_AC_VI_TXOP_STA 0x005e
74 #define EDCF_AC_VO_TXOP_STA 0x002f
75 #define EDCF_AC_BE_ACI_STA 0x03
76 #define EDCF_AC_BE_ECW_STA 0xA4
77 #define EDCF_AC_BK_ACI_STA 0x27
78 #define EDCF_AC_VO_TXOP_AP 0x002f
80 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
81 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83 #define APHY_SYMBOL_TIME 4
84 #define APHY_PREAMBLE_TIME 16
85 #define APHY_SIGNAL_TIME 4
86 #define APHY_SIFS_TIME 16
87 #define APHY_SERVICE_NBITS 16
88 #define APHY_TAIL_NBITS 6
89 #define BPHY_SIFS_TIME 10
90 #define BPHY_PLCP_SHORT_TIME 96
92 #define PREN_PREAMBLE 24
93 #define PREN_MM_EXT 12
94 #define PREN_PREAMBLE_EXT 4
96 #define DOT11_MAC_HDR_LEN 24
97 #define DOT11_ACK_LEN 10
98 #define DOT11_BA_LEN 4
99 #define DOT11_OFDM_SIGNAL_EXTENSION 6
100 #define DOT11_MIN_FRAG_LEN 256
101 #define DOT11_RTS_LEN 16
102 #define DOT11_CTS_LEN 10
103 #define DOT11_BA_BITMAP_LEN 128
104 #define DOT11_MIN_BEACON_PERIOD 1
105 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
106 #define DOT11_MAXNUMFRAGS 16
107 #define DOT11_MAX_FRAG_LEN 2346
109 #define BPHY_PLCP_TIME 192
110 #define RIFS_11N_TIME 2
112 /* length of the BCN template area */
113 #define BCN_TMPL_LEN 512
115 /* brcms_bss_info flag bit values */
116 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
118 /* chip rx buffer offset */
119 #define BRCMS_HWRXOFF 38
121 /* rfdisable delay timer 500 ms, runs of ALP clock */
122 #define RFDISABLE_DEFAULT 10000000
124 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
126 /* synthpu_dly times in us */
127 #define SYNTHPU_DLY_APHY_US 3700
128 #define SYNTHPU_DLY_BPHY_US 1050
129 #define SYNTHPU_DLY_NPHY_US 2048
130 #define SYNTHPU_DLY_LPPHY_US 300
132 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
134 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
135 #define EDCF_SHORT_S 0
137 #define EDCF_LONG_S 8
138 #define EDCF_LFB_S 12
139 #define EDCF_SHORT_M BITFIELD_MASK(4)
140 #define EDCF_SFB_M BITFIELD_MASK(4)
141 #define EDCF_LONG_M BITFIELD_MASK(4)
142 #define EDCF_LFB_M BITFIELD_MASK(4)
144 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
145 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
146 #define RETRY_LONG_DEF 4 /* Default Long retry count */
147 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
148 #define RETRY_LONG_FB 2 /* Long count for fb rate */
150 #define APHY_CWMIN 15
151 #define PHY_CWMAX 1023
153 #define EDCF_AIFSN_MIN 1
155 #define FRAGNUM_MASK 0xF
157 #define APHY_SLOT_TIME 9
158 #define BPHY_SLOT_TIME 20
160 #define WL_SPURAVOID_OFF 0
161 #define WL_SPURAVOID_ON1 1
162 #define WL_SPURAVOID_ON2 2
164 /* invalid core flags, use the saved coreflags */
165 #define BRCMS_USE_COREFLAGS 0xffffffff
167 /* values for PLCPHdr_override */
168 #define BRCMS_PLCP_AUTO -1
169 #define BRCMS_PLCP_SHORT 0
170 #define BRCMS_PLCP_LONG 1
172 /* values for g_protection_override and n_protection_override */
173 #define BRCMS_PROTECTION_AUTO -1
174 #define BRCMS_PROTECTION_OFF 0
175 #define BRCMS_PROTECTION_ON 1
176 #define BRCMS_PROTECTION_MMHDR_ONLY 2
177 #define BRCMS_PROTECTION_CTS_ONLY 3
179 /* values for g_protection_control and n_protection_control */
180 #define BRCMS_PROTECTION_CTL_OFF 0
181 #define BRCMS_PROTECTION_CTL_LOCAL 1
182 #define BRCMS_PROTECTION_CTL_OVERLAP 2
184 /* values for n_protection */
185 #define BRCMS_N_PROTECTION_OFF 0
186 #define BRCMS_N_PROTECTION_OPTIONAL 1
187 #define BRCMS_N_PROTECTION_20IN40 2
188 #define BRCMS_N_PROTECTION_MIXEDMODE 3
190 /* values for band specific 40MHz capabilities */
191 #define BRCMS_N_BW_20ALL 0
192 #define BRCMS_N_BW_40ALL 1
193 #define BRCMS_N_BW_20IN2G_40IN5G 2
195 /* bitflags for SGI support (sgi_rx iovar) */
196 #define BRCMS_N_SGI_20 0x01
197 #define BRCMS_N_SGI_40 0x02
199 /* defines used by the nrate iovar */
200 /* MSC in use,indicates b0-6 holds an mcs */
201 #define NRATE_MCS_INUSE 0x00000080
203 #define NRATE_RATE_MASK 0x0000007f
204 /* stf mode mask: siso, cdd, stbc, sdm */
205 #define NRATE_STF_MASK 0x0000ff00
207 #define NRATE_STF_SHIFT 8
208 /* bit indicate to override mcs only */
209 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
210 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
211 #define NRATE_SGI_SHIFT 23 /* sgi mode */
212 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
213 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
215 #define NRATE_STF_SISO 0 /* stf mode SISO */
216 #define NRATE_STF_CDD 1 /* stf mode CDD */
217 #define NRATE_STF_STBC 2 /* stf mode STBC */
218 #define NRATE_STF_SDM 3 /* stf mode SDM */
220 #define MAX_DMA_SEGS 4
222 /* # of entries in Tx FIFO */
224 /* Max # of entries in Rx FIFO based on 4kb page size */
227 /* Amount of headroom to leave in Tx FIFO */
228 #define TX_HEADROOM 4
230 /* try to keep this # rbufs posted to the chip */
231 #define NRXBUFPOST 32
233 /* max # frames to process in brcms_c_recv() */
235 /* max # tx status to process in wlc_txstatus() */
238 /* brcmu_format_flags() bit description structure */
239 struct brcms_c_bit_desc
{
245 * The following table lists the buffer memory allocated to xmt fifos in HW.
246 * the size is in units of 256bytes(one block), total size is HW dependent
247 * ucode has default fifo partition, sw can overwrite if necessary
249 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
250 * the twiki is updated before making changes.
253 /* Starting corerev for the fifo size table */
254 #define XMTFIFOTBL_STARTREV 17
262 struct edcf_acparam
{
271 /* TX FIFO number to WME/802.1E Access Category */
272 static const u8 wme_fifo2ac
[] = {
281 /* ieee80211 Access Category to TX FIFO number */
282 static const u8 wme_ac2fifo
[] = {
289 static const u16 xmtfifo_sz
[][NFIFO
] = {
290 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291 {20, 192, 192, 21, 17, 5},
296 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297 {20, 192, 192, 21, 17, 5},
298 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299 {9, 58, 22, 14, 14, 5},
300 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301 {20, 192, 192, 21, 17, 5},
302 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303 {20, 192, 192, 21, 17, 5},
304 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305 {9, 58, 22, 14, 14, 5},
312 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
313 {9, 58, 22, 14, 14, 5},
317 static const char * const fifo_names
[] = {
318 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
320 static const char fifo_names
[6][0];
324 /* pointer to most recently allocated wl/wlc */
325 static struct brcms_c_info
*wlc_info_dbg
= (struct brcms_c_info
*) (NULL
);
328 /* Mapping of ieee80211 AC numbers to tx fifos */
329 static const u8 ac_to_fifo_mapping
[IEEE80211_NUM_ACS
] = {
330 [IEEE80211_AC_VO
] = TX_AC_VO_FIFO
,
331 [IEEE80211_AC_VI
] = TX_AC_VI_FIFO
,
332 [IEEE80211_AC_BE
] = TX_AC_BE_FIFO
,
333 [IEEE80211_AC_BK
] = TX_AC_BK_FIFO
,
336 /* Mapping of tx fifos to ieee80211 AC numbers */
337 static const u8 fifo_to_ac_mapping
[IEEE80211_NUM_ACS
] = {
338 [TX_AC_BK_FIFO
] = IEEE80211_AC_BK
,
339 [TX_AC_BE_FIFO
] = IEEE80211_AC_BE
,
340 [TX_AC_VI_FIFO
] = IEEE80211_AC_VI
,
341 [TX_AC_VO_FIFO
] = IEEE80211_AC_VO
,
344 static u8
brcms_ac_to_fifo(u8 ac
)
346 if (ac
>= ARRAY_SIZE(ac_to_fifo_mapping
))
347 return TX_AC_BE_FIFO
;
348 return ac_to_fifo_mapping
[ac
];
351 static u8
brcms_fifo_to_ac(u8 fifo
)
353 if (fifo
>= ARRAY_SIZE(fifo_to_ac_mapping
))
354 return IEEE80211_AC_BE
;
355 return fifo_to_ac_mapping
[fifo
];
358 /* Find basic rate for a given rate */
359 static u8
brcms_basic_rate(struct brcms_c_info
*wlc
, u32 rspec
)
361 if (is_mcs_rate(rspec
))
362 return wlc
->band
->basic_rate
[mcs_table
[rspec
& RSPEC_RATE_MASK
]
364 return wlc
->band
->basic_rate
[rspec
& RSPEC_RATE_MASK
];
367 static u16
frametype(u32 rspec
, u8 mimoframe
)
369 if (is_mcs_rate(rspec
))
371 return is_cck_rate(rspec
) ? FT_CCK
: FT_OFDM
;
374 /* currently the best mechanism for determining SIFS is the band in use */
375 static u16
get_sifs(struct brcms_band
*band
)
377 return band
->bandtype
== BRCM_BAND_5G
? APHY_SIFS_TIME
:
382 * Detect Card removed.
383 * Even checking an sbconfig register read will not false trigger when the core
384 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
385 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
386 * reg with fixed 0/1 pattern (some platforms return all 0).
387 * If clocks are present, call the sb routine which will figure out if the
390 static bool brcms_deviceremoved(struct brcms_c_info
*wlc
)
395 return ai_deviceremoved(wlc
->hw
->sih
);
396 macctrl
= bcma_read32(wlc
->hw
->d11core
,
397 D11REGOFFS(maccontrol
));
398 return (macctrl
& (MCTL_PSM_JMP_0
| MCTL_IHR_EN
)) != MCTL_IHR_EN
;
401 /* sum the individual fifo tx pending packet counts */
402 static int brcms_txpktpendtot(struct brcms_c_info
*wlc
)
407 for (i
= 0; i
< ARRAY_SIZE(wlc
->hw
->di
); i
++)
409 pending
+= dma_txpending(wlc
->hw
->di
[i
]);
413 static bool brcms_is_mband_unlocked(struct brcms_c_info
*wlc
)
415 return wlc
->pub
->_nbands
> 1 && !wlc
->bandlocked
;
418 static int brcms_chspec_bw(u16 chanspec
)
420 if (CHSPEC_IS40(chanspec
))
422 if (CHSPEC_IS20(chanspec
))
428 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg
*cfg
)
433 kfree(cfg
->current_bss
);
437 static void brcms_c_detach_mfree(struct brcms_c_info
*wlc
)
442 brcms_c_bsscfg_mfree(wlc
->bsscfg
);
444 kfree(wlc
->modulecb
);
445 kfree(wlc
->default_bss
);
446 kfree(wlc
->protection
);
448 kfree(wlc
->bandstate
[0]);
449 kfree(wlc
->corestate
->macstat_snapshot
);
450 kfree(wlc
->corestate
);
451 kfree(wlc
->hw
->bandstate
[0]);
459 static struct brcms_bss_cfg
*brcms_c_bsscfg_malloc(uint unit
)
461 struct brcms_bss_cfg
*cfg
;
463 cfg
= kzalloc(sizeof(struct brcms_bss_cfg
), GFP_ATOMIC
);
467 cfg
->current_bss
= kzalloc(sizeof(struct brcms_bss_info
), GFP_ATOMIC
);
468 if (cfg
->current_bss
== NULL
)
474 brcms_c_bsscfg_mfree(cfg
);
478 static struct brcms_c_info
*
479 brcms_c_attach_malloc(uint unit
, uint
*err
, uint devid
)
481 struct brcms_c_info
*wlc
;
483 wlc
= kzalloc(sizeof(struct brcms_c_info
), GFP_ATOMIC
);
489 /* allocate struct brcms_c_pub state structure */
490 wlc
->pub
= kzalloc(sizeof(struct brcms_pub
), GFP_ATOMIC
);
491 if (wlc
->pub
== NULL
) {
497 /* allocate struct brcms_hardware state structure */
499 wlc
->hw
= kzalloc(sizeof(struct brcms_hardware
), GFP_ATOMIC
);
500 if (wlc
->hw
== NULL
) {
506 wlc
->hw
->bandstate
[0] =
507 kzalloc(sizeof(struct brcms_hw_band
) * MAXBANDS
, GFP_ATOMIC
);
508 if (wlc
->hw
->bandstate
[0] == NULL
) {
514 for (i
= 1; i
< MAXBANDS
; i
++)
515 wlc
->hw
->bandstate
[i
] = (struct brcms_hw_band
*)
516 ((unsigned long)wlc
->hw
->bandstate
[0] +
517 (sizeof(struct brcms_hw_band
) * i
));
521 kzalloc(sizeof(struct modulecb
) * BRCMS_MAXMODULES
, GFP_ATOMIC
);
522 if (wlc
->modulecb
== NULL
) {
527 wlc
->default_bss
= kzalloc(sizeof(struct brcms_bss_info
), GFP_ATOMIC
);
528 if (wlc
->default_bss
== NULL
) {
533 wlc
->bsscfg
= brcms_c_bsscfg_malloc(unit
);
534 if (wlc
->bsscfg
== NULL
) {
539 wlc
->protection
= kzalloc(sizeof(struct brcms_protection
),
541 if (wlc
->protection
== NULL
) {
546 wlc
->stf
= kzalloc(sizeof(struct brcms_stf
), GFP_ATOMIC
);
547 if (wlc
->stf
== NULL
) {
553 kzalloc(sizeof(struct brcms_band
)*MAXBANDS
, GFP_ATOMIC
);
554 if (wlc
->bandstate
[0] == NULL
) {
560 for (i
= 1; i
< MAXBANDS
; i
++)
561 wlc
->bandstate
[i
] = (struct brcms_band
*)
562 ((unsigned long)wlc
->bandstate
[0]
563 + (sizeof(struct brcms_band
)*i
));
566 wlc
->corestate
= kzalloc(sizeof(struct brcms_core
), GFP_ATOMIC
);
567 if (wlc
->corestate
== NULL
) {
572 wlc
->corestate
->macstat_snapshot
=
573 kzalloc(sizeof(struct macstat
), GFP_ATOMIC
);
574 if (wlc
->corestate
->macstat_snapshot
== NULL
) {
582 brcms_c_detach_mfree(wlc
);
587 * Update the slot timing for standard 11b/g (20us slots)
588 * or shortslot 11g (9us slots)
589 * The PSM needs to be suspended for this call.
591 static void brcms_b_update_slot_timing(struct brcms_hardware
*wlc_hw
,
594 struct bcma_device
*core
= wlc_hw
->d11core
;
597 /* 11g short slot: 11a timing */
598 bcma_write16(core
, D11REGOFFS(ifs_slot
), 0x0207);
599 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, APHY_SLOT_TIME
);
601 /* 11g long slot: 11b timing */
602 bcma_write16(core
, D11REGOFFS(ifs_slot
), 0x0212);
603 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, BPHY_SLOT_TIME
);
608 * calculate frame duration of a given rate and length, return
611 static uint
brcms_c_calc_frame_time(struct brcms_c_info
*wlc
, u32 ratespec
,
612 u8 preamble_type
, uint mac_len
)
614 uint nsyms
, dur
= 0, Ndps
, kNdps
;
615 uint rate
= rspec2rate(ratespec
);
618 brcms_err(wlc
->hw
->d11core
, "wl%d: WAR: using rate of 1 mbps\n",
623 if (is_mcs_rate(ratespec
)) {
624 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
625 int tot_streams
= mcs_2_txstreams(mcs
) + rspec_stc(ratespec
);
627 dur
= PREN_PREAMBLE
+ (tot_streams
* PREN_PREAMBLE_EXT
);
628 if (preamble_type
== BRCMS_MM_PREAMBLE
)
630 /* 1000Ndbps = kbps * 4 */
631 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
632 rspec_issgi(ratespec
)) * 4;
634 if (rspec_stc(ratespec
) == 0)
636 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
637 APHY_TAIL_NBITS
) * 1000, kNdps
);
639 /* STBC needs to have even number of symbols */
642 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
643 APHY_TAIL_NBITS
) * 1000, 2 * kNdps
);
645 dur
+= APHY_SYMBOL_TIME
* nsyms
;
646 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
647 dur
+= DOT11_OFDM_SIGNAL_EXTENSION
;
648 } else if (is_ofdm_rate(rate
)) {
649 dur
= APHY_PREAMBLE_TIME
;
650 dur
+= APHY_SIGNAL_TIME
;
651 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
653 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
655 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+ APHY_TAIL_NBITS
),
657 dur
+= APHY_SYMBOL_TIME
* nsyms
;
658 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
659 dur
+= DOT11_OFDM_SIGNAL_EXTENSION
;
662 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
665 mac_len
= mac_len
* 8 * 2;
666 /* calc ceiling of bits/rate = microseconds of air time */
667 dur
= (mac_len
+ rate
- 1) / rate
;
668 if (preamble_type
& BRCMS_SHORT_PREAMBLE
)
669 dur
+= BPHY_PLCP_SHORT_TIME
;
671 dur
+= BPHY_PLCP_TIME
;
676 static void brcms_c_write_inits(struct brcms_hardware
*wlc_hw
,
677 const struct d11init
*inits
)
679 struct bcma_device
*core
= wlc_hw
->d11core
;
685 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
687 for (i
= 0; inits
[i
].addr
!= cpu_to_le16(0xffff); i
++) {
688 size
= le16_to_cpu(inits
[i
].size
);
689 offset
= le16_to_cpu(inits
[i
].addr
);
690 value
= le32_to_cpu(inits
[i
].value
);
692 bcma_write16(core
, offset
, value
);
694 bcma_write32(core
, offset
, value
);
700 static void brcms_c_write_mhf(struct brcms_hardware
*wlc_hw
, u16
*mhfs
)
704 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
708 for (idx
= 0; idx
< MHFMAX
; idx
++)
709 brcms_b_write_shm(wlc_hw
, addr
[idx
], mhfs
[idx
]);
712 static void brcms_c_ucode_bsinit(struct brcms_hardware
*wlc_hw
)
714 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
716 /* init microcode host flags */
717 brcms_c_write_mhf(wlc_hw
, wlc_hw
->band
->mhfs
);
719 /* do band-specific ucode IHR, SHM, and SCR inits */
720 if (D11REV_IS(wlc_hw
->corerev
, 17) || D11REV_IS(wlc_hw
->corerev
, 23)) {
721 if (BRCMS_ISNPHY(wlc_hw
->band
))
722 brcms_c_write_inits(wlc_hw
, ucode
->d11n0bsinitvals16
);
724 brcms_err(wlc_hw
->d11core
,
725 "%s: wl%d: unsupported phy in corerev %d\n",
726 __func__
, wlc_hw
->unit
,
729 if (D11REV_IS(wlc_hw
->corerev
, 24)) {
730 if (BRCMS_ISLCNPHY(wlc_hw
->band
))
731 brcms_c_write_inits(wlc_hw
,
732 ucode
->d11lcn0bsinitvals24
);
734 brcms_err(wlc_hw
->d11core
,
735 "%s: wl%d: unsupported phy in core rev %d\n",
736 __func__
, wlc_hw
->unit
,
739 brcms_err(wlc_hw
->d11core
,
740 "%s: wl%d: unsupported corerev %d\n",
741 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
746 static void brcms_b_core_ioctl(struct brcms_hardware
*wlc_hw
, u32 m
, u32 v
)
748 struct bcma_device
*core
= wlc_hw
->d11core
;
749 u32 ioctl
= bcma_aread32(core
, BCMA_IOCTL
) & ~m
;
751 bcma_awrite32(core
, BCMA_IOCTL
, ioctl
| v
);
754 static void brcms_b_core_phy_clk(struct brcms_hardware
*wlc_hw
, bool clk
)
756 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: clk %d\n", wlc_hw
->unit
, clk
);
758 wlc_hw
->phyclk
= clk
;
760 if (OFF
== clk
) { /* clear gmode bit, put phy into reset */
762 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
| SICF_GMODE
),
763 (SICF_PRST
| SICF_FGC
));
765 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
), SICF_PRST
);
768 } else { /* take phy out of reset */
770 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
), SICF_FGC
);
772 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, 0);
778 /* low-level band switch utility routine */
779 static void brcms_c_setxband(struct brcms_hardware
*wlc_hw
, uint bandunit
)
781 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
784 wlc_hw
->band
= wlc_hw
->bandstate
[bandunit
];
788 * until we eliminate need for wlc->band refs in low level code
790 wlc_hw
->wlc
->band
= wlc_hw
->wlc
->bandstate
[bandunit
];
792 /* set gmode core flag */
793 if (wlc_hw
->sbclk
&& !wlc_hw
->noreset
) {
799 brcms_b_core_ioctl(wlc_hw
, SICF_GMODE
, gmode
);
803 /* switch to new band but leave it inactive */
804 static u32
brcms_c_setband_inact(struct brcms_c_info
*wlc
, uint bandunit
)
806 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
810 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
811 macctrl
= bcma_read32(wlc_hw
->d11core
,
812 D11REGOFFS(maccontrol
));
813 WARN_ON((macctrl
& MCTL_EN_MAC
) != 0);
815 /* disable interrupts */
816 macintmask
= brcms_intrsoff(wlc
->wl
);
819 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
821 brcms_b_core_phy_clk(wlc_hw
, OFF
);
823 brcms_c_setxband(wlc_hw
, bandunit
);
828 /* process an individual struct tx_status */
830 brcms_c_dotxstatus(struct brcms_c_info
*wlc
, struct tx_status
*txs
)
832 struct sk_buff
*p
= NULL
;
834 struct dma_pub
*dma
= NULL
;
835 struct d11txh
*txh
= NULL
;
836 struct scb
*scb
= NULL
;
838 int tx_rts
, tx_frame_count
, tx_rts_count
;
839 uint totlen
, supr_status
;
841 struct ieee80211_hdr
*h
;
843 struct ieee80211_tx_info
*tx_info
;
844 struct ieee80211_tx_rate
*txrate
;
848 trace_brcms_txstatus(&wlc
->hw
->d11core
->dev
, txs
->framelen
,
849 txs
->frameid
, txs
->status
, txs
->lasttxtime
,
850 txs
->sequence
, txs
->phyerr
, txs
->ackphyrxsh
);
852 /* discard intermediate indications for ucode with one legitimate case:
853 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
854 * but the subsequent tx of DATA failed. so it will start rts/cts
855 * from the beginning (resetting the rts transmission count)
857 if (!(txs
->status
& TX_STATUS_AMPDU
)
858 && (txs
->status
& TX_STATUS_INTERMEDIATE
)) {
859 brcms_dbg_tx(wlc
->hw
->d11core
, "INTERMEDIATE but not AMPDU\n");
864 queue
= txs
->frameid
& TXFID_QUEUE_MASK
;
865 if (queue
>= NFIFO
) {
866 brcms_err(wlc
->hw
->d11core
, "queue %u >= NFIFO\n", queue
);
870 dma
= wlc
->hw
->di
[queue
];
872 p
= dma_getnexttxp(wlc
->hw
->di
[queue
], DMA_RANGE_TRANSMITTED
);
874 brcms_err(wlc
->hw
->d11core
, "dma_getnexttxp returned null!\n");
878 txh
= (struct d11txh
*) (p
->data
);
879 mcl
= le16_to_cpu(txh
->MacTxControlLow
);
882 brcms_err(wlc
->hw
->d11core
, "phyerr 0x%x, rate 0x%x\n",
883 txs
->phyerr
, txh
->MainRates
);
885 if (txs
->frameid
!= le16_to_cpu(txh
->TxFrameID
)) {
886 brcms_err(wlc
->hw
->d11core
, "frameid != txh->TxFrameID\n");
889 tx_info
= IEEE80211_SKB_CB(p
);
890 h
= (struct ieee80211_hdr
*)((u8
*) (txh
+ 1) + D11_PHY_HDR_LEN
);
892 if (tx_info
->rate_driver_data
[0])
895 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
896 brcms_c_ampdu_dotxstatus(wlc
->ampdu
, scb
, p
, txs
);
902 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
903 * frames; this traces them for the rest.
905 trace_brcms_txdesc(&wlc
->hw
->d11core
->dev
, txh
, sizeof(*txh
));
907 supr_status
= txs
->status
& TX_STATUS_SUPR_MASK
;
908 if (supr_status
== TX_STATUS_SUPR_BADCH
) {
909 unsigned xfts
= le16_to_cpu(txh
->XtraFrameTypes
);
910 brcms_dbg_tx(wlc
->hw
->d11core
,
911 "Pkt tx suppressed, dest chan %u, current %d\n",
912 (xfts
>> XFTS_CHANNEL_SHIFT
) & 0xff,
913 CHSPEC_CHANNEL(wlc
->default_bss
->chanspec
));
916 tx_rts
= le16_to_cpu(txh
->MacTxControlLow
) & TXC_SENDRTS
;
918 (txs
->status
& TX_STATUS_FRM_RTX_MASK
) >> TX_STATUS_FRM_RTX_SHIFT
;
920 (txs
->status
& TX_STATUS_RTS_RTX_MASK
) >> TX_STATUS_RTS_RTX_SHIFT
;
922 lastframe
= !ieee80211_has_morefrags(h
->frame_control
);
925 brcms_err(wlc
->hw
->d11core
, "Not last frame!\n");
928 * Set information to be consumed by Minstrel ht.
930 * The "fallback limit" is the number of tx attempts a given
931 * MPDU is sent at the "primary" rate. Tx attempts beyond that
932 * limit are sent at the "secondary" rate.
933 * A 'short frame' does not exceed RTS treshold.
935 u16 sfbl
, /* Short Frame Rate Fallback Limit */
936 lfbl
, /* Long Frame Rate Fallback Limit */
939 if (queue
< IEEE80211_NUM_ACS
) {
940 sfbl
= GFIELD(wlc
->wme_retries
[wme_fifo2ac
[queue
]],
942 lfbl
= GFIELD(wlc
->wme_retries
[wme_fifo2ac
[queue
]],
949 txrate
= tx_info
->status
.rates
;
950 if (txrate
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
955 ieee80211_tx_info_clear_status(tx_info
);
957 if ((tx_frame_count
> fbl
) && (txrate
[1].idx
>= 0)) {
959 * rate selection requested a fallback rate
962 txrate
[0].count
= fbl
;
963 txrate
[1].count
= tx_frame_count
- fbl
;
966 * rate selection did not request fallback rate, or
969 txrate
[0].count
= tx_frame_count
;
971 * rc80211_minstrel.c:minstrel_tx_status() expects
972 * unused rates to be marked with idx = -1
978 /* clear the rest of the rates */
979 for (i
= 2; i
< IEEE80211_TX_MAX_RATES
; i
++) {
984 if (txs
->status
& TX_STATUS_ACK_RCV
)
985 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
992 /* remove PLCP & Broadcom tx descriptor header */
993 skb_pull(p
, D11_PHY_HDR_LEN
);
994 skb_pull(p
, D11_TXH_LEN
);
995 ieee80211_tx_status_irqsafe(wlc
->pub
->ieee_hw
, p
);
997 brcms_err(wlc
->hw
->d11core
,
998 "%s: Not last frame => not calling tx_status\n",
1007 trace_brcms_txdesc(&wlc
->hw
->d11core
->dev
, txh
,
1010 brcmu_pkt_buf_free_skb(p
);
1013 if (dma
&& queue
< NFIFO
) {
1014 u16 ac_queue
= brcms_fifo_to_ac(queue
);
1015 if (dma
->txavail
> TX_HEADROOM
&& queue
< TX_BCMC_FIFO
&&
1016 ieee80211_queue_stopped(wlc
->pub
->ieee_hw
, ac_queue
))
1017 ieee80211_wake_queue(wlc
->pub
->ieee_hw
, ac_queue
);
1024 /* process tx completion events in BMAC
1025 * Return true if more tx status need to be processed. false otherwise.
1028 brcms_b_txstatus(struct brcms_hardware
*wlc_hw
, bool bound
, bool *fatal
)
1030 struct bcma_device
*core
;
1031 struct tx_status txstatus
, *txs
;
1035 * Param 'max_tx_num' indicates max. # tx status to process before
1038 uint max_tx_num
= bound
? TXSBND
: -1;
1041 core
= wlc_hw
->d11core
;
1044 while (n
< max_tx_num
) {
1045 s1
= bcma_read32(core
, D11REGOFFS(frmtxstatus
));
1046 if (s1
== 0xffffffff) {
1047 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
1052 /* only process when valid */
1056 s2
= bcma_read32(core
, D11REGOFFS(frmtxstatus2
));
1057 txs
->status
= s1
& TXS_STATUS_MASK
;
1058 txs
->frameid
= (s1
& TXS_FID_MASK
) >> TXS_FID_SHIFT
;
1059 txs
->sequence
= s2
& TXS_SEQ_MASK
;
1060 txs
->phyerr
= (s2
& TXS_PTX_MASK
) >> TXS_PTX_SHIFT
;
1061 txs
->lasttxtime
= 0;
1063 *fatal
= brcms_c_dotxstatus(wlc_hw
->wlc
, txs
);
1069 return n
>= max_tx_num
;
1072 static void brcms_c_tbtt(struct brcms_c_info
*wlc
)
1074 if (!wlc
->bsscfg
->BSS
)
1076 * DirFrmQ is now valid...defer setting until end
1079 wlc
->qvalid
|= MCMD_DIRFRMQVAL
;
1082 /* set initial host flags value */
1084 brcms_c_mhfdef(struct brcms_c_info
*wlc
, u16
*mhfs
, u16 mhf2_init
)
1086 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1088 memset(mhfs
, 0, MHFMAX
* sizeof(u16
));
1090 mhfs
[MHF2
] |= mhf2_init
;
1092 /* prohibit use of slowclock on multifunction boards */
1093 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
1094 mhfs
[MHF1
] |= MHF1_FORCEFASTCLK
;
1096 if (BRCMS_ISNPHY(wlc_hw
->band
) && NREV_LT(wlc_hw
->band
->phyrev
, 2)) {
1097 mhfs
[MHF2
] |= MHF2_NPHY40MHZ_WAR
;
1098 mhfs
[MHF1
] |= MHF1_IQSWAP_WAR
;
1103 dmareg(uint direction
, uint fifonum
)
1105 if (direction
== DMA_TX
)
1106 return offsetof(struct d11regs
, fifo64regs
[fifonum
].dmaxmt
);
1107 return offsetof(struct d11regs
, fifo64regs
[fifonum
].dmarcv
);
1110 static bool brcms_b_attach_dmapio(struct brcms_c_info
*wlc
, uint j
, bool wme
)
1115 * ucode host flag 2 needed for pio mode, independent of band and fifo
1118 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1119 uint unit
= wlc_hw
->unit
;
1121 /* name and offsets for dma_attach */
1122 snprintf(name
, sizeof(name
), "wl%d", unit
);
1124 if (wlc_hw
->di
[0] == NULL
) { /* Init FIFOs */
1125 int dma_attach_err
= 0;
1129 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1130 * RX: RX_FIFO (RX data packets)
1132 wlc_hw
->di
[0] = dma_attach(name
, wlc
,
1133 (wme
? dmareg(DMA_TX
, 0) : 0),
1135 (wme
? NTXD
: 0), NRXD
,
1136 RXBUFSZ
, -1, NRXBUFPOST
,
1138 dma_attach_err
|= (NULL
== wlc_hw
->di
[0]);
1142 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1143 * (legacy) TX_DATA_FIFO (TX data packets)
1146 wlc_hw
->di
[1] = dma_attach(name
, wlc
,
1147 dmareg(DMA_TX
, 1), 0,
1148 NTXD
, 0, 0, -1, 0, 0);
1149 dma_attach_err
|= (NULL
== wlc_hw
->di
[1]);
1153 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1156 wlc_hw
->di
[2] = dma_attach(name
, wlc
,
1157 dmareg(DMA_TX
, 2), 0,
1158 NTXD
, 0, 0, -1, 0, 0);
1159 dma_attach_err
|= (NULL
== wlc_hw
->di
[2]);
1162 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1163 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1165 wlc_hw
->di
[3] = dma_attach(name
, wlc
,
1169 dma_attach_err
|= (NULL
== wlc_hw
->di
[3]);
1170 /* Cleaner to leave this as if with AP defined */
1172 if (dma_attach_err
) {
1173 brcms_err(wlc_hw
->d11core
,
1174 "wl%d: wlc_attach: dma_attach failed\n",
1179 /* get pointer to dma engine tx flow control variable */
1180 for (i
= 0; i
< NFIFO
; i
++)
1182 wlc_hw
->txavail
[i
] =
1183 (uint
*) dma_getvar(wlc_hw
->di
[i
],
1187 /* initial ucode host flags */
1188 brcms_c_mhfdef(wlc
, wlc_hw
->band
->mhfs
, pio_mhf2
);
1193 static void brcms_b_detach_dmapio(struct brcms_hardware
*wlc_hw
)
1197 for (j
= 0; j
< NFIFO
; j
++) {
1198 if (wlc_hw
->di
[j
]) {
1199 dma_detach(wlc_hw
->di
[j
]);
1200 wlc_hw
->di
[j
] = NULL
;
1206 * Initialize brcms_c_info default values ...
1207 * may get overrides later in this function
1208 * BMAC_NOTES, move low out and resolve the dangling ones
1210 static void brcms_b_info_init(struct brcms_hardware
*wlc_hw
)
1212 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1214 /* set default sw macintmask value */
1215 wlc
->defmacintmask
= DEF_MACINTMASK
;
1217 /* various 802.11g modes */
1218 wlc_hw
->shortslot
= false;
1220 wlc_hw
->SFBL
= RETRY_SHORT_FB
;
1221 wlc_hw
->LFBL
= RETRY_LONG_FB
;
1223 /* default mac retry limits */
1224 wlc_hw
->SRL
= RETRY_SHORT_DEF
;
1225 wlc_hw
->LRL
= RETRY_LONG_DEF
;
1226 wlc_hw
->chanspec
= ch20mhz_chspec(1);
1229 static void brcms_b_wait_for_wake(struct brcms_hardware
*wlc_hw
)
1231 /* delay before first read of ucode state */
1234 /* wait until ucode is no longer asleep */
1235 SPINWAIT((brcms_b_read_shm(wlc_hw
, M_UCODE_DBGST
) ==
1236 DBGST_ASLEEP
), wlc_hw
->wlc
->fastpwrup_dly
);
1239 /* control chip clock to save power, enable dynamic clock or force fast clock */
1240 static void brcms_b_clkctl_clk(struct brcms_hardware
*wlc_hw
, enum bcma_clkmode mode
)
1242 if (ai_get_cccaps(wlc_hw
->sih
) & CC_CAP_PMU
) {
1243 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1244 * on backplane, but mac core will still run on ALP(not HT) when
1245 * it enters powersave mode, which means the FCA bit may not be
1246 * set. Should wakeup mac if driver wants it to run on HT.
1250 if (mode
== BCMA_CLKMODE_FAST
) {
1251 bcma_set32(wlc_hw
->d11core
,
1252 D11REGOFFS(clk_ctl_st
),
1258 ((bcma_read32(wlc_hw
->d11core
,
1259 D11REGOFFS(clk_ctl_st
)) &
1261 PMU_MAX_TRANSITION_DLY
);
1262 WARN_ON(!(bcma_read32(wlc_hw
->d11core
,
1263 D11REGOFFS(clk_ctl_st
)) &
1266 if ((ai_get_pmurev(wlc_hw
->sih
) == 0) &&
1267 (bcma_read32(wlc_hw
->d11core
,
1268 D11REGOFFS(clk_ctl_st
)) &
1269 (CCS_FORCEHT
| CCS_HTAREQ
)))
1271 ((bcma_read32(wlc_hw
->d11core
,
1272 offsetof(struct d11regs
,
1275 PMU_MAX_TRANSITION_DLY
);
1276 bcma_mask32(wlc_hw
->d11core
,
1277 D11REGOFFS(clk_ctl_st
),
1281 wlc_hw
->forcefastclk
= (mode
== BCMA_CLKMODE_FAST
);
1284 /* old chips w/o PMU, force HT through cc,
1285 * then use FCA to verify mac is running fast clock
1288 wlc_hw
->forcefastclk
= ai_clkctl_cc(wlc_hw
->sih
, mode
);
1290 /* check fast clock is available (if core is not in reset) */
1291 if (wlc_hw
->forcefastclk
&& wlc_hw
->clk
)
1292 WARN_ON(!(bcma_aread32(wlc_hw
->d11core
, BCMA_IOST
) &
1296 * keep the ucode wake bit on if forcefastclk is on since we
1297 * do not want ucode to put us back to slow clock when it dozes
1298 * for PM mode. Code below matches the wake override bit with
1299 * current forcefastclk state. Only setting bit in wake_override
1300 * instead of waking ucode immediately since old code had this
1301 * behavior. Older code set wlc->forcefastclk but only had the
1302 * wake happen if the wakup_ucode work (protected by an up
1303 * check) was executed just below.
1305 if (wlc_hw
->forcefastclk
)
1306 mboolset(wlc_hw
->wake_override
,
1307 BRCMS_WAKE_OVERRIDE_FORCEFAST
);
1309 mboolclr(wlc_hw
->wake_override
,
1310 BRCMS_WAKE_OVERRIDE_FORCEFAST
);
1314 /* set or clear ucode host flag bits
1315 * it has an optimization for no-change write
1316 * it only writes through shared memory when the core has clock;
1317 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1320 * bands values are: BRCM_BAND_AUTO <--- Current band only
1321 * BRCM_BAND_5G <--- 5G band only
1322 * BRCM_BAND_2G <--- 2G band only
1323 * BRCM_BAND_ALL <--- All bands
1326 brcms_b_mhf(struct brcms_hardware
*wlc_hw
, u8 idx
, u16 mask
, u16 val
,
1330 u16 addr
[MHFMAX
] = {
1331 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1334 struct brcms_hw_band
*band
;
1336 if ((val
& ~mask
) || idx
>= MHFMAX
)
1337 return; /* error condition */
1340 /* Current band only or all bands,
1341 * then set the band to current band
1343 case BRCM_BAND_AUTO
:
1345 band
= wlc_hw
->band
;
1348 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1351 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1354 band
= NULL
; /* error condition */
1358 save
= band
->mhfs
[idx
];
1359 band
->mhfs
[idx
] = (band
->mhfs
[idx
] & ~mask
) | val
;
1361 /* optimization: only write through if changed, and
1362 * changed band is the current band
1364 if (wlc_hw
->clk
&& (band
->mhfs
[idx
] != save
)
1365 && (band
== wlc_hw
->band
))
1366 brcms_b_write_shm(wlc_hw
, addr
[idx
],
1367 (u16
) band
->mhfs
[idx
]);
1370 if (bands
== BRCM_BAND_ALL
) {
1371 wlc_hw
->bandstate
[0]->mhfs
[idx
] =
1372 (wlc_hw
->bandstate
[0]->mhfs
[idx
] & ~mask
) | val
;
1373 wlc_hw
->bandstate
[1]->mhfs
[idx
] =
1374 (wlc_hw
->bandstate
[1]->mhfs
[idx
] & ~mask
) | val
;
1378 /* set the maccontrol register to desired reset state and
1379 * initialize the sw cache of the register
1381 static void brcms_c_mctrl_reset(struct brcms_hardware
*wlc_hw
)
1383 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1384 wlc_hw
->maccontrol
= 0;
1385 wlc_hw
->suspended_fifos
= 0;
1386 wlc_hw
->wake_override
= 0;
1387 wlc_hw
->mute_override
= 0;
1388 brcms_b_mctrl(wlc_hw
, ~0, MCTL_IHR_EN
| MCTL_WAKE
);
1392 * write the software state of maccontrol and
1393 * overrides to the maccontrol register
1395 static void brcms_c_mctrl_write(struct brcms_hardware
*wlc_hw
)
1397 u32 maccontrol
= wlc_hw
->maccontrol
;
1399 /* OR in the wake bit if overridden */
1400 if (wlc_hw
->wake_override
)
1401 maccontrol
|= MCTL_WAKE
;
1403 /* set AP and INFRA bits for mute if needed */
1404 if (wlc_hw
->mute_override
) {
1405 maccontrol
&= ~(MCTL_AP
);
1406 maccontrol
|= MCTL_INFRA
;
1409 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(maccontrol
),
1413 /* set or clear maccontrol bits */
1414 void brcms_b_mctrl(struct brcms_hardware
*wlc_hw
, u32 mask
, u32 val
)
1420 return; /* error condition */
1421 maccontrol
= wlc_hw
->maccontrol
;
1422 new_maccontrol
= (maccontrol
& ~mask
) | val
;
1424 /* if the new maccontrol value is the same as the old, nothing to do */
1425 if (new_maccontrol
== maccontrol
)
1428 /* something changed, cache the new value */
1429 wlc_hw
->maccontrol
= new_maccontrol
;
1431 /* write the new values with overrides applied */
1432 brcms_c_mctrl_write(wlc_hw
);
1435 void brcms_c_ucode_wake_override_set(struct brcms_hardware
*wlc_hw
,
1438 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
)) {
1439 mboolset(wlc_hw
->wake_override
, override_bit
);
1443 mboolset(wlc_hw
->wake_override
, override_bit
);
1445 brcms_c_mctrl_write(wlc_hw
);
1446 brcms_b_wait_for_wake(wlc_hw
);
1449 void brcms_c_ucode_wake_override_clear(struct brcms_hardware
*wlc_hw
,
1452 mboolclr(wlc_hw
->wake_override
, override_bit
);
1454 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
))
1457 brcms_c_mctrl_write(wlc_hw
);
1460 /* When driver needs ucode to stop beaconing, it has to make sure that
1461 * MCTL_AP is clear and MCTL_INFRA is set
1462 * Mode MCTL_AP MCTL_INFRA
1464 * STA 0 1 <--- This will ensure no beacons
1467 static void brcms_c_ucode_mute_override_set(struct brcms_hardware
*wlc_hw
)
1469 wlc_hw
->mute_override
= 1;
1471 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1472 * override, then there is no change to write
1474 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1477 brcms_c_mctrl_write(wlc_hw
);
1480 /* Clear the override on AP and INFRA bits */
1481 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware
*wlc_hw
)
1483 if (wlc_hw
->mute_override
== 0)
1486 wlc_hw
->mute_override
= 0;
1488 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1489 * override, then there is no change to write
1491 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1494 brcms_c_mctrl_write(wlc_hw
);
1498 * Write a MAC address to the given match reg offset in the RXE match engine.
1501 brcms_b_set_addrmatch(struct brcms_hardware
*wlc_hw
, int match_reg_offset
,
1504 struct bcma_device
*core
= wlc_hw
->d11core
;
1509 brcms_dbg_rx(core
, "wl%d: brcms_b_set_addrmatch\n", wlc_hw
->unit
);
1511 mac_l
= addr
[0] | (addr
[1] << 8);
1512 mac_m
= addr
[2] | (addr
[3] << 8);
1513 mac_h
= addr
[4] | (addr
[5] << 8);
1515 /* enter the MAC addr into the RXE match registers */
1516 bcma_write16(core
, D11REGOFFS(rcm_ctl
),
1517 RCM_INC_DATA
| match_reg_offset
);
1518 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_l
);
1519 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_m
);
1520 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_h
);
1524 brcms_b_write_template_ram(struct brcms_hardware
*wlc_hw
, int offset
, int len
,
1527 struct bcma_device
*core
= wlc_hw
->d11core
;
1532 brcms_dbg_info(core
, "wl%d\n", wlc_hw
->unit
);
1534 bcma_write32(core
, D11REGOFFS(tplatewrptr
), offset
);
1536 /* if MCTL_BIGEND bit set in mac control register,
1537 * the chip swaps data in fifo, as well as data in
1540 be_bit
= (bcma_read32(core
, D11REGOFFS(maccontrol
)) & MCTL_BIGEND
) != 0;
1543 memcpy(&word
, buf
, sizeof(u32
));
1546 word_be
= cpu_to_be32(word
);
1547 word
= *(u32
*)&word_be
;
1549 word_le
= cpu_to_le32(word
);
1550 word
= *(u32
*)&word_le
;
1553 bcma_write32(core
, D11REGOFFS(tplatewrdata
), word
);
1555 buf
= (u8
*) buf
+ sizeof(u32
);
1560 static void brcms_b_set_cwmin(struct brcms_hardware
*wlc_hw
, u16 newmin
)
1562 wlc_hw
->band
->CWmin
= newmin
;
1564 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
1565 OBJADDR_SCR_SEL
| S_DOT11_CWMIN
);
1566 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
1567 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), newmin
);
1570 static void brcms_b_set_cwmax(struct brcms_hardware
*wlc_hw
, u16 newmax
)
1572 wlc_hw
->band
->CWmax
= newmax
;
1574 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
1575 OBJADDR_SCR_SEL
| S_DOT11_CWMAX
);
1576 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
1577 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), newmax
);
1580 void brcms_b_bw_set(struct brcms_hardware
*wlc_hw
, u16 bw
)
1584 /* request FAST clock if not on */
1585 fastclk
= wlc_hw
->forcefastclk
;
1587 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
1589 wlc_phy_bw_state_set(wlc_hw
->band
->pi
, bw
);
1591 brcms_b_phy_reset(wlc_hw
);
1592 wlc_phy_init(wlc_hw
->band
->pi
, wlc_phy_chanspec_get(wlc_hw
->band
->pi
));
1594 /* restore the clk */
1596 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
1599 static void brcms_b_upd_synthpu(struct brcms_hardware
*wlc_hw
)
1602 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1603 /* update SYNTHPU_DLY */
1605 if (BRCMS_ISLCNPHY(wlc
->band
))
1606 v
= SYNTHPU_DLY_LPPHY_US
;
1607 else if (BRCMS_ISNPHY(wlc
->band
) && (NREV_GE(wlc
->band
->phyrev
, 3)))
1608 v
= SYNTHPU_DLY_NPHY_US
;
1610 v
= SYNTHPU_DLY_BPHY_US
;
1612 brcms_b_write_shm(wlc_hw
, M_SYNTHPU_DLY
, v
);
1615 static void brcms_c_ucode_txant_set(struct brcms_hardware
*wlc_hw
)
1618 u16 phytxant
= wlc_hw
->bmac_phytxant
;
1619 u16 mask
= PHY_TXC_ANT_MASK
;
1621 /* set the Probe Response frame phy control word */
1622 phyctl
= brcms_b_read_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
);
1623 phyctl
= (phyctl
& ~mask
) | phytxant
;
1624 brcms_b_write_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
, phyctl
);
1626 /* set the Response (ACK/CTS) frame phy control word */
1627 phyctl
= brcms_b_read_shm(wlc_hw
, M_RSP_PCTLWD
);
1628 phyctl
= (phyctl
& ~mask
) | phytxant
;
1629 brcms_b_write_shm(wlc_hw
, M_RSP_PCTLWD
, phyctl
);
1632 static u16
brcms_b_ofdm_ratetable_offset(struct brcms_hardware
*wlc_hw
,
1637 struct plcp_signal_rate_lookup
{
1641 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1642 const struct plcp_signal_rate_lookup rate_lookup
[] = {
1643 {BRCM_RATE_6M
, 0xB},
1644 {BRCM_RATE_9M
, 0xF},
1645 {BRCM_RATE_12M
, 0xA},
1646 {BRCM_RATE_18M
, 0xE},
1647 {BRCM_RATE_24M
, 0x9},
1648 {BRCM_RATE_36M
, 0xD},
1649 {BRCM_RATE_48M
, 0x8},
1650 {BRCM_RATE_54M
, 0xC}
1653 for (i
= 0; i
< ARRAY_SIZE(rate_lookup
); i
++) {
1654 if (rate
== rate_lookup
[i
].rate
) {
1655 plcp_rate
= rate_lookup
[i
].signal_rate
;
1660 /* Find the SHM pointer to the rate table entry by looking in the
1663 return 2 * brcms_b_read_shm(wlc_hw
, M_RT_DIRMAP_A
+ (plcp_rate
* 2));
1666 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware
*wlc_hw
)
1670 BRCM_RATE_6M
, BRCM_RATE_9M
, BRCM_RATE_12M
, BRCM_RATE_18M
,
1671 BRCM_RATE_24M
, BRCM_RATE_36M
, BRCM_RATE_48M
, BRCM_RATE_54M
1677 if (!BRCMS_PHY_11N_CAP(wlc_hw
->band
))
1680 /* walk the phy rate table and update the entries */
1681 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
1684 entry_ptr
= brcms_b_ofdm_ratetable_offset(wlc_hw
, rate
);
1686 /* read the SHM Rate Table entry OFDM PCTL1 values */
1688 brcms_b_read_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
);
1690 /* modify the value */
1691 pctl1
&= ~PHY_TXC1_MODE_MASK
;
1692 pctl1
|= (wlc_hw
->hw_stf_ss_opmode
<< PHY_TXC1_MODE_SHIFT
);
1694 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1695 brcms_b_write_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
,
1700 /* band-specific init */
1701 static void brcms_b_bsinit(struct brcms_c_info
*wlc
, u16 chanspec
)
1703 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1705 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
1706 wlc_hw
->band
->bandunit
);
1708 brcms_c_ucode_bsinit(wlc_hw
);
1710 wlc_phy_init(wlc_hw
->band
->pi
, chanspec
);
1712 brcms_c_ucode_txant_set(wlc_hw
);
1715 * cwmin is band-specific, update hardware
1716 * with value for current band
1718 brcms_b_set_cwmin(wlc_hw
, wlc_hw
->band
->CWmin
);
1719 brcms_b_set_cwmax(wlc_hw
, wlc_hw
->band
->CWmax
);
1721 brcms_b_update_slot_timing(wlc_hw
,
1722 wlc_hw
->band
->bandtype
== BRCM_BAND_5G
?
1723 true : wlc_hw
->shortslot
);
1725 /* write phytype and phyvers */
1726 brcms_b_write_shm(wlc_hw
, M_PHYTYPE
, (u16
) wlc_hw
->band
->phytype
);
1727 brcms_b_write_shm(wlc_hw
, M_PHYVER
, (u16
) wlc_hw
->band
->phyrev
);
1730 * initialize the txphyctl1 rate table since
1731 * shmem is shared between bands
1733 brcms_upd_ofdm_pctl1_table(wlc_hw
);
1735 brcms_b_upd_synthpu(wlc_hw
);
1738 /* Perform a soft reset of the PHY PLL */
1739 void brcms_b_core_phypll_reset(struct brcms_hardware
*wlc_hw
)
1741 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_addr
),
1744 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1747 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1750 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1755 /* light way to turn on phy clock without reset for NPHY only
1756 * refer to brcms_b_core_phy_clk for full version
1758 void brcms_b_phyclk_fgc(struct brcms_hardware
*wlc_hw
, bool clk
)
1760 /* support(necessary for NPHY and HYPHY) only */
1761 if (!BRCMS_ISNPHY(wlc_hw
->band
))
1765 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, SICF_FGC
);
1767 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, 0);
1771 void brcms_b_macphyclk_set(struct brcms_hardware
*wlc_hw
, bool clk
)
1774 brcms_b_core_ioctl(wlc_hw
, SICF_MPCLKE
, SICF_MPCLKE
);
1776 brcms_b_core_ioctl(wlc_hw
, SICF_MPCLKE
, 0);
1779 void brcms_b_phy_reset(struct brcms_hardware
*wlc_hw
)
1781 struct brcms_phy_pub
*pih
= wlc_hw
->band
->pi
;
1783 bool phy_in_reset
= false;
1785 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: reset phy\n", wlc_hw
->unit
);
1790 phy_bw_clkbits
= wlc_phy_clk_bwbits(wlc_hw
->band
->pi
);
1792 /* Specific reset sequence required for NPHY rev 3 and 4 */
1793 if (BRCMS_ISNPHY(wlc_hw
->band
) && NREV_GE(wlc_hw
->band
->phyrev
, 3) &&
1794 NREV_LE(wlc_hw
->band
->phyrev
, 4)) {
1795 /* Set the PHY bandwidth */
1796 brcms_b_core_ioctl(wlc_hw
, SICF_BWMASK
, phy_bw_clkbits
);
1800 /* Perform a soft reset of the PHY PLL */
1801 brcms_b_core_phypll_reset(wlc_hw
);
1804 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_PCLKE
),
1805 (SICF_PRST
| SICF_PCLKE
));
1806 phy_in_reset
= true;
1808 brcms_b_core_ioctl(wlc_hw
,
1809 (SICF_PRST
| SICF_PCLKE
| SICF_BWMASK
),
1810 (SICF_PRST
| SICF_PCLKE
| phy_bw_clkbits
));
1814 brcms_b_core_phy_clk(wlc_hw
, ON
);
1817 wlc_phy_anacore(pih
, ON
);
1820 /* switch to and initialize new band */
1821 static void brcms_b_setband(struct brcms_hardware
*wlc_hw
, uint bandunit
,
1823 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1826 /* Enable the d11 core before accessing it */
1827 if (!bcma_core_is_enabled(wlc_hw
->d11core
)) {
1828 bcma_core_enable(wlc_hw
->d11core
, 0);
1829 brcms_c_mctrl_reset(wlc_hw
);
1832 macintmask
= brcms_c_setband_inact(wlc
, bandunit
);
1837 brcms_b_core_phy_clk(wlc_hw
, ON
);
1839 /* band-specific initializations */
1840 brcms_b_bsinit(wlc
, chanspec
);
1843 * If there are any pending software interrupt bits,
1844 * then replace these with a harmless nonzero value
1845 * so brcms_c_dpc() will re-enable interrupts when done.
1847 if (wlc
->macintstatus
)
1848 wlc
->macintstatus
= MI_DMAINT
;
1850 /* restore macintmask */
1851 brcms_intrsrestore(wlc
->wl
, macintmask
);
1853 /* ucode should still be suspended.. */
1854 WARN_ON((bcma_read32(wlc_hw
->d11core
, D11REGOFFS(maccontrol
)) &
1858 static bool brcms_c_isgoodchip(struct brcms_hardware
*wlc_hw
)
1861 /* reject unsupported corerev */
1862 if (!CONF_HAS(D11CONF
, wlc_hw
->corerev
)) {
1863 wiphy_err(wlc_hw
->wlc
->wiphy
, "unsupported core rev %d\n",
1871 /* Validate some board info parameters */
1872 static bool brcms_c_validboardtype(struct brcms_hardware
*wlc_hw
)
1874 uint boardrev
= wlc_hw
->boardrev
;
1876 /* 4 bits each for board type, major, minor, and tiny version */
1877 uint brt
= (boardrev
& 0xf000) >> 12;
1878 uint b0
= (boardrev
& 0xf00) >> 8;
1879 uint b1
= (boardrev
& 0xf0) >> 4;
1880 uint b2
= boardrev
& 0xf;
1882 /* voards from other vendors are always considered valid */
1883 if (ai_get_boardvendor(wlc_hw
->sih
) != PCI_VENDOR_ID_BROADCOM
)
1886 /* do some boardrev sanity checks when boardvendor is Broadcom */
1890 if (boardrev
<= 0xff)
1893 if ((brt
> 2) || (brt
== 0) || (b0
> 9) || (b0
== 0) || (b1
> 9)
1900 static void brcms_c_get_macaddr(struct brcms_hardware
*wlc_hw
, u8 etheraddr
[ETH_ALEN
])
1902 struct ssb_sprom
*sprom
= &wlc_hw
->d11core
->bus
->sprom
;
1904 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1905 if (!is_zero_ether_addr(sprom
->il0mac
)) {
1906 memcpy(etheraddr
, sprom
->il0mac
, 6);
1910 if (wlc_hw
->_nbands
> 1)
1911 memcpy(etheraddr
, sprom
->et1mac
, 6);
1913 memcpy(etheraddr
, sprom
->il0mac
, 6);
1916 /* power both the pll and external oscillator on/off */
1917 static void brcms_b_xtal(struct brcms_hardware
*wlc_hw
, bool want
)
1919 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: want %d\n", wlc_hw
->unit
, want
);
1922 * dont power down if plldown is false or
1923 * we must poll hw radio disable
1925 if (!want
&& wlc_hw
->pllreq
)
1928 wlc_hw
->sbclk
= want
;
1929 if (!wlc_hw
->sbclk
) {
1930 wlc_hw
->clk
= false;
1931 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
1932 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
1937 * Return true if radio is disabled, otherwise false.
1938 * hw radio disable signal is an external pin, users activate it asynchronously
1939 * this function could be called when driver is down and w/o clock
1940 * it operates on different registers depending on corerev and boardflag.
1942 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware
*wlc_hw
)
1947 xtal
= wlc_hw
->sbclk
;
1949 brcms_b_xtal(wlc_hw
, ON
);
1951 /* may need to take core out of reset first */
1955 * mac no longer enables phyclk automatically when driver
1956 * accesses phyreg throughput mac. This can be skipped since
1957 * only mac reg is accessed below
1959 if (D11REV_GE(wlc_hw
->corerev
, 18))
1960 flags
|= SICF_PCLKE
;
1963 * TODO: test suspend/resume
1965 * AI chip doesn't restore bar0win2 on
1966 * hibernation/resume, need sw fixup
1969 bcma_core_enable(wlc_hw
->d11core
, flags
);
1970 brcms_c_mctrl_reset(wlc_hw
);
1973 v
= ((bcma_read32(wlc_hw
->d11core
,
1974 D11REGOFFS(phydebug
)) & PDBG_RFD
) != 0);
1976 /* put core back into reset */
1978 bcma_core_disable(wlc_hw
->d11core
, 0);
1981 brcms_b_xtal(wlc_hw
, OFF
);
1986 static bool wlc_dma_rxreset(struct brcms_hardware
*wlc_hw
, uint fifo
)
1988 struct dma_pub
*di
= wlc_hw
->di
[fifo
];
1989 return dma_rxreset(di
);
1993 * ensure fask clock during reset
1995 * reset d11(out of reset)
1996 * reset phy(out of reset)
1997 * clear software macintstatus for fresh new start
1998 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2000 void brcms_b_corereset(struct brcms_hardware
*wlc_hw
, u32 flags
)
2005 if (flags
== BRCMS_USE_COREFLAGS
)
2006 flags
= (wlc_hw
->band
->pi
? wlc_hw
->band
->core_flags
: 0);
2008 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: core reset\n", wlc_hw
->unit
);
2010 /* request FAST clock if not on */
2011 fastclk
= wlc_hw
->forcefastclk
;
2013 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
2015 /* reset the dma engines except first time thru */
2016 if (bcma_core_is_enabled(wlc_hw
->d11core
)) {
2017 for (i
= 0; i
< NFIFO
; i
++)
2018 if ((wlc_hw
->di
[i
]) && (!dma_txreset(wlc_hw
->di
[i
])))
2019 brcms_err(wlc_hw
->d11core
, "wl%d: %s: "
2020 "dma_txreset[%d]: cannot stop dma\n",
2021 wlc_hw
->unit
, __func__
, i
);
2023 if ((wlc_hw
->di
[RX_FIFO
])
2024 && (!wlc_dma_rxreset(wlc_hw
, RX_FIFO
)))
2025 brcms_err(wlc_hw
->d11core
, "wl%d: %s: dma_rxreset"
2026 "[%d]: cannot stop dma\n",
2027 wlc_hw
->unit
, __func__
, RX_FIFO
);
2029 /* if noreset, just stop the psm and return */
2030 if (wlc_hw
->noreset
) {
2031 wlc_hw
->wlc
->macintstatus
= 0; /* skip wl_dpc after down */
2032 brcms_b_mctrl(wlc_hw
, MCTL_PSM_RUN
| MCTL_EN_MAC
, 0);
2037 * mac no longer enables phyclk automatically when driver accesses
2038 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2039 * band->pi is invalid. need to enable PHY CLK
2041 if (D11REV_GE(wlc_hw
->corerev
, 18))
2042 flags
|= SICF_PCLKE
;
2046 * In chips with PMU, the fastclk request goes through d11 core
2047 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2049 * This adds some delay and we can optimize it by also requesting
2050 * fastclk through chipcommon during this period if necessary. But
2051 * that has to work coordinate with other driver like mips/arm since
2052 * they may touch chipcommon as well.
2054 wlc_hw
->clk
= false;
2055 bcma_core_enable(wlc_hw
->d11core
, flags
);
2057 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
2058 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, true);
2060 brcms_c_mctrl_reset(wlc_hw
);
2062 if (ai_get_cccaps(wlc_hw
->sih
) & CC_CAP_PMU
)
2063 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
2065 brcms_b_phy_reset(wlc_hw
);
2067 /* turn on PHY_PLL */
2068 brcms_b_core_phypll_ctl(wlc_hw
, true);
2070 /* clear sw intstatus */
2071 wlc_hw
->wlc
->macintstatus
= 0;
2073 /* restore the clk setting */
2075 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
2078 /* txfifo sizes needs to be modified(increased) since the newer cores
2081 static void brcms_b_corerev_fifofixup(struct brcms_hardware
*wlc_hw
)
2083 struct bcma_device
*core
= wlc_hw
->d11core
;
2085 u16 txfifo_startblk
= TXFIFO_START_BLK
, txfifo_endblk
;
2086 u16 txfifo_def
, txfifo_def1
;
2089 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2090 txfifo_startblk
= TXFIFO_START_BLK
;
2092 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2093 for (fifo_nu
= 0; fifo_nu
< NFIFO
; fifo_nu
++) {
2095 txfifo_endblk
= txfifo_startblk
+ wlc_hw
->xmtfifo_sz
[fifo_nu
];
2096 txfifo_def
= (txfifo_startblk
& 0xff) |
2097 (((txfifo_endblk
- 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT
);
2098 txfifo_def1
= ((txfifo_startblk
>> 8) & 0x1) |
2100 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT
);
2102 TXFIFOCMD_RESET_MASK
| (fifo_nu
<< TXFIFOCMD_FIFOSEL_SHIFT
);
2104 bcma_write16(core
, D11REGOFFS(xmtfifocmd
), txfifo_cmd
);
2105 bcma_write16(core
, D11REGOFFS(xmtfifodef
), txfifo_def
);
2106 bcma_write16(core
, D11REGOFFS(xmtfifodef1
), txfifo_def1
);
2108 bcma_write16(core
, D11REGOFFS(xmtfifocmd
), txfifo_cmd
);
2110 txfifo_startblk
+= wlc_hw
->xmtfifo_sz
[fifo_nu
];
2113 * need to propagate to shm location to be in sync since ucode/hw won't
2116 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE0
,
2117 wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]);
2118 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE1
,
2119 wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]);
2120 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE2
,
2121 ((wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
] << 8) | wlc_hw
->
2122 xmtfifo_sz
[TX_AC_BK_FIFO
]));
2123 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE3
,
2124 ((wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
] << 8) | wlc_hw
->
2125 xmtfifo_sz
[TX_BCMC_FIFO
]));
2128 /* This function is used for changing the tsf frac register
2129 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2130 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2131 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2132 * HTPHY Formula is 2^26/freq(MHz) e.g.
2133 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2134 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2135 * For spuron: 123MHz -> 2^26/123 = 545600.5
2136 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2137 * For spur off: 120MHz -> 2^26/120 = 559240.5
2138 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2141 void brcms_b_switch_macfreq(struct brcms_hardware
*wlc_hw
, u8 spurmode
)
2143 struct bcma_device
*core
= wlc_hw
->d11core
;
2145 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43224
) ||
2146 (ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43225
)) {
2147 if (spurmode
== WL_SPURAVOID_ON2
) { /* 126Mhz */
2148 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x2082);
2149 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2150 } else if (spurmode
== WL_SPURAVOID_ON1
) { /* 123Mhz */
2151 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x5341);
2152 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2153 } else { /* 120Mhz */
2154 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x8889);
2155 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2157 } else if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
2158 if (spurmode
== WL_SPURAVOID_ON1
) { /* 82Mhz */
2159 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x7CE0);
2160 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0xC);
2161 } else { /* 80Mhz */
2162 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0xCCCD);
2163 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0xC);
2168 /* Initialize GPIOs that are controlled by D11 core */
2169 static void brcms_c_gpio_init(struct brcms_c_info
*wlc
)
2171 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2174 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2175 brcms_b_mctrl(wlc_hw
, MCTL_GPOUT_SEL_MASK
, 0);
2178 * Common GPIO setup:
2179 * G0 = LED 0 = WLAN Activity
2180 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2181 * G2 = LED 2 = WLAN 5 GHz Radio State
2182 * G4 = radio disable input (HI enabled, LO disabled)
2187 /* Allocate GPIOs for mimo antenna diversity feature */
2188 if (wlc_hw
->antsel_type
== ANTSEL_2x3
) {
2189 /* Enable antenna diversity, use 2x3 mode */
2190 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2191 MHF3_ANTSEL_EN
, BRCM_BAND_ALL
);
2192 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
,
2193 MHF3_ANTSEL_MODE
, BRCM_BAND_ALL
);
2195 /* init superswitch control */
2196 wlc_phy_antsel_init(wlc_hw
->band
->pi
, false);
2198 } else if (wlc_hw
->antsel_type
== ANTSEL_2x4
) {
2199 gm
|= gc
|= (BOARD_GPIO_12
| BOARD_GPIO_13
);
2201 * The board itself is powered by these GPIOs
2202 * (when not sending pattern) so set them high
2204 bcma_set16(wlc_hw
->d11core
, D11REGOFFS(psm_gpio_oe
),
2205 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2206 bcma_set16(wlc_hw
->d11core
, D11REGOFFS(psm_gpio_out
),
2207 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2209 /* Enable antenna diversity, use 2x4 mode */
2210 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2211 MHF3_ANTSEL_EN
, BRCM_BAND_ALL
);
2212 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
, 0,
2215 /* Configure the desired clock to be 4Mhz */
2216 brcms_b_write_shm(wlc_hw
, M_ANTSEL_CLKDIV
,
2217 ANTSEL_CLKDIV_4MHZ
);
2221 * gpio 9 controls the PA. ucode is responsible
2222 * for wiggling out and oe
2224 if (wlc_hw
->boardflags
& BFL_PACTRL
)
2225 gm
|= gc
|= BOARD_GPIO_PACTRL
;
2227 /* apply to gpiocontrol register */
2228 bcma_chipco_gpio_control(&wlc_hw
->d11core
->bus
->drv_cc
, gm
, gc
);
2231 static void brcms_ucode_write(struct brcms_hardware
*wlc_hw
,
2232 const __le32 ucode
[], const size_t nbytes
)
2234 struct bcma_device
*core
= wlc_hw
->d11core
;
2238 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
2240 count
= (nbytes
/ sizeof(u32
));
2242 bcma_write32(core
, D11REGOFFS(objaddr
),
2243 OBJADDR_AUTO_INC
| OBJADDR_UCM_SEL
);
2244 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2245 for (i
= 0; i
< count
; i
++)
2246 bcma_write32(core
, D11REGOFFS(objdata
), le32_to_cpu(ucode
[i
]));
2250 static void brcms_ucode_download(struct brcms_hardware
*wlc_hw
)
2252 struct brcms_c_info
*wlc
;
2253 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
2257 if (wlc_hw
->ucode_loaded
)
2260 if (D11REV_IS(wlc_hw
->corerev
, 17) || D11REV_IS(wlc_hw
->corerev
, 23)) {
2261 if (BRCMS_ISNPHY(wlc_hw
->band
)) {
2262 brcms_ucode_write(wlc_hw
, ucode
->bcm43xx_16_mimo
,
2263 ucode
->bcm43xx_16_mimosz
);
2264 wlc_hw
->ucode_loaded
= true;
2266 brcms_err(wlc_hw
->d11core
,
2267 "%s: wl%d: unsupported phy in corerev %d\n",
2268 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2269 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2270 if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
2271 brcms_ucode_write(wlc_hw
, ucode
->bcm43xx_24_lcn
,
2272 ucode
->bcm43xx_24_lcnsz
);
2273 wlc_hw
->ucode_loaded
= true;
2275 brcms_err(wlc_hw
->d11core
,
2276 "%s: wl%d: unsupported phy in corerev %d\n",
2277 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2282 void brcms_b_txant_set(struct brcms_hardware
*wlc_hw
, u16 phytxant
)
2284 /* update sw state */
2285 wlc_hw
->bmac_phytxant
= phytxant
;
2287 /* push to ucode if up */
2290 brcms_c_ucode_txant_set(wlc_hw
);
2294 u16
brcms_b_get_txant(struct brcms_hardware
*wlc_hw
)
2296 return (u16
) wlc_hw
->wlc
->stf
->txant
;
2299 void brcms_b_antsel_type_set(struct brcms_hardware
*wlc_hw
, u8 antsel_type
)
2301 wlc_hw
->antsel_type
= antsel_type
;
2303 /* Update the antsel type for phy module to use */
2304 wlc_phy_antsel_type_set(wlc_hw
->band
->pi
, antsel_type
);
2307 static void brcms_b_fifoerrors(struct brcms_hardware
*wlc_hw
)
2311 uint intstatus
, idx
;
2312 struct bcma_device
*core
= wlc_hw
->d11core
;
2314 unit
= wlc_hw
->unit
;
2316 for (idx
= 0; idx
< NFIFO
; idx
++) {
2317 /* read intstatus register and ignore any non-error bits */
2320 D11REGOFFS(intctrlregs
[idx
].intstatus
)) &
2325 brcms_dbg_int(core
, "wl%d: intstatus%d 0x%x\n",
2326 unit
, idx
, intstatus
);
2328 if (intstatus
& I_RO
) {
2329 brcms_err(core
, "wl%d: fifo %d: receive fifo "
2330 "overflow\n", unit
, idx
);
2334 if (intstatus
& I_PC
) {
2335 brcms_err(core
, "wl%d: fifo %d: descriptor error\n",
2340 if (intstatus
& I_PD
) {
2341 brcms_err(core
, "wl%d: fifo %d: data error\n", unit
,
2346 if (intstatus
& I_DE
) {
2347 brcms_err(core
, "wl%d: fifo %d: descriptor protocol "
2348 "error\n", unit
, idx
);
2352 if (intstatus
& I_RU
)
2353 brcms_err(core
, "wl%d: fifo %d: receive descriptor "
2354 "underflow\n", idx
, unit
);
2356 if (intstatus
& I_XU
) {
2357 brcms_err(core
, "wl%d: fifo %d: transmit fifo "
2358 "underflow\n", idx
, unit
);
2363 brcms_fatal_error(wlc_hw
->wlc
->wl
); /* big hammer */
2367 D11REGOFFS(intctrlregs
[idx
].intstatus
),
2372 void brcms_c_intrson(struct brcms_c_info
*wlc
)
2374 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2375 wlc
->macintmask
= wlc
->defmacintmask
;
2376 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), wlc
->macintmask
);
2379 u32
brcms_c_intrsoff(struct brcms_c_info
*wlc
)
2381 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2387 macintmask
= wlc
->macintmask
; /* isr can still happen */
2389 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), 0);
2390 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(macintmask
));
2391 udelay(1); /* ensure int line is no longer driven */
2392 wlc
->macintmask
= 0;
2394 /* return previous macintmask; resolve race between us and our isr */
2395 return wlc
->macintstatus
? 0 : macintmask
;
2398 void brcms_c_intrsrestore(struct brcms_c_info
*wlc
, u32 macintmask
)
2400 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2404 wlc
->macintmask
= macintmask
;
2405 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), wlc
->macintmask
);
2408 /* assumes that the d11 MAC is enabled */
2409 static void brcms_b_tx_fifo_suspend(struct brcms_hardware
*wlc_hw
,
2412 u8 fifo
= 1 << tx_fifo
;
2414 /* Two clients of this code, 11h Quiet period and scanning. */
2416 /* only suspend if not already suspended */
2417 if ((wlc_hw
->suspended_fifos
& fifo
) == fifo
)
2420 /* force the core awake only if not already */
2421 if (wlc_hw
->suspended_fifos
== 0)
2422 brcms_c_ucode_wake_override_set(wlc_hw
,
2423 BRCMS_WAKE_OVERRIDE_TXFIFO
);
2425 wlc_hw
->suspended_fifos
|= fifo
;
2427 if (wlc_hw
->di
[tx_fifo
]) {
2429 * Suspending AMPDU transmissions in the middle can cause
2430 * underflow which may result in mismatch between ucode and
2431 * driver so suspend the mac before suspending the FIFO
2433 if (BRCMS_PHY_11N_CAP(wlc_hw
->band
))
2434 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
2436 dma_txsuspend(wlc_hw
->di
[tx_fifo
]);
2438 if (BRCMS_PHY_11N_CAP(wlc_hw
->band
))
2439 brcms_c_enable_mac(wlc_hw
->wlc
);
2443 static void brcms_b_tx_fifo_resume(struct brcms_hardware
*wlc_hw
,
2446 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2447 * but need to be done here for PIO otherwise the watchdog will catch
2448 * the inconsistency and fire
2450 /* Two clients of this code, 11h Quiet period and scanning. */
2451 if (wlc_hw
->di
[tx_fifo
])
2452 dma_txresume(wlc_hw
->di
[tx_fifo
]);
2454 /* allow core to sleep again */
2455 if (wlc_hw
->suspended_fifos
== 0)
2458 wlc_hw
->suspended_fifos
&= ~(1 << tx_fifo
);
2459 if (wlc_hw
->suspended_fifos
== 0)
2460 brcms_c_ucode_wake_override_clear(wlc_hw
,
2461 BRCMS_WAKE_OVERRIDE_TXFIFO
);
2465 /* precondition: requires the mac core to be enabled */
2466 static void brcms_b_mute(struct brcms_hardware
*wlc_hw
, bool mute_tx
)
2468 static const u8 null_ether_addr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
2471 /* suspend tx fifos */
2472 brcms_b_tx_fifo_suspend(wlc_hw
, TX_DATA_FIFO
);
2473 brcms_b_tx_fifo_suspend(wlc_hw
, TX_CTL_FIFO
);
2474 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_BK_FIFO
);
2475 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_VI_FIFO
);
2477 /* zero the address match register so we do not send ACKs */
2478 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2481 /* resume tx fifos */
2482 brcms_b_tx_fifo_resume(wlc_hw
, TX_DATA_FIFO
);
2483 brcms_b_tx_fifo_resume(wlc_hw
, TX_CTL_FIFO
);
2484 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_BK_FIFO
);
2485 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_VI_FIFO
);
2487 /* Restore address */
2488 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2492 wlc_phy_mute_upd(wlc_hw
->band
->pi
, mute_tx
, 0);
2495 brcms_c_ucode_mute_override_set(wlc_hw
);
2497 brcms_c_ucode_mute_override_clear(wlc_hw
);
2501 brcms_c_mute(struct brcms_c_info
*wlc
, bool mute_tx
)
2503 brcms_b_mute(wlc
->hw
, mute_tx
);
2507 * Read and clear macintmask and macintstatus and intstatus registers.
2508 * This routine should be called with interrupts off
2510 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2511 * 0 if the interrupt is not for us, or we are in some special cases;
2512 * device interrupt status bits otherwise.
2514 static inline u32
wlc_intstatus(struct brcms_c_info
*wlc
, bool in_isr
)
2516 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2517 struct bcma_device
*core
= wlc_hw
->d11core
;
2518 u32 macintstatus
, mask
;
2520 /* macintstatus includes a DMA interrupt summary bit */
2521 macintstatus
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2522 mask
= in_isr
? wlc
->macintmask
: wlc
->defmacintmask
;
2524 trace_brcms_macintstatus(&core
->dev
, in_isr
, macintstatus
, mask
);
2526 /* detect cardbus removed, in power down(suspend) and in reset */
2527 if (brcms_deviceremoved(wlc
))
2530 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2531 * handle that case here.
2533 if (macintstatus
== 0xffffffff)
2536 /* defer unsolicited interrupts */
2537 macintstatus
&= mask
;
2540 if (macintstatus
== 0)
2543 /* turn off the interrupts */
2544 bcma_write32(core
, D11REGOFFS(macintmask
), 0);
2545 (void)bcma_read32(core
, D11REGOFFS(macintmask
));
2546 wlc
->macintmask
= 0;
2548 /* clear device interrupts */
2549 bcma_write32(core
, D11REGOFFS(macintstatus
), macintstatus
);
2551 /* MI_DMAINT is indication of non-zero intstatus */
2552 if (macintstatus
& MI_DMAINT
)
2554 * only fifo interrupt enabled is I_RI in
2555 * RX_FIFO. If MI_DMAINT is set, assume it
2556 * is set and clear the interrupt.
2558 bcma_write32(core
, D11REGOFFS(intctrlregs
[RX_FIFO
].intstatus
),
2561 return macintstatus
;
2564 /* Update wlc->macintstatus and wlc->intstatus[]. */
2565 /* Return true if they are updated successfully. false otherwise */
2566 bool brcms_c_intrsupd(struct brcms_c_info
*wlc
)
2570 /* read and clear macintstatus and intstatus registers */
2571 macintstatus
= wlc_intstatus(wlc
, false);
2573 /* device is removed */
2574 if (macintstatus
== 0xffffffff)
2577 /* update interrupt status in software */
2578 wlc
->macintstatus
|= macintstatus
;
2584 * First-level interrupt processing.
2585 * Return true if this was our interrupt
2586 * and if further brcms_c_dpc() processing is required,
2589 bool brcms_c_isr(struct brcms_c_info
*wlc
)
2591 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2594 if (!wlc_hw
->up
|| !wlc
->macintmask
)
2597 /* read and clear macintstatus and intstatus registers */
2598 macintstatus
= wlc_intstatus(wlc
, true);
2600 if (macintstatus
== 0xffffffff) {
2601 brcms_err(wlc_hw
->d11core
,
2602 "DEVICEREMOVED detected in the ISR code path\n");
2606 /* it is not for us */
2607 if (macintstatus
== 0)
2610 /* save interrupt status bits */
2611 wlc
->macintstatus
= macintstatus
;
2617 void brcms_c_suspend_mac_and_wait(struct brcms_c_info
*wlc
)
2619 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2620 struct bcma_device
*core
= wlc_hw
->d11core
;
2623 brcms_dbg_mac80211(core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
2624 wlc_hw
->band
->bandunit
);
2627 * Track overlapping suspend requests
2629 wlc_hw
->mac_suspend_depth
++;
2630 if (wlc_hw
->mac_suspend_depth
> 1)
2633 /* force the core awake */
2634 brcms_c_ucode_wake_override_set(wlc_hw
, BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
2636 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2638 if (mc
== 0xffffffff) {
2639 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2641 brcms_down(wlc
->wl
);
2644 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2645 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2646 WARN_ON(!(mc
& MCTL_EN_MAC
));
2648 mi
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2649 if (mi
== 0xffffffff) {
2650 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2652 brcms_down(wlc
->wl
);
2655 WARN_ON(mi
& MI_MACSSPNDD
);
2657 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, 0);
2659 SPINWAIT(!(bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
),
2660 BRCMS_MAX_MAC_SUSPEND
);
2662 if (!(bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
)) {
2663 brcms_err(core
, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2664 " and MI_MACSSPNDD is still not on.\n",
2665 wlc_hw
->unit
, BRCMS_MAX_MAC_SUSPEND
);
2666 brcms_err(core
, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2667 "psm_brc 0x%04x\n", wlc_hw
->unit
,
2668 bcma_read32(core
, D11REGOFFS(psmdebug
)),
2669 bcma_read32(core
, D11REGOFFS(phydebug
)),
2670 bcma_read16(core
, D11REGOFFS(psm_brc
)));
2673 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2674 if (mc
== 0xffffffff) {
2675 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2677 brcms_down(wlc
->wl
);
2680 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2681 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2682 WARN_ON(mc
& MCTL_EN_MAC
);
2685 void brcms_c_enable_mac(struct brcms_c_info
*wlc
)
2687 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2688 struct bcma_device
*core
= wlc_hw
->d11core
;
2691 brcms_dbg_mac80211(core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
2692 wlc
->band
->bandunit
);
2695 * Track overlapping suspend requests
2697 wlc_hw
->mac_suspend_depth
--;
2698 if (wlc_hw
->mac_suspend_depth
> 0)
2701 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2702 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2703 WARN_ON(mc
& MCTL_EN_MAC
);
2704 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2706 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, MCTL_EN_MAC
);
2707 bcma_write32(core
, D11REGOFFS(macintstatus
), MI_MACSSPNDD
);
2709 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2710 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2711 WARN_ON(!(mc
& MCTL_EN_MAC
));
2712 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2714 mi
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2715 WARN_ON(mi
& MI_MACSSPNDD
);
2717 brcms_c_ucode_wake_override_clear(wlc_hw
,
2718 BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
2721 void brcms_b_band_stf_ss_set(struct brcms_hardware
*wlc_hw
, u8 stf_mode
)
2723 wlc_hw
->hw_stf_ss_opmode
= stf_mode
;
2726 brcms_upd_ofdm_pctl1_table(wlc_hw
);
2729 static bool brcms_b_validate_chip_access(struct brcms_hardware
*wlc_hw
)
2731 struct bcma_device
*core
= wlc_hw
->d11core
;
2733 struct wiphy
*wiphy
= wlc_hw
->wlc
->wiphy
;
2735 /* Validate dchip register access */
2737 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2738 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2739 w
= bcma_read32(core
, D11REGOFFS(objdata
));
2741 /* Can we write and read back a 32bit register? */
2742 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2743 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2744 bcma_write32(core
, D11REGOFFS(objdata
), (u32
) 0xaa5555aa);
2746 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2747 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2748 val
= bcma_read32(core
, D11REGOFFS(objdata
));
2749 if (val
!= (u32
) 0xaa5555aa) {
2750 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
2751 "expected 0xaa5555aa\n", wlc_hw
->unit
, val
);
2755 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2756 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2757 bcma_write32(core
, D11REGOFFS(objdata
), (u32
) 0x55aaaa55);
2759 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2760 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2761 val
= bcma_read32(core
, D11REGOFFS(objdata
));
2762 if (val
!= (u32
) 0x55aaaa55) {
2763 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
2764 "expected 0x55aaaa55\n", wlc_hw
->unit
, val
);
2768 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2769 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2770 bcma_write32(core
, D11REGOFFS(objdata
), w
);
2772 /* clear CFPStart */
2773 bcma_write32(core
, D11REGOFFS(tsf_cfpstart
), 0);
2775 w
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2776 if ((w
!= (MCTL_IHR_EN
| MCTL_WAKE
)) &&
2777 (w
!= (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
))) {
2778 wiphy_err(wiphy
, "wl%d: validate_chip_access: maccontrol = "
2779 "0x%x, expected 0x%x or 0x%x\n", wlc_hw
->unit
, w
,
2780 (MCTL_IHR_EN
| MCTL_WAKE
),
2781 (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
));
2788 #define PHYPLL_WAIT_US 100000
2790 void brcms_b_core_phypll_ctl(struct brcms_hardware
*wlc_hw
, bool on
)
2792 struct bcma_device
*core
= wlc_hw
->d11core
;
2795 brcms_dbg_info(core
, "wl%d\n", wlc_hw
->unit
);
2800 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
2801 bcma_set32(core
, D11REGOFFS(clk_ctl_st
),
2803 CCS_ERSRC_REQ_D11PLL
|
2804 CCS_ERSRC_REQ_PHYPLL
);
2805 SPINWAIT((bcma_read32(core
, D11REGOFFS(clk_ctl_st
)) &
2806 CCS_ERSRC_AVAIL_HT
) != CCS_ERSRC_AVAIL_HT
,
2809 tmp
= bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2810 if ((tmp
& CCS_ERSRC_AVAIL_HT
) != CCS_ERSRC_AVAIL_HT
)
2811 brcms_err(core
, "%s: turn on PHY PLL failed\n",
2814 bcma_set32(core
, D11REGOFFS(clk_ctl_st
),
2815 tmp
| CCS_ERSRC_REQ_D11PLL
|
2816 CCS_ERSRC_REQ_PHYPLL
);
2817 SPINWAIT((bcma_read32(core
, D11REGOFFS(clk_ctl_st
)) &
2818 (CCS_ERSRC_AVAIL_D11PLL
|
2819 CCS_ERSRC_AVAIL_PHYPLL
)) !=
2820 (CCS_ERSRC_AVAIL_D11PLL
|
2821 CCS_ERSRC_AVAIL_PHYPLL
), PHYPLL_WAIT_US
);
2823 tmp
= bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2825 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
2827 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
2828 brcms_err(core
, "%s: turn on PHY PLL failed\n",
2833 * Since the PLL may be shared, other cores can still
2834 * be requesting it; so we'll deassert the request but
2835 * not wait for status to comply.
2837 bcma_mask32(core
, D11REGOFFS(clk_ctl_st
),
2838 ~CCS_ERSRC_REQ_PHYPLL
);
2839 (void)bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2843 static void brcms_c_coredisable(struct brcms_hardware
*wlc_hw
)
2847 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: disable core\n", wlc_hw
->unit
);
2849 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
2854 if (wlc_hw
->noreset
)
2858 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
2860 /* turn off analog core */
2861 wlc_phy_anacore(wlc_hw
->band
->pi
, OFF
);
2863 /* turn off PHYPLL to save power */
2864 brcms_b_core_phypll_ctl(wlc_hw
, false);
2866 wlc_hw
->clk
= false;
2867 bcma_core_disable(wlc_hw
->d11core
, 0);
2868 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
2871 static void brcms_c_flushqueues(struct brcms_c_info
*wlc
)
2873 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2876 /* free any posted tx packets */
2877 for (i
= 0; i
< NFIFO
; i
++) {
2878 if (wlc_hw
->di
[i
]) {
2879 dma_txreclaim(wlc_hw
->di
[i
], DMA_RANGE_ALL
);
2880 if (i
< TX_BCMC_FIFO
)
2881 ieee80211_wake_queue(wlc
->pub
->ieee_hw
,
2882 brcms_fifo_to_ac(i
));
2886 /* free any posted rx packets */
2887 dma_rxreclaim(wlc_hw
->di
[RX_FIFO
]);
2891 brcms_b_read_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, u32 sel
)
2893 struct bcma_device
*core
= wlc_hw
->d11core
;
2894 u16 objoff
= D11REGOFFS(objdata
);
2896 bcma_write32(core
, D11REGOFFS(objaddr
), sel
| (offset
>> 2));
2897 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2901 return bcma_read16(core
, objoff
);
2905 brcms_b_write_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, u16 v
,
2908 struct bcma_device
*core
= wlc_hw
->d11core
;
2909 u16 objoff
= D11REGOFFS(objdata
);
2911 bcma_write32(core
, D11REGOFFS(objaddr
), sel
| (offset
>> 2));
2912 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2916 bcma_wflush16(core
, objoff
, v
);
2920 * Read a single u16 from shared memory.
2921 * SHM 'offset' needs to be an even address
2923 u16
brcms_b_read_shm(struct brcms_hardware
*wlc_hw
, uint offset
)
2925 return brcms_b_read_objmem(wlc_hw
, offset
, OBJADDR_SHM_SEL
);
2929 * Write a single u16 to shared memory.
2930 * SHM 'offset' needs to be an even address
2932 void brcms_b_write_shm(struct brcms_hardware
*wlc_hw
, uint offset
, u16 v
)
2934 brcms_b_write_objmem(wlc_hw
, offset
, v
, OBJADDR_SHM_SEL
);
2938 * Copy a buffer to shared memory of specified type .
2939 * SHM 'offset' needs to be an even address and
2940 * Buffer length 'len' must be an even number of bytes
2941 * 'sel' selects the type of memory
2944 brcms_b_copyto_objmem(struct brcms_hardware
*wlc_hw
, uint offset
,
2945 const void *buf
, int len
, u32 sel
)
2948 const u8
*p
= (const u8
*)buf
;
2951 if (len
<= 0 || (offset
& 1) || (len
& 1))
2954 for (i
= 0; i
< len
; i
+= 2) {
2955 v
= p
[i
] | (p
[i
+ 1] << 8);
2956 brcms_b_write_objmem(wlc_hw
, offset
+ i
, v
, sel
);
2961 * Copy a piece of shared memory of specified type to a buffer .
2962 * SHM 'offset' needs to be an even address and
2963 * Buffer length 'len' must be an even number of bytes
2964 * 'sel' selects the type of memory
2967 brcms_b_copyfrom_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, void *buf
,
2974 if (len
<= 0 || (offset
& 1) || (len
& 1))
2977 for (i
= 0; i
< len
; i
+= 2) {
2978 v
= brcms_b_read_objmem(wlc_hw
, offset
+ i
, sel
);
2980 p
[i
+ 1] = (v
>> 8) & 0xFF;
2984 /* Copy a buffer to shared memory.
2985 * SHM 'offset' needs to be an even address and
2986 * Buffer length 'len' must be an even number of bytes
2988 static void brcms_c_copyto_shm(struct brcms_c_info
*wlc
, uint offset
,
2989 const void *buf
, int len
)
2991 brcms_b_copyto_objmem(wlc
->hw
, offset
, buf
, len
, OBJADDR_SHM_SEL
);
2994 static void brcms_b_retrylimit_upd(struct brcms_hardware
*wlc_hw
,
3000 /* write retry limit to SCR, shouldn't need to suspend */
3002 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
3003 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
3004 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
3005 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), wlc_hw
->SRL
);
3006 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
3007 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
3008 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
3009 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), wlc_hw
->LRL
);
3013 static void brcms_b_pllreq(struct brcms_hardware
*wlc_hw
, bool set
, u32 req_bit
)
3016 if (mboolisset(wlc_hw
->pllreq
, req_bit
))
3019 mboolset(wlc_hw
->pllreq
, req_bit
);
3021 if (mboolisset(wlc_hw
->pllreq
, BRCMS_PLLREQ_FLIP
)) {
3023 brcms_b_xtal(wlc_hw
, ON
);
3026 if (!mboolisset(wlc_hw
->pllreq
, req_bit
))
3029 mboolclr(wlc_hw
->pllreq
, req_bit
);
3031 if (mboolisset(wlc_hw
->pllreq
, BRCMS_PLLREQ_FLIP
)) {
3033 brcms_b_xtal(wlc_hw
, OFF
);
3038 static void brcms_b_antsel_set(struct brcms_hardware
*wlc_hw
, u32 antsel_avail
)
3040 wlc_hw
->antsel_avail
= antsel_avail
;
3044 * conditions under which the PM bit should be set in outgoing frames
3045 * and STAY_AWAKE is meaningful
3047 static bool brcms_c_ps_allowed(struct brcms_c_info
*wlc
)
3049 struct brcms_bss_cfg
*cfg
= wlc
->bsscfg
;
3051 /* disallow PS when one of the following global conditions meets */
3052 if (!wlc
->pub
->associated
)
3055 /* disallow PS when one of these meets when not scanning */
3056 if (wlc
->filter_flags
& FIF_PROMISC_IN_BSS
)
3059 if (cfg
->associated
) {
3061 * disallow PS when one of the following
3062 * bsscfg specific conditions meets
3073 static void brcms_c_statsupd(struct brcms_c_info
*wlc
)
3076 struct macstat macstats
;
3083 /* if driver down, make no sense to update stats */
3088 /* save last rx fifo 0 overflow count */
3089 rxf0ovfl
= wlc
->core
->macstat_snapshot
->rxf0ovfl
;
3091 /* save last tx fifo underflow count */
3092 for (i
= 0; i
< NFIFO
; i
++)
3093 txfunfl
[i
] = wlc
->core
->macstat_snapshot
->txfunfl
[i
];
3096 /* Read mac stats from contiguous shared memory */
3097 brcms_b_copyfrom_objmem(wlc
->hw
, M_UCODE_MACSTAT
, &macstats
,
3098 sizeof(struct macstat
), OBJADDR_SHM_SEL
);
3101 /* check for rx fifo 0 overflow */
3102 delta
= (u16
) (wlc
->core
->macstat_snapshot
->rxf0ovfl
- rxf0ovfl
);
3104 brcms_err(wlc
->hw
->d11core
, "wl%d: %u rx fifo 0 overflows!\n",
3105 wlc
->pub
->unit
, delta
);
3107 /* check for tx fifo underflows */
3108 for (i
= 0; i
< NFIFO
; i
++) {
3110 (u16
) (wlc
->core
->macstat_snapshot
->txfunfl
[i
] -
3113 brcms_err(wlc
->hw
->d11core
,
3114 "wl%d: %u tx fifo %d underflows!\n",
3115 wlc
->pub
->unit
, delta
, i
);
3119 /* merge counters from dma module */
3120 for (i
= 0; i
< NFIFO
; i
++) {
3122 dma_counterreset(wlc
->hw
->di
[i
]);
3126 static void brcms_b_reset(struct brcms_hardware
*wlc_hw
)
3128 /* reset the core */
3129 if (!brcms_deviceremoved(wlc_hw
->wlc
))
3130 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
3132 /* purge the dma rings */
3133 brcms_c_flushqueues(wlc_hw
->wlc
);
3136 void brcms_c_reset(struct brcms_c_info
*wlc
)
3138 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
3140 /* slurp up hw mac counters before core reset */
3141 brcms_c_statsupd(wlc
);
3143 /* reset our snapshot of macstat counters */
3144 memset((char *)wlc
->core
->macstat_snapshot
, 0,
3145 sizeof(struct macstat
));
3147 brcms_b_reset(wlc
->hw
);
3150 void brcms_c_init_scb(struct scb
*scb
)
3154 memset(scb
, 0, sizeof(struct scb
));
3155 scb
->flags
= SCB_WMECAP
| SCB_HTCAP
;
3156 for (i
= 0; i
< NUMPRIO
; i
++) {
3158 scb
->seqctl
[i
] = 0xFFFF;
3161 scb
->seqctl_nonqos
= 0xFFFF;
3162 scb
->magic
= SCB_MAGIC
;
3167 * download ucode/PCM
3168 * let ucode run to suspended
3169 * download ucode inits
3170 * config other core registers
3173 static void brcms_b_coreinit(struct brcms_c_info
*wlc
)
3175 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
3176 struct bcma_device
*core
= wlc_hw
->d11core
;
3180 bool fifosz_fixup
= false;
3183 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
3185 brcms_dbg_info(core
, "wl%d: core init\n", wlc_hw
->unit
);
3188 brcms_b_mctrl(wlc_hw
, ~0, (MCTL_IHR_EN
| MCTL_PSM_JMP_0
| MCTL_WAKE
));
3190 brcms_ucode_download(wlc_hw
);
3192 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3194 fifosz_fixup
= true;
3196 /* let the PSM run to the suspended state, set mode to BSS STA */
3197 bcma_write32(core
, D11REGOFFS(macintstatus
), -1);
3198 brcms_b_mctrl(wlc_hw
, ~0,
3199 (MCTL_IHR_EN
| MCTL_INFRA
| MCTL_PSM_RUN
| MCTL_WAKE
));
3201 /* wait for ucode to self-suspend after auto-init */
3202 SPINWAIT(((bcma_read32(core
, D11REGOFFS(macintstatus
)) &
3203 MI_MACSSPNDD
) == 0), 1000 * 1000);
3204 if ((bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
) == 0)
3205 brcms_err(core
, "wl%d: wlc_coreinit: ucode did not self-"
3206 "suspend!\n", wlc_hw
->unit
);
3208 brcms_c_gpio_init(wlc
);
3210 sflags
= bcma_aread32(core
, BCMA_IOST
);
3212 if (D11REV_IS(wlc_hw
->corerev
, 17) || D11REV_IS(wlc_hw
->corerev
, 23)) {
3213 if (BRCMS_ISNPHY(wlc_hw
->band
))
3214 brcms_c_write_inits(wlc_hw
, ucode
->d11n0initvals16
);
3216 brcms_err(core
, "%s: wl%d: unsupported phy in corerev"
3217 " %d\n", __func__
, wlc_hw
->unit
,
3219 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
3220 if (BRCMS_ISLCNPHY(wlc_hw
->band
))
3221 brcms_c_write_inits(wlc_hw
, ucode
->d11lcn0initvals24
);
3223 brcms_err(core
, "%s: wl%d: unsupported phy in corerev"
3224 " %d\n", __func__
, wlc_hw
->unit
,
3227 brcms_err(core
, "%s: wl%d: unsupported corerev %d\n",
3228 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
3231 /* For old ucode, txfifo sizes needs to be modified(increased) */
3233 brcms_b_corerev_fifofixup(wlc_hw
);
3235 /* check txfifo allocations match between ucode and driver */
3236 buf
[TX_AC_BE_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE0
);
3237 if (buf
[TX_AC_BE_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]) {
3241 buf
[TX_AC_VI_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE1
);
3242 if (buf
[TX_AC_VI_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]) {
3246 buf
[TX_AC_BK_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE2
);
3247 buf
[TX_AC_VO_FIFO
] = (buf
[TX_AC_BK_FIFO
] >> 8) & 0xff;
3248 buf
[TX_AC_BK_FIFO
] &= 0xff;
3249 if (buf
[TX_AC_BK_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BK_FIFO
]) {
3253 if (buf
[TX_AC_VO_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
]) {
3257 buf
[TX_BCMC_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE3
);
3258 buf
[TX_ATIM_FIFO
] = (buf
[TX_BCMC_FIFO
] >> 8) & 0xff;
3259 buf
[TX_BCMC_FIFO
] &= 0xff;
3260 if (buf
[TX_BCMC_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_BCMC_FIFO
]) {
3264 if (buf
[TX_ATIM_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
]) {
3269 brcms_err(core
, "wlc_coreinit: txfifo mismatch: ucode size %d"
3270 " driver size %d index %d\n", buf
[i
],
3271 wlc_hw
->xmtfifo_sz
[i
], i
);
3273 /* make sure we can still talk to the mac */
3274 WARN_ON(bcma_read32(core
, D11REGOFFS(maccontrol
)) == 0xffffffff);
3276 /* band-specific inits done by wlc_bsinit() */
3278 /* Set up frame burst size and antenna swap threshold init values */
3279 brcms_b_write_shm(wlc_hw
, M_MBURST_SIZE
, MAXTXFRAMEBURST
);
3280 brcms_b_write_shm(wlc_hw
, M_MAX_ANTCNT
, ANTCNT
);
3282 /* enable one rx interrupt per received frame */
3283 bcma_write32(core
, D11REGOFFS(intrcvlazy
[0]), (1 << IRL_FC_SHIFT
));
3285 /* set the station mode (BSS STA) */
3286 brcms_b_mctrl(wlc_hw
,
3287 (MCTL_INFRA
| MCTL_DISCARD_PMQ
| MCTL_AP
),
3288 (MCTL_INFRA
| MCTL_DISCARD_PMQ
));
3290 /* set up Beacon interval */
3291 bcnint_us
= 0x8000 << 10;
3292 bcma_write32(core
, D11REGOFFS(tsf_cfprep
),
3293 (bcnint_us
<< CFPREP_CBI_SHIFT
));
3294 bcma_write32(core
, D11REGOFFS(tsf_cfpstart
), bcnint_us
);
3295 bcma_write32(core
, D11REGOFFS(macintstatus
), MI_GP1
);
3297 /* write interrupt mask */
3298 bcma_write32(core
, D11REGOFFS(intctrlregs
[RX_FIFO
].intmask
),
3301 /* allow the MAC to control the PHY clock (dynamic on/off) */
3302 brcms_b_macphyclk_set(wlc_hw
, ON
);
3304 /* program dynamic clock control fast powerup delay register */
3305 wlc
->fastpwrup_dly
= ai_clkctl_fast_pwrup_delay(wlc_hw
->sih
);
3306 bcma_write16(core
, D11REGOFFS(scc_fastpwrup_dly
), wlc
->fastpwrup_dly
);
3308 /* tell the ucode the corerev */
3309 brcms_b_write_shm(wlc_hw
, M_MACHW_VER
, (u16
) wlc_hw
->corerev
);
3311 /* tell the ucode MAC capabilities */
3312 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_L
,
3313 (u16
) (wlc_hw
->machwcap
& 0xffff));
3314 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_H
,
3316 machwcap
>> 16) & 0xffff));
3318 /* write retry limits to SCR, this done after PSM init */
3319 bcma_write32(core
, D11REGOFFS(objaddr
),
3320 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
3321 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
3322 bcma_write32(core
, D11REGOFFS(objdata
), wlc_hw
->SRL
);
3323 bcma_write32(core
, D11REGOFFS(objaddr
),
3324 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
3325 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
3326 bcma_write32(core
, D11REGOFFS(objdata
), wlc_hw
->LRL
);
3328 /* write rate fallback retry limits */
3329 brcms_b_write_shm(wlc_hw
, M_SFRMTXCNTFBRTHSD
, wlc_hw
->SFBL
);
3330 brcms_b_write_shm(wlc_hw
, M_LFRMTXCNTFBRTHSD
, wlc_hw
->LFBL
);
3332 bcma_mask16(core
, D11REGOFFS(ifs_ctl
), 0x0FFF);
3333 bcma_write16(core
, D11REGOFFS(ifs_aifsn
), EDCF_AIFSN_MIN
);
3335 /* init the tx dma engines */
3336 for (i
= 0; i
< NFIFO
; i
++) {
3338 dma_txinit(wlc_hw
->di
[i
]);
3341 /* init the rx dma engine(s) and post receive buffers */
3342 dma_rxinit(wlc_hw
->di
[RX_FIFO
]);
3343 dma_rxfill(wlc_hw
->di
[RX_FIFO
]);
3347 static brcms_b_init(struct brcms_hardware
*wlc_hw
, u16 chanspec
) {
3350 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
3352 /* request FAST clock if not on */
3353 fastclk
= wlc_hw
->forcefastclk
;
3355 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
3357 /* disable interrupts */
3358 macintmask
= brcms_intrsoff(wlc
->wl
);
3360 /* set up the specified band and chanspec */
3361 brcms_c_setxband(wlc_hw
, chspec_bandunit(chanspec
));
3362 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
3364 /* do one-time phy inits and calibration */
3365 wlc_phy_cal_init(wlc_hw
->band
->pi
);
3367 /* core-specific initialization */
3368 brcms_b_coreinit(wlc
);
3370 /* band-specific inits */
3371 brcms_b_bsinit(wlc
, chanspec
);
3373 /* restore macintmask */
3374 brcms_intrsrestore(wlc
->wl
, macintmask
);
3376 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3377 * is suspended and brcms_c_enable_mac() will clear this override bit.
3379 mboolset(wlc_hw
->wake_override
, BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
3382 * initialize mac_suspend_depth to 1 to match ucode
3383 * initial suspended state
3385 wlc_hw
->mac_suspend_depth
= 1;
3387 /* restore the clk */
3389 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
3392 static void brcms_c_set_phy_chanspec(struct brcms_c_info
*wlc
,
3395 /* Save our copy of the chanspec */
3396 wlc
->chanspec
= chanspec
;
3398 /* Set the chanspec and power limits for this locale */
3399 brcms_c_channel_set_chanspec(wlc
->cmi
, chanspec
, BRCMS_TXPWR_MAX
);
3401 if (wlc
->stf
->ss_algosel_auto
)
3402 brcms_c_stf_ss_algo_channel_get(wlc
, &wlc
->stf
->ss_algo_channel
,
3405 brcms_c_stf_ss_update(wlc
, wlc
->band
);
3409 brcms_default_rateset(struct brcms_c_info
*wlc
, struct brcms_c_rateset
*rs
)
3411 brcms_c_rateset_default(rs
, NULL
, wlc
->band
->phytype
,
3412 wlc
->band
->bandtype
, false, BRCMS_RATE_MASK_FULL
,
3413 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
),
3414 brcms_chspec_bw(wlc
->default_bss
->chanspec
),
3415 wlc
->stf
->txstreams
);
3418 /* derive wlc->band->basic_rate[] table from 'rateset' */
3419 static void brcms_c_rate_lookup_init(struct brcms_c_info
*wlc
,
3420 struct brcms_c_rateset
*rateset
)
3426 u8
*br
= wlc
->band
->basic_rate
;
3429 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3430 memset(br
, 0, BRCM_MAXRATE
+ 1);
3432 /* For each basic rate in the rates list, make an entry in the
3433 * best basic lookup.
3435 for (i
= 0; i
< rateset
->count
; i
++) {
3436 /* only make an entry for a basic rate */
3437 if (!(rateset
->rates
[i
] & BRCMS_RATE_FLAG
))
3440 /* mask off basic bit */
3441 rate
= (rateset
->rates
[i
] & BRCMS_RATE_MASK
);
3443 if (rate
> BRCM_MAXRATE
) {
3444 brcms_err(wlc
->hw
->d11core
, "brcms_c_rate_lookup_init: "
3445 "invalid rate 0x%X in rate set\n",
3453 /* The rate lookup table now has non-zero entries for each
3454 * basic rate, equal to the basic rate: br[basicN] = basicN
3456 * To look up the best basic rate corresponding to any
3457 * particular rate, code can use the basic_rate table
3460 * basic_rate = wlc->band->basic_rate[tx_rate]
3462 * Make sure there is a best basic rate entry for
3463 * every rate by walking up the table from low rates
3464 * to high, filling in holes in the lookup table
3467 for (i
= 0; i
< wlc
->band
->hw_rateset
.count
; i
++) {
3468 rate
= wlc
->band
->hw_rateset
.rates
[i
];
3470 if (br
[rate
] != 0) {
3471 /* This rate is a basic rate.
3472 * Keep track of the best basic rate so far by
3475 if (is_ofdm_rate(rate
))
3483 /* This rate is not a basic rate so figure out the
3484 * best basic rate less than this rate and fill in
3485 * the hole in the table
3488 br
[rate
] = is_ofdm_rate(rate
) ? ofdm_basic
: cck_basic
;
3493 if (is_ofdm_rate(rate
)) {
3495 * In 11g and 11a, the OFDM mandatory rates
3496 * are 6, 12, and 24 Mbps
3498 if (rate
>= BRCM_RATE_24M
)
3499 mandatory
= BRCM_RATE_24M
;
3500 else if (rate
>= BRCM_RATE_12M
)
3501 mandatory
= BRCM_RATE_12M
;
3503 mandatory
= BRCM_RATE_6M
;
3505 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3509 br
[rate
] = mandatory
;
3513 static void brcms_c_bandinit_ordered(struct brcms_c_info
*wlc
,
3516 struct brcms_c_rateset default_rateset
;
3518 uint i
, band_order
[2];
3521 * We might have been bandlocked during down and the chip
3522 * power-cycled (hibernate). Figure out the right band to park on
3524 if (wlc
->bandlocked
|| wlc
->pub
->_nbands
== 1) {
3525 /* updated in brcms_c_bandlock() */
3526 parkband
= wlc
->band
->bandunit
;
3527 band_order
[0] = band_order
[1] = parkband
;
3529 /* park on the band of the specified chanspec */
3530 parkband
= chspec_bandunit(chanspec
);
3532 /* order so that parkband initialize last */
3533 band_order
[0] = parkband
^ 1;
3534 band_order
[1] = parkband
;
3537 /* make each band operational, software state init */
3538 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++) {
3539 uint j
= band_order
[i
];
3541 wlc
->band
= wlc
->bandstate
[j
];
3543 brcms_default_rateset(wlc
, &default_rateset
);
3545 /* fill in hw_rate */
3546 brcms_c_rateset_filter(&default_rateset
, &wlc
->band
->hw_rateset
,
3547 false, BRCMS_RATES_CCK_OFDM
, BRCMS_RATE_MASK
,
3548 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
));
3550 /* init basic rate lookup */
3551 brcms_c_rate_lookup_init(wlc
, &default_rateset
);
3554 /* sync up phy/radio chanspec */
3555 brcms_c_set_phy_chanspec(wlc
, chanspec
);
3559 * Set or clear filtering related maccontrol bits based on
3560 * specified filter flags
3562 void brcms_c_mac_promisc(struct brcms_c_info
*wlc
, uint filter_flags
)
3564 u32 promisc_bits
= 0;
3566 wlc
->filter_flags
= filter_flags
;
3568 if (filter_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
))
3569 promisc_bits
|= MCTL_PROMISC
;
3571 if (filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
3572 promisc_bits
|= MCTL_BCNS_PROMISC
;
3574 if (filter_flags
& FIF_FCSFAIL
)
3575 promisc_bits
|= MCTL_KEEPBADFCS
;
3577 if (filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
))
3578 promisc_bits
|= MCTL_KEEPCONTROL
;
3580 brcms_b_mctrl(wlc
->hw
,
3581 MCTL_PROMISC
| MCTL_BCNS_PROMISC
|
3582 MCTL_KEEPCONTROL
| MCTL_KEEPBADFCS
,
3587 * ucode, hwmac update
3588 * Channel dependent updates for ucode and hw
3590 static void brcms_c_ucode_mac_upd(struct brcms_c_info
*wlc
)
3592 /* enable or disable any active IBSSs depending on whether or not
3593 * we are on the home channel
3595 if (wlc
->home_chanspec
== wlc_phy_chanspec_get(wlc
->band
->pi
)) {
3596 if (wlc
->pub
->associated
) {
3598 * BMAC_NOTE: This is something that should be fixed
3599 * in ucode inits. I think that the ucode inits set
3600 * up the bcn templates and shm values with a bogus
3601 * beacon. This should not be done in the inits. If
3602 * ucode needs to set up a beacon for testing, the
3603 * test routines should write it down, not expect the
3604 * inits to populate a bogus beacon.
3606 if (BRCMS_PHY_11N_CAP(wlc
->band
))
3607 brcms_b_write_shm(wlc
->hw
,
3608 M_BCN_TXTSF_OFFSET
, 0);
3611 /* disable an active IBSS if we are not on the home channel */
3615 static void brcms_c_write_rate_shm(struct brcms_c_info
*wlc
, u8 rate
,
3619 u8 basic_phy_rate
, basic_index
;
3620 u16 dir_table
, basic_table
;
3623 /* Shared memory address for the table we are reading */
3624 dir_table
= is_ofdm_rate(basic_rate
) ? M_RT_DIRMAP_A
: M_RT_DIRMAP_B
;
3626 /* Shared memory address for the table we are writing */
3627 basic_table
= is_ofdm_rate(rate
) ? M_RT_BBRSMAP_A
: M_RT_BBRSMAP_B
;
3630 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3631 * the index into the rate table.
3633 phy_rate
= rate_info
[rate
] & BRCMS_RATE_MASK
;
3634 basic_phy_rate
= rate_info
[basic_rate
] & BRCMS_RATE_MASK
;
3635 index
= phy_rate
& 0xf;
3636 basic_index
= basic_phy_rate
& 0xf;
3638 /* Find the SHM pointer to the ACK rate entry by looking in the
3641 basic_ptr
= brcms_b_read_shm(wlc
->hw
, (dir_table
+ basic_index
* 2));
3643 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3644 * to the correct basic rate for the given incoming rate
3646 brcms_b_write_shm(wlc
->hw
, (basic_table
+ index
* 2), basic_ptr
);
3649 static const struct brcms_c_rateset
*
3650 brcms_c_rateset_get_hwrs(struct brcms_c_info
*wlc
)
3652 const struct brcms_c_rateset
*rs_dflt
;
3654 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
3655 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
3656 rs_dflt
= &ofdm_mimo_rates
;
3658 rs_dflt
= &cck_ofdm_mimo_rates
;
3659 } else if (wlc
->band
->gmode
)
3660 rs_dflt
= &cck_ofdm_rates
;
3662 rs_dflt
= &cck_rates
;
3667 static void brcms_c_set_ratetable(struct brcms_c_info
*wlc
)
3669 const struct brcms_c_rateset
*rs_dflt
;
3670 struct brcms_c_rateset rs
;
3671 u8 rate
, basic_rate
;
3674 rs_dflt
= brcms_c_rateset_get_hwrs(wlc
);
3676 brcms_c_rateset_copy(rs_dflt
, &rs
);
3677 brcms_c_rateset_mcs_upd(&rs
, wlc
->stf
->txstreams
);
3679 /* walk the phy rate table and update SHM basic rate lookup table */
3680 for (i
= 0; i
< rs
.count
; i
++) {
3681 rate
= rs
.rates
[i
] & BRCMS_RATE_MASK
;
3683 /* for a given rate brcms_basic_rate returns the rate at
3684 * which a response ACK/CTS should be sent.
3686 basic_rate
= brcms_basic_rate(wlc
, rate
);
3687 if (basic_rate
== 0)
3688 /* This should only happen if we are using a
3689 * restricted rateset.
3691 basic_rate
= rs
.rates
[0] & BRCMS_RATE_MASK
;
3693 brcms_c_write_rate_shm(wlc
, rate
, basic_rate
);
3697 /* band-specific init */
3698 static void brcms_c_bsinit(struct brcms_c_info
*wlc
)
3700 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d: bandunit %d\n",
3701 wlc
->pub
->unit
, wlc
->band
->bandunit
);
3703 /* write ucode ACK/CTS rate table */
3704 brcms_c_set_ratetable(wlc
);
3706 /* update some band specific mac configuration */
3707 brcms_c_ucode_mac_upd(wlc
);
3709 /* init antenna selection */
3710 brcms_c_antsel_init(wlc
->asi
);
3714 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3716 brcms_c_duty_cycle_set(struct brcms_c_info
*wlc
, int duty_cycle
, bool isOFDM
,
3719 int idle_busy_ratio_x_16
= 0;
3721 isOFDM
? M_TX_IDLE_BUSY_RATIO_X_16_OFDM
:
3722 M_TX_IDLE_BUSY_RATIO_X_16_CCK
;
3723 if (duty_cycle
> 100 || duty_cycle
< 0) {
3724 brcms_err(wlc
->hw
->d11core
,
3725 "wl%d: duty cycle value off limit\n",
3730 idle_busy_ratio_x_16
= (100 - duty_cycle
) * 16 / duty_cycle
;
3731 /* Only write to shared memory when wl is up */
3733 brcms_b_write_shm(wlc
->hw
, offset
, (u16
) idle_busy_ratio_x_16
);
3736 wlc
->tx_duty_cycle_ofdm
= (u16
) duty_cycle
;
3738 wlc
->tx_duty_cycle_cck
= (u16
) duty_cycle
;
3743 /* push sw hps and wake state through hardware */
3744 static void brcms_c_set_ps_ctrl(struct brcms_c_info
*wlc
)
3750 hps
= brcms_c_ps_allowed(wlc
);
3752 brcms_dbg_mac80211(wlc
->hw
->d11core
, "wl%d: hps %d\n", wlc
->pub
->unit
,
3755 v1
= bcma_read32(wlc
->hw
->d11core
, D11REGOFFS(maccontrol
));
3760 brcms_b_mctrl(wlc
->hw
, MCTL_WAKE
| MCTL_HPS
, v2
);
3762 awake_before
= ((v1
& MCTL_WAKE
) || ((v1
& MCTL_HPS
) == 0));
3765 brcms_b_wait_for_wake(wlc
->hw
);
3769 * Write this BSS config's MAC address to core.
3770 * Updates RXE match engine.
3772 static int brcms_c_set_mac(struct brcms_bss_cfg
*bsscfg
)
3775 struct brcms_c_info
*wlc
= bsscfg
->wlc
;
3777 /* enter the MAC addr into the RXE match registers */
3778 brcms_c_set_addrmatch(wlc
, RCM_MAC_OFFSET
, bsscfg
->cur_etheraddr
);
3780 brcms_c_ampdu_macaddr_upd(wlc
);
3785 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3786 * Updates RXE match engine.
3788 static void brcms_c_set_bssid(struct brcms_bss_cfg
*bsscfg
)
3790 /* we need to update BSSID in RXE match registers */
3791 brcms_c_set_addrmatch(bsscfg
->wlc
, RCM_BSSID_OFFSET
, bsscfg
->BSSID
);
3794 static void brcms_b_set_shortslot(struct brcms_hardware
*wlc_hw
, bool shortslot
)
3796 wlc_hw
->shortslot
= shortslot
;
3798 if (wlc_hw
->band
->bandtype
== BRCM_BAND_2G
&& wlc_hw
->up
) {
3799 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
3800 brcms_b_update_slot_timing(wlc_hw
, shortslot
);
3801 brcms_c_enable_mac(wlc_hw
->wlc
);
3806 * Suspend the the MAC and update the slot timing
3807 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3809 static void brcms_c_switch_shortslot(struct brcms_c_info
*wlc
, bool shortslot
)
3811 /* use the override if it is set */
3812 if (wlc
->shortslot_override
!= BRCMS_SHORTSLOT_AUTO
)
3813 shortslot
= (wlc
->shortslot_override
== BRCMS_SHORTSLOT_ON
);
3815 if (wlc
->shortslot
== shortslot
)
3818 wlc
->shortslot
= shortslot
;
3820 brcms_b_set_shortslot(wlc
->hw
, shortslot
);
3823 static void brcms_c_set_home_chanspec(struct brcms_c_info
*wlc
, u16 chanspec
)
3825 if (wlc
->home_chanspec
!= chanspec
) {
3826 wlc
->home_chanspec
= chanspec
;
3828 if (wlc
->bsscfg
->associated
)
3829 wlc
->bsscfg
->current_bss
->chanspec
= chanspec
;
3834 brcms_b_set_chanspec(struct brcms_hardware
*wlc_hw
, u16 chanspec
,
3835 bool mute_tx
, struct txpwr_limits
*txpwr
)
3839 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: 0x%x\n", wlc_hw
->unit
,
3842 wlc_hw
->chanspec
= chanspec
;
3844 /* Switch bands if necessary */
3845 if (wlc_hw
->_nbands
> 1) {
3846 bandunit
= chspec_bandunit(chanspec
);
3847 if (wlc_hw
->band
->bandunit
!= bandunit
) {
3848 /* brcms_b_setband disables other bandunit,
3849 * use light band switch if not up yet
3852 wlc_phy_chanspec_radio_set(wlc_hw
->
3853 bandstate
[bandunit
]->
3855 brcms_b_setband(wlc_hw
, bandunit
, chanspec
);
3857 brcms_c_setxband(wlc_hw
, bandunit
);
3862 wlc_phy_initcal_enable(wlc_hw
->band
->pi
, !mute_tx
);
3866 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
,
3868 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
3870 wlc_phy_chanspec_set(wlc_hw
->band
->pi
, chanspec
);
3871 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
, chanspec
);
3873 /* Update muting of the channel */
3874 brcms_b_mute(wlc_hw
, mute_tx
);
3878 /* switch to and initialize new band */
3879 static void brcms_c_setband(struct brcms_c_info
*wlc
,
3882 wlc
->band
= wlc
->bandstate
[bandunit
];
3887 /* wait for at least one beacon before entering sleeping state */
3888 brcms_c_set_ps_ctrl(wlc
);
3890 /* band-specific initializations */
3891 brcms_c_bsinit(wlc
);
3894 static void brcms_c_set_chanspec(struct brcms_c_info
*wlc
, u16 chanspec
)
3897 bool switchband
= false;
3898 u16 old_chanspec
= wlc
->chanspec
;
3900 if (!brcms_c_valid_chanspec_db(wlc
->cmi
, chanspec
)) {
3901 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: Bad channel %d\n",
3902 wlc
->pub
->unit
, __func__
, CHSPEC_CHANNEL(chanspec
));
3906 /* Switch bands if necessary */
3907 if (wlc
->pub
->_nbands
> 1) {
3908 bandunit
= chspec_bandunit(chanspec
);
3909 if (wlc
->band
->bandunit
!= bandunit
|| wlc
->bandinit_pending
) {
3911 if (wlc
->bandlocked
) {
3912 brcms_err(wlc
->hw
->d11core
,
3913 "wl%d: %s: chspec %d band is locked!\n",
3914 wlc
->pub
->unit
, __func__
,
3915 CHSPEC_CHANNEL(chanspec
));
3919 * should the setband call come after the
3920 * brcms_b_chanspec() ? if the setband updates
3921 * (brcms_c_bsinit) use low level calls to inspect and
3922 * set state, the state inspected may be from the wrong
3923 * band, or the following brcms_b_set_chanspec() may
3926 brcms_c_setband(wlc
, bandunit
);
3930 /* sync up phy/radio chanspec */
3931 brcms_c_set_phy_chanspec(wlc
, chanspec
);
3933 /* init antenna selection */
3934 if (brcms_chspec_bw(old_chanspec
) != brcms_chspec_bw(chanspec
)) {
3935 brcms_c_antsel_init(wlc
->asi
);
3937 /* Fix the hardware rateset based on bw.
3938 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3940 brcms_c_rateset_bw_mcs_filter(&wlc
->band
->hw_rateset
,
3941 wlc
->band
->mimo_cap_40
? brcms_chspec_bw(chanspec
) : 0);
3944 /* update some mac configuration since chanspec changed */
3945 brcms_c_ucode_mac_upd(wlc
);
3949 * This function changes the phytxctl for beacon based on current
3950 * beacon ratespec AND txant setting as per this table:
3951 * ratespec CCK ant = wlc->stf->txant
3954 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info
*wlc
,
3958 u16 phytxant
= wlc
->stf
->phytxant
;
3959 u16 mask
= PHY_TXC_ANT_MASK
;
3961 /* for non-siso rates or default setting, use the available chains */
3962 if (BRCMS_PHY_11N_CAP(wlc
->band
))
3963 phytxant
= brcms_c_stf_phytxchain_sel(wlc
, bcn_rspec
);
3965 phyctl
= brcms_b_read_shm(wlc
->hw
, M_BCN_PCTLWD
);
3966 phyctl
= (phyctl
& ~mask
) | phytxant
;
3967 brcms_b_write_shm(wlc
->hw
, M_BCN_PCTLWD
, phyctl
);
3971 * centralized protection config change function to simplify debugging, no
3972 * consistency checking this should be called only on changes to avoid overhead
3973 * in periodic function
3975 void brcms_c_protection_upd(struct brcms_c_info
*wlc
, uint idx
, int val
)
3978 * Cannot use brcms_dbg_* here because this function is called
3979 * before wlc is sufficiently initialized.
3981 BCMMSG(wlc
->wiphy
, "idx %d, val %d\n", idx
, val
);
3984 case BRCMS_PROT_G_SPEC
:
3985 wlc
->protection
->_g
= (bool) val
;
3987 case BRCMS_PROT_G_OVR
:
3988 wlc
->protection
->g_override
= (s8
) val
;
3990 case BRCMS_PROT_G_USER
:
3991 wlc
->protection
->gmode_user
= (u8
) val
;
3993 case BRCMS_PROT_OVERLAP
:
3994 wlc
->protection
->overlap
= (s8
) val
;
3996 case BRCMS_PROT_N_USER
:
3997 wlc
->protection
->nmode_user
= (s8
) val
;
3999 case BRCMS_PROT_N_CFG
:
4000 wlc
->protection
->n_cfg
= (s8
) val
;
4002 case BRCMS_PROT_N_CFG_OVR
:
4003 wlc
->protection
->n_cfg_override
= (s8
) val
;
4005 case BRCMS_PROT_N_NONGF
:
4006 wlc
->protection
->nongf
= (bool) val
;
4008 case BRCMS_PROT_N_NONGF_OVR
:
4009 wlc
->protection
->nongf_override
= (s8
) val
;
4011 case BRCMS_PROT_N_PAM_OVR
:
4012 wlc
->protection
->n_pam_override
= (s8
) val
;
4014 case BRCMS_PROT_N_OBSS
:
4015 wlc
->protection
->n_obss
= (bool) val
;
4024 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info
*wlc
, int val
)
4027 brcms_c_update_beacon(wlc
);
4028 brcms_c_update_probe_resp(wlc
, true);
4032 static void brcms_c_ht_update_ldpc(struct brcms_c_info
*wlc
, s8 val
)
4034 wlc
->stf
->ldpc
= val
;
4037 brcms_c_update_beacon(wlc
);
4038 brcms_c_update_probe_resp(wlc
, true);
4039 wlc_phy_ldpc_override_set(wlc
->band
->pi
, (val
? true : false));
4043 void brcms_c_wme_setparams(struct brcms_c_info
*wlc
, u16 aci
,
4044 const struct ieee80211_tx_queue_params
*params
,
4048 struct shm_acparams acp_shm
;
4051 /* Only apply params if the core is out of reset and has clocks */
4053 brcms_err(wlc
->hw
->d11core
, "wl%d: %s : no-clock\n",
4054 wlc
->pub
->unit
, __func__
);
4058 memset((char *)&acp_shm
, 0, sizeof(struct shm_acparams
));
4059 /* fill in shm ac params struct */
4060 acp_shm
.txop
= params
->txop
;
4061 /* convert from units of 32us to us for ucode */
4062 wlc
->edcf_txop
[aci
& 0x3] = acp_shm
.txop
=
4063 EDCF_TXOP2USEC(acp_shm
.txop
);
4064 acp_shm
.aifs
= (params
->aifs
& EDCF_AIFSN_MASK
);
4066 if (aci
== IEEE80211_AC_VI
&& acp_shm
.txop
== 0
4067 && acp_shm
.aifs
< EDCF_AIFSN_MAX
)
4070 if (acp_shm
.aifs
< EDCF_AIFSN_MIN
4071 || acp_shm
.aifs
> EDCF_AIFSN_MAX
) {
4072 brcms_err(wlc
->hw
->d11core
, "wl%d: edcf_setparams: bad "
4073 "aifs %d\n", wlc
->pub
->unit
, acp_shm
.aifs
);
4075 acp_shm
.cwmin
= params
->cw_min
;
4076 acp_shm
.cwmax
= params
->cw_max
;
4077 acp_shm
.cwcur
= acp_shm
.cwmin
;
4079 bcma_read16(wlc
->hw
->d11core
, D11REGOFFS(tsf_random
)) &
4081 acp_shm
.reggap
= acp_shm
.bslots
+ acp_shm
.aifs
;
4082 /* Indicate the new params to the ucode */
4083 acp_shm
.status
= brcms_b_read_shm(wlc
->hw
, (M_EDCF_QINFO
+
4086 M_EDCF_STATUS_OFF
));
4087 acp_shm
.status
|= WME_STATUS_NEWAC
;
4089 /* Fill in shm acparam table */
4090 shm_entry
= (u16
*) &acp_shm
;
4091 for (i
= 0; i
< (int)sizeof(struct shm_acparams
); i
+= 2)
4092 brcms_b_write_shm(wlc
->hw
,
4094 wme_ac2fifo
[aci
] * M_EDCF_QLEN
+ i
,
4099 brcms_c_suspend_mac_and_wait(wlc
);
4100 brcms_c_enable_mac(wlc
);
4104 static void brcms_c_edcf_setparams(struct brcms_c_info
*wlc
, bool suspend
)
4108 struct ieee80211_tx_queue_params txq_pars
;
4109 static const struct edcf_acparam default_edcf_acparams
[] = {
4110 {EDCF_AC_BE_ACI_STA
, EDCF_AC_BE_ECW_STA
, EDCF_AC_BE_TXOP_STA
},
4111 {EDCF_AC_BK_ACI_STA
, EDCF_AC_BK_ECW_STA
, EDCF_AC_BK_TXOP_STA
},
4112 {EDCF_AC_VI_ACI_STA
, EDCF_AC_VI_ECW_STA
, EDCF_AC_VI_TXOP_STA
},
4113 {EDCF_AC_VO_ACI_STA
, EDCF_AC_VO_ECW_STA
, EDCF_AC_VO_TXOP_STA
}
4114 }; /* ucode needs these parameters during its initialization */
4115 const struct edcf_acparam
*edcf_acp
= &default_edcf_acparams
[0];
4117 for (i_ac
= 0; i_ac
< IEEE80211_NUM_ACS
; i_ac
++, edcf_acp
++) {
4118 /* find out which ac this set of params applies to */
4119 aci
= (edcf_acp
->ACI
& EDCF_ACI_MASK
) >> EDCF_ACI_SHIFT
;
4121 /* fill in shm ac params struct */
4122 txq_pars
.txop
= edcf_acp
->TXOP
;
4123 txq_pars
.aifs
= edcf_acp
->ACI
;
4125 /* CWmin = 2^(ECWmin) - 1 */
4126 txq_pars
.cw_min
= EDCF_ECW2CW(edcf_acp
->ECW
& EDCF_ECWMIN_MASK
);
4127 /* CWmax = 2^(ECWmax) - 1 */
4128 txq_pars
.cw_max
= EDCF_ECW2CW((edcf_acp
->ECW
& EDCF_ECWMAX_MASK
)
4129 >> EDCF_ECWMAX_SHIFT
);
4130 brcms_c_wme_setparams(wlc
, aci
, &txq_pars
, suspend
);
4134 brcms_c_suspend_mac_and_wait(wlc
);
4135 brcms_c_enable_mac(wlc
);
4139 static void brcms_c_radio_monitor_start(struct brcms_c_info
*wlc
)
4141 /* Don't start the timer if HWRADIO feature is disabled */
4142 if (wlc
->radio_monitor
)
4145 wlc
->radio_monitor
= true;
4146 brcms_b_pllreq(wlc
->hw
, true, BRCMS_PLLREQ_RADIO_MON
);
4147 brcms_add_timer(wlc
->radio_timer
, TIMER_INTERVAL_RADIOCHK
, true);
4150 static bool brcms_c_radio_monitor_stop(struct brcms_c_info
*wlc
)
4152 if (!wlc
->radio_monitor
)
4155 wlc
->radio_monitor
= false;
4156 brcms_b_pllreq(wlc
->hw
, false, BRCMS_PLLREQ_RADIO_MON
);
4157 return brcms_del_timer(wlc
->radio_timer
);
4160 /* read hwdisable state and propagate to wlc flag */
4161 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info
*wlc
)
4163 if (wlc
->pub
->hw_off
)
4166 if (brcms_b_radio_read_hwdisabled(wlc
->hw
))
4167 mboolset(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
);
4169 mboolclr(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
);
4172 /* update hwradio status and return it */
4173 bool brcms_c_check_radio_disabled(struct brcms_c_info
*wlc
)
4175 brcms_c_radio_hwdisable_upd(wlc
);
4177 return mboolisset(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
) ?
4181 /* periodical query hw radio button while driver is "down" */
4182 static void brcms_c_radio_timer(void *arg
)
4184 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) arg
;
4186 if (brcms_deviceremoved(wlc
)) {
4187 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: dead chip\n",
4188 wlc
->pub
->unit
, __func__
);
4189 brcms_down(wlc
->wl
);
4193 brcms_c_radio_hwdisable_upd(wlc
);
4196 /* common low-level watchdog code */
4197 static void brcms_b_watchdog(struct brcms_c_info
*wlc
)
4199 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
4204 /* increment second count */
4207 /* Check for FIFO error interrupts */
4208 brcms_b_fifoerrors(wlc_hw
);
4210 /* make sure RX dma has buffers */
4211 dma_rxfill(wlc
->hw
->di
[RX_FIFO
]);
4213 wlc_phy_watchdog(wlc_hw
->band
->pi
);
4216 /* common watchdog code */
4217 static void brcms_c_watchdog(struct brcms_c_info
*wlc
)
4219 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
4224 if (brcms_deviceremoved(wlc
)) {
4225 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: dead chip\n",
4226 wlc
->pub
->unit
, __func__
);
4227 brcms_down(wlc
->wl
);
4231 /* increment second count */
4234 brcms_c_radio_hwdisable_upd(wlc
);
4235 /* if radio is disable, driver may be down, quit here */
4236 if (wlc
->pub
->radio_disabled
)
4239 brcms_b_watchdog(wlc
);
4242 * occasionally sample mac stat counters to
4243 * detect 16-bit counter wrap
4245 if ((wlc
->pub
->now
% SW_TIMER_MAC_STAT_UPD
) == 0)
4246 brcms_c_statsupd(wlc
);
4248 if (BRCMS_ISNPHY(wlc
->band
) &&
4249 ((wlc
->pub
->now
- wlc
->tempsense_lasttime
) >=
4250 BRCMS_TEMPSENSE_PERIOD
)) {
4251 wlc
->tempsense_lasttime
= wlc
->pub
->now
;
4252 brcms_c_tempsense_upd(wlc
);
4256 static void brcms_c_watchdog_by_timer(void *arg
)
4258 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) arg
;
4260 brcms_c_watchdog(wlc
);
4263 static bool brcms_c_timers_init(struct brcms_c_info
*wlc
, int unit
)
4265 wlc
->wdtimer
= brcms_init_timer(wlc
->wl
, brcms_c_watchdog_by_timer
,
4267 if (!wlc
->wdtimer
) {
4268 wiphy_err(wlc
->wiphy
, "wl%d: wl_init_timer for wdtimer "
4273 wlc
->radio_timer
= brcms_init_timer(wlc
->wl
, brcms_c_radio_timer
,
4275 if (!wlc
->radio_timer
) {
4276 wiphy_err(wlc
->wiphy
, "wl%d: wl_init_timer for radio_timer "
4288 * Initialize brcms_c_info default values ...
4289 * may get overrides later in this function
4291 static void brcms_c_info_init(struct brcms_c_info
*wlc
, int unit
)
4295 /* Save our copy of the chanspec */
4296 wlc
->chanspec
= ch20mhz_chspec(1);
4298 /* various 802.11g modes */
4299 wlc
->shortslot
= false;
4300 wlc
->shortslot_override
= BRCMS_SHORTSLOT_AUTO
;
4302 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_OVR
, BRCMS_PROTECTION_AUTO
);
4303 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_SPEC
, false);
4305 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_CFG_OVR
,
4306 BRCMS_PROTECTION_AUTO
);
4307 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_CFG
, BRCMS_N_PROTECTION_OFF
);
4308 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_NONGF_OVR
,
4309 BRCMS_PROTECTION_AUTO
);
4310 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_NONGF
, false);
4311 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_PAM_OVR
, AUTO
);
4313 brcms_c_protection_upd(wlc
, BRCMS_PROT_OVERLAP
,
4314 BRCMS_PROTECTION_CTL_OVERLAP
);
4316 /* 802.11g draft 4.0 NonERP elt advertisement */
4317 wlc
->include_legacy_erp
= true;
4319 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_DEF
;
4320 wlc
->stf
->txant
= ANT_TX_DEF
;
4322 wlc
->prb_resp_timeout
= BRCMS_PRB_RESP_TIMEOUT
;
4324 wlc
->usr_fragthresh
= DOT11_DEFAULT_FRAG_LEN
;
4325 for (i
= 0; i
< NFIFO
; i
++)
4326 wlc
->fragthresh
[i
] = DOT11_DEFAULT_FRAG_LEN
;
4327 wlc
->RTSThresh
= DOT11_DEFAULT_RTS_LEN
;
4329 /* default rate fallback retry limits */
4330 wlc
->SFBL
= RETRY_SHORT_FB
;
4331 wlc
->LFBL
= RETRY_LONG_FB
;
4333 /* default mac retry limits */
4334 wlc
->SRL
= RETRY_SHORT_DEF
;
4335 wlc
->LRL
= RETRY_LONG_DEF
;
4337 /* WME QoS mode is Auto by default */
4338 wlc
->pub
->_ampdu
= AMPDU_AGG_HOST
;
4339 wlc
->pub
->bcmerror
= 0;
4342 static uint
brcms_c_attach_module(struct brcms_c_info
*wlc
)
4346 unit
= wlc
->pub
->unit
;
4348 wlc
->asi
= brcms_c_antsel_attach(wlc
);
4349 if (wlc
->asi
== NULL
) {
4350 wiphy_err(wlc
->wiphy
, "wl%d: attach: antsel_attach "
4356 wlc
->ampdu
= brcms_c_ampdu_attach(wlc
);
4357 if (wlc
->ampdu
== NULL
) {
4358 wiphy_err(wlc
->wiphy
, "wl%d: attach: ampdu_attach "
4364 if ((brcms_c_stf_attach(wlc
) != 0)) {
4365 wiphy_err(wlc
->wiphy
, "wl%d: attach: stf_attach "
4374 struct brcms_pub
*brcms_c_pub(struct brcms_c_info
*wlc
)
4380 * run backplane attach, init nvram
4382 * initialize software state for each core and band
4383 * put the whole chip in reset(driver down state), no clock
4385 static int brcms_b_attach(struct brcms_c_info
*wlc
, struct bcma_device
*core
,
4386 uint unit
, bool piomode
)
4388 struct brcms_hardware
*wlc_hw
;
4392 struct shared_phy_params sha_params
;
4393 struct wiphy
*wiphy
= wlc
->wiphy
;
4394 struct pci_dev
*pcidev
= core
->bus
->host_pci
;
4395 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
4397 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
)
4398 brcms_dbg_info(core
, "wl%d: vendor 0x%x device 0x%x\n", unit
,
4402 brcms_dbg_info(core
, "wl%d: vendor 0x%x device 0x%x\n", unit
,
4403 core
->bus
->boardinfo
.vendor
,
4404 core
->bus
->boardinfo
.type
);
4410 wlc_hw
->unit
= unit
;
4411 wlc_hw
->band
= wlc_hw
->bandstate
[0];
4412 wlc_hw
->_piomode
= piomode
;
4414 /* populate struct brcms_hardware with default values */
4415 brcms_b_info_init(wlc_hw
);
4418 * Do the hardware portion of the attach. Also initialize software
4419 * state that depends on the particular hardware we are running.
4421 wlc_hw
->sih
= ai_attach(core
->bus
);
4422 if (wlc_hw
->sih
== NULL
) {
4423 wiphy_err(wiphy
, "wl%d: brcms_b_attach: si_attach failed\n",
4429 /* verify again the device is supported */
4430 if (!brcms_c_chipmatch(core
)) {
4431 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported device\n",
4437 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
4438 wlc_hw
->vendorid
= pcidev
->vendor
;
4439 wlc_hw
->deviceid
= pcidev
->device
;
4441 wlc_hw
->vendorid
= core
->bus
->boardinfo
.vendor
;
4442 wlc_hw
->deviceid
= core
->bus
->boardinfo
.type
;
4445 wlc_hw
->d11core
= core
;
4446 wlc_hw
->corerev
= core
->id
.rev
;
4448 /* validate chip, chiprev and corerev */
4449 if (!brcms_c_isgoodchip(wlc_hw
)) {
4454 /* initialize power control registers */
4455 ai_clkctl_init(wlc_hw
->sih
);
4457 /* request fastclock and force fastclock for the rest of attach
4458 * bring the d11 core out of reset.
4459 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4460 * is still false; But it will be called again inside wlc_corereset,
4461 * after d11 is out of reset.
4463 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
4464 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
4466 if (!brcms_b_validate_chip_access(wlc_hw
)) {
4467 wiphy_err(wiphy
, "wl%d: brcms_b_attach: validate_chip_access "
4473 /* get the board rev, used just below */
4474 j
= sprom
->board_rev
;
4475 /* promote srom boardrev of 0xFF to 1 */
4476 if (j
== BOARDREV_PROMOTABLE
)
4477 j
= BOARDREV_PROMOTED
;
4478 wlc_hw
->boardrev
= (u16
) j
;
4479 if (!brcms_c_validboardtype(wlc_hw
)) {
4480 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported Broadcom "
4481 "board type (0x%x)" " or revision level (0x%x)\n",
4482 unit
, ai_get_boardtype(wlc_hw
->sih
),
4487 wlc_hw
->sromrev
= sprom
->revision
;
4488 wlc_hw
->boardflags
= sprom
->boardflags_lo
+ (sprom
->boardflags_hi
<< 16);
4489 wlc_hw
->boardflags2
= sprom
->boardflags2_lo
+ (sprom
->boardflags2_hi
<< 16);
4491 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
4492 brcms_b_pllreq(wlc_hw
, true, BRCMS_PLLREQ_SHARED
);
4494 /* check device id(srom, nvram etc.) to set bands */
4495 if (wlc_hw
->deviceid
== BCM43224_D11N_ID
||
4496 wlc_hw
->deviceid
== BCM43224_D11N_ID_VEN1
||
4497 wlc_hw
->deviceid
== BCM43224_CHIP_ID
)
4498 /* Dualband boards */
4499 wlc_hw
->_nbands
= 2;
4501 wlc_hw
->_nbands
= 1;
4503 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43225
))
4504 wlc_hw
->_nbands
= 1;
4506 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4507 * unconditionally does the init of these values
4509 wlc
->vendorid
= wlc_hw
->vendorid
;
4510 wlc
->deviceid
= wlc_hw
->deviceid
;
4511 wlc
->pub
->sih
= wlc_hw
->sih
;
4512 wlc
->pub
->corerev
= wlc_hw
->corerev
;
4513 wlc
->pub
->sromrev
= wlc_hw
->sromrev
;
4514 wlc
->pub
->boardrev
= wlc_hw
->boardrev
;
4515 wlc
->pub
->boardflags
= wlc_hw
->boardflags
;
4516 wlc
->pub
->boardflags2
= wlc_hw
->boardflags2
;
4517 wlc
->pub
->_nbands
= wlc_hw
->_nbands
;
4519 wlc_hw
->physhim
= wlc_phy_shim_attach(wlc_hw
, wlc
->wl
, wlc
);
4521 if (wlc_hw
->physhim
== NULL
) {
4522 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4528 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4529 sha_params
.sih
= wlc_hw
->sih
;
4530 sha_params
.physhim
= wlc_hw
->physhim
;
4531 sha_params
.unit
= unit
;
4532 sha_params
.corerev
= wlc_hw
->corerev
;
4533 sha_params
.vid
= wlc_hw
->vendorid
;
4534 sha_params
.did
= wlc_hw
->deviceid
;
4535 sha_params
.chip
= ai_get_chip_id(wlc_hw
->sih
);
4536 sha_params
.chiprev
= ai_get_chiprev(wlc_hw
->sih
);
4537 sha_params
.chippkg
= ai_get_chippkg(wlc_hw
->sih
);
4538 sha_params
.sromrev
= wlc_hw
->sromrev
;
4539 sha_params
.boardtype
= ai_get_boardtype(wlc_hw
->sih
);
4540 sha_params
.boardrev
= wlc_hw
->boardrev
;
4541 sha_params
.boardflags
= wlc_hw
->boardflags
;
4542 sha_params
.boardflags2
= wlc_hw
->boardflags2
;
4544 /* alloc and save pointer to shared phy state area */
4545 wlc_hw
->phy_sh
= wlc_phy_shared_attach(&sha_params
);
4546 if (!wlc_hw
->phy_sh
) {
4551 /* initialize software state for each core and band */
4552 for (j
= 0; j
< wlc_hw
->_nbands
; j
++) {
4554 * band0 is always 2.4Ghz
4555 * band1, if present, is 5Ghz
4558 brcms_c_setxband(wlc_hw
, j
);
4560 wlc_hw
->band
->bandunit
= j
;
4561 wlc_hw
->band
->bandtype
= j
? BRCM_BAND_5G
: BRCM_BAND_2G
;
4562 wlc
->band
->bandunit
= j
;
4563 wlc
->band
->bandtype
= j
? BRCM_BAND_5G
: BRCM_BAND_2G
;
4564 wlc
->core
->coreidx
= core
->core_index
;
4566 wlc_hw
->machwcap
= bcma_read32(core
, D11REGOFFS(machwcap
));
4567 wlc_hw
->machwcap_backup
= wlc_hw
->machwcap
;
4569 /* init tx fifo size */
4570 WARN_ON((wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
) < 0 ||
4571 (wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
) >
4572 ARRAY_SIZE(xmtfifo_sz
));
4573 wlc_hw
->xmtfifo_sz
=
4574 xmtfifo_sz
[(wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
)];
4575 WARN_ON(!wlc_hw
->xmtfifo_sz
[0]);
4577 /* Get a phy for this band */
4579 wlc_phy_attach(wlc_hw
->phy_sh
, core
,
4580 wlc_hw
->band
->bandtype
,
4582 if (wlc_hw
->band
->pi
== NULL
) {
4583 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_"
4584 "attach failed\n", unit
);
4589 wlc_phy_machwcap_set(wlc_hw
->band
->pi
, wlc_hw
->machwcap
);
4591 wlc_phy_get_phyversion(wlc_hw
->band
->pi
, &wlc_hw
->band
->phytype
,
4592 &wlc_hw
->band
->phyrev
,
4593 &wlc_hw
->band
->radioid
,
4594 &wlc_hw
->band
->radiorev
);
4595 wlc_hw
->band
->abgphy_encore
=
4596 wlc_phy_get_encore(wlc_hw
->band
->pi
);
4597 wlc
->band
->abgphy_encore
= wlc_phy_get_encore(wlc_hw
->band
->pi
);
4598 wlc_hw
->band
->core_flags
=
4599 wlc_phy_get_coreflags(wlc_hw
->band
->pi
);
4601 /* verify good phy_type & supported phy revision */
4602 if (BRCMS_ISNPHY(wlc_hw
->band
)) {
4603 if (NCONF_HAS(wlc_hw
->band
->phyrev
))
4607 } else if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
4608 if (LCNCONF_HAS(wlc_hw
->band
->phyrev
))
4614 wiphy_err(wiphy
, "wl%d: brcms_b_attach: unsupported "
4615 "phy type/rev (%d/%d)\n", unit
,
4616 wlc_hw
->band
->phytype
, wlc_hw
->band
->phyrev
);
4623 * BMAC_NOTE: wlc->band->pi should not be set below and should
4624 * be done in the high level attach. However we can not make
4625 * that change until all low level access is changed to
4626 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4627 * keeping wlc_hw->band->pi as well for incremental update of
4628 * low level fns, and cut over low only init when all fns
4631 wlc
->band
->pi
= wlc_hw
->band
->pi
;
4632 wlc
->band
->phytype
= wlc_hw
->band
->phytype
;
4633 wlc
->band
->phyrev
= wlc_hw
->band
->phyrev
;
4634 wlc
->band
->radioid
= wlc_hw
->band
->radioid
;
4635 wlc
->band
->radiorev
= wlc_hw
->band
->radiorev
;
4637 /* default contention windows size limits */
4638 wlc_hw
->band
->CWmin
= APHY_CWMIN
;
4639 wlc_hw
->band
->CWmax
= PHY_CWMAX
;
4641 if (!brcms_b_attach_dmapio(wlc
, j
, wme
)) {
4647 /* disable core to match driver "down" state */
4648 brcms_c_coredisable(wlc_hw
);
4650 /* Match driver "down" state */
4651 ai_pci_down(wlc_hw
->sih
);
4653 /* turn off pll and xtal to match driver "down" state */
4654 brcms_b_xtal(wlc_hw
, OFF
);
4656 /* *******************************************************************
4657 * The hardware is in the DOWN state at this point. D11 core
4658 * or cores are in reset with clocks off, and the board PLLs
4659 * are off if possible.
4661 * Beyond this point, wlc->sbclk == false and chip registers
4662 * should not be touched.
4663 *********************************************************************
4666 /* init etheraddr state variables */
4667 brcms_c_get_macaddr(wlc_hw
, wlc_hw
->etheraddr
);
4669 if (is_broadcast_ether_addr(wlc_hw
->etheraddr
) ||
4670 is_zero_ether_addr(wlc_hw
->etheraddr
)) {
4671 wiphy_err(wiphy
, "wl%d: brcms_b_attach: bad macaddr\n",
4677 brcms_dbg_info(wlc_hw
->d11core
, "deviceid 0x%x nbands %d board 0x%x\n",
4678 wlc_hw
->deviceid
, wlc_hw
->_nbands
,
4679 ai_get_boardtype(wlc_hw
->sih
));
4684 wiphy_err(wiphy
, "wl%d: brcms_b_attach: failed with err %d\n", unit
,
4689 static void brcms_c_attach_antgain_init(struct brcms_c_info
*wlc
)
4692 unit
= wlc
->pub
->unit
;
4694 if ((wlc
->band
->antgain
== -1) && (wlc
->pub
->sromrev
== 1)) {
4695 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4696 wlc
->band
->antgain
= 8;
4697 } else if (wlc
->band
->antgain
== -1) {
4698 wiphy_err(wlc
->wiphy
, "wl%d: %s: Invalid antennas available in"
4699 " srom, using 2dB\n", unit
, __func__
);
4700 wlc
->band
->antgain
= 8;
4703 /* Older sroms specified gain in whole dbm only. In order
4704 * be able to specify qdbm granularity and remain backward
4705 * compatible the whole dbms are now encoded in only
4706 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4707 * 6 bit signed number ranges from -32 - 31.
4711 * 0xc1 = 1.75 db (1 + 3 quarters),
4712 * 0x3f = -1 (-1 + 0 quarters),
4713 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4714 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4716 gain
= wlc
->band
->antgain
& 0x3f;
4717 gain
<<= 2; /* Sign extend */
4719 fract
= (wlc
->band
->antgain
& 0xc0) >> 6;
4720 wlc
->band
->antgain
= 4 * gain
+ fract
;
4724 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info
*wlc
)
4729 struct ssb_sprom
*sprom
= &wlc
->hw
->d11core
->bus
->sprom
;
4731 unit
= wlc
->pub
->unit
;
4732 bandtype
= wlc
->band
->bandtype
;
4734 /* get antennas available */
4735 if (bandtype
== BRCM_BAND_5G
)
4736 aa
= sprom
->ant_available_a
;
4738 aa
= sprom
->ant_available_bg
;
4740 if ((aa
< 1) || (aa
> 15)) {
4741 wiphy_err(wlc
->wiphy
, "wl%d: %s: Invalid antennas available in"
4742 " srom (0x%x), using 3\n", unit
, __func__
, aa
);
4746 /* reset the defaults if we have a single antenna */
4748 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_FORCE_0
;
4749 wlc
->stf
->txant
= ANT_TX_FORCE_0
;
4750 } else if (aa
== 2) {
4751 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_FORCE_1
;
4752 wlc
->stf
->txant
= ANT_TX_FORCE_1
;
4756 /* Compute Antenna Gain */
4757 if (bandtype
== BRCM_BAND_5G
)
4758 wlc
->band
->antgain
= sprom
->antenna_gain
.a1
;
4760 wlc
->band
->antgain
= sprom
->antenna_gain
.a0
;
4762 brcms_c_attach_antgain_init(wlc
);
4767 static void brcms_c_bss_default_init(struct brcms_c_info
*wlc
)
4770 struct brcms_band
*band
;
4771 struct brcms_bss_info
*bi
= wlc
->default_bss
;
4773 /* init default and target BSS with some sane initial values */
4774 memset((char *)(bi
), 0, sizeof(struct brcms_bss_info
));
4775 bi
->beacon_period
= BEACON_INTERVAL_DEFAULT
;
4777 /* fill the default channel as the first valid channel
4778 * starting from the 2G channels
4780 chanspec
= ch20mhz_chspec(1);
4781 wlc
->home_chanspec
= bi
->chanspec
= chanspec
;
4783 /* find the band of our default channel */
4785 if (wlc
->pub
->_nbands
> 1 &&
4786 band
->bandunit
!= chspec_bandunit(chanspec
))
4787 band
= wlc
->bandstate
[OTHERBANDUNIT(wlc
)];
4789 /* init bss rates to the band specific default rate set */
4790 brcms_c_rateset_default(&bi
->rateset
, NULL
, band
->phytype
,
4791 band
->bandtype
, false, BRCMS_RATE_MASK_FULL
,
4792 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
),
4793 brcms_chspec_bw(chanspec
), wlc
->stf
->txstreams
);
4795 if (wlc
->pub
->_n_enab
& SUPPORT_11N
)
4796 bi
->flags
|= BRCMS_BSS_HT
;
4799 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info
*wlc
, u8 bwcap
)
4802 struct brcms_band
*band
;
4804 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++) {
4805 band
= wlc
->bandstate
[i
];
4806 if (band
->bandtype
== BRCM_BAND_5G
) {
4807 if ((bwcap
== BRCMS_N_BW_40ALL
)
4808 || (bwcap
== BRCMS_N_BW_20IN2G_40IN5G
))
4809 band
->mimo_cap_40
= true;
4811 band
->mimo_cap_40
= false;
4813 if (bwcap
== BRCMS_N_BW_40ALL
)
4814 band
->mimo_cap_40
= true;
4816 band
->mimo_cap_40
= false;
4821 static void brcms_c_timers_deinit(struct brcms_c_info
*wlc
)
4823 /* free timer state */
4825 brcms_free_timer(wlc
->wdtimer
);
4826 wlc
->wdtimer
= NULL
;
4828 if (wlc
->radio_timer
) {
4829 brcms_free_timer(wlc
->radio_timer
);
4830 wlc
->radio_timer
= NULL
;
4834 static void brcms_c_detach_module(struct brcms_c_info
*wlc
)
4837 brcms_c_antsel_detach(wlc
->asi
);
4842 brcms_c_ampdu_detach(wlc
->ampdu
);
4846 brcms_c_stf_detach(wlc
);
4852 static int brcms_b_detach(struct brcms_c_info
*wlc
)
4855 struct brcms_hw_band
*band
;
4856 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
4861 brcms_b_detach_dmapio(wlc_hw
);
4863 band
= wlc_hw
->band
;
4864 for (i
= 0; i
< wlc_hw
->_nbands
; i
++) {
4866 /* Detach this band's phy */
4867 wlc_phy_detach(band
->pi
);
4870 band
= wlc_hw
->bandstate
[OTHERBANDUNIT(wlc
)];
4873 /* Free shared phy state */
4874 kfree(wlc_hw
->phy_sh
);
4876 wlc_phy_shim_detach(wlc_hw
->physhim
);
4879 ai_detach(wlc_hw
->sih
);
4888 * Return a count of the number of driver callbacks still pending.
4890 * General policy is that brcms_c_detach can only dealloc/free software states.
4891 * It can NOT touch hardware registers since the d11core may be in reset and
4892 * clock may not be available.
4893 * One exception is sb register access, which is possible if crystal is turned
4894 * on after "down" state, driver should avoid software timer with the exception
4897 uint
brcms_c_detach(struct brcms_c_info
*wlc
)
4904 callbacks
+= brcms_b_detach(wlc
);
4906 /* delete software timers */
4907 if (!brcms_c_radio_monitor_stop(wlc
))
4910 brcms_c_channel_mgr_detach(wlc
->cmi
);
4912 brcms_c_timers_deinit(wlc
);
4914 brcms_c_detach_module(wlc
);
4916 brcms_c_detach_mfree(wlc
);
4920 /* update state that depends on the current value of "ap" */
4921 static void brcms_c_ap_upd(struct brcms_c_info
*wlc
)
4923 /* STA-BSS; short capable */
4924 wlc
->PLCPHdr_override
= BRCMS_PLCP_SHORT
;
4927 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4928 static void brcms_b_hw_up(struct brcms_hardware
*wlc_hw
)
4930 if (wlc_hw
->wlc
->pub
->hw_up
)
4933 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
4936 * Enable pll and xtal, initialize the power control registers,
4937 * and force fastclock for the remainder of brcms_c_up().
4939 brcms_b_xtal(wlc_hw
, ON
);
4940 ai_clkctl_init(wlc_hw
->sih
);
4941 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
4944 * TODO: test suspend/resume
4946 * AI chip doesn't restore bar0win2 on
4947 * hibernation/resume, need sw fixup
4951 * Inform phy that a POR reset has occurred so
4952 * it does a complete phy init
4954 wlc_phy_por_inform(wlc_hw
->band
->pi
);
4956 wlc_hw
->ucode_loaded
= false;
4957 wlc_hw
->wlc
->pub
->hw_up
= true;
4959 if ((wlc_hw
->boardflags
& BFL_FEM
)
4960 && (ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
4962 (wlc_hw
->boardrev
>= 0x1250
4963 && (wlc_hw
->boardflags
& BFL_FEM_BT
)))
4964 ai_epa_4313war(wlc_hw
->sih
);
4968 static int brcms_b_up_prep(struct brcms_hardware
*wlc_hw
)
4970 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
4973 * Enable pll and xtal, initialize the power control registers,
4974 * and force fastclock for the remainder of brcms_c_up().
4976 brcms_b_xtal(wlc_hw
, ON
);
4977 ai_clkctl_init(wlc_hw
->sih
);
4978 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
4981 * Configure pci/pcmcia here instead of in brcms_c_attach()
4982 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
4984 bcma_core_pci_irq_ctl(&wlc_hw
->d11core
->bus
->drv_pci
[0], wlc_hw
->d11core
,
4988 * Need to read the hwradio status here to cover the case where the
4989 * system is loaded with the hw radio disabled. We do not want to
4990 * bring the driver up in this case.
4992 if (brcms_b_radio_read_hwdisabled(wlc_hw
)) {
4993 /* put SB PCI in down state again */
4994 ai_pci_down(wlc_hw
->sih
);
4995 brcms_b_xtal(wlc_hw
, OFF
);
4999 ai_pci_up(wlc_hw
->sih
);
5001 /* reset the d11 core */
5002 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
5007 static int brcms_b_up_finish(struct brcms_hardware
*wlc_hw
)
5010 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, true);
5012 /* FULLY enable dynamic power control and d11 core interrupt */
5013 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
5014 brcms_intrson(wlc_hw
->wlc
->wl
);
5019 * Write WME tunable parameters for retransmit/max rate
5020 * from wlc struct to ucode
5022 static void brcms_c_wme_retries_write(struct brcms_c_info
*wlc
)
5026 /* Need clock to do this */
5030 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++)
5031 brcms_b_write_shm(wlc
->hw
, M_AC_TXLMT_ADDR(ac
),
5032 wlc
->wme_retries
[ac
]);
5035 /* make interface operational */
5036 int brcms_c_up(struct brcms_c_info
*wlc
)
5038 struct ieee80211_channel
*ch
;
5040 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
5042 /* HW is turned off so don't try to access it */
5043 if (wlc
->pub
->hw_off
|| brcms_deviceremoved(wlc
))
5046 if (!wlc
->pub
->hw_up
) {
5047 brcms_b_hw_up(wlc
->hw
);
5048 wlc
->pub
->hw_up
= true;
5051 if ((wlc
->pub
->boardflags
& BFL_FEM
)
5052 && (ai_get_chip_id(wlc
->hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
5053 if (wlc
->pub
->boardrev
>= 0x1250
5054 && (wlc
->pub
->boardflags
& BFL_FEM_BT
))
5055 brcms_b_mhf(wlc
->hw
, MHF5
, MHF5_4313_GPIOCTRL
,
5056 MHF5_4313_GPIOCTRL
, BRCM_BAND_ALL
);
5058 brcms_b_mhf(wlc
->hw
, MHF4
, MHF4_EXTPA_ENABLE
,
5059 MHF4_EXTPA_ENABLE
, BRCM_BAND_ALL
);
5063 * Need to read the hwradio status here to cover the case where the
5064 * system is loaded with the hw radio disabled. We do not want to bring
5065 * the driver up in this case. If radio is disabled, abort up, lower
5066 * power, start radio timer and return 0(for NDIS) don't call
5067 * radio_update to avoid looping brcms_c_up.
5069 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5071 if (!wlc
->pub
->radio_disabled
) {
5072 int status
= brcms_b_up_prep(wlc
->hw
);
5073 if (status
== -ENOMEDIUM
) {
5075 (wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
)) {
5076 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
5077 mboolset(wlc
->pub
->radio_disabled
,
5078 WL_RADIO_HW_DISABLE
);
5080 if (bsscfg
->enable
&& bsscfg
->BSS
)
5081 brcms_err(wlc
->hw
->d11core
,
5082 "wl%d: up: rfdisable -> "
5083 "bsscfg_disable()\n",
5089 if (wlc
->pub
->radio_disabled
) {
5090 brcms_c_radio_monitor_start(wlc
);
5094 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5097 brcms_c_radio_monitor_stop(wlc
);
5099 /* Set EDCF hostflags */
5100 brcms_b_mhf(wlc
->hw
, MHF1
, MHF1_EDCF
, MHF1_EDCF
, BRCM_BAND_ALL
);
5102 brcms_init(wlc
->wl
);
5103 wlc
->pub
->up
= true;
5105 if (wlc
->bandinit_pending
) {
5106 ch
= wlc
->pub
->ieee_hw
->conf
.channel
;
5107 brcms_c_suspend_mac_and_wait(wlc
);
5108 brcms_c_set_chanspec(wlc
, ch20mhz_chspec(ch
->hw_value
));
5109 wlc
->bandinit_pending
= false;
5110 brcms_c_enable_mac(wlc
);
5113 brcms_b_up_finish(wlc
->hw
);
5115 /* Program the TX wme params with the current settings */
5116 brcms_c_wme_retries_write(wlc
);
5118 /* start one second watchdog timer */
5119 brcms_add_timer(wlc
->wdtimer
, TIMER_INTERVAL_WATCHDOG
, true);
5120 wlc
->WDarmed
= true;
5122 /* ensure antenna config is up to date */
5123 brcms_c_stf_phy_txant_upd(wlc
);
5124 /* ensure LDPC config is in sync */
5125 brcms_c_ht_update_ldpc(wlc
, wlc
->stf
->ldpc
);
5130 static uint
brcms_c_down_del_timer(struct brcms_c_info
*wlc
)
5137 static int brcms_b_bmac_down_prep(struct brcms_hardware
*wlc_hw
)
5145 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
5147 /* disable interrupts */
5149 wlc_hw
->wlc
->macintmask
= 0;
5151 /* now disable interrupts */
5152 brcms_intrsoff(wlc_hw
->wlc
->wl
);
5154 /* ensure we're running on the pll clock again */
5155 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
5157 /* down phy at the last of this stage */
5158 callbacks
+= wlc_phy_down(wlc_hw
->band
->pi
);
5163 static int brcms_b_down_finish(struct brcms_hardware
*wlc_hw
)
5172 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, false);
5174 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
5177 wlc_hw
->sbclk
= false;
5178 wlc_hw
->clk
= false;
5179 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
5181 /* reclaim any posted packets */
5182 brcms_c_flushqueues(wlc_hw
->wlc
);
5185 /* Reset and disable the core */
5186 if (bcma_core_is_enabled(wlc_hw
->d11core
)) {
5187 if (bcma_read32(wlc_hw
->d11core
,
5188 D11REGOFFS(maccontrol
)) & MCTL_EN_MAC
)
5189 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
5190 callbacks
+= brcms_reset(wlc_hw
->wlc
->wl
);
5191 brcms_c_coredisable(wlc_hw
);
5194 /* turn off primary xtal and pll */
5195 if (!wlc_hw
->noreset
) {
5196 ai_pci_down(wlc_hw
->sih
);
5197 brcms_b_xtal(wlc_hw
, OFF
);
5205 * Mark the interface nonoperational, stop the software mechanisms,
5206 * disable the hardware, free any transient buffer state.
5207 * Return a count of the number of driver callbacks still pending.
5209 uint
brcms_c_down(struct brcms_c_info
*wlc
)
5214 bool dev_gone
= false;
5216 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
5218 /* check if we are already in the going down path */
5219 if (wlc
->going_down
) {
5220 brcms_err(wlc
->hw
->d11core
,
5221 "wl%d: %s: Driver going down so return\n",
5222 wlc
->pub
->unit
, __func__
);
5228 wlc
->going_down
= true;
5230 callbacks
+= brcms_b_bmac_down_prep(wlc
->hw
);
5232 dev_gone
= brcms_deviceremoved(wlc
);
5234 /* Call any registered down handlers */
5235 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5236 if (wlc
->modulecb
[i
].down_fn
)
5238 wlc
->modulecb
[i
].down_fn(wlc
->modulecb
[i
].hdl
);
5241 /* cancel the watchdog timer */
5243 if (!brcms_del_timer(wlc
->wdtimer
))
5245 wlc
->WDarmed
= false;
5247 /* cancel all other timers */
5248 callbacks
+= brcms_c_down_del_timer(wlc
);
5250 wlc
->pub
->up
= false;
5252 wlc_phy_mute_upd(wlc
->band
->pi
, false, PHY_MUTE_ALL
);
5254 callbacks
+= brcms_b_down_finish(wlc
->hw
);
5256 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5259 wlc
->going_down
= false;
5263 /* Set the current gmode configuration */
5264 int brcms_c_set_gmode(struct brcms_c_info
*wlc
, u8 gmode
, bool config
)
5268 struct brcms_c_rateset rs
;
5269 /* Default to 54g Auto */
5270 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5271 s8 shortslot
= BRCMS_SHORTSLOT_AUTO
;
5272 bool shortslot_restrict
= false; /* Restrict association to stations
5273 * that support shortslot
5275 bool ofdm_basic
= false; /* Make 6, 12, and 24 basic rates */
5276 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5277 int preamble
= BRCMS_PLCP_LONG
;
5278 bool preamble_restrict
= false; /* Restrict association to stations
5279 * that support short preambles
5281 struct brcms_band
*band
;
5283 /* if N-support is enabled, allow Gmode set as long as requested
5284 * Gmode is not GMODE_LEGACY_B
5286 if ((wlc
->pub
->_n_enab
& SUPPORT_11N
) && gmode
== GMODE_LEGACY_B
)
5289 /* verify that we are dealing with 2G band and grab the band pointer */
5290 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
5292 else if ((wlc
->pub
->_nbands
> 1) &&
5293 (wlc
->bandstate
[OTHERBANDUNIT(wlc
)]->bandtype
== BRCM_BAND_2G
))
5294 band
= wlc
->bandstate
[OTHERBANDUNIT(wlc
)];
5298 /* update configuration value */
5300 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_USER
, gmode
);
5302 /* Clear rateset override */
5303 memset(&rs
, 0, sizeof(struct brcms_c_rateset
));
5306 case GMODE_LEGACY_B
:
5307 shortslot
= BRCMS_SHORTSLOT_OFF
;
5308 brcms_c_rateset_copy(&gphy_legacy_rates
, &rs
);
5316 /* Accept defaults */
5321 preamble
= BRCMS_PLCP_SHORT
;
5322 preamble_restrict
= true;
5325 case GMODE_PERFORMANCE
:
5326 shortslot
= BRCMS_SHORTSLOT_ON
;
5327 shortslot_restrict
= true;
5329 preamble
= BRCMS_PLCP_SHORT
;
5330 preamble_restrict
= true;
5335 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: invalid gmode %d\n",
5336 wlc
->pub
->unit
, __func__
, gmode
);
5340 band
->gmode
= gmode
;
5342 wlc
->shortslot_override
= shortslot
;
5344 /* Use the default 11g rateset */
5346 brcms_c_rateset_copy(&cck_ofdm_rates
, &rs
);
5349 for (i
= 0; i
< rs
.count
; i
++) {
5350 if (rs
.rates
[i
] == BRCM_RATE_6M
5351 || rs
.rates
[i
] == BRCM_RATE_12M
5352 || rs
.rates
[i
] == BRCM_RATE_24M
)
5353 rs
.rates
[i
] |= BRCMS_RATE_FLAG
;
5357 /* Set default bss rateset */
5358 wlc
->default_bss
->rateset
.count
= rs
.count
;
5359 memcpy(wlc
->default_bss
->rateset
.rates
, rs
.rates
,
5360 sizeof(wlc
->default_bss
->rateset
.rates
));
5365 int brcms_c_set_nmode(struct brcms_c_info
*wlc
)
5370 if (wlc
->stf
->txstreams
== WL_11N_3x3
)
5375 /* force GMODE_AUTO if NMODE is ON */
5376 brcms_c_set_gmode(wlc
, GMODE_AUTO
, true);
5377 if (nmode
== WL_11N_3x3
)
5378 wlc
->pub
->_n_enab
= SUPPORT_HT
;
5380 wlc
->pub
->_n_enab
= SUPPORT_11N
;
5381 wlc
->default_bss
->flags
|= BRCMS_BSS_HT
;
5382 /* add the mcs rates to the default and hw ratesets */
5383 brcms_c_rateset_mcs_build(&wlc
->default_bss
->rateset
,
5384 wlc
->stf
->txstreams
);
5385 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++)
5386 memcpy(wlc
->bandstate
[i
]->hw_rateset
.mcs
,
5387 wlc
->default_bss
->rateset
.mcs
, MCSSET_LEN
);
5393 brcms_c_set_internal_rateset(struct brcms_c_info
*wlc
,
5394 struct brcms_c_rateset
*rs_arg
)
5396 struct brcms_c_rateset rs
, new;
5399 memcpy(&rs
, rs_arg
, sizeof(struct brcms_c_rateset
));
5401 /* check for bad count value */
5402 if ((rs
.count
== 0) || (rs
.count
> BRCMS_NUMRATES
))
5405 /* try the current band */
5406 bandunit
= wlc
->band
->bandunit
;
5407 memcpy(&new, &rs
, sizeof(struct brcms_c_rateset
));
5408 if (brcms_c_rate_hwrs_filter_sort_validate
5409 (&new, &wlc
->bandstate
[bandunit
]->hw_rateset
, true,
5410 wlc
->stf
->txstreams
))
5413 /* try the other band */
5414 if (brcms_is_mband_unlocked(wlc
)) {
5415 bandunit
= OTHERBANDUNIT(wlc
);
5416 memcpy(&new, &rs
, sizeof(struct brcms_c_rateset
));
5417 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5419 bandstate
[bandunit
]->
5421 wlc
->stf
->txstreams
))
5428 /* apply new rateset */
5429 memcpy(&wlc
->default_bss
->rateset
, &new,
5430 sizeof(struct brcms_c_rateset
));
5431 memcpy(&wlc
->bandstate
[bandunit
]->defrateset
, &new,
5432 sizeof(struct brcms_c_rateset
));
5436 static void brcms_c_ofdm_rateset_war(struct brcms_c_info
*wlc
)
5441 if (wlc
->bsscfg
->associated
)
5442 r
= wlc
->bsscfg
->current_bss
->rateset
.rates
[0];
5444 r
= wlc
->default_bss
->rateset
.rates
[0];
5446 wlc_phy_ofdm_rateset_war(wlc
->band
->pi
, war
);
5449 int brcms_c_set_channel(struct brcms_c_info
*wlc
, u16 channel
)
5451 u16 chspec
= ch20mhz_chspec(channel
);
5453 if (channel
< 0 || channel
> MAXCHANNEL
)
5456 if (!brcms_c_valid_chanspec_db(wlc
->cmi
, chspec
))
5460 if (!wlc
->pub
->up
&& brcms_is_mband_unlocked(wlc
)) {
5461 if (wlc
->band
->bandunit
!= chspec_bandunit(chspec
))
5462 wlc
->bandinit_pending
= true;
5464 wlc
->bandinit_pending
= false;
5467 wlc
->default_bss
->chanspec
= chspec
;
5468 /* brcms_c_BSSinit() will sanitize the rateset before
5470 if (wlc
->pub
->up
&& (wlc_phy_chanspec_get(wlc
->band
->pi
) != chspec
)) {
5471 brcms_c_set_home_chanspec(wlc
, chspec
);
5472 brcms_c_suspend_mac_and_wait(wlc
);
5473 brcms_c_set_chanspec(wlc
, chspec
);
5474 brcms_c_enable_mac(wlc
);
5479 int brcms_c_set_rate_limit(struct brcms_c_info
*wlc
, u16 srl
, u16 lrl
)
5483 if (srl
< 1 || srl
> RETRY_SHORT_MAX
||
5484 lrl
< 1 || lrl
> RETRY_SHORT_MAX
)
5490 brcms_b_retrylimit_upd(wlc
->hw
, wlc
->SRL
, wlc
->LRL
);
5492 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++) {
5493 wlc
->wme_retries
[ac
] = SFIELD(wlc
->wme_retries
[ac
],
5494 EDCF_SHORT
, wlc
->SRL
);
5495 wlc
->wme_retries
[ac
] = SFIELD(wlc
->wme_retries
[ac
],
5496 EDCF_LONG
, wlc
->LRL
);
5498 brcms_c_wme_retries_write(wlc
);
5503 void brcms_c_get_current_rateset(struct brcms_c_info
*wlc
,
5504 struct brcm_rateset
*currs
)
5506 struct brcms_c_rateset
*rs
;
5508 if (wlc
->pub
->associated
)
5509 rs
= &wlc
->bsscfg
->current_bss
->rateset
;
5511 rs
= &wlc
->default_bss
->rateset
;
5513 /* Copy only legacy rateset section */
5514 currs
->count
= rs
->count
;
5515 memcpy(&currs
->rates
, &rs
->rates
, rs
->count
);
5518 int brcms_c_set_rateset(struct brcms_c_info
*wlc
, struct brcm_rateset
*rs
)
5520 struct brcms_c_rateset internal_rs
;
5523 if (rs
->count
> BRCMS_NUMRATES
)
5526 memset(&internal_rs
, 0, sizeof(struct brcms_c_rateset
));
5528 /* Copy only legacy rateset section */
5529 internal_rs
.count
= rs
->count
;
5530 memcpy(&internal_rs
.rates
, &rs
->rates
, internal_rs
.count
);
5532 /* merge rateset coming in with the current mcsset */
5533 if (wlc
->pub
->_n_enab
& SUPPORT_11N
) {
5534 struct brcms_bss_info
*mcsset_bss
;
5535 if (wlc
->bsscfg
->associated
)
5536 mcsset_bss
= wlc
->bsscfg
->current_bss
;
5538 mcsset_bss
= wlc
->default_bss
;
5539 memcpy(internal_rs
.mcs
, &mcsset_bss
->rateset
.mcs
[0],
5543 bcmerror
= brcms_c_set_internal_rateset(wlc
, &internal_rs
);
5545 brcms_c_ofdm_rateset_war(wlc
);
5550 int brcms_c_set_beacon_period(struct brcms_c_info
*wlc
, u16 period
)
5552 if (period
< DOT11_MIN_BEACON_PERIOD
||
5553 period
> DOT11_MAX_BEACON_PERIOD
)
5556 wlc
->default_bss
->beacon_period
= period
;
5560 u16
brcms_c_get_phy_type(struct brcms_c_info
*wlc
, int phyidx
)
5562 return wlc
->band
->phytype
;
5565 void brcms_c_set_shortslot_override(struct brcms_c_info
*wlc
, s8 sslot_override
)
5567 wlc
->shortslot_override
= sslot_override
;
5570 * shortslot is an 11g feature, so no more work if we are
5571 * currently on the 5G band
5573 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
5576 if (wlc
->pub
->up
&& wlc
->pub
->associated
) {
5577 /* let watchdog or beacon processing update shortslot */
5578 } else if (wlc
->pub
->up
) {
5579 /* unassociated shortslot is off */
5580 brcms_c_switch_shortslot(wlc
, false);
5582 /* driver is down, so just update the brcms_c_info
5584 if (wlc
->shortslot_override
== BRCMS_SHORTSLOT_AUTO
)
5585 wlc
->shortslot
= false;
5588 (wlc
->shortslot_override
==
5589 BRCMS_SHORTSLOT_ON
);
5594 * register watchdog and down handlers.
5596 int brcms_c_module_register(struct brcms_pub
*pub
,
5597 const char *name
, struct brcms_info
*hdl
,
5598 int (*d_fn
)(void *handle
))
5600 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) pub
->wlc
;
5603 /* find an empty entry and just add, no duplication check! */
5604 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5605 if (wlc
->modulecb
[i
].name
[0] == '\0') {
5606 strncpy(wlc
->modulecb
[i
].name
, name
,
5607 sizeof(wlc
->modulecb
[i
].name
) - 1);
5608 wlc
->modulecb
[i
].hdl
= hdl
;
5609 wlc
->modulecb
[i
].down_fn
= d_fn
;
5617 /* unregister module callbacks */
5618 int brcms_c_module_unregister(struct brcms_pub
*pub
, const char *name
,
5619 struct brcms_info
*hdl
)
5621 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) pub
->wlc
;
5627 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5628 if (!strcmp(wlc
->modulecb
[i
].name
, name
) &&
5629 (wlc
->modulecb
[i
].hdl
== hdl
)) {
5630 memset(&wlc
->modulecb
[i
], 0, sizeof(struct modulecb
));
5635 /* table not found! */
5639 static bool brcms_c_chipmatch_pci(struct bcma_device
*core
)
5641 struct pci_dev
*pcidev
= core
->bus
->host_pci
;
5642 u16 vendor
= pcidev
->vendor
;
5643 u16 device
= pcidev
->device
;
5645 if (vendor
!= PCI_VENDOR_ID_BROADCOM
) {
5646 pr_err("unknown vendor id %04x\n", vendor
);
5650 if (device
== BCM43224_D11N_ID_VEN1
|| device
== BCM43224_CHIP_ID
)
5652 if ((device
== BCM43224_D11N_ID
) || (device
== BCM43225_D11N2G_ID
))
5654 if (device
== BCM4313_D11N2G_ID
)
5656 if ((device
== BCM43236_D11N_ID
) || (device
== BCM43236_D11N2G_ID
))
5659 pr_err("unknown device id %04x\n", device
);
5663 static bool brcms_c_chipmatch_soc(struct bcma_device
*core
)
5665 struct bcma_chipinfo
*chipinfo
= &core
->bus
->chipinfo
;
5667 if (chipinfo
->id
== BCMA_CHIP_ID_BCM4716
)
5670 pr_err("unknown chip id %04x\n", chipinfo
->id
);
5674 bool brcms_c_chipmatch(struct bcma_device
*core
)
5676 switch (core
->bus
->hosttype
) {
5677 case BCMA_HOSTTYPE_PCI
:
5678 return brcms_c_chipmatch_pci(core
);
5679 case BCMA_HOSTTYPE_SOC
:
5680 return brcms_c_chipmatch_soc(core
);
5682 pr_err("unknown host type: %i\n", core
->bus
->hosttype
);
5687 u16
brcms_b_rate_shm_offset(struct brcms_hardware
*wlc_hw
, u8 rate
)
5692 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5693 if (is_ofdm_rate(rate
))
5694 table_ptr
= M_RT_DIRMAP_A
;
5696 table_ptr
= M_RT_DIRMAP_B
;
5698 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5699 * the index into the rate table.
5701 phy_rate
= rate_info
[rate
] & BRCMS_RATE_MASK
;
5702 index
= phy_rate
& 0xf;
5704 /* Find the SHM pointer to the rate table entry by looking in the
5707 return 2 * brcms_b_read_shm(wlc_hw
, table_ptr
+ (index
* 2));
5711 * bcmc_fid_generate:
5712 * Generate frame ID for a BCMC packet. The frag field is not used
5713 * for MC frames so is used as part of the sequence number.
5716 bcmc_fid_generate(struct brcms_c_info
*wlc
, struct brcms_bss_cfg
*bsscfg
,
5721 frameid
= le16_to_cpu(txh
->TxFrameID
) & ~(TXFID_SEQ_MASK
|
5725 mc_fid_counter
++) << TXFID_SEQ_SHIFT
) & TXFID_SEQ_MASK
) |
5732 brcms_c_calc_ack_time(struct brcms_c_info
*wlc
, u32 rspec
,
5738 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5739 * is less than or equal to the rate of the immediately previous
5742 rspec
= brcms_basic_rate(wlc
, rspec
);
5743 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5745 brcms_c_calc_frame_time(wlc
, rspec
, preamble_type
,
5746 (DOT11_ACK_LEN
+ FCS_LEN
));
5751 brcms_c_calc_cts_time(struct brcms_c_info
*wlc
, u32 rspec
,
5754 return brcms_c_calc_ack_time(wlc
, rspec
, preamble_type
);
5758 brcms_c_calc_ba_time(struct brcms_c_info
*wlc
, u32 rspec
,
5762 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5763 * is less than or equal to the rate of the immediately previous
5766 rspec
= brcms_basic_rate(wlc
, rspec
);
5767 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5768 return brcms_c_calc_frame_time(wlc
, rspec
, preamble_type
,
5769 (DOT11_BA_LEN
+ DOT11_BA_BITMAP_LEN
+
5773 /* brcms_c_compute_frame_dur()
5775 * Calculate the 802.11 MAC header DUR field for MPDU
5776 * DUR for a single frame = 1 SIFS + 1 ACK
5777 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5779 * rate MPDU rate in unit of 500kbps
5780 * next_frag_len next MPDU length in bytes
5781 * preamble_type use short/GF or long/MM PLCP header
5784 brcms_c_compute_frame_dur(struct brcms_c_info
*wlc
, u32 rate
,
5785 u8 preamble_type
, uint next_frag_len
)
5789 sifs
= get_sifs(wlc
->band
);
5792 dur
+= (u16
) brcms_c_calc_ack_time(wlc
, rate
, preamble_type
);
5794 if (next_frag_len
) {
5795 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5797 /* add another SIFS and the frag time */
5800 (u16
) brcms_c_calc_frame_time(wlc
, rate
, preamble_type
,
5806 /* The opposite of brcms_c_calc_frame_time */
5808 brcms_c_calc_frame_len(struct brcms_c_info
*wlc
, u32 ratespec
,
5809 u8 preamble_type
, uint dur
)
5811 uint nsyms
, mac_len
, Ndps
, kNdps
;
5812 uint rate
= rspec2rate(ratespec
);
5814 if (is_mcs_rate(ratespec
)) {
5815 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
5816 int tot_streams
= mcs_2_txstreams(mcs
) + rspec_stc(ratespec
);
5817 dur
-= PREN_PREAMBLE
+ (tot_streams
* PREN_PREAMBLE_EXT
);
5818 /* payload calculation matches that of regular ofdm */
5819 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
5820 dur
-= DOT11_OFDM_SIGNAL_EXTENSION
;
5821 /* kNdbps = kbps * 4 */
5822 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
5823 rspec_issgi(ratespec
)) * 4;
5824 nsyms
= dur
/ APHY_SYMBOL_TIME
;
5827 ((APHY_SERVICE_NBITS
+ APHY_TAIL_NBITS
) * 1000)) / 8000;
5828 } else if (is_ofdm_rate(ratespec
)) {
5829 dur
-= APHY_PREAMBLE_TIME
;
5830 dur
-= APHY_SIGNAL_TIME
;
5831 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5833 nsyms
= dur
/ APHY_SYMBOL_TIME
;
5836 (APHY_SERVICE_NBITS
+ APHY_TAIL_NBITS
)) / 8;
5838 if (preamble_type
& BRCMS_SHORT_PREAMBLE
)
5839 dur
-= BPHY_PLCP_SHORT_TIME
;
5841 dur
-= BPHY_PLCP_TIME
;
5842 mac_len
= dur
* rate
;
5843 /* divide out factor of 2 in rate (1/2 mbps) */
5844 mac_len
= mac_len
/ 8 / 2;
5850 * Return true if the specified rate is supported by the specified band.
5851 * BRCM_BAND_AUTO indicates the current band.
5853 static bool brcms_c_valid_rate(struct brcms_c_info
*wlc
, u32 rspec
, int band
,
5856 struct brcms_c_rateset
*hw_rateset
;
5859 if ((band
== BRCM_BAND_AUTO
) || (band
== wlc
->band
->bandtype
))
5860 hw_rateset
= &wlc
->band
->hw_rateset
;
5861 else if (wlc
->pub
->_nbands
> 1)
5862 hw_rateset
= &wlc
->bandstate
[OTHERBANDUNIT(wlc
)]->hw_rateset
;
5864 /* other band specified and we are a single band device */
5867 /* check if this is a mimo rate */
5868 if (is_mcs_rate(rspec
)) {
5869 if ((rspec
& RSPEC_RATE_MASK
) >= MCS_TABLE_SIZE
)
5872 return isset(hw_rateset
->mcs
, (rspec
& RSPEC_RATE_MASK
));
5875 for (i
= 0; i
< hw_rateset
->count
; i
++)
5876 if (hw_rateset
->rates
[i
] == rspec2rate(rspec
))
5880 brcms_err(wlc
->hw
->d11core
, "wl%d: valid_rate: rate spec 0x%x "
5881 "not in hw_rateset\n", wlc
->pub
->unit
, rspec
);
5887 mac80211_wlc_set_nrate(struct brcms_c_info
*wlc
, struct brcms_band
*cur_band
,
5890 struct bcma_device
*core
= wlc
->hw
->d11core
;
5891 u8 stf
= (int_val
& NRATE_STF_MASK
) >> NRATE_STF_SHIFT
;
5892 u8 rate
= int_val
& NRATE_RATE_MASK
;
5894 bool ismcs
= ((int_val
& NRATE_MCS_INUSE
) == NRATE_MCS_INUSE
);
5895 bool issgi
= ((int_val
& NRATE_SGI_MASK
) >> NRATE_SGI_SHIFT
);
5896 bool override_mcs_only
= ((int_val
& NRATE_OVERRIDE_MCS_ONLY
)
5897 == NRATE_OVERRIDE_MCS_ONLY
);
5903 /* validate the combination of rate/mcs/stf is allowed */
5904 if ((wlc
->pub
->_n_enab
& SUPPORT_11N
) && ismcs
) {
5905 /* mcs only allowed when nmode */
5906 if (stf
> PHY_TXC1_MODE_SDM
) {
5907 brcms_err(core
, "wl%d: %s: Invalid stf\n",
5908 wlc
->pub
->unit
, __func__
);
5913 /* mcs 32 is a special case, DUP mode 40 only */
5915 if (!CHSPEC_IS40(wlc
->home_chanspec
) ||
5916 ((stf
!= PHY_TXC1_MODE_SISO
)
5917 && (stf
!= PHY_TXC1_MODE_CDD
))) {
5918 brcms_err(core
, "wl%d: %s: Invalid mcs 32\n",
5919 wlc
->pub
->unit
, __func__
);
5923 /* mcs > 7 must use stf SDM */
5924 } else if (rate
> HIGHEST_SINGLE_STREAM_MCS
) {
5925 /* mcs > 7 must use stf SDM */
5926 if (stf
!= PHY_TXC1_MODE_SDM
) {
5927 brcms_dbg_mac80211(core
, "wl%d: enabling "
5928 "SDM mode for mcs %d\n",
5929 wlc
->pub
->unit
, rate
);
5930 stf
= PHY_TXC1_MODE_SDM
;
5934 * MCS 0-7 may use SISO, CDD, and for
5937 if ((stf
> PHY_TXC1_MODE_STBC
) ||
5938 (!BRCMS_STBC_CAP_PHY(wlc
)
5939 && (stf
== PHY_TXC1_MODE_STBC
))) {
5940 brcms_err(core
, "wl%d: %s: Invalid STBC\n",
5941 wlc
->pub
->unit
, __func__
);
5946 } else if (is_ofdm_rate(rate
)) {
5947 if ((stf
!= PHY_TXC1_MODE_CDD
) && (stf
!= PHY_TXC1_MODE_SISO
)) {
5948 brcms_err(core
, "wl%d: %s: Invalid OFDM\n",
5949 wlc
->pub
->unit
, __func__
);
5953 } else if (is_cck_rate(rate
)) {
5954 if ((cur_band
->bandtype
!= BRCM_BAND_2G
)
5955 || (stf
!= PHY_TXC1_MODE_SISO
)) {
5956 brcms_err(core
, "wl%d: %s: Invalid CCK\n",
5957 wlc
->pub
->unit
, __func__
);
5962 brcms_err(core
, "wl%d: %s: Unknown rate type\n",
5963 wlc
->pub
->unit
, __func__
);
5967 /* make sure multiple antennae are available for non-siso rates */
5968 if ((stf
!= PHY_TXC1_MODE_SISO
) && (wlc
->stf
->txstreams
== 1)) {
5969 brcms_err(core
, "wl%d: %s: SISO antenna but !SISO "
5970 "request\n", wlc
->pub
->unit
, __func__
);
5977 rspec
|= RSPEC_MIMORATE
;
5978 /* For STBC populate the STC field of the ratespec */
5979 if (stf
== PHY_TXC1_MODE_STBC
) {
5981 stc
= 1; /* Nss for single stream is always 1 */
5982 rspec
|= (stc
<< RSPEC_STC_SHIFT
);
5986 rspec
|= (stf
<< RSPEC_STF_SHIFT
);
5988 if (override_mcs_only
)
5989 rspec
|= RSPEC_OVERRIDE_MCS_ONLY
;
5992 rspec
|= RSPEC_SHORT_GI
;
5995 && !brcms_c_valid_rate(wlc
, rspec
, cur_band
->bandtype
, true))
6004 * Compute PLCP, but only requires actual rate and length of pkt.
6005 * Rate is given in the driver standard multiple of 500 kbps.
6006 * le is set for 11 Mbps rate if necessary.
6007 * Broken out for PRQ.
6010 static void brcms_c_cck_plcp_set(struct brcms_c_info
*wlc
, int rate_500
,
6011 uint length
, u8
*plcp
)
6024 usec
= (length
<< 4) / 11;
6025 if ((length
<< 4) - (usec
* 11) > 0)
6029 usec
= (length
<< 3) / 11;
6030 if ((length
<< 3) - (usec
* 11) > 0) {
6032 if ((usec
* 11) - (length
<< 3) >= 8)
6033 le
= D11B_PLCP_SIGNAL_LE
;
6038 brcms_err(wlc
->hw
->d11core
,
6039 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6041 rate_500
= BRCM_RATE_1M
;
6045 /* PLCP signal byte */
6046 plcp
[0] = rate_500
* 5; /* r (500kbps) * 5 == r (100kbps) */
6047 /* PLCP service byte */
6048 plcp
[1] = (u8
) (le
| D11B_PLCP_SIGNAL_LOCKED
);
6049 /* PLCP length u16, little endian */
6050 plcp
[2] = usec
& 0xff;
6051 plcp
[3] = (usec
>> 8) & 0xff;
6057 /* Rate: 802.11 rate code, length: PSDU length in octets */
6058 static void brcms_c_compute_mimo_plcp(u32 rspec
, uint length
, u8
*plcp
)
6060 u8 mcs
= (u8
) (rspec
& RSPEC_RATE_MASK
);
6062 if (rspec_is40mhz(rspec
) || (mcs
== 32))
6063 plcp
[0] |= MIMO_PLCP_40MHZ
;
6064 BRCMS_SET_MIMO_PLCP_LEN(plcp
, length
);
6065 plcp
[3] = rspec_mimoplcp3(rspec
); /* rspec already holds this byte */
6066 plcp
[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6067 plcp
[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6071 /* Rate: 802.11 rate code, length: PSDU length in octets */
6073 brcms_c_compute_ofdm_plcp(u32 rspec
, u32 length
, u8
*plcp
)
6077 int rate
= rspec2rate(rspec
);
6080 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6083 rate_signal
= rate_info
[rate
] & BRCMS_RATE_MASK
;
6084 memset(plcp
, 0, D11_PHY_HDR_LEN
);
6085 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr
*) plcp
, rate_signal
);
6087 tmp
= (length
& 0xfff) << 5;
6088 plcp
[2] |= (tmp
>> 16) & 0xff;
6089 plcp
[1] |= (tmp
>> 8) & 0xff;
6090 plcp
[0] |= tmp
& 0xff;
6093 /* Rate: 802.11 rate code, length: PSDU length in octets */
6094 static void brcms_c_compute_cck_plcp(struct brcms_c_info
*wlc
, u32 rspec
,
6095 uint length
, u8
*plcp
)
6097 int rate
= rspec2rate(rspec
);
6099 brcms_c_cck_plcp_set(wlc
, rate
, length
, plcp
);
6103 brcms_c_compute_plcp(struct brcms_c_info
*wlc
, u32 rspec
,
6104 uint length
, u8
*plcp
)
6106 if (is_mcs_rate(rspec
))
6107 brcms_c_compute_mimo_plcp(rspec
, length
, plcp
);
6108 else if (is_ofdm_rate(rspec
))
6109 brcms_c_compute_ofdm_plcp(rspec
, length
, plcp
);
6111 brcms_c_compute_cck_plcp(wlc
, rspec
, length
, plcp
);
6114 /* brcms_c_compute_rtscts_dur()
6116 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6117 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6118 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6120 * cts cts-to-self or rts/cts
6121 * rts_rate rts or cts rate in unit of 500kbps
6122 * rate next MPDU rate in unit of 500kbps
6123 * frame_len next MPDU frame length in bytes
6126 brcms_c_compute_rtscts_dur(struct brcms_c_info
*wlc
, bool cts_only
,
6128 u32 frame_rate
, u8 rts_preamble_type
,
6129 u8 frame_preamble_type
, uint frame_len
, bool ba
)
6133 sifs
= get_sifs(wlc
->band
);
6139 (u16
) brcms_c_calc_cts_time(wlc
, rts_rate
,
6147 (u16
) brcms_c_calc_frame_time(wlc
, frame_rate
, frame_preamble_type
,
6151 (u16
) brcms_c_calc_ba_time(wlc
, frame_rate
,
6152 BRCMS_SHORT_PREAMBLE
);
6155 (u16
) brcms_c_calc_ack_time(wlc
, frame_rate
,
6156 frame_preamble_type
);
6160 static u16
brcms_c_phytxctl1_calc(struct brcms_c_info
*wlc
, u32 rspec
)
6165 if (BRCMS_ISLCNPHY(wlc
->band
)) {
6166 bw
= PHY_TXC1_BW_20MHZ
;
6168 bw
= rspec_get_bw(rspec
);
6169 /* 10Mhz is not supported yet */
6170 if (bw
< PHY_TXC1_BW_20MHZ
) {
6171 brcms_err(wlc
->hw
->d11core
, "phytxctl1_calc: bw %d is "
6172 "not supported yet, set to 20L\n", bw
);
6173 bw
= PHY_TXC1_BW_20MHZ
;
6177 if (is_mcs_rate(rspec
)) {
6178 uint mcs
= rspec
& RSPEC_RATE_MASK
;
6180 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6181 phyctl1
= rspec_phytxbyte2(rspec
);
6182 /* set the upper byte of phyctl1 */
6183 phyctl1
|= (mcs_table
[mcs
].tx_phy_ctl3
<< 8);
6184 } else if (is_cck_rate(rspec
) && !BRCMS_ISLCNPHY(wlc
->band
)
6185 && !BRCMS_ISSSLPNPHY(wlc
->band
)) {
6187 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6188 * Data Rate. Eventually MIMOPHY would also be converted to
6191 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6192 phyctl1
= (bw
| (rspec_stf(rspec
) << PHY_TXC1_MODE_SHIFT
));
6193 } else { /* legacy OFDM/CCK */
6195 /* get the phyctl byte from rate phycfg table */
6196 phycfg
= brcms_c_rate_legacy_phyctl(rspec2rate(rspec
));
6198 brcms_err(wlc
->hw
->d11core
, "phytxctl1_calc: wrong "
6199 "legacy OFDM/CCK rate\n");
6202 /* set the upper byte of phyctl1 */
6204 (bw
| (phycfg
<< 8) |
6205 (rspec_stf(rspec
) << PHY_TXC1_MODE_SHIFT
));
6211 * Add struct d11txh, struct cck_phy_hdr.
6213 * 'p' data must start with 802.11 MAC header
6214 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6216 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6220 brcms_c_d11hdrs_mac80211(struct brcms_c_info
*wlc
, struct ieee80211_hw
*hw
,
6221 struct sk_buff
*p
, struct scb
*scb
, uint frag
,
6222 uint nfrags
, uint queue
, uint next_frag_len
)
6224 struct ieee80211_hdr
*h
;
6226 u8
*plcp
, plcp_fallback
[D11_PHY_HDR_LEN
];
6227 int len
, phylen
, rts_phylen
;
6228 u16 mch
, phyctl
, xfts
, mainrates
;
6229 u16 seq
= 0, mcl
= 0, status
= 0, frameid
= 0;
6230 u32 rspec
[2] = { BRCM_RATE_1M
, BRCM_RATE_1M
};
6231 u32 rts_rspec
[2] = { BRCM_RATE_1M
, BRCM_RATE_1M
};
6232 bool use_rts
= false;
6233 bool use_cts
= false;
6234 bool use_rifs
= false;
6235 bool short_preamble
[2] = { false, false };
6236 u8 preamble_type
[2] = { BRCMS_LONG_PREAMBLE
, BRCMS_LONG_PREAMBLE
};
6237 u8 rts_preamble_type
[2] = { BRCMS_LONG_PREAMBLE
, BRCMS_LONG_PREAMBLE
};
6238 u8
*rts_plcp
, rts_plcp_fallback
[D11_PHY_HDR_LEN
];
6239 struct ieee80211_rts
*rts
= NULL
;
6242 bool hwtkmic
= false;
6243 u16 mimo_ctlchbw
= PHY_TXC1_BW_20MHZ
;
6244 #define ANTCFG_NONE 0xFF
6245 u8 antcfg
= ANTCFG_NONE
;
6246 u8 fbantcfg
= ANTCFG_NONE
;
6247 uint phyctl1_stf
= 0;
6249 struct ieee80211_tx_rate
*txrate
[2];
6251 struct ieee80211_tx_info
*tx_info
;
6254 u8 mimo_preamble_type
;
6256 /* locate 802.11 MAC header */
6257 h
= (struct ieee80211_hdr
*)(p
->data
);
6258 qos
= ieee80211_is_data_qos(h
->frame_control
);
6260 /* compute length of frame in bytes for use in PLCP computations */
6262 phylen
= len
+ FCS_LEN
;
6265 tx_info
= IEEE80211_SKB_CB(p
);
6268 plcp
= skb_push(p
, D11_PHY_HDR_LEN
);
6270 /* add Broadcom tx descriptor header */
6271 txh
= (struct d11txh
*) skb_push(p
, D11_TXH_LEN
);
6272 memset(txh
, 0, D11_TXH_LEN
);
6275 if (tx_info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
6276 /* non-AP STA should never use BCMC queue */
6277 if (queue
== TX_BCMC_FIFO
) {
6278 brcms_err(wlc
->hw
->d11core
,
6279 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6280 wlc
->pub
->unit
, __func__
);
6281 frameid
= bcmc_fid_generate(wlc
, NULL
, txh
);
6283 /* Increment the counter for first fragment */
6284 if (tx_info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
6285 scb
->seqnum
[p
->priority
]++;
6287 /* extract fragment number from frame first */
6288 seq
= le16_to_cpu(h
->seq_ctrl
) & FRAGNUM_MASK
;
6289 seq
|= (scb
->seqnum
[p
->priority
] << SEQNUM_SHIFT
);
6290 h
->seq_ctrl
= cpu_to_le16(seq
);
6292 frameid
= ((seq
<< TXFID_SEQ_SHIFT
) & TXFID_SEQ_MASK
) |
6293 (queue
& TXFID_QUEUE_MASK
);
6296 frameid
|= queue
& TXFID_QUEUE_MASK
;
6298 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6299 if (ieee80211_is_beacon(h
->frame_control
))
6300 mcl
|= TXC_IGNOREPMQ
;
6302 txrate
[0] = tx_info
->control
.rates
;
6303 txrate
[1] = txrate
[0] + 1;
6306 * if rate control algorithm didn't give us a fallback
6307 * rate, use the primary rate
6309 if (txrate
[1]->idx
< 0)
6310 txrate
[1] = txrate
[0];
6312 for (k
= 0; k
< hw
->max_rates
; k
++) {
6313 is_mcs
= txrate
[k
]->flags
& IEEE80211_TX_RC_MCS
? true : false;
6315 if ((txrate
[k
]->idx
>= 0)
6316 && (txrate
[k
]->idx
<
6317 hw
->wiphy
->bands
[tx_info
->band
]->n_bitrates
)) {
6319 hw
->wiphy
->bands
[tx_info
->band
]->
6320 bitrates
[txrate
[k
]->idx
].hw_value
;
6323 flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
?
6326 rspec
[k
] = BRCM_RATE_1M
;
6329 rspec
[k
] = mac80211_wlc_set_nrate(wlc
, wlc
->band
,
6330 NRATE_MCS_INUSE
| txrate
[k
]->idx
);
6334 * Currently only support same setting for primay and
6335 * fallback rates. Unify flags for each rate into a
6336 * single value for the frame
6340 flags
& IEEE80211_TX_RC_USE_RTS_CTS
? true : false;
6343 flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
? true : false;
6348 * determine and validate primary rate
6349 * and fallback rates
6351 if (!rspec_active(rspec
[k
])) {
6352 rspec
[k
] = BRCM_RATE_1M
;
6354 if (!is_multicast_ether_addr(h
->addr1
)) {
6355 /* set tx antenna config */
6356 brcms_c_antsel_antcfg_get(wlc
->asi
, false,
6357 false, 0, 0, &antcfg
, &fbantcfg
);
6362 phyctl1_stf
= wlc
->stf
->ss_opmode
;
6364 if (wlc
->pub
->_n_enab
& SUPPORT_11N
) {
6365 for (k
= 0; k
< hw
->max_rates
; k
++) {
6367 * apply siso/cdd to single stream mcs's or ofdm
6368 * if rspec is auto selected
6370 if (((is_mcs_rate(rspec
[k
]) &&
6371 is_single_stream(rspec
[k
] & RSPEC_RATE_MASK
)) ||
6372 is_ofdm_rate(rspec
[k
]))
6373 && ((rspec
[k
] & RSPEC_OVERRIDE_MCS_ONLY
)
6374 || !(rspec
[k
] & RSPEC_OVERRIDE
))) {
6375 rspec
[k
] &= ~(RSPEC_STF_MASK
| RSPEC_STC_MASK
);
6377 /* For SISO MCS use STBC if possible */
6378 if (is_mcs_rate(rspec
[k
])
6379 && BRCMS_STF_SS_STBC_TX(wlc
, scb
)) {
6382 /* Nss for single stream is always 1 */
6384 rspec
[k
] |= (PHY_TXC1_MODE_STBC
<<
6386 (stc
<< RSPEC_STC_SHIFT
);
6389 (phyctl1_stf
<< RSPEC_STF_SHIFT
);
6393 * Is the phy configured to use 40MHZ frames? If
6394 * so then pick the desired txbw
6396 if (brcms_chspec_bw(wlc
->chanspec
) == BRCMS_40_MHZ
) {
6397 /* default txbw is 20in40 SB */
6398 mimo_ctlchbw
= mimo_txbw
=
6399 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6401 ? PHY_TXC1_BW_20MHZ_UP
: PHY_TXC1_BW_20MHZ
;
6403 if (is_mcs_rate(rspec
[k
])) {
6404 /* mcs 32 must be 40b/w DUP */
6405 if ((rspec
[k
] & RSPEC_RATE_MASK
)
6408 PHY_TXC1_BW_40MHZ_DUP
;
6410 } else if (wlc
->mimo_40txbw
!= AUTO
)
6411 mimo_txbw
= wlc
->mimo_40txbw
;
6412 /* else check if dst is using 40 Mhz */
6413 else if (scb
->flags
& SCB_IS40
)
6414 mimo_txbw
= PHY_TXC1_BW_40MHZ
;
6415 } else if (is_ofdm_rate(rspec
[k
])) {
6416 if (wlc
->ofdm_40txbw
!= AUTO
)
6417 mimo_txbw
= wlc
->ofdm_40txbw
;
6418 } else if (wlc
->cck_40txbw
!= AUTO
) {
6419 mimo_txbw
= wlc
->cck_40txbw
;
6423 * mcs32 is 40 b/w only.
6424 * This is possible for probe packets on
6427 if ((rspec
[k
] & RSPEC_RATE_MASK
) == 32)
6429 rspec
[k
] = RSPEC_MIMORATE
;
6431 mimo_txbw
= PHY_TXC1_BW_20MHZ
;
6434 /* Set channel width */
6435 rspec
[k
] &= ~RSPEC_BW_MASK
;
6436 if ((k
== 0) || ((k
> 0) && is_mcs_rate(rspec
[k
])))
6437 rspec
[k
] |= (mimo_txbw
<< RSPEC_BW_SHIFT
);
6439 rspec
[k
] |= (mimo_ctlchbw
<< RSPEC_BW_SHIFT
);
6441 /* Disable short GI, not supported yet */
6442 rspec
[k
] &= ~RSPEC_SHORT_GI
;
6444 mimo_preamble_type
= BRCMS_MM_PREAMBLE
;
6445 if (txrate
[k
]->flags
& IEEE80211_TX_RC_GREEN_FIELD
)
6446 mimo_preamble_type
= BRCMS_GF_PREAMBLE
;
6448 if ((txrate
[k
]->flags
& IEEE80211_TX_RC_MCS
)
6449 && (!is_mcs_rate(rspec
[k
]))) {
6450 brcms_err(wlc
->hw
->d11core
,
6451 "wl%d: %s: IEEE80211_TX_"
6452 "RC_MCS != is_mcs_rate(rspec)\n",
6453 wlc
->pub
->unit
, __func__
);
6456 if (is_mcs_rate(rspec
[k
])) {
6457 preamble_type
[k
] = mimo_preamble_type
;
6460 * if SGI is selected, then forced mm
6463 if ((rspec
[k
] & RSPEC_SHORT_GI
)
6464 && is_single_stream(rspec
[k
] &
6466 preamble_type
[k
] = BRCMS_MM_PREAMBLE
;
6469 /* should be better conditionalized */
6470 if (!is_mcs_rate(rspec
[0])
6471 && (tx_info
->control
.rates
[0].
6472 flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
))
6473 preamble_type
[k
] = BRCMS_SHORT_PREAMBLE
;
6476 for (k
= 0; k
< hw
->max_rates
; k
++) {
6477 /* Set ctrlchbw as 20Mhz */
6478 rspec
[k
] &= ~RSPEC_BW_MASK
;
6479 rspec
[k
] |= (PHY_TXC1_BW_20MHZ
<< RSPEC_BW_SHIFT
);
6481 /* for nphy, stf of ofdm frames must follow policies */
6482 if (BRCMS_ISNPHY(wlc
->band
) && is_ofdm_rate(rspec
[k
])) {
6483 rspec
[k
] &= ~RSPEC_STF_MASK
;
6484 rspec
[k
] |= phyctl1_stf
<< RSPEC_STF_SHIFT
;
6489 /* Reset these for use with AMPDU's */
6490 txrate
[0]->count
= 0;
6491 txrate
[1]->count
= 0;
6493 /* (2) PROTECTION, may change rspec */
6494 if ((ieee80211_is_data(h
->frame_control
) ||
6495 ieee80211_is_mgmt(h
->frame_control
)) &&
6496 (phylen
> wlc
->RTSThresh
) && !is_multicast_ether_addr(h
->addr1
))
6499 /* (3) PLCP: determine PLCP header and MAC duration,
6500 * fill struct d11txh */
6501 brcms_c_compute_plcp(wlc
, rspec
[0], phylen
, plcp
);
6502 brcms_c_compute_plcp(wlc
, rspec
[1], phylen
, plcp_fallback
);
6503 memcpy(&txh
->FragPLCPFallback
,
6504 plcp_fallback
, sizeof(txh
->FragPLCPFallback
));
6506 /* Length field now put in CCK FBR CRC field */
6507 if (is_cck_rate(rspec
[1])) {
6508 txh
->FragPLCPFallback
[4] = phylen
& 0xff;
6509 txh
->FragPLCPFallback
[5] = (phylen
& 0xff00) >> 8;
6512 /* MIMO-RATE: need validation ?? */
6513 mainrates
= is_ofdm_rate(rspec
[0]) ?
6514 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr
*) plcp
) :
6517 /* DUR field for main rate */
6518 if (!ieee80211_is_pspoll(h
->frame_control
) &&
6519 !is_multicast_ether_addr(h
->addr1
) && !use_rifs
) {
6521 brcms_c_compute_frame_dur(wlc
, rspec
[0], preamble_type
[0],
6523 h
->duration_id
= cpu_to_le16(durid
);
6524 } else if (use_rifs
) {
6525 /* NAV protect to end of next max packet size */
6527 (u16
) brcms_c_calc_frame_time(wlc
, rspec
[0],
6529 DOT11_MAX_FRAG_LEN
);
6530 durid
+= RIFS_11N_TIME
;
6531 h
->duration_id
= cpu_to_le16(durid
);
6534 /* DUR field for fallback rate */
6535 if (ieee80211_is_pspoll(h
->frame_control
))
6536 txh
->FragDurFallback
= h
->duration_id
;
6537 else if (is_multicast_ether_addr(h
->addr1
) || use_rifs
)
6538 txh
->FragDurFallback
= 0;
6540 durid
= brcms_c_compute_frame_dur(wlc
, rspec
[1],
6541 preamble_type
[1], next_frag_len
);
6542 txh
->FragDurFallback
= cpu_to_le16(durid
);
6545 /* (4) MAC-HDR: MacTxControlLow */
6547 mcl
|= TXC_STARTMSDU
;
6549 if (!is_multicast_ether_addr(h
->addr1
))
6550 mcl
|= TXC_IMMEDACK
;
6552 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
6553 mcl
|= TXC_FREQBAND_5G
;
6555 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc
->band
->pi
)))
6558 /* set AMIC bit if using hardware TKIP MIC */
6562 txh
->MacTxControlLow
= cpu_to_le16(mcl
);
6564 /* MacTxControlHigh */
6567 /* Set fallback rate preamble type */
6568 if ((preamble_type
[1] == BRCMS_SHORT_PREAMBLE
) ||
6569 (preamble_type
[1] == BRCMS_GF_PREAMBLE
)) {
6570 if (rspec2rate(rspec
[1]) != BRCM_RATE_1M
)
6571 mch
|= TXC_PREAMBLE_DATA_FB_SHORT
;
6574 /* MacFrameControl */
6575 memcpy(&txh
->MacFrameControl
, &h
->frame_control
, sizeof(u16
));
6576 txh
->TxFesTimeNormal
= cpu_to_le16(0);
6578 txh
->TxFesTimeFallback
= cpu_to_le16(0);
6581 memcpy(&txh
->TxFrameRA
, &h
->addr1
, ETH_ALEN
);
6584 txh
->TxFrameID
= cpu_to_le16(frameid
);
6587 * TxStatus, Note the case of recreating the first frag of a suppressed
6588 * frame then we may need to reset the retry cnt's via the status reg
6590 txh
->TxStatus
= cpu_to_le16(status
);
6593 * extra fields for ucode AMPDU aggregation, the new fields are added to
6594 * the END of previous structure so that it's compatible in driver.
6596 txh
->MaxNMpdus
= cpu_to_le16(0);
6597 txh
->MaxABytes_MRT
= cpu_to_le16(0);
6598 txh
->MaxABytes_FBR
= cpu_to_le16(0);
6599 txh
->MinMBytes
= cpu_to_le16(0);
6601 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6602 * furnish struct d11txh */
6603 /* RTS PLCP header and RTS frame */
6604 if (use_rts
|| use_cts
) {
6605 if (use_rts
&& use_cts
)
6608 for (k
= 0; k
< 2; k
++) {
6609 rts_rspec
[k
] = brcms_c_rspec_to_rts_rspec(wlc
, rspec
[k
],
6614 if (!is_ofdm_rate(rts_rspec
[0]) &&
6615 !((rspec2rate(rts_rspec
[0]) == BRCM_RATE_1M
) ||
6616 (wlc
->PLCPHdr_override
== BRCMS_PLCP_LONG
))) {
6617 rts_preamble_type
[0] = BRCMS_SHORT_PREAMBLE
;
6618 mch
|= TXC_PREAMBLE_RTS_MAIN_SHORT
;
6621 if (!is_ofdm_rate(rts_rspec
[1]) &&
6622 !((rspec2rate(rts_rspec
[1]) == BRCM_RATE_1M
) ||
6623 (wlc
->PLCPHdr_override
== BRCMS_PLCP_LONG
))) {
6624 rts_preamble_type
[1] = BRCMS_SHORT_PREAMBLE
;
6625 mch
|= TXC_PREAMBLE_RTS_FB_SHORT
;
6628 /* RTS/CTS additions to MacTxControlLow */
6630 txh
->MacTxControlLow
|= cpu_to_le16(TXC_SENDCTS
);
6632 txh
->MacTxControlLow
|= cpu_to_le16(TXC_SENDRTS
);
6633 txh
->MacTxControlLow
|= cpu_to_le16(TXC_LONGFRAME
);
6636 /* RTS PLCP header */
6637 rts_plcp
= txh
->RTSPhyHeader
;
6639 rts_phylen
= DOT11_CTS_LEN
+ FCS_LEN
;
6641 rts_phylen
= DOT11_RTS_LEN
+ FCS_LEN
;
6643 brcms_c_compute_plcp(wlc
, rts_rspec
[0], rts_phylen
, rts_plcp
);
6645 /* fallback rate version of RTS PLCP header */
6646 brcms_c_compute_plcp(wlc
, rts_rspec
[1], rts_phylen
,
6648 memcpy(&txh
->RTSPLCPFallback
, rts_plcp_fallback
,
6649 sizeof(txh
->RTSPLCPFallback
));
6651 /* RTS frame fields... */
6652 rts
= (struct ieee80211_rts
*)&txh
->rts_frame
;
6654 durid
= brcms_c_compute_rtscts_dur(wlc
, use_cts
, rts_rspec
[0],
6655 rspec
[0], rts_preamble_type
[0],
6656 preamble_type
[0], phylen
, false);
6657 rts
->duration
= cpu_to_le16(durid
);
6658 /* fallback rate version of RTS DUR field */
6659 durid
= brcms_c_compute_rtscts_dur(wlc
, use_cts
,
6660 rts_rspec
[1], rspec
[1],
6661 rts_preamble_type
[1],
6662 preamble_type
[1], phylen
, false);
6663 txh
->RTSDurFallback
= cpu_to_le16(durid
);
6666 rts
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_CTL
|
6667 IEEE80211_STYPE_CTS
);
6669 memcpy(&rts
->ra
, &h
->addr2
, ETH_ALEN
);
6671 rts
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_CTL
|
6672 IEEE80211_STYPE_RTS
);
6674 memcpy(&rts
->ra
, &h
->addr1
, 2 * ETH_ALEN
);
6678 * low 8 bits: main frag rate/mcs,
6679 * high 8 bits: rts/cts rate/mcs
6681 mainrates
|= (is_ofdm_rate(rts_rspec
[0]) ?
6683 (struct ofdm_phy_hdr
*) rts_plcp
) :
6686 memset((char *)txh
->RTSPhyHeader
, 0, D11_PHY_HDR_LEN
);
6687 memset((char *)&txh
->rts_frame
, 0,
6688 sizeof(struct ieee80211_rts
));
6689 memset((char *)txh
->RTSPLCPFallback
, 0,
6690 sizeof(txh
->RTSPLCPFallback
));
6691 txh
->RTSDurFallback
= 0;
6694 #ifdef SUPPORT_40MHZ
6695 /* add null delimiter count */
6696 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && is_mcs_rate(rspec
))
6697 txh
->RTSPLCPFallback
[AMPDU_FBR_NULL_DELIM
] =
6698 brcm_c_ampdu_null_delim_cnt(wlc
->ampdu
, scb
, rspec
, phylen
);
6703 * Now that RTS/RTS FB preamble types are updated, write
6706 txh
->MacTxControlHigh
= cpu_to_le16(mch
);
6709 * MainRates (both the rts and frag plcp rates have
6710 * been calculated now)
6712 txh
->MainRates
= cpu_to_le16(mainrates
);
6714 /* XtraFrameTypes */
6715 xfts
= frametype(rspec
[1], wlc
->mimoft
);
6716 xfts
|= (frametype(rts_rspec
[0], wlc
->mimoft
) << XFTS_RTS_FT_SHIFT
);
6717 xfts
|= (frametype(rts_rspec
[1], wlc
->mimoft
) << XFTS_FBRRTS_FT_SHIFT
);
6718 xfts
|= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc
->band
->pi
)) <<
6720 txh
->XtraFrameTypes
= cpu_to_le16(xfts
);
6722 /* PhyTxControlWord */
6723 phyctl
= frametype(rspec
[0], wlc
->mimoft
);
6724 if ((preamble_type
[0] == BRCMS_SHORT_PREAMBLE
) ||
6725 (preamble_type
[0] == BRCMS_GF_PREAMBLE
)) {
6726 if (rspec2rate(rspec
[0]) != BRCM_RATE_1M
)
6727 phyctl
|= PHY_TXC_SHORT_HDR
;
6730 /* phytxant is properly bit shifted */
6731 phyctl
|= brcms_c_stf_d11hdrs_phyctl_txant(wlc
, rspec
[0]);
6732 txh
->PhyTxControlWord
= cpu_to_le16(phyctl
);
6734 /* PhyTxControlWord_1 */
6735 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
6738 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rspec
[0]);
6739 txh
->PhyTxControlWord_1
= cpu_to_le16(phyctl1
);
6740 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rspec
[1]);
6741 txh
->PhyTxControlWord_1_Fbr
= cpu_to_le16(phyctl1
);
6743 if (use_rts
|| use_cts
) {
6744 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rts_rspec
[0]);
6745 txh
->PhyTxControlWord_1_Rts
= cpu_to_le16(phyctl1
);
6746 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rts_rspec
[1]);
6747 txh
->PhyTxControlWord_1_FbrRts
= cpu_to_le16(phyctl1
);
6751 * For mcs frames, if mixedmode(overloaded with long preamble)
6752 * is going to be set, fill in non-zero MModeLen and/or
6753 * MModeFbrLen it will be unnecessary if they are separated
6755 if (is_mcs_rate(rspec
[0]) &&
6756 (preamble_type
[0] == BRCMS_MM_PREAMBLE
)) {
6758 brcms_c_calc_lsig_len(wlc
, rspec
[0], phylen
);
6759 txh
->MModeLen
= cpu_to_le16(mmodelen
);
6762 if (is_mcs_rate(rspec
[1]) &&
6763 (preamble_type
[1] == BRCMS_MM_PREAMBLE
)) {
6765 brcms_c_calc_lsig_len(wlc
, rspec
[1], phylen
);
6766 txh
->MModeFbrLen
= cpu_to_le16(mmodefbrlen
);
6770 ac
= skb_get_queue_mapping(p
);
6771 if ((scb
->flags
& SCB_WMECAP
) && qos
&& wlc
->edcf_txop
[ac
]) {
6772 uint frag_dur
, dur
, dur_fallback
;
6774 /* WME: Update TXOP threshold */
6775 if (!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && frag
== 0) {
6777 brcms_c_calc_frame_time(wlc
, rspec
[0],
6778 preamble_type
[0], phylen
);
6781 /* 1 RTS or CTS-to-self frame */
6783 brcms_c_calc_cts_time(wlc
, rts_rspec
[0],
6784 rts_preamble_type
[0]);
6786 brcms_c_calc_cts_time(wlc
, rts_rspec
[1],
6787 rts_preamble_type
[1]);
6788 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6789 dur
+= le16_to_cpu(rts
->duration
);
6791 le16_to_cpu(txh
->RTSDurFallback
);
6792 } else if (use_rifs
) {
6796 /* frame + SIFS + ACK */
6799 brcms_c_compute_frame_dur(wlc
, rspec
[0],
6800 preamble_type
[0], 0);
6803 brcms_c_calc_frame_time(wlc
, rspec
[1],
6807 brcms_c_compute_frame_dur(wlc
, rspec
[1],
6808 preamble_type
[1], 0);
6810 /* NEED to set TxFesTimeNormal (hard) */
6811 txh
->TxFesTimeNormal
= cpu_to_le16((u16
) dur
);
6813 * NEED to set fallback rate version of
6814 * TxFesTimeNormal (hard)
6816 txh
->TxFesTimeFallback
=
6817 cpu_to_le16((u16
) dur_fallback
);
6820 * update txop byte threshold (txop minus intraframe
6823 if (wlc
->edcf_txop
[ac
] >= (dur
- frag_dur
)) {
6827 brcms_c_calc_frame_len(wlc
,
6828 rspec
[0], preamble_type
[0],
6829 (wlc
->edcf_txop
[ac
] -
6831 /* range bound the fragthreshold */
6832 if (newfragthresh
< DOT11_MIN_FRAG_LEN
)
6835 else if (newfragthresh
>
6836 wlc
->usr_fragthresh
)
6838 wlc
->usr_fragthresh
;
6839 /* update the fragthresh and do txc update */
6840 if (wlc
->fragthresh
[queue
] !=
6841 (u16
) newfragthresh
)
6842 wlc
->fragthresh
[queue
] =
6843 (u16
) newfragthresh
;
6845 brcms_err(wlc
->hw
->d11core
,
6846 "wl%d: %s txop invalid "
6848 wlc
->pub
->unit
, fifo_names
[queue
],
6849 rspec2rate(rspec
[0]));
6852 if (dur
> wlc
->edcf_txop
[ac
])
6853 brcms_err(wlc
->hw
->d11core
,
6854 "wl%d: %s: %s txop "
6855 "exceeded phylen %d/%d dur %d/%d\n",
6856 wlc
->pub
->unit
, __func__
,
6858 phylen
, wlc
->fragthresh
[queue
],
6859 dur
, wlc
->edcf_txop
[ac
]);
6866 static int brcms_c_tx(struct brcms_c_info
*wlc
, struct sk_buff
*skb
)
6868 struct dma_pub
*dma
;
6869 int fifo
, ret
= -ENOSPC
;
6871 u16 frameid
= INVALIDFID
;
6873 fifo
= brcms_ac_to_fifo(skb_get_queue_mapping(skb
));
6874 dma
= wlc
->hw
->di
[fifo
];
6875 txh
= (struct d11txh
*)(skb
->data
);
6877 if (dma
->txavail
== 0) {
6879 * We sometimes get a frame from mac80211 after stopping
6880 * the queues. This only ever seems to be a single frame
6881 * and is seems likely to be a race. TX_HEADROOM should
6882 * ensure that we have enough space to handle these stray
6883 * packets, so warn if there isn't. If we're out of space
6884 * in the tx ring and the tx queue isn't stopped then
6885 * we've really got a bug; warn loudly if that happens.
6887 brcms_warn(wlc
->hw
->d11core
,
6888 "Received frame for tx with no space in DMA ring\n");
6889 WARN_ON(!ieee80211_queue_stopped(wlc
->pub
->ieee_hw
,
6890 skb_get_queue_mapping(skb
)));
6894 /* When a BC/MC frame is being committed to the BCMC fifo
6895 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6897 if (fifo
== TX_BCMC_FIFO
)
6898 frameid
= le16_to_cpu(txh
->TxFrameID
);
6900 /* Commit BCMC sequence number in the SHM frame ID location */
6901 if (frameid
!= INVALIDFID
) {
6903 * To inform the ucode of the last mcast frame posted
6904 * so that it can clear moredata bit
6906 brcms_b_write_shm(wlc
->hw
, M_BCMC_FID
, frameid
);
6909 ret
= brcms_c_txfifo(wlc
, fifo
, skb
);
6911 * The only reason for brcms_c_txfifo to fail is because
6912 * there weren't any DMA descriptors, but we've already
6913 * checked for that. So if it does fail yell loudly.
6920 bool brcms_c_sendpkt_mac80211(struct brcms_c_info
*wlc
, struct sk_buff
*sdu
,
6921 struct ieee80211_hw
*hw
)
6924 struct scb
*scb
= &wlc
->pri_scb
;
6926 fifo
= brcms_ac_to_fifo(skb_get_queue_mapping(sdu
));
6927 brcms_c_d11hdrs_mac80211(wlc
, hw
, sdu
, scb
, 0, 1, fifo
, 0);
6928 if (!brcms_c_tx(wlc
, sdu
))
6931 /* packet discarded */
6932 dev_kfree_skb_any(sdu
);
6937 brcms_c_txfifo(struct brcms_c_info
*wlc
, uint fifo
, struct sk_buff
*p
)
6939 struct dma_pub
*dma
= wlc
->hw
->di
[fifo
];
6943 ret
= dma_txfast(wlc
, dma
, p
);
6945 wiphy_err(wlc
->wiphy
, "txfifo: fatal, toss frames !!!\n");
6948 * Stop queue if DMA ring is full. Reserve some free descriptors,
6949 * as we sometimes receive a frame from mac80211 after the queues
6952 queue
= skb_get_queue_mapping(p
);
6953 if (dma
->txavail
<= TX_HEADROOM
&& fifo
< TX_BCMC_FIFO
&&
6954 !ieee80211_queue_stopped(wlc
->pub
->ieee_hw
, queue
))
6955 ieee80211_stop_queue(wlc
->pub
->ieee_hw
, queue
);
6961 brcms_c_rspec_to_rts_rspec(struct brcms_c_info
*wlc
, u32 rspec
,
6962 bool use_rspec
, u16 mimo_ctlchbw
)
6967 /* use frame rate as rts rate */
6969 else if (wlc
->band
->gmode
&& wlc
->protection
->_g
&& !is_cck_rate(rspec
))
6970 /* Use 11Mbps as the g protection RTS target rate and fallback.
6971 * Use the brcms_basic_rate() lookup to find the best basic rate
6972 * under the target in case 11 Mbps is not Basic.
6973 * 6 and 9 Mbps are not usually selected by rate selection, but
6974 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6977 rts_rspec
= brcms_basic_rate(wlc
, BRCM_RATE_11M
);
6979 /* calculate RTS rate and fallback rate based on the frame rate
6980 * RTS must be sent at a basic rate since it is a
6981 * control frame, sec 9.6 of 802.11 spec
6983 rts_rspec
= brcms_basic_rate(wlc
, rspec
);
6985 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
6986 /* set rts txbw to correct side band */
6987 rts_rspec
&= ~RSPEC_BW_MASK
;
6990 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6991 * 20MHz channel (DUP), otherwise send RTS on control channel
6993 if (rspec_is40mhz(rspec
) && !is_cck_rate(rts_rspec
))
6994 rts_rspec
|= (PHY_TXC1_BW_40MHZ_DUP
<< RSPEC_BW_SHIFT
);
6996 rts_rspec
|= (mimo_ctlchbw
<< RSPEC_BW_SHIFT
);
6998 /* pick siso/cdd as default for ofdm */
6999 if (is_ofdm_rate(rts_rspec
)) {
7000 rts_rspec
&= ~RSPEC_STF_MASK
;
7001 rts_rspec
|= (wlc
->stf
->ss_opmode
<< RSPEC_STF_SHIFT
);
7007 /* Update beacon listen interval in shared memory */
7008 static void brcms_c_bcn_li_upd(struct brcms_c_info
*wlc
)
7010 /* wake up every DTIM is the default */
7011 if (wlc
->bcn_li_dtim
== 1)
7012 brcms_b_write_shm(wlc
->hw
, M_BCN_LI
, 0);
7014 brcms_b_write_shm(wlc
->hw
, M_BCN_LI
,
7015 (wlc
->bcn_li_dtim
<< 8) | wlc
->bcn_li_bcn
);
7019 brcms_b_read_tsf(struct brcms_hardware
*wlc_hw
, u32
*tsf_l_ptr
,
7022 struct bcma_device
*core
= wlc_hw
->d11core
;
7024 /* read the tsf timer low, then high to get an atomic read */
7025 *tsf_l_ptr
= bcma_read32(core
, D11REGOFFS(tsf_timerlow
));
7026 *tsf_h_ptr
= bcma_read32(core
, D11REGOFFS(tsf_timerhigh
));
7030 * recover 64bit TSF value from the 16bit TSF value in the rx header
7031 * given the assumption that the TSF passed in header is within 65ms
7032 * of the current tsf.
7035 * 3.......6.......8.......0.......2.......4.......6.......8......0
7036 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7038 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7039 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7040 * receive call sequence after rx interrupt. Only the higher 16 bits
7041 * are used. Finally, the tsf_h is read from the tsf register.
7043 static u64
brcms_c_recover_tsf64(struct brcms_c_info
*wlc
,
7044 struct d11rxhdr
*rxh
)
7047 u16 rx_tsf_0_15
, rx_tsf_16_31
;
7049 brcms_b_read_tsf(wlc
->hw
, &tsf_l
, &tsf_h
);
7051 rx_tsf_16_31
= (u16
)(tsf_l
>> 16);
7052 rx_tsf_0_15
= rxh
->RxTSFTime
;
7055 * a greater tsf time indicates the low 16 bits of
7056 * tsf_l wrapped, so decrement the high 16 bits.
7058 if ((u16
)tsf_l
< rx_tsf_0_15
) {
7060 if (rx_tsf_16_31
== 0xffff)
7064 return ((u64
)tsf_h
<< 32) | (((u32
)rx_tsf_16_31
<< 16) + rx_tsf_0_15
);
7068 prep_mac80211_status(struct brcms_c_info
*wlc
, struct d11rxhdr
*rxh
,
7070 struct ieee80211_rx_status
*rx_status
)
7075 unsigned char *plcp
;
7077 /* fill in TSF and flag its presence */
7078 rx_status
->mactime
= brcms_c_recover_tsf64(wlc
, rxh
);
7079 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7081 channel
= BRCMS_CHAN_CHANNEL(rxh
->RxChan
);
7084 channel
> 14 ? IEEE80211_BAND_5GHZ
: IEEE80211_BAND_2GHZ
;
7086 ieee80211_channel_to_frequency(channel
, rx_status
->band
);
7088 rx_status
->signal
= wlc_phy_rssi_compute(wlc
->hw
->band
->pi
, rxh
);
7092 rx_status
->antenna
=
7093 (rxh
->PhyRxStatus_0
& PRXS0_RXANT_UPSUBBAND
) ? 1 : 0;
7097 rspec
= brcms_c_compute_rspec(rxh
, plcp
);
7098 if (is_mcs_rate(rspec
)) {
7099 rx_status
->rate_idx
= rspec
& RSPEC_RATE_MASK
;
7100 rx_status
->flag
|= RX_FLAG_HT
;
7101 if (rspec_is40mhz(rspec
))
7102 rx_status
->flag
|= RX_FLAG_40MHZ
;
7104 switch (rspec2rate(rspec
)) {
7106 rx_status
->rate_idx
= 0;
7109 rx_status
->rate_idx
= 1;
7112 rx_status
->rate_idx
= 2;
7115 rx_status
->rate_idx
= 3;
7118 rx_status
->rate_idx
= 4;
7121 rx_status
->rate_idx
= 5;
7124 rx_status
->rate_idx
= 6;
7127 rx_status
->rate_idx
= 7;
7130 rx_status
->rate_idx
= 8;
7133 rx_status
->rate_idx
= 9;
7136 rx_status
->rate_idx
= 10;
7139 rx_status
->rate_idx
= 11;
7142 brcms_err(wlc
->hw
->d11core
,
7143 "%s: Unknown rate\n", __func__
);
7147 * For 5GHz, we should decrease the index as it is
7148 * a subset of the 2.4G rates. See bitrates field
7149 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7151 if (rx_status
->band
== IEEE80211_BAND_5GHZ
)
7152 rx_status
->rate_idx
-= BRCMS_LEGACY_5G_RATE_OFFSET
;
7154 /* Determine short preamble and rate_idx */
7156 if (is_cck_rate(rspec
)) {
7157 if (rxh
->PhyRxStatus_0
& PRXS0_SHORTH
)
7158 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
7159 } else if (is_ofdm_rate(rspec
)) {
7160 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
7162 brcms_err(wlc
->hw
->d11core
, "%s: Unknown modulation\n",
7167 if (plcp3_issgi(plcp
[3]))
7168 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
7170 if (rxh
->RxStatus1
& RXS_DECERR
) {
7171 rx_status
->flag
|= RX_FLAG_FAILED_PLCP_CRC
;
7172 brcms_err(wlc
->hw
->d11core
, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7175 if (rxh
->RxStatus1
& RXS_FCSERR
) {
7176 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7177 brcms_err(wlc
->hw
->d11core
, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7183 brcms_c_recvctl(struct brcms_c_info
*wlc
, struct d11rxhdr
*rxh
,
7187 struct ieee80211_rx_status rx_status
;
7188 struct ieee80211_hdr
*hdr
;
7190 memset(&rx_status
, 0, sizeof(rx_status
));
7191 prep_mac80211_status(wlc
, rxh
, p
, &rx_status
);
7193 /* mac header+body length, exclude CRC and plcp header */
7194 len_mpdu
= p
->len
- D11_PHY_HDR_LEN
- FCS_LEN
;
7195 skb_pull(p
, D11_PHY_HDR_LEN
);
7196 __skb_trim(p
, len_mpdu
);
7198 /* unmute transmit */
7199 if (wlc
->hw
->suspended_fifos
) {
7200 hdr
= (struct ieee80211_hdr
*)p
->data
;
7201 if (ieee80211_is_beacon(hdr
->frame_control
))
7202 brcms_b_mute(wlc
->hw
, false);
7205 memcpy(IEEE80211_SKB_RXCB(p
), &rx_status
, sizeof(rx_status
));
7206 ieee80211_rx_irqsafe(wlc
->pub
->ieee_hw
, p
);
7209 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7210 * number of bytes goes in the length field
7212 * Formula given by HT PHY Spec v 1.13
7213 * len = 3(nsyms + nstream + 3) - 3
7216 brcms_c_calc_lsig_len(struct brcms_c_info
*wlc
, u32 ratespec
,
7219 uint nsyms
, len
= 0, kNdps
;
7221 if (is_mcs_rate(ratespec
)) {
7222 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
7223 int tot_streams
= (mcs_2_txstreams(mcs
) + 1) +
7224 rspec_stc(ratespec
);
7227 * the payload duration calculation matches that
7230 /* 1000Ndbps = kbps * 4 */
7231 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
7232 rspec_issgi(ratespec
)) * 4;
7234 if (rspec_stc(ratespec
) == 0)
7236 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
7237 APHY_TAIL_NBITS
) * 1000, kNdps
);
7239 /* STBC needs to have even number of symbols */
7242 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
7243 APHY_TAIL_NBITS
) * 1000, 2 * kNdps
);
7245 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7246 nsyms
+= (tot_streams
+ 3);
7248 * 3 bytes/symbol @ legacy 6Mbps rate
7249 * (-3) excluding service bits and tail bits
7251 len
= (3 * nsyms
) - 3;
7258 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info
*wlc
, uint frame_len
)
7260 const struct brcms_c_rateset
*rs_dflt
;
7261 struct brcms_c_rateset rs
;
7264 u8 plcp
[D11_PHY_HDR_LEN
];
7268 sifs
= get_sifs(wlc
->band
);
7270 rs_dflt
= brcms_c_rateset_get_hwrs(wlc
);
7272 brcms_c_rateset_copy(rs_dflt
, &rs
);
7273 brcms_c_rateset_mcs_upd(&rs
, wlc
->stf
->txstreams
);
7276 * walk the phy rate table and update MAC core SHM
7277 * basic rate table entries
7279 for (i
= 0; i
< rs
.count
; i
++) {
7280 rate
= rs
.rates
[i
] & BRCMS_RATE_MASK
;
7282 entry_ptr
= brcms_b_rate_shm_offset(wlc
->hw
, rate
);
7284 /* Calculate the Probe Response PLCP for the given rate */
7285 brcms_c_compute_plcp(wlc
, rate
, frame_len
, plcp
);
7288 * Calculate the duration of the Probe Response
7289 * frame plus SIFS for the MAC
7291 dur
= (u16
) brcms_c_calc_frame_time(wlc
, rate
,
7292 BRCMS_LONG_PREAMBLE
, frame_len
);
7295 /* Update the SHM Rate Table entry Probe Response values */
7296 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_PLCP_POS
,
7297 (u16
) (plcp
[0] + (plcp
[1] << 8)));
7298 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_PLCP_POS
+ 2,
7299 (u16
) (plcp
[2] + (plcp
[3] << 8)));
7300 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_DUR_POS
, dur
);
7304 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7306 * PLCP header is 6 bytes.
7307 * 802.11 A3 header is 24 bytes.
7308 * Max beacon frame body template length is 112 bytes.
7309 * Max probe resp frame body template length is 110 bytes.
7311 * *len on input contains the max length of the packet available.
7313 * The *len value is set to the number of bytes in buf used, and starts
7314 * with the PLCP and included up to, but not including, the 4 byte FCS.
7317 brcms_c_bcn_prb_template(struct brcms_c_info
*wlc
, u16 type
,
7319 struct brcms_bss_cfg
*cfg
, u16
*buf
, int *len
)
7321 static const u8 ether_bcast
[ETH_ALEN
] = {255, 255, 255, 255, 255, 255};
7322 struct cck_phy_hdr
*plcp
;
7323 struct ieee80211_mgmt
*h
;
7324 int hdr_len
, body_len
;
7326 hdr_len
= D11_PHY_HDR_LEN
+ DOT11_MAC_HDR_LEN
;
7328 /* calc buffer size provided for frame body */
7329 body_len
= *len
- hdr_len
;
7330 /* return actual size */
7331 *len
= hdr_len
+ body_len
;
7333 /* format PHY and MAC headers */
7334 memset((char *)buf
, 0, hdr_len
);
7336 plcp
= (struct cck_phy_hdr
*) buf
;
7339 * PLCP for Probe Response frames are filled in from
7342 if (type
== IEEE80211_STYPE_BEACON
)
7344 brcms_c_compute_plcp(wlc
, bcn_rspec
,
7345 (DOT11_MAC_HDR_LEN
+ body_len
+ FCS_LEN
),
7348 /* "Regular" and 16 MBSS but not for 4 MBSS */
7349 /* Update the phytxctl for the beacon based on the rspec */
7350 brcms_c_beacon_phytxctl_txant_upd(wlc
, bcn_rspec
);
7352 h
= (struct ieee80211_mgmt
*)&plcp
[1];
7354 /* fill in 802.11 header */
7355 h
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
| type
);
7357 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7358 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7359 if (type
== IEEE80211_STYPE_BEACON
)
7360 memcpy(&h
->da
, ðer_bcast
, ETH_ALEN
);
7361 memcpy(&h
->sa
, &cfg
->cur_etheraddr
, ETH_ALEN
);
7362 memcpy(&h
->bssid
, &cfg
->BSSID
, ETH_ALEN
);
7364 /* SEQ filled in by MAC */
7367 int brcms_c_get_header_len(void)
7373 * Update all beacons for the system.
7375 void brcms_c_update_beacon(struct brcms_c_info
*wlc
)
7377 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
7379 if (bsscfg
->up
&& !bsscfg
->BSS
)
7380 /* Clear the soft intmask */
7381 wlc
->defmacintmask
&= ~MI_BCNTPL
;
7384 /* Write ssid into shared memory */
7386 brcms_c_shm_ssid_upd(struct brcms_c_info
*wlc
, struct brcms_bss_cfg
*cfg
)
7388 u8
*ssidptr
= cfg
->SSID
;
7390 u8 ssidbuf
[IEEE80211_MAX_SSID_LEN
];
7392 /* padding the ssid with zero and copy it into shm */
7393 memset(ssidbuf
, 0, IEEE80211_MAX_SSID_LEN
);
7394 memcpy(ssidbuf
, ssidptr
, cfg
->SSID_len
);
7396 brcms_c_copyto_shm(wlc
, base
, ssidbuf
, IEEE80211_MAX_SSID_LEN
);
7397 brcms_b_write_shm(wlc
->hw
, M_SSIDLEN
, (u16
) cfg
->SSID_len
);
7401 brcms_c_bss_update_probe_resp(struct brcms_c_info
*wlc
,
7402 struct brcms_bss_cfg
*cfg
,
7405 u16 prb_resp
[BCN_TMPL_LEN
/ 2];
7406 int len
= BCN_TMPL_LEN
;
7409 * write the probe response to hardware, or save in
7410 * the config structure
7413 /* create the probe response template */
7414 brcms_c_bcn_prb_template(wlc
, IEEE80211_STYPE_PROBE_RESP
, 0,
7415 cfg
, prb_resp
, &len
);
7418 brcms_c_suspend_mac_and_wait(wlc
);
7420 /* write the probe response into the template region */
7421 brcms_b_write_template_ram(wlc
->hw
, T_PRS_TPL_BASE
,
7422 (len
+ 3) & ~3, prb_resp
);
7424 /* write the length of the probe response frame (+PLCP/-FCS) */
7425 brcms_b_write_shm(wlc
->hw
, M_PRB_RESP_FRM_LEN
, (u16
) len
);
7427 /* write the SSID and SSID length */
7428 brcms_c_shm_ssid_upd(wlc
, cfg
);
7431 * Write PLCP headers and durations for probe response frames
7432 * at all rates. Use the actual frame length covered by the
7433 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7434 * by subtracting the PLCP len and adding the FCS.
7436 len
+= (-D11_PHY_HDR_LEN
+ FCS_LEN
);
7437 brcms_c_mod_prb_rsp_rate_table(wlc
, (u16
) len
);
7440 brcms_c_enable_mac(wlc
);
7443 void brcms_c_update_probe_resp(struct brcms_c_info
*wlc
, bool suspend
)
7445 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
7447 /* update AP or IBSS probe responses */
7448 if (bsscfg
->up
&& !bsscfg
->BSS
)
7449 brcms_c_bss_update_probe_resp(wlc
, bsscfg
, suspend
);
7452 int brcms_b_xmtfifo_sz_get(struct brcms_hardware
*wlc_hw
, uint fifo
,
7458 *blocks
= wlc_hw
->xmtfifo_sz
[fifo
];
7464 brcms_c_set_addrmatch(struct brcms_c_info
*wlc
, int match_reg_offset
,
7467 brcms_b_set_addrmatch(wlc
->hw
, match_reg_offset
, addr
);
7468 if (match_reg_offset
== RCM_BSSID_OFFSET
)
7469 memcpy(wlc
->bsscfg
->BSSID
, addr
, ETH_ALEN
);
7473 * Flag 'scan in progress' to withhold dynamic phy calibration
7475 void brcms_c_scan_start(struct brcms_c_info
*wlc
)
7477 wlc_phy_hold_upd(wlc
->band
->pi
, PHY_HOLD_FOR_SCAN
, true);
7480 void brcms_c_scan_stop(struct brcms_c_info
*wlc
)
7482 wlc_phy_hold_upd(wlc
->band
->pi
, PHY_HOLD_FOR_SCAN
, false);
7485 void brcms_c_associate_upd(struct brcms_c_info
*wlc
, bool state
)
7487 wlc
->pub
->associated
= state
;
7488 wlc
->bsscfg
->associated
= state
;
7492 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7493 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7494 * when later on hardware releases them, they can be handled appropriately.
7496 void brcms_c_inval_dma_pkts(struct brcms_hardware
*hw
,
7497 struct ieee80211_sta
*sta
,
7498 void (*dma_callback_fn
))
7500 struct dma_pub
*dmah
;
7502 for (i
= 0; i
< NFIFO
; i
++) {
7505 dma_walk_packets(dmah
, dma_callback_fn
, sta
);
7509 int brcms_c_get_curband(struct brcms_c_info
*wlc
)
7511 return wlc
->band
->bandunit
;
7514 bool brcms_c_tx_flush_completed(struct brcms_c_info
*wlc
)
7518 /* Kick DMA to send any pending AMPDU */
7519 for (i
= 0; i
< ARRAY_SIZE(wlc
->hw
->di
); i
++)
7521 dma_kick_tx(wlc
->hw
->di
[i
]);
7523 return !brcms_txpktpendtot(wlc
);
7526 void brcms_c_set_beacon_listen_interval(struct brcms_c_info
*wlc
, u8 interval
)
7528 wlc
->bcn_li_bcn
= interval
;
7530 brcms_c_bcn_li_upd(wlc
);
7533 int brcms_c_set_tx_power(struct brcms_c_info
*wlc
, int txpwr
)
7537 /* Remove override bit and clip to max qdbm value */
7538 qdbm
= min_t(uint
, txpwr
* BRCMS_TXPWR_DB_FACTOR
, 0xff);
7539 return wlc_phy_txpower_set(wlc
->band
->pi
, qdbm
, false);
7542 int brcms_c_get_tx_power(struct brcms_c_info
*wlc
)
7547 wlc_phy_txpower_get(wlc
->band
->pi
, &qdbm
, &override
);
7549 /* Return qdbm units */
7550 return (int)(qdbm
/ BRCMS_TXPWR_DB_FACTOR
);
7553 /* Process received frames */
7555 * Return true if more frames need to be processed. false otherwise.
7556 * Param 'bound' indicates max. # frames to process before break out.
7558 static void brcms_c_recv(struct brcms_c_info
*wlc
, struct sk_buff
*p
)
7560 struct d11rxhdr
*rxh
;
7561 struct ieee80211_hdr
*h
;
7565 /* frame starts with rxhdr */
7566 rxh
= (struct d11rxhdr
*) (p
->data
);
7568 /* strip off rxhdr */
7569 skb_pull(p
, BRCMS_HWRXOFF
);
7571 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7572 if (rxh
->RxStatus1
& RXS_PBPRES
) {
7574 brcms_err(wlc
->hw
->d11core
,
7575 "wl%d: recv: rcvd runt of len %d\n",
7576 wlc
->pub
->unit
, p
->len
);
7582 h
= (struct ieee80211_hdr
*)(p
->data
+ D11_PHY_HDR_LEN
);
7585 if (rxh
->RxStatus1
& RXS_FCSERR
) {
7586 if (!(wlc
->filter_flags
& FIF_FCSFAIL
))
7590 /* check received pkt has at least frame control field */
7591 if (len
< D11_PHY_HDR_LEN
+ sizeof(h
->frame_control
))
7594 /* not supporting A-MSDU */
7595 is_amsdu
= rxh
->RxStatus2
& RXS_AMSDU_MASK
;
7599 brcms_c_recvctl(wlc
, rxh
, p
);
7603 brcmu_pkt_buf_free_skb(p
);
7606 /* Process received frames */
7608 * Return true if more frames need to be processed. false otherwise.
7609 * Param 'bound' indicates max. # frames to process before break out.
7612 brcms_b_recv(struct brcms_hardware
*wlc_hw
, uint fifo
, bool bound
)
7615 struct sk_buff
*next
= NULL
;
7616 struct sk_buff_head recv_frames
;
7619 uint bound_limit
= bound
? RXBND
: -1;
7622 skb_queue_head_init(&recv_frames
);
7624 /* gather received frames */
7626 /* !give others some time to run! */
7627 if (n
>= bound_limit
)
7630 morepending
= dma_rx(wlc_hw
->di
[fifo
], &recv_frames
);
7632 } while (morepending
);
7634 /* post more rbufs */
7635 dma_rxfill(wlc_hw
->di
[fifo
]);
7637 /* process each frame */
7638 skb_queue_walk_safe(&recv_frames
, p
, next
) {
7639 struct d11rxhdr_le
*rxh_le
;
7640 struct d11rxhdr
*rxh
;
7642 skb_unlink(p
, &recv_frames
);
7643 rxh_le
= (struct d11rxhdr_le
*)p
->data
;
7644 rxh
= (struct d11rxhdr
*)p
->data
;
7646 /* fixup rx header endianness */
7647 rxh
->RxFrameSize
= le16_to_cpu(rxh_le
->RxFrameSize
);
7648 rxh
->PhyRxStatus_0
= le16_to_cpu(rxh_le
->PhyRxStatus_0
);
7649 rxh
->PhyRxStatus_1
= le16_to_cpu(rxh_le
->PhyRxStatus_1
);
7650 rxh
->PhyRxStatus_2
= le16_to_cpu(rxh_le
->PhyRxStatus_2
);
7651 rxh
->PhyRxStatus_3
= le16_to_cpu(rxh_le
->PhyRxStatus_3
);
7652 rxh
->PhyRxStatus_4
= le16_to_cpu(rxh_le
->PhyRxStatus_4
);
7653 rxh
->PhyRxStatus_5
= le16_to_cpu(rxh_le
->PhyRxStatus_5
);
7654 rxh
->RxStatus1
= le16_to_cpu(rxh_le
->RxStatus1
);
7655 rxh
->RxStatus2
= le16_to_cpu(rxh_le
->RxStatus2
);
7656 rxh
->RxTSFTime
= le16_to_cpu(rxh_le
->RxTSFTime
);
7657 rxh
->RxChan
= le16_to_cpu(rxh_le
->RxChan
);
7659 brcms_c_recv(wlc_hw
->wlc
, p
);
7665 /* second-level interrupt processing
7666 * Return true if another dpc needs to be re-scheduled. false otherwise.
7667 * Param 'bounded' indicates if applicable loops should be bounded.
7669 bool brcms_c_dpc(struct brcms_c_info
*wlc
, bool bounded
)
7672 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
7673 struct bcma_device
*core
= wlc_hw
->d11core
;
7675 if (brcms_deviceremoved(wlc
)) {
7676 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
7678 brcms_down(wlc
->wl
);
7682 /* grab and clear the saved software intstatus bits */
7683 macintstatus
= wlc
->macintstatus
;
7684 wlc
->macintstatus
= 0;
7686 brcms_dbg_int(core
, "wl%d: macintstatus 0x%x\n",
7687 wlc_hw
->unit
, macintstatus
);
7689 WARN_ON(macintstatus
& MI_PRQ
); /* PRQ Interrupt in non-MBSS */
7692 if (macintstatus
& MI_TFS
) {
7694 if (brcms_b_txstatus(wlc
->hw
, bounded
, &fatal
))
7695 wlc
->macintstatus
|= MI_TFS
;
7697 brcms_err(core
, "MI_TFS: fatal\n");
7702 if (macintstatus
& (MI_TBTT
| MI_DTIM_TBTT
))
7705 /* ATIM window end */
7706 if (macintstatus
& MI_ATIMWINEND
) {
7707 brcms_dbg_info(core
, "end of ATIM window\n");
7708 bcma_set32(core
, D11REGOFFS(maccommand
), wlc
->qvalid
);
7713 * received data or control frame, MI_DMAINT is
7714 * indication of RX_FIFO interrupt
7716 if (macintstatus
& MI_DMAINT
)
7717 if (brcms_b_recv(wlc_hw
, RX_FIFO
, bounded
))
7718 wlc
->macintstatus
|= MI_DMAINT
;
7720 /* noise sample collected */
7721 if (macintstatus
& MI_BG_NOISE
)
7722 wlc_phy_noise_sample_intr(wlc_hw
->band
->pi
);
7724 if (macintstatus
& MI_GP0
) {
7725 brcms_err(core
, "wl%d: PSM microcode watchdog fired at %d "
7726 "(seconds). Resetting.\n", wlc_hw
->unit
, wlc_hw
->now
);
7728 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7729 __func__
, ai_get_chip_id(wlc_hw
->sih
),
7730 ai_get_chiprev(wlc_hw
->sih
));
7731 brcms_fatal_error(wlc_hw
->wlc
->wl
);
7734 /* gptimer timeout */
7735 if (macintstatus
& MI_TO
)
7736 bcma_write32(core
, D11REGOFFS(gptimer
), 0);
7738 if (macintstatus
& MI_RFDISABLE
) {
7739 brcms_dbg_info(core
, "wl%d: BMAC Detected a change on the"
7740 " RF Disable Input\n", wlc_hw
->unit
);
7741 brcms_rfkill_set_hw_state(wlc
->wl
);
7744 /* it isn't done and needs to be resched if macintstatus is non-zero */
7745 return wlc
->macintstatus
!= 0;
7748 brcms_fatal_error(wlc_hw
->wlc
->wl
);
7749 return wlc
->macintstatus
!= 0;
7752 void brcms_c_init(struct brcms_c_info
*wlc
, bool mute_tx
)
7754 struct bcma_device
*core
= wlc
->hw
->d11core
;
7755 struct ieee80211_channel
*ch
= wlc
->pub
->ieee_hw
->conf
.channel
;
7758 brcms_dbg_info(core
, "wl%d\n", wlc
->pub
->unit
);
7760 chanspec
= ch20mhz_chspec(ch
->hw_value
);
7762 brcms_b_init(wlc
->hw
, chanspec
);
7764 /* update beacon listen interval */
7765 brcms_c_bcn_li_upd(wlc
);
7767 /* write ethernet address to core */
7768 brcms_c_set_mac(wlc
->bsscfg
);
7769 brcms_c_set_bssid(wlc
->bsscfg
);
7771 /* Update tsf_cfprep if associated and up */
7772 if (wlc
->pub
->associated
&& wlc
->bsscfg
->up
) {
7775 /* get beacon period and convert to uS */
7776 bi
= wlc
->bsscfg
->current_bss
->beacon_period
<< 10;
7778 * update since init path would reset
7781 bcma_write32(core
, D11REGOFFS(tsf_cfprep
),
7782 bi
<< CFPREP_CBI_SHIFT
);
7784 /* Update maccontrol PM related bits */
7785 brcms_c_set_ps_ctrl(wlc
);
7788 brcms_c_bandinit_ordered(wlc
, chanspec
);
7790 /* init probe response timeout */
7791 brcms_b_write_shm(wlc
->hw
, M_PRS_MAXTIME
, wlc
->prb_resp_timeout
);
7793 /* init max burst txop (framebursting) */
7794 brcms_b_write_shm(wlc
->hw
, M_MBURST_TXOP
,
7796 _rifs
? (EDCF_AC_VO_TXOP_AP
<< 5) : MAXFRAMEBURST_TXOP
));
7798 /* initialize maximum allowed duty cycle */
7799 brcms_c_duty_cycle_set(wlc
, wlc
->tx_duty_cycle_ofdm
, true, true);
7800 brcms_c_duty_cycle_set(wlc
, wlc
->tx_duty_cycle_cck
, false, true);
7803 * Update some shared memory locations related to
7804 * max AMPDU size allowed to received
7806 brcms_c_ampdu_shm_upd(wlc
->ampdu
);
7808 /* band-specific inits */
7809 brcms_c_bsinit(wlc
);
7811 /* Enable EDCF mode (while the MAC is suspended) */
7812 bcma_set16(core
, D11REGOFFS(ifs_ctl
), IFS_USEEDCF
);
7813 brcms_c_edcf_setparams(wlc
, false);
7815 /* read the ucode version if we have not yet done so */
7816 if (wlc
->ucode_rev
== 0) {
7818 brcms_b_read_shm(wlc
->hw
, M_BOM_REV_MAJOR
) << NBITS(u16
);
7819 wlc
->ucode_rev
|= brcms_b_read_shm(wlc
->hw
, M_BOM_REV_MINOR
);
7822 /* ..now really unleash hell (allow the MAC out of suspend) */
7823 brcms_c_enable_mac(wlc
);
7825 /* suspend the tx fifos and mute the phy for preism cac time */
7827 brcms_b_mute(wlc
->hw
, true);
7829 /* enable the RF Disable Delay timer */
7830 bcma_write32(core
, D11REGOFFS(rfdisabledly
), RFDISABLE_DEFAULT
);
7833 * Initialize WME parameters; if they haven't been set by some other
7834 * mechanism (IOVar, etc) then read them from the hardware.
7836 if (GFIELD(wlc
->wme_retries
[0], EDCF_SHORT
) == 0) {
7837 /* Uninitialized; read from HW */
7840 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++)
7841 wlc
->wme_retries
[ac
] =
7842 brcms_b_read_shm(wlc
->hw
, M_AC_TXLMT_ADDR(ac
));
7847 * The common driver entry routine. Error codes should be unique
7849 struct brcms_c_info
*
7850 brcms_c_attach(struct brcms_info
*wl
, struct bcma_device
*core
, uint unit
,
7851 bool piomode
, uint
*perr
)
7853 struct brcms_c_info
*wlc
;
7856 struct brcms_pub
*pub
;
7858 /* allocate struct brcms_c_info state and its substructures */
7859 wlc
= brcms_c_attach_malloc(unit
, &err
, 0);
7862 wlc
->wiphy
= wl
->wiphy
;
7869 wlc
->band
= wlc
->bandstate
[0];
7870 wlc
->core
= wlc
->corestate
;
7873 pub
->_piomode
= piomode
;
7874 wlc
->bandinit_pending
= false;
7876 /* populate struct brcms_c_info with default values */
7877 brcms_c_info_init(wlc
, unit
);
7879 /* update sta/ap related parameters */
7880 brcms_c_ap_upd(wlc
);
7883 * low level attach steps(all hw accesses go
7884 * inside, no more in rest of the attach)
7886 err
= brcms_b_attach(wlc
, core
, unit
, piomode
);
7890 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_PAM_OVR
, OFF
);
7892 pub
->phy_11ncapable
= BRCMS_PHY_11N_CAP(wlc
->band
);
7894 /* disable allowed duty cycle */
7895 wlc
->tx_duty_cycle_ofdm
= 0;
7896 wlc
->tx_duty_cycle_cck
= 0;
7898 brcms_c_stf_phy_chain_calc(wlc
);
7900 /* txchain 1: txant 0, txchain 2: txant 1 */
7901 if (BRCMS_ISNPHY(wlc
->band
) && (wlc
->stf
->txstreams
== 1))
7902 wlc
->stf
->txant
= wlc
->stf
->hw_txchain
- 1;
7904 /* push to BMAC driver */
7905 wlc_phy_stf_chain_init(wlc
->band
->pi
, wlc
->stf
->hw_txchain
,
7906 wlc
->stf
->hw_rxchain
);
7908 /* pull up some info resulting from the low attach */
7909 for (i
= 0; i
< NFIFO
; i
++)
7910 wlc
->core
->txavail
[i
] = wlc
->hw
->txavail
[i
];
7912 memcpy(&wlc
->perm_etheraddr
, &wlc
->hw
->etheraddr
, ETH_ALEN
);
7913 memcpy(&pub
->cur_etheraddr
, &wlc
->hw
->etheraddr
, ETH_ALEN
);
7915 for (j
= 0; j
< wlc
->pub
->_nbands
; j
++) {
7916 wlc
->band
= wlc
->bandstate
[j
];
7918 if (!brcms_c_attach_stf_ant_init(wlc
)) {
7923 /* default contention windows size limits */
7924 wlc
->band
->CWmin
= APHY_CWMIN
;
7925 wlc
->band
->CWmax
= PHY_CWMAX
;
7927 /* init gmode value */
7928 if (wlc
->band
->bandtype
== BRCM_BAND_2G
) {
7929 wlc
->band
->gmode
= GMODE_AUTO
;
7930 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_USER
,
7934 /* init _n_enab supported mode */
7935 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
7936 pub
->_n_enab
= SUPPORT_11N
;
7937 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_USER
,
7939 SUPPORT_11N
) ? WL_11N_2x2
:
7943 /* init per-band default rateset, depend on band->gmode */
7944 brcms_default_rateset(wlc
, &wlc
->band
->defrateset
);
7946 /* fill in hw_rateset */
7947 brcms_c_rateset_filter(&wlc
->band
->defrateset
,
7948 &wlc
->band
->hw_rateset
, false,
7949 BRCMS_RATES_CCK_OFDM
, BRCMS_RATE_MASK
,
7950 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
));
7954 * update antenna config due to
7955 * wlc->stf->txant/txchain/ant_rx_ovr change
7957 brcms_c_stf_phy_txant_upd(wlc
);
7959 /* attach each modules */
7960 err
= brcms_c_attach_module(wlc
);
7964 if (!brcms_c_timers_init(wlc
, unit
)) {
7965 wiphy_err(wl
->wiphy
, "wl%d: %s: init_timer failed\n", unit
,
7971 /* depend on rateset, gmode */
7972 wlc
->cmi
= brcms_c_channel_mgr_attach(wlc
);
7974 wiphy_err(wl
->wiphy
, "wl%d: %s: channel_mgr_attach failed"
7975 "\n", unit
, __func__
);
7980 /* init default when all parameters are ready, i.e. ->rateset */
7981 brcms_c_bss_default_init(wlc
);
7984 * Complete the wlc default state initializations..
7987 wlc
->bsscfg
->wlc
= wlc
;
7989 wlc
->mimoft
= FT_HT
;
7990 wlc
->mimo_40txbw
= AUTO
;
7991 wlc
->ofdm_40txbw
= AUTO
;
7992 wlc
->cck_40txbw
= AUTO
;
7993 brcms_c_update_mimo_band_bwcap(wlc
, BRCMS_N_BW_20IN2G_40IN5G
);
7995 /* Set default values of SGI */
7996 if (BRCMS_SGI_CAP_PHY(wlc
)) {
7997 brcms_c_ht_update_sgi_rx(wlc
, (BRCMS_N_SGI_20
|
7999 } else if (BRCMS_ISSSLPNPHY(wlc
->band
)) {
8000 brcms_c_ht_update_sgi_rx(wlc
, (BRCMS_N_SGI_20
|
8003 brcms_c_ht_update_sgi_rx(wlc
, 0);
8006 brcms_b_antsel_set(wlc
->hw
, wlc
->asi
->antsel_avail
);
8014 wiphy_err(wl
->wiphy
, "wl%d: %s: failed with err %d\n",
8015 unit
, __func__
, err
);
8017 brcms_c_detach(wlc
);