drivers/net/wireless/brcm80211/include/chipcommon.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _SBCHIPC_H
  18 #define _SBCHIPC_H
  19
  20 #include "defs.h"               /* for PAD macro */
  21
  22 struct chipcregs {
  23         u32 chipid;             /* 0x0 */
  24         u32 capabilities;
  25         u32 corecontrol;        /* corerev >= 1 */
  26         u32 bist;
  27
  28         /* OTP */
  29         u32 otpstatus;  /* 0x10, corerev >= 10 */
  30         u32 otpcontrol;
  31         u32 otpprog;
  32         u32 otplayout;  /* corerev >= 23 */
  33
  34         /* Interrupt control */
  35         u32 intstatus;  /* 0x20 */
  36         u32 intmask;
  37
  38         /* Chip specific regs */
  39         u32 chipcontrol;        /* 0x28, rev >= 11 */
  40         u32 chipstatus; /* 0x2c, rev >= 11 */
  41
  42         /* Jtag Master */
  43         u32 jtagcmd;            /* 0x30, rev >= 10 */
  44         u32 jtagir;
  45         u32 jtagdr;
  46         u32 jtagctrl;
  47
  48         /* serial flash interface registers */
  49         u32 flashcontrol;       /* 0x40 */
  50         u32 flashaddress;
  51         u32 flashdata;
  52         u32 PAD[1];
  53
  54         /* Silicon backplane configuration broadcast control */
  55         u32 broadcastaddress;   /* 0x50 */
  56         u32 broadcastdata;
  57
  58         /* gpio - cleared only by power-on-reset */
  59         u32 gpiopullup; /* 0x58, corerev >= 20 */
  60         u32 gpiopulldown;       /* 0x5c, corerev >= 20 */
  61         u32 gpioin;             /* 0x60 */
  62         u32 gpioout;            /* 0x64 */
  63         u32 gpioouten;  /* 0x68 */
  64         u32 gpiocontrol;        /* 0x6C */
  65         u32 gpiointpolarity;    /* 0x70 */
  66         u32 gpiointmask;        /* 0x74 */
  67
  68         /* GPIO events corerev >= 11 */
  69         u32 gpioevent;
  70         u32 gpioeventintmask;
  71
  72         /* Watchdog timer */
  73         u32 watchdog;   /* 0x80 */
  74
  75         /* GPIO events corerev >= 11 */
  76         u32 gpioeventintpolarity;
  77
  78         /* GPIO based LED powersave registers corerev >= 16 */
  79         u32 gpiotimerval;       /* 0x88 */
  80         u32 gpiotimeroutmask;
  81
  82         /* clock control */
  83         u32 clockcontrol_n;     /* 0x90 */
  84         u32 clockcontrol_sb;    /* aka m0 */
  85         u32 clockcontrol_pci;   /* aka m1 */
  86         u32 clockcontrol_m2;    /* mii/uart/mipsref */
  87         u32 clockcontrol_m3;    /* cpu */
  88         u32 clkdiv;             /* corerev >= 3 */
  89         u32 gpiodebugsel;       /* corerev >= 28 */
  90         u32 capabilities_ext;   /* 0xac  */
  91
  92         /* pll delay registers (corerev >= 4) */
  93         u32 pll_on_delay;       /* 0xb0 */
  94         u32 fref_sel_delay;
  95         u32 slow_clk_ctl;       /* 5 < corerev < 10 */
  96         u32 PAD;
  97
  98         /* Instaclock registers (corerev >= 10) */
  99         u32 system_clk_ctl;     /* 0xc0 */
 100         u32 clkstatestretch;
 101         u32 PAD[2];
 102
 103         /* Indirect backplane access (corerev >= 22) */
 104         u32 bp_addrlow; /* 0xd0 */
 105         u32 bp_addrhigh;
 106         u32 bp_data;
 107         u32 PAD;
 108         u32 bp_indaccess;
 109         u32 PAD[3];
 110
 111         /* More clock dividers (corerev >= 32) */
 112         u32 clkdiv2;
 113         u32 PAD[2];
 114
 115         /* In AI chips, pointer to erom */
 116         u32 eromptr;            /* 0xfc */
 117
 118         /* ExtBus control registers (corerev >= 3) */
 119         u32 pcmcia_config;      /* 0x100 */
 120         u32 pcmcia_memwait;
 121         u32 pcmcia_attrwait;
 122         u32 pcmcia_iowait;
 123         u32 ide_config;
 124         u32 ide_memwait;
 125         u32 ide_attrwait;
 126         u32 ide_iowait;
 127         u32 prog_config;
 128         u32 prog_waitcount;
 129         u32 flash_config;
 130         u32 flash_waitcount;
 131         u32 SECI_config;        /* 0x130 SECI configuration */
 132         u32 PAD[3];
 133
 134         /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
 135         u32 eci_output; /* 0x140 */
 136         u32 eci_control;
 137         u32 eci_inputlo;
 138         u32 eci_inputmi;
 139         u32 eci_inputhi;
 140         u32 eci_inputintpolaritylo;
 141         u32 eci_inputintpolaritymi;
 142         u32 eci_inputintpolarityhi;
 143         u32 eci_intmasklo;
 144         u32 eci_intmaskmi;
 145         u32 eci_intmaskhi;
 146         u32 eci_eventlo;
 147         u32 eci_eventmi;
 148         u32 eci_eventhi;
 149         u32 eci_eventmasklo;
 150         u32 eci_eventmaskmi;
 151         u32 eci_eventmaskhi;
 152         u32 PAD[3];
 153
 154         /* SROM interface (corerev >= 32) */
 155         u32 sromcontrol;        /* 0x190 */
 156         u32 sromaddress;
 157         u32 sromdata;
 158         u32 PAD[17];
 159
 160         /* Clock control and hardware workarounds (corerev >= 20) */
 161         u32 clk_ctl_st; /* 0x1e0 */
 162         u32 hw_war;
 163         u32 PAD[70];
 164
 165         /* UARTs */
 166         u8 uart0data;   /* 0x300 */
 167         u8 uart0imr;
 168         u8 uart0fcr;
 169         u8 uart0lcr;
 170         u8 uart0mcr;
 171         u8 uart0lsr;
 172         u8 uart0msr;
 173         u8 uart0scratch;
 174         u8 PAD[248];            /* corerev >= 1 */
 175
 176         u8 uart1data;   /* 0x400 */
 177         u8 uart1imr;
 178         u8 uart1fcr;
 179         u8 uart1lcr;
 180         u8 uart1mcr;
 181         u8 uart1lsr;
 182         u8 uart1msr;
 183         u8 uart1scratch;
 184         u32 PAD[126];
 185
 186         /* PMU registers (corerev >= 20) */
 187         u32 pmucontrol; /* 0x600 */
 188         u32 pmucapabilities;
 189         u32 pmustatus;
 190         u32 res_state;
 191         u32 res_pending;
 192         u32 pmutimer;
 193         u32 min_res_mask;
 194         u32 max_res_mask;
 195         u32 res_table_sel;
 196         u32 res_dep_mask;
 197         u32 res_updn_timer;
 198         u32 res_timer;
 199         u32 clkstretch;
 200         u32 pmuwatchdog;
 201         u32 gpiosel;            /* 0x638, rev >= 1 */
 202         u32 gpioenable; /* 0x63c, rev >= 1 */
 203         u32 res_req_timer_sel;
 204         u32 res_req_timer;
 205         u32 res_req_mask;
 206         u32 PAD;
 207         u32 chipcontrol_addr;   /* 0x650 */
 208         u32 chipcontrol_data;   /* 0x654 */
 209         u32 regcontrol_addr;
 210         u32 regcontrol_data;
 211         u32 pllcontrol_addr;
 212         u32 pllcontrol_data;
 213         u32 pmustrapopt;        /* 0x668, corerev >= 28 */
 214         u32 pmu_xtalfreq;       /* 0x66C, pmurev >= 10 */
 215         u32 PAD[100];
 216         u16 sromotp[768];
 217 };
 218
 219 /* chipid */
 220 #define CID_ID_MASK             0x0000ffff      /* Chip Id mask */
 221 #define CID_REV_MASK            0x000f0000      /* Chip Revision mask */
 222 #define CID_REV_SHIFT           16      /* Chip Revision shift */
 223 #define CID_PKG_MASK            0x00f00000      /* Package Option mask */
 224 #define CID_PKG_SHIFT           20      /* Package Option shift */
 225 #define CID_CC_MASK             0x0f000000      /* CoreCount (corerev >= 4) */
 226 #define CID_CC_SHIFT            24
 227 #define CID_TYPE_MASK           0xf0000000      /* Chip Type */
 228 #define CID_TYPE_SHIFT          28
 229
 230 /* capabilities */
 231 #define CC_CAP_UARTS_MASK       0x00000003      /* Number of UARTs */
 232 #define CC_CAP_MIPSEB           0x00000004      /* MIPS is in big-endian mode */
 233 #define CC_CAP_UCLKSEL          0x00000018      /* UARTs clock select */
 234 /* UARTs are driven by internal divided clock */
 235 #define CC_CAP_UINTCLK          0x00000008
 236 #define CC_CAP_UARTGPIO         0x00000020      /* UARTs own GPIOs 15:12 */
 237 #define CC_CAP_EXTBUS_MASK      0x000000c0      /* External bus mask */
 238 #define CC_CAP_EXTBUS_NONE      0x00000000      /* No ExtBus present */
 239 #define CC_CAP_EXTBUS_FULL      0x00000040      /* ExtBus: PCMCIA, IDE & Prog */
 240 #define CC_CAP_EXTBUS_PROG      0x00000080      /* ExtBus: ProgIf only */
 241 #define CC_CAP_FLASH_MASK       0x00000700      /* Type of flash */
 242 #define CC_CAP_PLL_MASK         0x00038000      /* Type of PLL */
 243 #define CC_CAP_PWR_CTL          0x00040000      /* Power control */
 244 #define CC_CAP_OTPSIZE          0x00380000      /* OTP Size (0 = none) */
 245 #define CC_CAP_OTPSIZE_SHIFT    19      /* OTP Size shift */
 246 #define CC_CAP_OTPSIZE_BASE     5       /* OTP Size base */
 247 #define CC_CAP_JTAGP            0x00400000      /* JTAG Master Present */
 248 #define CC_CAP_ROM              0x00800000      /* Internal boot rom active */
 249 #define CC_CAP_BKPLN64          0x08000000      /* 64-bit backplane */
 250 #define CC_CAP_PMU              0x10000000      /* PMU Present, rev >= 20 */
 251 #define CC_CAP_SROM             0x40000000      /* Srom Present, rev >= 32 */
 252 /* Nand flash present, rev >= 35 */
 253 #define CC_CAP_NFLASH           0x80000000
 254
 255 #define CC_CAP2_SECI            0x00000001      /* SECI Present, rev >= 36 */
 256 /* GSIO (spi/i2c) present, rev >= 37 */
 257 #define CC_CAP2_GSIO            0x00000002
 258
 259 /* pmucapabilities */
 260 #define PCAP_REV_MASK   0x000000ff
 261 #define PCAP_RC_MASK    0x00001f00
 262 #define PCAP_RC_SHIFT   8
 263 #define PCAP_TC_MASK    0x0001e000
 264 #define PCAP_TC_SHIFT   13
 265 #define PCAP_PC_MASK    0x001e0000
 266 #define PCAP_PC_SHIFT   17
 267 #define PCAP_VC_MASK    0x01e00000
 268 #define PCAP_VC_SHIFT   21
 269 #define PCAP_CC_MASK    0x1e000000
 270 #define PCAP_CC_SHIFT   25
 271 #define PCAP5_PC_MASK   0x003e0000      /* PMU corerev >= 5 */
 272 #define PCAP5_PC_SHIFT  17
 273 #define PCAP5_VC_MASK   0x07c00000
 274 #define PCAP5_VC_SHIFT  22
 275 #define PCAP5_CC_MASK   0xf8000000
 276 #define PCAP5_CC_SHIFT  27
 277
 278 /*
 279 * Maximum delay for the PMU state transition in us.
 280 * This is an upper bound intended for spinwaits etc.
 281 */
 282 #define PMU_MAX_TRANSITION_DLY  15000
 283
 284 #endif                          /* _SBCHIPC_H */