1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *****************************************************************************/
31 #include <linux/etherdevice.h>
32 #include <linux/ieee80211.h>
33 #include <linux/slab.h>
34 #include <linux/sched.h>
35 #include <linux/pm_runtime.h>
36 #include <net/ip6_checksum.h>
39 #include "iwl-debug.h"
44 #include "iwl-op-mode.h"
46 /* FIXME: need to abstract out TX command (once we know what it looks like) */
47 #include "dvm/commands.h"
49 #define IWL_TX_CRC_SIZE 4
50 #define IWL_TX_DELIMITER_SIZE 4
52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
57 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
58 * of buffer descriptors, each of which points to one or more data buffers for
59 * the device to read from or fill. Driver and device exchange status of each
60 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
61 * entries in each circular buffer, to protect against confusing empty and full
64 * The device reads or writes the data in the queues via the device's several
65 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
67 * For Tx queue, there are low mark and high mark limits. If, after queuing
68 * the packet for Tx, free space become < low mark, Tx queue stopped. When
69 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
72 ***************************************************/
74 static int iwl_queue_space(const struct iwl_queue
*q
)
80 * To avoid ambiguity between empty and completely full queues, there
81 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
82 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
83 * to reserve any queue entries for this purpose.
85 if (q
->n_window
< TFD_QUEUE_SIZE_MAX
)
88 max
= TFD_QUEUE_SIZE_MAX
- 1;
91 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
92 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
94 used
= (q
->write_ptr
- q
->read_ptr
) & (TFD_QUEUE_SIZE_MAX
- 1);
96 if (WARN_ON(used
> max
))
103 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
105 static int iwl_queue_init(struct iwl_queue
*q
, int slots_num
, u32 id
)
107 q
->n_window
= slots_num
;
110 /* slots_num must be power-of-two size, otherwise
111 * get_cmd_index is broken. */
112 if (WARN_ON(!is_power_of_2(slots_num
)))
115 q
->low_mark
= q
->n_window
/ 4;
119 q
->high_mark
= q
->n_window
/ 8;
120 if (q
->high_mark
< 2)
129 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
130 struct iwl_dma_ptr
*ptr
, size_t size
)
132 if (WARN_ON(ptr
->addr
))
135 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
136 &ptr
->dma
, GFP_KERNEL
);
143 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
144 struct iwl_dma_ptr
*ptr
)
146 if (unlikely(!ptr
->addr
))
149 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
150 memset(ptr
, 0, sizeof(*ptr
));
153 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
155 struct iwl_txq
*txq
= (void *)data
;
156 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
157 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
159 spin_lock(&txq
->lock
);
160 /* check if triggered erroneously */
161 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
162 spin_unlock(&txq
->lock
);
165 spin_unlock(&txq
->lock
);
167 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
168 jiffies_to_msecs(txq
->wd_timeout
));
170 iwl_trans_pcie_log_scd_error(trans
, txq
);
172 iwl_force_nmi(trans
);
176 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
178 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
179 struct iwl_txq
*txq
, u16 byte_cnt
)
181 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
182 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
183 int write_ptr
= txq
->q
.write_ptr
;
184 int txq_id
= txq
->q
.id
;
187 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
189 struct iwl_tx_cmd
*tx_cmd
=
190 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
192 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
194 sta_id
= tx_cmd
->sta_id
;
195 sec_ctl
= tx_cmd
->sec_ctl
;
197 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
199 len
+= IEEE80211_CCMP_MIC_LEN
;
201 case TX_CMD_SEC_TKIP
:
202 len
+= IEEE80211_TKIP_ICV_LEN
;
205 len
+= IEEE80211_WEP_IV_LEN
+ IEEE80211_WEP_ICV_LEN
;
209 if (trans_pcie
->bc_table_dword
)
210 len
= DIV_ROUND_UP(len
, 4);
212 if (WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
))
215 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
217 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
219 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
221 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
224 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
227 struct iwl_trans_pcie
*trans_pcie
=
228 IWL_TRANS_GET_PCIE_TRANS(trans
);
229 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
230 int txq_id
= txq
->q
.id
;
231 int read_ptr
= txq
->q
.read_ptr
;
234 struct iwl_tx_cmd
*tx_cmd
=
235 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
237 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
239 if (txq_id
!= trans_pcie
->cmd_queue
)
240 sta_id
= tx_cmd
->sta_id
;
242 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
243 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
245 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
247 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
251 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
253 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
,
256 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
258 int txq_id
= txq
->q
.id
;
260 lockdep_assert_held(&txq
->lock
);
263 * explicitly wake up the NIC if:
264 * 1. shadow registers aren't enabled
265 * 2. NIC is woken up for CMD regardless of shadow outside this function
266 * 3. there is a chance that the NIC is asleep
268 if (!trans
->cfg
->base_params
->shadow_reg_enable
&&
269 txq_id
!= trans_pcie
->cmd_queue
&&
270 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
272 * wake up nic if it's powered down ...
273 * uCode will wake up, and interrupt us again, so next
274 * time we'll skip this part.
276 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
278 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
279 IWL_DEBUG_INFO(trans
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
281 iwl_set_bit(trans
, CSR_GP_CNTRL
,
282 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
283 txq
->need_update
= true;
289 * if not in power-save mode, uCode will never sleep when we're
290 * trying to tx (during RFKILL, we're not trying to tx).
292 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
, txq
->q
.write_ptr
);
294 iwl_write32(trans
, HBUS_TARG_WRPTR
,
295 txq
->q
.write_ptr
| (txq_id
<< 8));
298 void iwl_pcie_txq_check_wrptrs(struct iwl_trans
*trans
)
300 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
303 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
304 struct iwl_txq
*txq
= &trans_pcie
->txq
[i
];
306 spin_lock_bh(&txq
->lock
);
307 if (trans_pcie
->txq
[i
].need_update
) {
308 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
309 trans_pcie
->txq
[i
].need_update
= false;
311 spin_unlock_bh(&txq
->lock
);
315 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
317 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
319 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
320 if (sizeof(dma_addr_t
) > sizeof(u32
))
322 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
327 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
328 dma_addr_t addr
, u16 len
)
330 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
331 u16 hi_n_len
= len
<< 4;
333 put_unaligned_le32(addr
, &tb
->lo
);
334 if (sizeof(dma_addr_t
) > sizeof(u32
))
335 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
337 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
339 tfd
->num_tbs
= idx
+ 1;
342 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
344 return tfd
->num_tbs
& 0x1f;
347 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
348 struct iwl_cmd_meta
*meta
,
354 /* Sanity check on number of chunks */
355 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
357 if (num_tbs
>= IWL_NUM_OF_TBS
) {
358 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
359 /* @todo issue fatal error, it is quite serious situation */
363 /* first TB is never freed - it's the bidirectional DMA data */
365 for (i
= 1; i
< num_tbs
; i
++) {
366 if (meta
->flags
& BIT(i
+ CMD_TB_BITMAP_POS
))
367 dma_unmap_page(trans
->dev
,
368 iwl_pcie_tfd_tb_get_addr(tfd
, i
),
369 iwl_pcie_tfd_tb_get_len(tfd
, i
),
372 dma_unmap_single(trans
->dev
,
373 iwl_pcie_tfd_tb_get_addr(tfd
, i
),
374 iwl_pcie_tfd_tb_get_len(tfd
, i
),
381 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
382 * @trans - transport private data
384 * @dma_dir - the direction of the DMA mapping
386 * Does NOT advance any TFD circular buffer read/write indexes
387 * Does NOT free the TFD itself (which is within circular buffer)
389 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
391 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
393 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
394 * idx is bounded by n_window
396 int rd_ptr
= txq
->q
.read_ptr
;
397 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
399 lockdep_assert_held(&txq
->lock
);
401 /* We have only q->n_window txq->entries, but we use
402 * TFD_QUEUE_SIZE_MAX tfds
404 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
410 skb
= txq
->entries
[idx
].skb
;
412 /* Can be called from irqs-disabled context
413 * If skb is not NULL, it means that the whole queue is being
414 * freed and that the queue is not empty - free the skb
417 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
418 txq
->entries
[idx
].skb
= NULL
;
423 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
424 dma_addr_t addr
, u16 len
, bool reset
)
427 struct iwl_tfd
*tfd
, *tfd_tmp
;
432 tfd
= &tfd_tmp
[q
->write_ptr
];
435 memset(tfd
, 0, sizeof(*tfd
));
437 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
439 /* Each TFD can point to a maximum 20 Tx buffers */
440 if (num_tbs
>= IWL_NUM_OF_TBS
) {
441 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
446 if (WARN(addr
& ~IWL_TX_DMA_MASK
,
447 "Unaligned address = %llx\n", (unsigned long long)addr
))
450 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
455 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
456 struct iwl_txq
*txq
, int slots_num
,
459 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
460 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
464 if (WARN_ON(txq
->entries
|| txq
->tfds
))
467 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
469 txq
->trans_pcie
= trans_pcie
;
471 txq
->q
.n_window
= slots_num
;
473 txq
->entries
= kcalloc(slots_num
,
474 sizeof(struct iwl_pcie_txq_entry
),
480 if (txq_id
== trans_pcie
->cmd_queue
)
481 for (i
= 0; i
< slots_num
; i
++) {
482 txq
->entries
[i
].cmd
=
483 kmalloc(sizeof(struct iwl_device_cmd
),
485 if (!txq
->entries
[i
].cmd
)
489 /* Circular buffer of transmit frame descriptors (TFDs),
490 * shared with device */
491 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
492 &txq
->q
.dma_addr
, GFP_KERNEL
);
496 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN
!= sizeof(*txq
->first_tb_bufs
));
498 tb0_buf_sz
= sizeof(*txq
->first_tb_bufs
) * slots_num
;
500 txq
->first_tb_bufs
= dma_alloc_coherent(trans
->dev
, tb0_buf_sz
,
503 if (!txq
->first_tb_bufs
)
510 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
512 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
513 for (i
= 0; i
< slots_num
; i
++)
514 kfree(txq
->entries
[i
].cmd
);
522 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
523 int slots_num
, u32 txq_id
)
527 txq
->need_update
= false;
529 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
530 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
531 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
533 /* Initialize queue's high/low-water marks, and head/tail indexes */
534 ret
= iwl_queue_init(&txq
->q
, slots_num
, txq_id
);
538 spin_lock_init(&txq
->lock
);
539 __skb_queue_head_init(&txq
->overflow_q
);
542 * Tell nic where to find circular buffer of Tx Frame Descriptors for
543 * given Tx queue, and enable the DMA channel used for that queue.
544 * Circular buffer (TFD queue in DRAM) physical base address */
545 if (trans
->cfg
->use_tfh
)
546 iwl_write_direct64(trans
,
547 FH_MEM_CBBC_QUEUE(trans
, txq_id
),
550 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(trans
, txq_id
),
551 txq
->q
.dma_addr
>> 8);
556 static void iwl_pcie_free_tso_page(struct iwl_trans_pcie
*trans_pcie
,
559 struct page
**page_ptr
;
561 page_ptr
= (void *)((u8
*)skb
->cb
+ trans_pcie
->page_offs
);
564 __free_page(*page_ptr
);
569 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans
*trans
)
571 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
573 lockdep_assert_held(&trans_pcie
->reg_lock
);
575 if (trans_pcie
->ref_cmd_in_flight
) {
576 trans_pcie
->ref_cmd_in_flight
= false;
577 IWL_DEBUG_RPM(trans
, "clear ref_cmd_in_flight - unref\n");
578 iwl_trans_unref(trans
);
581 if (!trans
->cfg
->base_params
->apmg_wake_up_wa
)
583 if (WARN_ON(!trans_pcie
->cmd_hold_nic_awake
))
586 trans_pcie
->cmd_hold_nic_awake
= false;
587 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
588 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
592 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
594 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
596 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
597 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
598 struct iwl_queue
*q
= &txq
->q
;
600 spin_lock_bh(&txq
->lock
);
601 while (q
->write_ptr
!= q
->read_ptr
) {
602 IWL_DEBUG_TX_REPLY(trans
, "Q %d Free %d\n",
603 txq_id
, q
->read_ptr
);
605 if (txq_id
!= trans_pcie
->cmd_queue
) {
606 struct sk_buff
*skb
= txq
->entries
[q
->read_ptr
].skb
;
608 if (WARN_ON_ONCE(!skb
))
611 iwl_pcie_free_tso_page(trans_pcie
, skb
);
613 iwl_pcie_txq_free_tfd(trans
, txq
);
614 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
);
616 if (q
->read_ptr
== q
->write_ptr
) {
619 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
620 if (txq_id
!= trans_pcie
->cmd_queue
) {
621 IWL_DEBUG_RPM(trans
, "Q %d - last tx freed\n",
623 iwl_trans_unref(trans
);
625 iwl_pcie_clear_cmd_in_flight(trans
);
627 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
632 while (!skb_queue_empty(&txq
->overflow_q
)) {
633 struct sk_buff
*skb
= __skb_dequeue(&txq
->overflow_q
);
635 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
638 spin_unlock_bh(&txq
->lock
);
640 /* just in case - this queue may have been stopped */
641 iwl_wake_queue(trans
, txq
);
645 * iwl_pcie_txq_free - Deallocate DMA queue.
646 * @txq: Transmit queue to deallocate.
648 * Empty queue by removing and destroying all BD's.
650 * 0-fill, but do not free "txq" descriptor structure.
652 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
654 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
655 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
656 struct device
*dev
= trans
->dev
;
662 iwl_pcie_txq_unmap(trans
, txq_id
);
664 /* De-alloc array of command/tx buffers */
665 if (txq_id
== trans_pcie
->cmd_queue
)
666 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
667 kzfree(txq
->entries
[i
].cmd
);
668 kzfree(txq
->entries
[i
].free_buf
);
671 /* De-alloc circular buffer of TFDs */
673 dma_free_coherent(dev
,
674 sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
,
675 txq
->tfds
, txq
->q
.dma_addr
);
679 dma_free_coherent(dev
,
680 sizeof(*txq
->first_tb_bufs
) * txq
->q
.n_window
,
681 txq
->first_tb_bufs
, txq
->first_tb_dma
);
687 del_timer_sync(&txq
->stuck_timer
);
689 /* 0-fill queue descriptor structure */
690 memset(txq
, 0, sizeof(*txq
));
693 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
695 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
696 int nq
= trans
->cfg
->base_params
->num_of_queues
;
699 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
700 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
702 /* make sure all queue are not stopped/used */
703 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
704 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
706 if (trans
->cfg
->use_tfh
)
709 trans_pcie
->scd_base_addr
=
710 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
712 WARN_ON(scd_base_addr
!= 0 &&
713 scd_base_addr
!= trans_pcie
->scd_base_addr
);
715 /* reset context data, TX status and translation data */
716 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
717 SCD_CONTEXT_MEM_LOWER_BOUND
,
720 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
721 trans_pcie
->scd_bc_tbls
.dma
>> 10);
723 /* The chain extension of the SCD doesn't work well. This feature is
724 * enabled by default by the HW, so we need to disable it manually.
726 if (trans
->cfg
->base_params
->scd_chain_ext_wa
)
727 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
729 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
730 trans_pcie
->cmd_fifo
,
731 trans_pcie
->cmd_q_wdg_timeout
);
733 /* Activate all Tx DMA/FIFO channels */
734 iwl_scd_activate_fifos(trans
);
736 /* Enable DMA channel */
737 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
738 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
739 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
740 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
742 /* Update FH chicken bits */
743 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
744 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
745 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
747 /* Enable L1-Active */
748 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
749 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
750 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
753 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
755 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
758 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
760 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
761 if (trans
->cfg
->use_tfh
)
762 iwl_write_direct64(trans
,
763 FH_MEM_CBBC_QUEUE(trans
, txq_id
),
766 iwl_write_direct32(trans
,
767 FH_MEM_CBBC_QUEUE(trans
, txq_id
),
768 txq
->q
.dma_addr
>> 8);
769 iwl_pcie_txq_unmap(trans
, txq_id
);
771 txq
->q
.write_ptr
= 0;
774 /* Tell NIC where to find the "keep warm" buffer */
775 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
776 trans_pcie
->kw
.dma
>> 4);
779 * Send 0 as the scd_base_addr since the device may have be reset
780 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
783 iwl_pcie_tx_start(trans
, 0);
786 static void iwl_pcie_tx_stop_fh(struct iwl_trans
*trans
)
788 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
793 spin_lock(&trans_pcie
->irq_lock
);
795 if (!iwl_trans_grab_nic_access(trans
, &flags
))
798 /* Stop each Tx DMA channel */
799 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
800 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
801 mask
|= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
);
804 /* Wait for DMA channels to be idle */
805 ret
= iwl_poll_bit(trans
, FH_TSSR_TX_STATUS_REG
, mask
, mask
, 5000);
808 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
809 ch
, iwl_read32(trans
, FH_TSSR_TX_STATUS_REG
));
811 iwl_trans_release_nic_access(trans
, &flags
);
814 spin_unlock(&trans_pcie
->irq_lock
);
818 * iwl_pcie_tx_stop - Stop all Tx DMA channels
820 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
822 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
825 /* Turn off all Tx DMA fifos */
826 iwl_scd_deactivate_fifos(trans
);
828 /* Turn off all Tx DMA channels */
829 iwl_pcie_tx_stop_fh(trans
);
832 * This function can be called before the op_mode disabled the
833 * queues. This happens when we have an rfkill interrupt.
834 * Since we stop Tx altogether - mark the queues as stopped.
836 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
837 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
839 /* This can happen: start_hw, stop_device */
840 if (!trans_pcie
->txq
)
843 /* Unmap DMA from host system and free skb's */
844 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
846 iwl_pcie_txq_unmap(trans
, txq_id
);
852 * iwl_trans_tx_free - Free TXQ Context
854 * Destroy all TX DMA queues and structures
856 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
859 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
862 if (trans_pcie
->txq
) {
864 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
865 iwl_pcie_txq_free(trans
, txq_id
);
868 kfree(trans_pcie
->txq
);
869 trans_pcie
->txq
= NULL
;
871 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
873 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
877 * iwl_pcie_tx_alloc - allocate TX context
878 * Allocate all Tx DMA structures and initialize them
880 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
883 int txq_id
, slots_num
;
884 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
886 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
887 sizeof(struct iwlagn_scd_bc_tbl
);
889 /*It is not allowed to alloc twice, so warn when this happens.
890 * We cannot rely on the previous allocation, so free and fail */
891 if (WARN_ON(trans_pcie
->txq
)) {
896 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
899 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
903 /* Alloc keep-warm buffer */
904 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
906 IWL_ERR(trans
, "Keep Warm allocation failed\n");
910 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
911 sizeof(struct iwl_txq
), GFP_KERNEL
);
912 if (!trans_pcie
->txq
) {
913 IWL_ERR(trans
, "Not enough memory for txq\n");
918 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
919 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
921 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
922 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
923 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
926 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
934 iwl_pcie_tx_free(trans
);
938 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
940 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
942 int txq_id
, slots_num
;
945 if (!trans_pcie
->txq
) {
946 ret
= iwl_pcie_tx_alloc(trans
);
952 spin_lock(&trans_pcie
->irq_lock
);
954 /* Turn off all Tx DMA fifos */
955 iwl_scd_deactivate_fifos(trans
);
957 /* Tell NIC where to find the "keep warm" buffer */
958 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
959 trans_pcie
->kw
.dma
>> 4);
961 spin_unlock(&trans_pcie
->irq_lock
);
963 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
964 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
966 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
967 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
968 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
971 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
976 if (trans
->cfg
->use_tfh
) {
977 iwl_write_direct32(trans
, TFH_TRANSFER_MODE
,
978 TFH_TRANSFER_MAX_PENDING_REQ
|
980 TFH_CHUNK_SPLIT_MODE
);
984 iwl_set_bits_prph(trans
, SCD_GP_CTRL
, SCD_GP_CTRL_AUTO_ACTIVE_MODE
);
985 if (trans
->cfg
->base_params
->num_of_queues
> 20)
986 iwl_set_bits_prph(trans
, SCD_GP_CTRL
,
987 SCD_GP_CTRL_ENABLE_31_QUEUES
);
991 /*Upon error, free only if we allocated something */
993 iwl_pcie_tx_free(trans
);
997 static inline void iwl_pcie_txq_progress(struct iwl_txq
*txq
)
999 lockdep_assert_held(&txq
->lock
);
1001 if (!txq
->wd_timeout
)
1005 * station is asleep and we send data - that must
1006 * be uAPSD or PS-Poll. Don't rearm the timer.
1012 * if empty delete timer, otherwise move timer forward
1013 * since we're making progress on this queue
1015 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
1016 del_timer(&txq
->stuck_timer
);
1018 mod_timer(&txq
->stuck_timer
, jiffies
+ txq
->wd_timeout
);
1021 /* Frees buffers until index _not_ inclusive */
1022 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
1023 struct sk_buff_head
*skbs
)
1025 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1026 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1027 int tfd_num
= ssn
& (TFD_QUEUE_SIZE_MAX
- 1);
1028 struct iwl_queue
*q
= &txq
->q
;
1031 /* This function is not meant to release cmd queue*/
1032 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
1035 spin_lock_bh(&txq
->lock
);
1038 IWL_DEBUG_TX_QUEUES(trans
, "Q %d inactive - ignoring idx %d\n",
1043 if (txq
->q
.read_ptr
== tfd_num
)
1046 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
1047 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
1049 /*Since we free until index _not_ inclusive, the one before index is
1050 * the last we will free. This one must be used */
1051 last_to_free
= iwl_queue_dec_wrap(tfd_num
);
1053 if (!iwl_queue_used(q
, last_to_free
)) {
1055 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1056 __func__
, txq_id
, last_to_free
, TFD_QUEUE_SIZE_MAX
,
1057 q
->write_ptr
, q
->read_ptr
);
1061 if (WARN_ON(!skb_queue_empty(skbs
)))
1065 q
->read_ptr
!= tfd_num
;
1066 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
1067 struct sk_buff
*skb
= txq
->entries
[txq
->q
.read_ptr
].skb
;
1069 if (WARN_ON_ONCE(!skb
))
1072 iwl_pcie_free_tso_page(trans_pcie
, skb
);
1074 __skb_queue_tail(skbs
, skb
);
1076 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
1078 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
1080 iwl_pcie_txq_free_tfd(trans
, txq
);
1083 iwl_pcie_txq_progress(txq
);
1085 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1086 test_bit(txq_id
, trans_pcie
->queue_stopped
)) {
1087 struct sk_buff_head overflow_skbs
;
1089 __skb_queue_head_init(&overflow_skbs
);
1090 skb_queue_splice_init(&txq
->overflow_q
, &overflow_skbs
);
1093 * This is tricky: we are in reclaim path which is non
1094 * re-entrant, so noone will try to take the access the
1095 * txq data from that path. We stopped tx, so we can't
1096 * have tx as well. Bottom line, we can unlock and re-lock
1099 spin_unlock_bh(&txq
->lock
);
1101 while (!skb_queue_empty(&overflow_skbs
)) {
1102 struct sk_buff
*skb
= __skb_dequeue(&overflow_skbs
);
1103 struct iwl_device_cmd
*dev_cmd_ptr
;
1105 dev_cmd_ptr
= *(void **)((u8
*)skb
->cb
+
1106 trans_pcie
->dev_cmd_offs
);
1109 * Note that we can very well be overflowing again.
1110 * In that case, iwl_queue_space will be small again
1111 * and we won't wake mac80211's queue.
1113 iwl_trans_pcie_tx(trans
, skb
, dev_cmd_ptr
, txq_id
);
1115 spin_lock_bh(&txq
->lock
);
1117 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
1118 iwl_wake_queue(trans
, txq
);
1121 if (q
->read_ptr
== q
->write_ptr
) {
1122 IWL_DEBUG_RPM(trans
, "Q %d - last tx reclaimed\n", q
->id
);
1123 iwl_trans_unref(trans
);
1127 spin_unlock_bh(&txq
->lock
);
1130 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans
*trans
,
1131 const struct iwl_host_cmd
*cmd
)
1133 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1136 lockdep_assert_held(&trans_pcie
->reg_lock
);
1138 if (!(cmd
->flags
& CMD_SEND_IN_IDLE
) &&
1139 !trans_pcie
->ref_cmd_in_flight
) {
1140 trans_pcie
->ref_cmd_in_flight
= true;
1141 IWL_DEBUG_RPM(trans
, "set ref_cmd_in_flight - ref\n");
1142 iwl_trans_ref(trans
);
1146 * wake up the NIC to make sure that the firmware will see the host
1147 * command - we will let the NIC sleep once all the host commands
1148 * returned. This needs to be done only on NICs that have
1149 * apmg_wake_up_wa set.
1151 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1152 !trans_pcie
->cmd_hold_nic_awake
) {
1153 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1154 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1156 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1157 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1158 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1159 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
),
1162 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1163 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1164 IWL_ERR(trans
, "Failed to wake NIC for hcmd\n");
1167 trans_pcie
->cmd_hold_nic_awake
= true;
1174 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1176 * When FW advances 'R' index, all entries between old and new 'R' index
1177 * need to be reclaimed. As result, some free space forms. If there is
1178 * enough free space (> low mark), wake the stack that feeds us.
1180 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
1182 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1183 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1184 struct iwl_queue
*q
= &txq
->q
;
1185 unsigned long flags
;
1188 lockdep_assert_held(&txq
->lock
);
1190 if ((idx
>= TFD_QUEUE_SIZE_MAX
) || (!iwl_queue_used(q
, idx
))) {
1192 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1193 __func__
, txq_id
, idx
, TFD_QUEUE_SIZE_MAX
,
1194 q
->write_ptr
, q
->read_ptr
);
1198 for (idx
= iwl_queue_inc_wrap(idx
); q
->read_ptr
!= idx
;
1199 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
1202 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1203 idx
, q
->write_ptr
, q
->read_ptr
);
1204 iwl_force_nmi(trans
);
1208 if (q
->read_ptr
== q
->write_ptr
) {
1209 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1210 iwl_pcie_clear_cmd_in_flight(trans
);
1211 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1214 iwl_pcie_txq_progress(txq
);
1217 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1220 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1225 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1227 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1228 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1230 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1233 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1235 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1237 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1242 /* Receiver address (actually, Rx station's index into station table),
1243 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1244 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1246 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, u16 ssn
,
1247 const struct iwl_trans_txq_scd_cfg
*cfg
,
1248 unsigned int wdg_timeout
)
1250 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1251 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1254 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1255 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1257 if (cfg
&& trans
->cfg
->use_tfh
)
1258 WARN_ONCE(1, "Expected no calls to SCD configuration");
1260 txq
->wd_timeout
= msecs_to_jiffies(wdg_timeout
);
1265 /* Disable the scheduler prior configuring the cmd queue */
1266 if (txq_id
== trans_pcie
->cmd_queue
&&
1267 trans_pcie
->scd_set_active
)
1268 iwl_scd_enable_set_active(trans
, 0);
1270 /* Stop this Tx queue before configuring it */
1271 iwl_scd_txq_set_inactive(trans
, txq_id
);
1273 /* Set this queue as a chain-building queue unless it is CMD */
1274 if (txq_id
!= trans_pcie
->cmd_queue
)
1275 iwl_scd_txq_set_chain(trans
, txq_id
);
1277 if (cfg
->aggregate
) {
1278 u16 ra_tid
= BUILD_RAxTID(cfg
->sta_id
, cfg
->tid
);
1280 /* Map receiver-address / traffic-ID to this queue */
1281 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1283 /* enable aggregations for the queue */
1284 iwl_scd_txq_enable_agg(trans
, txq_id
);
1288 * disable aggregations for the queue, this will also
1289 * make the ra_tid mapping configuration irrelevant
1290 * since it is now a non-AGG queue.
1292 iwl_scd_txq_disable_agg(trans
, txq_id
);
1294 ssn
= txq
->q
.read_ptr
;
1298 /* Place first TFD at index corresponding to start sequence number.
1299 * Assumes that ssn_idx is valid (!= 0xFFF) */
1300 txq
->q
.read_ptr
= (ssn
& 0xff);
1301 txq
->q
.write_ptr
= (ssn
& 0xff);
1302 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1303 (ssn
& 0xff) | (txq_id
<< 8));
1306 u8 frame_limit
= cfg
->frame_limit
;
1308 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1310 /* Set up Tx window size and frame limit for this queue */
1311 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1312 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1313 iwl_trans_write_mem32(trans
,
1314 trans_pcie
->scd_base_addr
+
1315 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1316 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1317 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1318 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1319 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1321 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1322 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1323 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1324 (cfg
->fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1325 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1326 SCD_QUEUE_STTS_REG_MSK
);
1328 /* enable the scheduler for this queue (only) */
1329 if (txq_id
== trans_pcie
->cmd_queue
&&
1330 trans_pcie
->scd_set_active
)
1331 iwl_scd_enable_set_active(trans
, BIT(txq_id
));
1333 IWL_DEBUG_TX_QUEUES(trans
,
1334 "Activate queue %d on FIFO %d WrPtr: %d\n",
1335 txq_id
, fifo
, ssn
& 0xff);
1337 IWL_DEBUG_TX_QUEUES(trans
,
1338 "Activate queue %d WrPtr: %d\n",
1339 txq_id
, ssn
& 0xff);
1345 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans
*trans
, u32 txq_id
,
1348 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1349 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1351 txq
->ampdu
= !shared_mode
;
1354 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
,
1357 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1358 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1359 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1360 static const u32 zero_val
[4] = {};
1362 trans_pcie
->txq
[txq_id
].frozen_expiry_remainder
= 0;
1363 trans_pcie
->txq
[txq_id
].frozen
= false;
1366 * Upon HW Rfkill - we stop the device, and then stop the queues
1367 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1368 * allow the op_mode to call txq_disable after it already called
1371 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1372 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
),
1373 "queue %d not used", txq_id
);
1377 if (configure_scd
&& trans
->cfg
->use_tfh
)
1378 WARN_ONCE(1, "Expected no calls to SCD configuration");
1380 if (configure_scd
) {
1381 iwl_scd_txq_set_inactive(trans
, txq_id
);
1383 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1384 ARRAY_SIZE(zero_val
));
1387 iwl_pcie_txq_unmap(trans
, txq_id
);
1388 trans_pcie
->txq
[txq_id
].ampdu
= false;
1390 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1393 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1396 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1397 * @priv: device private data point
1398 * @cmd: a pointer to the ucode command structure
1400 * The function returns < 0 values to indicate the operation
1401 * failed. On success, it returns the index (>= 0) of command in the
1404 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1405 struct iwl_host_cmd
*cmd
)
1407 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1408 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1409 struct iwl_queue
*q
= &txq
->q
;
1410 struct iwl_device_cmd
*out_cmd
;
1411 struct iwl_cmd_meta
*out_meta
;
1412 unsigned long flags
;
1413 void *dup_buf
= NULL
;
1414 dma_addr_t phys_addr
;
1416 u16 copy_size
, cmd_size
, tb0_size
;
1417 bool had_nocopy
= false;
1418 u8 group_id
= iwl_cmd_groupid(cmd
->id
);
1421 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1422 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1424 if (WARN(!trans_pcie
->wide_cmd_header
&&
1425 group_id
> IWL_ALWAYS_LONG_GROUP
,
1426 "unsupported wide command %#x\n", cmd
->id
))
1429 if (group_id
!= 0) {
1430 copy_size
= sizeof(struct iwl_cmd_header_wide
);
1431 cmd_size
= sizeof(struct iwl_cmd_header_wide
);
1433 copy_size
= sizeof(struct iwl_cmd_header
);
1434 cmd_size
= sizeof(struct iwl_cmd_header
);
1437 /* need one for the header if the first is NOCOPY */
1438 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1440 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1441 cmddata
[i
] = cmd
->data
[i
];
1442 cmdlen
[i
] = cmd
->len
[i
];
1447 /* need at least IWL_FIRST_TB_SIZE copied */
1448 if (copy_size
< IWL_FIRST_TB_SIZE
) {
1449 int copy
= IWL_FIRST_TB_SIZE
- copy_size
;
1451 if (copy
> cmdlen
[i
])
1458 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1460 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1464 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1466 * This is also a chunk that isn't copied
1467 * to the static buffer so set had_nocopy.
1471 /* only allowed once */
1472 if (WARN_ON(dup_buf
)) {
1477 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1482 /* NOCOPY must not be followed by normal! */
1483 if (WARN_ON(had_nocopy
)) {
1487 copy_size
+= cmdlen
[i
];
1489 cmd_size
+= cmd
->len
[i
];
1493 * If any of the command structures end up being larger than
1494 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1495 * allocated into separate TFDs, then we will need to
1496 * increase the size of the buffers.
1498 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1499 "Command %s (%#x) is too large (%d bytes)\n",
1500 iwl_get_cmd_string(trans
, cmd
->id
),
1501 cmd
->id
, copy_size
)) {
1506 spin_lock_bh(&txq
->lock
);
1508 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1509 spin_unlock_bh(&txq
->lock
);
1511 IWL_ERR(trans
, "No space in command queue\n");
1512 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1517 idx
= get_cmd_index(q
, q
->write_ptr
);
1518 out_cmd
= txq
->entries
[idx
].cmd
;
1519 out_meta
= &txq
->entries
[idx
].meta
;
1521 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1522 if (cmd
->flags
& CMD_WANT_SKB
)
1523 out_meta
->source
= cmd
;
1525 /* set up the header */
1526 if (group_id
!= 0) {
1527 out_cmd
->hdr_wide
.cmd
= iwl_cmd_opcode(cmd
->id
);
1528 out_cmd
->hdr_wide
.group_id
= group_id
;
1529 out_cmd
->hdr_wide
.version
= iwl_cmd_version(cmd
->id
);
1530 out_cmd
->hdr_wide
.length
=
1531 cpu_to_le16(cmd_size
-
1532 sizeof(struct iwl_cmd_header_wide
));
1533 out_cmd
->hdr_wide
.reserved
= 0;
1534 out_cmd
->hdr_wide
.sequence
=
1535 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1536 INDEX_TO_SEQ(q
->write_ptr
));
1538 cmd_pos
= sizeof(struct iwl_cmd_header_wide
);
1539 copy_size
= sizeof(struct iwl_cmd_header_wide
);
1541 out_cmd
->hdr
.cmd
= iwl_cmd_opcode(cmd
->id
);
1542 out_cmd
->hdr
.sequence
=
1543 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1544 INDEX_TO_SEQ(q
->write_ptr
));
1545 out_cmd
->hdr
.group_id
= 0;
1547 cmd_pos
= sizeof(struct iwl_cmd_header
);
1548 copy_size
= sizeof(struct iwl_cmd_header
);
1551 /* and copy the data that needs to be copied */
1552 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1558 /* copy everything if not nocopy/dup */
1559 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1560 IWL_HCMD_DFL_DUP
))) {
1563 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1570 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1571 * in total (for bi-directional DMA), but copy up to what
1572 * we can fit into the payload for debug dump purposes.
1574 copy
= min_t(int, TFD_MAX_PAYLOAD_SIZE
- cmd_pos
, cmd
->len
[i
]);
1576 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1579 /* However, treat copy_size the proper way, we need it below */
1580 if (copy_size
< IWL_FIRST_TB_SIZE
) {
1581 copy
= IWL_FIRST_TB_SIZE
- copy_size
;
1583 if (copy
> cmd
->len
[i
])
1590 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1591 iwl_get_cmd_string(trans
, cmd
->id
),
1592 group_id
, out_cmd
->hdr
.cmd
,
1593 le16_to_cpu(out_cmd
->hdr
.sequence
),
1594 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1596 /* start the TFD with the minimum copy bytes */
1597 tb0_size
= min_t(int, copy_size
, IWL_FIRST_TB_SIZE
);
1598 memcpy(&txq
->first_tb_bufs
[idx
], &out_cmd
->hdr
, tb0_size
);
1599 iwl_pcie_txq_build_tfd(trans
, txq
,
1600 iwl_pcie_get_first_tb_dma(txq
, idx
),
1603 /* map first command fragment, if any remains */
1604 if (copy_size
> tb0_size
) {
1605 phys_addr
= dma_map_single(trans
->dev
,
1606 ((u8
*)&out_cmd
->hdr
) + tb0_size
,
1607 copy_size
- tb0_size
,
1609 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1610 iwl_pcie_tfd_unmap(trans
, out_meta
,
1611 &txq
->tfds
[q
->write_ptr
]);
1616 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1617 copy_size
- tb0_size
, false);
1620 /* map the remaining (adjusted) nocopy/dup fragments */
1621 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1622 const void *data
= cmddata
[i
];
1626 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1629 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1631 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1632 cmdlen
[i
], DMA_TO_DEVICE
);
1633 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1634 iwl_pcie_tfd_unmap(trans
, out_meta
,
1635 &txq
->tfds
[q
->write_ptr
]);
1640 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], false);
1643 BUILD_BUG_ON(IWL_NUM_OF_TBS
+ CMD_TB_BITMAP_POS
>
1644 sizeof(out_meta
->flags
) * BITS_PER_BYTE
);
1645 out_meta
->flags
= cmd
->flags
;
1646 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1647 kzfree(txq
->entries
[idx
].free_buf
);
1648 txq
->entries
[idx
].free_buf
= dup_buf
;
1650 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr_wide
);
1652 /* start timer if queue currently empty */
1653 if (q
->read_ptr
== q
->write_ptr
&& txq
->wd_timeout
)
1654 mod_timer(&txq
->stuck_timer
, jiffies
+ txq
->wd_timeout
);
1656 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1657 ret
= iwl_pcie_set_cmd_in_flight(trans
, cmd
);
1660 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1664 /* Increment and update queue's write index */
1665 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
1666 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1668 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1671 spin_unlock_bh(&txq
->lock
);
1679 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1680 * @rxb: Rx buffer to reclaim
1682 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1683 struct iwl_rx_cmd_buffer
*rxb
)
1685 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1686 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1687 u8 group_id
= iwl_cmd_groupid(pkt
->hdr
.group_id
);
1689 int txq_id
= SEQ_TO_QUEUE(sequence
);
1690 int index
= SEQ_TO_INDEX(sequence
);
1692 struct iwl_device_cmd
*cmd
;
1693 struct iwl_cmd_meta
*meta
;
1694 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1695 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1697 /* If a Tx command is being handled and it isn't in the actual
1698 * command queue then there a command routing bug has been introduced
1699 * in the queue management code. */
1700 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1701 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1702 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1703 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1704 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1705 iwl_print_hex_error(trans
, pkt
, 32);
1709 spin_lock_bh(&txq
->lock
);
1711 cmd_index
= get_cmd_index(&txq
->q
, index
);
1712 cmd
= txq
->entries
[cmd_index
].cmd
;
1713 meta
= &txq
->entries
[cmd_index
].meta
;
1714 cmd_id
= iwl_cmd_id(cmd
->hdr
.cmd
, group_id
, 0);
1716 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1718 /* Input error checking is done when commands are added to queue. */
1719 if (meta
->flags
& CMD_WANT_SKB
) {
1720 struct page
*p
= rxb_steal_page(rxb
);
1722 meta
->source
->resp_pkt
= pkt
;
1723 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1724 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1727 if (meta
->flags
& CMD_WANT_ASYNC_CALLBACK
)
1728 iwl_op_mode_async_cb(trans
->op_mode
, cmd
);
1730 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1732 if (!(meta
->flags
& CMD_ASYNC
)) {
1733 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
)) {
1735 "HCMD_ACTIVE already clear for command %s\n",
1736 iwl_get_cmd_string(trans
, cmd_id
));
1738 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1739 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1740 iwl_get_cmd_string(trans
, cmd_id
));
1741 wake_up(&trans_pcie
->wait_command_queue
);
1744 if (meta
->flags
& CMD_MAKE_TRANS_IDLE
) {
1745 IWL_DEBUG_INFO(trans
, "complete %s - mark trans as idle\n",
1746 iwl_get_cmd_string(trans
, cmd
->hdr
.cmd
));
1747 set_bit(STATUS_TRANS_IDLE
, &trans
->status
);
1748 wake_up(&trans_pcie
->d0i3_waitq
);
1751 if (meta
->flags
& CMD_WAKE_UP_TRANS
) {
1752 IWL_DEBUG_INFO(trans
, "complete %s - clear trans idle flag\n",
1753 iwl_get_cmd_string(trans
, cmd
->hdr
.cmd
));
1754 clear_bit(STATUS_TRANS_IDLE
, &trans
->status
);
1755 wake_up(&trans_pcie
->d0i3_waitq
);
1760 spin_unlock_bh(&txq
->lock
);
1763 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1765 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1766 struct iwl_host_cmd
*cmd
)
1770 /* An asynchronous command can not expect an SKB to be set. */
1771 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1774 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1777 "Error sending %s: enqueue_hcmd failed: %d\n",
1778 iwl_get_cmd_string(trans
, cmd
->id
), ret
);
1784 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1785 struct iwl_host_cmd
*cmd
)
1787 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1791 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1792 iwl_get_cmd_string(trans
, cmd
->id
));
1794 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE
,
1796 "Command %s: a command is already active!\n",
1797 iwl_get_cmd_string(trans
, cmd
->id
)))
1800 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1801 iwl_get_cmd_string(trans
, cmd
->id
));
1803 if (pm_runtime_suspended(&trans_pcie
->pci_dev
->dev
)) {
1804 ret
= wait_event_timeout(trans_pcie
->d0i3_waitq
,
1805 pm_runtime_active(&trans_pcie
->pci_dev
->dev
),
1806 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT
));
1808 IWL_ERR(trans
, "Timeout exiting D0i3 before hcmd\n");
1813 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1816 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1818 "Error sending %s: enqueue_hcmd failed: %d\n",
1819 iwl_get_cmd_string(trans
, cmd
->id
), ret
);
1823 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1824 !test_bit(STATUS_SYNC_HCMD_ACTIVE
,
1826 HOST_COMPLETE_TIMEOUT
);
1828 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1829 struct iwl_queue
*q
= &txq
->q
;
1831 IWL_ERR(trans
, "Error sending %s: time out after %dms.\n",
1832 iwl_get_cmd_string(trans
, cmd
->id
),
1833 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1835 IWL_ERR(trans
, "Current CMD queue read_ptr %d write_ptr %d\n",
1836 q
->read_ptr
, q
->write_ptr
);
1838 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1839 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1840 iwl_get_cmd_string(trans
, cmd
->id
));
1843 iwl_force_nmi(trans
);
1844 iwl_trans_fw_error(trans
);
1849 if (test_bit(STATUS_FW_ERROR
, &trans
->status
)) {
1850 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1851 iwl_get_cmd_string(trans
, cmd
->id
));
1857 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1858 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1859 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1864 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1865 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1866 iwl_get_cmd_string(trans
, cmd
->id
));
1874 if (cmd
->flags
& CMD_WANT_SKB
) {
1876 * Cancel the CMD_WANT_SKB flag for the cmd in the
1877 * TX cmd queue. Otherwise in case the cmd comes
1878 * in later, it will possibly set an invalid
1879 * address (cmd->meta.source).
1881 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1882 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1885 if (cmd
->resp_pkt
) {
1887 cmd
->resp_pkt
= NULL
;
1893 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1895 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1896 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1897 IWL_DEBUG_RF_KILL(trans
, "Dropping CMD 0x%x: RF KILL\n",
1902 if (cmd
->flags
& CMD_ASYNC
)
1903 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1905 /* We still can fail on RFKILL that can be asserted while we wait */
1906 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1909 static int iwl_fill_data_tbs(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1910 struct iwl_txq
*txq
, u8 hdr_len
,
1911 struct iwl_cmd_meta
*out_meta
,
1912 struct iwl_device_cmd
*dev_cmd
, u16 tb1_len
)
1914 struct iwl_queue
*q
= &txq
->q
;
1919 * Set up TFD's third entry to point directly to remainder
1920 * of skb's head, if any
1922 tb2_len
= skb_headlen(skb
) - hdr_len
;
1925 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1926 skb
->data
+ hdr_len
,
1927 tb2_len
, DMA_TO_DEVICE
);
1928 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1929 iwl_pcie_tfd_unmap(trans
, out_meta
,
1930 &txq
->tfds
[q
->write_ptr
]);
1933 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, false);
1936 /* set up the remaining entries to point to the data */
1937 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1938 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1942 if (!skb_frag_size(frag
))
1945 tb_phys
= skb_frag_dma_map(trans
->dev
, frag
, 0,
1946 skb_frag_size(frag
), DMA_TO_DEVICE
);
1948 if (unlikely(dma_mapping_error(trans
->dev
, tb_phys
))) {
1949 iwl_pcie_tfd_unmap(trans
, out_meta
,
1950 &txq
->tfds
[q
->write_ptr
]);
1953 tb_idx
= iwl_pcie_txq_build_tfd(trans
, txq
, tb_phys
,
1954 skb_frag_size(frag
), false);
1956 out_meta
->flags
|= BIT(tb_idx
+ CMD_TB_BITMAP_POS
);
1959 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1960 &txq
->tfds
[txq
->q
.write_ptr
],
1961 sizeof(struct iwl_tfd
),
1962 &dev_cmd
->hdr
, IWL_FIRST_TB_SIZE
+ tb1_len
,
1963 skb
->data
+ hdr_len
, tb2_len
);
1964 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1965 hdr_len
, skb
->len
- hdr_len
);
1970 static struct iwl_tso_hdr_page
*
1971 get_page_hdr(struct iwl_trans
*trans
, size_t len
)
1973 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1974 struct iwl_tso_hdr_page
*p
= this_cpu_ptr(trans_pcie
->tso_hdr_page
);
1979 /* enough room on this page */
1980 if (p
->pos
+ len
< (u8
*)page_address(p
->page
) + PAGE_SIZE
)
1983 /* We don't have enough room on this page, get a new one. */
1984 __free_page(p
->page
);
1987 p
->page
= alloc_page(GFP_ATOMIC
);
1990 p
->pos
= page_address(p
->page
);
1994 static void iwl_compute_pseudo_hdr_csum(void *iph
, struct tcphdr
*tcph
,
1995 bool ipv6
, unsigned int len
)
1998 struct ipv6hdr
*iphv6
= iph
;
2000 tcph
->check
= ~csum_ipv6_magic(&iphv6
->saddr
, &iphv6
->daddr
,
2001 len
+ tcph
->doff
* 4,
2004 struct iphdr
*iphv4
= iph
;
2006 ip_send_check(iphv4
);
2007 tcph
->check
= ~csum_tcpudp_magic(iphv4
->saddr
, iphv4
->daddr
,
2008 len
+ tcph
->doff
* 4,
2013 static int iwl_fill_data_tbs_amsdu(struct iwl_trans
*trans
, struct sk_buff
*skb
,
2014 struct iwl_txq
*txq
, u8 hdr_len
,
2015 struct iwl_cmd_meta
*out_meta
,
2016 struct iwl_device_cmd
*dev_cmd
, u16 tb1_len
)
2018 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
2019 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
2020 unsigned int snap_ip_tcp_hdrlen
, ip_hdrlen
, total_len
, hdr_room
;
2021 unsigned int mss
= skb_shinfo(skb
)->gso_size
;
2022 struct iwl_queue
*q
= &txq
->q
;
2023 u16 length
, iv_len
, amsdu_pad
;
2025 struct iwl_tso_hdr_page
*hdr_page
;
2026 struct page
**page_ptr
;
2030 /* if the packet is protected, then it must be CCMP or GCMP */
2031 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN
!= IEEE80211_GCMP_HDR_LEN
);
2032 iv_len
= ieee80211_has_protected(hdr
->frame_control
) ?
2033 IEEE80211_CCMP_HDR_LEN
: 0;
2035 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
2036 &txq
->tfds
[txq
->q
.write_ptr
],
2037 sizeof(struct iwl_tfd
),
2038 &dev_cmd
->hdr
, IWL_FIRST_TB_SIZE
+ tb1_len
,
2041 ip_hdrlen
= skb_transport_header(skb
) - skb_network_header(skb
);
2042 snap_ip_tcp_hdrlen
= 8 + ip_hdrlen
+ tcp_hdrlen(skb
);
2043 total_len
= skb
->len
- snap_ip_tcp_hdrlen
- hdr_len
- iv_len
;
2046 /* total amount of header we may need for this A-MSDU */
2047 hdr_room
= DIV_ROUND_UP(total_len
, mss
) *
2048 (3 + snap_ip_tcp_hdrlen
+ sizeof(struct ethhdr
)) + iv_len
;
2050 /* Our device supports 9 segments at most, it will fit in 1 page */
2051 hdr_page
= get_page_hdr(trans
, hdr_room
);
2055 get_page(hdr_page
->page
);
2056 start_hdr
= hdr_page
->pos
;
2057 page_ptr
= (void *)((u8
*)skb
->cb
+ trans_pcie
->page_offs
);
2058 *page_ptr
= hdr_page
->page
;
2059 memcpy(hdr_page
->pos
, skb
->data
+ hdr_len
, iv_len
);
2060 hdr_page
->pos
+= iv_len
;
2063 * Pull the ieee80211 header + IV to be able to use TSO core,
2064 * we will restore it for the tx_status flow.
2066 skb_pull(skb
, hdr_len
+ iv_len
);
2068 tso_start(skb
, &tso
);
2071 /* this is the data left for this subframe */
2072 unsigned int data_left
=
2073 min_t(unsigned int, mss
, total_len
);
2074 struct sk_buff
*csum_skb
= NULL
;
2075 unsigned int hdr_tb_len
;
2076 dma_addr_t hdr_tb_phys
;
2077 struct tcphdr
*tcph
;
2080 total_len
-= data_left
;
2082 memset(hdr_page
->pos
, 0, amsdu_pad
);
2083 hdr_page
->pos
+= amsdu_pad
;
2084 amsdu_pad
= (4 - (sizeof(struct ethhdr
) + snap_ip_tcp_hdrlen
+
2086 ether_addr_copy(hdr_page
->pos
, ieee80211_get_DA(hdr
));
2087 hdr_page
->pos
+= ETH_ALEN
;
2088 ether_addr_copy(hdr_page
->pos
, ieee80211_get_SA(hdr
));
2089 hdr_page
->pos
+= ETH_ALEN
;
2091 length
= snap_ip_tcp_hdrlen
+ data_left
;
2092 *((__be16
*)hdr_page
->pos
) = cpu_to_be16(length
);
2093 hdr_page
->pos
+= sizeof(length
);
2096 * This will copy the SNAP as well which will be considered
2099 tso_build_hdr(skb
, hdr_page
->pos
, &tso
, data_left
, !total_len
);
2100 iph
= hdr_page
->pos
+ 8;
2101 tcph
= (void *)(iph
+ ip_hdrlen
);
2103 /* For testing on current hardware only */
2104 if (trans_pcie
->sw_csum_tx
) {
2105 csum_skb
= alloc_skb(data_left
+ tcp_hdrlen(skb
),
2112 iwl_compute_pseudo_hdr_csum(iph
, tcph
,
2117 memcpy(skb_put(csum_skb
, tcp_hdrlen(skb
)),
2118 tcph
, tcp_hdrlen(skb
));
2119 skb_set_transport_header(csum_skb
, 0);
2120 csum_skb
->csum_start
=
2121 (unsigned char *)tcp_hdr(csum_skb
) -
2125 hdr_page
->pos
+= snap_ip_tcp_hdrlen
;
2127 hdr_tb_len
= hdr_page
->pos
- start_hdr
;
2128 hdr_tb_phys
= dma_map_single(trans
->dev
, start_hdr
,
2129 hdr_tb_len
, DMA_TO_DEVICE
);
2130 if (unlikely(dma_mapping_error(trans
->dev
, hdr_tb_phys
))) {
2131 dev_kfree_skb(csum_skb
);
2135 iwl_pcie_txq_build_tfd(trans
, txq
, hdr_tb_phys
,
2137 trace_iwlwifi_dev_tx_tso_chunk(trans
->dev
, start_hdr
,
2140 /* prepare the start_hdr for the next subframe */
2141 start_hdr
= hdr_page
->pos
;
2143 /* put the payload */
2145 unsigned int size
= min_t(unsigned int, tso
.size
,
2149 if (trans_pcie
->sw_csum_tx
)
2150 memcpy(skb_put(csum_skb
, size
), tso
.data
, size
);
2152 tb_phys
= dma_map_single(trans
->dev
, tso
.data
,
2153 size
, DMA_TO_DEVICE
);
2154 if (unlikely(dma_mapping_error(trans
->dev
, tb_phys
))) {
2155 dev_kfree_skb(csum_skb
);
2160 iwl_pcie_txq_build_tfd(trans
, txq
, tb_phys
,
2162 trace_iwlwifi_dev_tx_tso_chunk(trans
->dev
, tso
.data
,
2166 tso_build_data(skb
, &tso
, size
);
2169 /* For testing on early hardware only */
2170 if (trans_pcie
->sw_csum_tx
) {
2173 csum
= skb_checksum(csum_skb
,
2174 skb_checksum_start_offset(csum_skb
),
2176 skb_checksum_start_offset(csum_skb
),
2178 dev_kfree_skb(csum_skb
);
2179 dma_sync_single_for_cpu(trans
->dev
, hdr_tb_phys
,
2180 hdr_tb_len
, DMA_TO_DEVICE
);
2181 tcph
->check
= csum_fold(csum
);
2182 dma_sync_single_for_device(trans
->dev
, hdr_tb_phys
,
2183 hdr_tb_len
, DMA_TO_DEVICE
);
2187 /* re -add the WiFi header and IV */
2188 skb_push(skb
, hdr_len
+ iv_len
);
2193 iwl_pcie_tfd_unmap(trans
, out_meta
, &txq
->tfds
[q
->write_ptr
]);
2196 #else /* CONFIG_INET */
2197 static int iwl_fill_data_tbs_amsdu(struct iwl_trans
*trans
, struct sk_buff
*skb
,
2198 struct iwl_txq
*txq
, u8 hdr_len
,
2199 struct iwl_cmd_meta
*out_meta
,
2200 struct iwl_device_cmd
*dev_cmd
, u16 tb1_len
)
2202 /* No A-MSDU without CONFIG_INET */
2207 #endif /* CONFIG_INET */
2209 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
2210 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
2212 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2213 struct ieee80211_hdr
*hdr
;
2214 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
2215 struct iwl_cmd_meta
*out_meta
;
2216 struct iwl_txq
*txq
;
2217 struct iwl_queue
*q
;
2218 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
2221 bool wait_write_ptr
;
2227 txq
= &trans_pcie
->txq
[txq_id
];
2230 if (WARN_ONCE(!test_bit(txq_id
, trans_pcie
->queue_used
),
2231 "TX on unused queue %d\n", txq_id
))
2234 if (unlikely(trans_pcie
->sw_csum_tx
&&
2235 skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
2236 int offs
= skb_checksum_start_offset(skb
);
2237 int csum_offs
= offs
+ skb
->csum_offset
;
2240 if (skb_ensure_writable(skb
, csum_offs
+ sizeof(__sum16
)))
2243 csum
= skb_checksum(skb
, offs
, skb
->len
- offs
, 0);
2244 *(__sum16
*)(skb
->data
+ csum_offs
) = csum_fold(csum
);
2246 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2249 if (skb_is_nonlinear(skb
) &&
2250 skb_shinfo(skb
)->nr_frags
> IWL_PCIE_MAX_FRAGS
&&
2251 __skb_linearize(skb
))
2254 /* mac80211 always puts the full header into the SKB's head,
2255 * so there's no need to check if it's readable there
2257 hdr
= (struct ieee80211_hdr
*)skb
->data
;
2258 fc
= hdr
->frame_control
;
2259 hdr_len
= ieee80211_hdrlen(fc
);
2261 spin_lock(&txq
->lock
);
2263 if (iwl_queue_space(q
) < q
->high_mark
) {
2264 iwl_stop_queue(trans
, txq
);
2266 /* don't put the packet on the ring, if there is no room */
2267 if (unlikely(iwl_queue_space(q
) < 3)) {
2268 struct iwl_device_cmd
**dev_cmd_ptr
;
2270 dev_cmd_ptr
= (void *)((u8
*)skb
->cb
+
2271 trans_pcie
->dev_cmd_offs
);
2273 *dev_cmd_ptr
= dev_cmd
;
2274 __skb_queue_tail(&txq
->overflow_q
, skb
);
2276 spin_unlock(&txq
->lock
);
2281 /* In AGG mode, the index in the ring must correspond to the WiFi
2282 * sequence number. This is a HW requirements to help the SCD to parse
2284 * Check here that the packets are in the right place on the ring.
2286 wifi_seq
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
2287 WARN_ONCE(txq
->ampdu
&&
2288 (wifi_seq
& 0xff) != q
->write_ptr
,
2289 "Q: %d WiFi Seq %d tfdNum %d",
2290 txq_id
, wifi_seq
, q
->write_ptr
);
2292 /* Set up driver data for this TFD */
2293 txq
->entries
[q
->write_ptr
].skb
= skb
;
2294 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
2296 dev_cmd
->hdr
.sequence
=
2297 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
2298 INDEX_TO_SEQ(q
->write_ptr
)));
2300 tb0_phys
= iwl_pcie_get_first_tb_dma(txq
, q
->write_ptr
);
2301 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
2302 offsetof(struct iwl_tx_cmd
, scratch
);
2304 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
2305 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
2307 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2308 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
2309 out_meta
->flags
= 0;
2312 * The second TB (tb1) points to the remainder of the TX command
2313 * and the 802.11 header - dword aligned size
2314 * (This calculation modifies the TX command, so do it before the
2315 * setup of the first TB)
2317 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
2318 hdr_len
- IWL_FIRST_TB_SIZE
;
2319 /* do not align A-MSDU to dword as the subframe header aligns it */
2320 amsdu
= ieee80211_is_data_qos(fc
) &&
2321 (*ieee80211_get_qos_ctl(hdr
) &
2322 IEEE80211_QOS_CTL_A_MSDU_PRESENT
);
2323 if (trans_pcie
->sw_csum_tx
|| !amsdu
) {
2324 tb1_len
= ALIGN(len
, 4);
2325 /* Tell NIC about any 2-byte padding after MAC header */
2327 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
2332 /* The first TB points to bi-directional DMA data */
2333 memcpy(&txq
->first_tb_bufs
[q
->write_ptr
], &dev_cmd
->hdr
,
2335 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
2336 IWL_FIRST_TB_SIZE
, true);
2338 /* there must be data left over for TB1 or this code must be changed */
2339 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_FIRST_TB_SIZE
);
2341 /* map the data for TB1 */
2342 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_FIRST_TB_SIZE
;
2343 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
2344 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
2346 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, false);
2349 if (unlikely(iwl_fill_data_tbs_amsdu(trans
, skb
, txq
, hdr_len
,
2353 } else if (unlikely(iwl_fill_data_tbs(trans
, skb
, txq
, hdr_len
,
2354 out_meta
, dev_cmd
, tb1_len
))) {
2358 /* Set up entry for this TFD in Tx byte-count array */
2359 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
2361 wait_write_ptr
= ieee80211_has_morefrags(fc
);
2363 /* start timer if queue currently empty */
2364 if (q
->read_ptr
== q
->write_ptr
) {
2365 if (txq
->wd_timeout
) {
2367 * If the TXQ is active, then set the timer, if not,
2368 * set the timer in remainder so that the timer will
2369 * be armed with the right value when the station will
2373 mod_timer(&txq
->stuck_timer
,
2374 jiffies
+ txq
->wd_timeout
);
2376 txq
->frozen_expiry_remainder
= txq
->wd_timeout
;
2378 IWL_DEBUG_RPM(trans
, "Q: %d first tx - take ref\n", q
->id
);
2379 iwl_trans_ref(trans
);
2382 /* Tell device the write index *just past* this latest filled TFD */
2383 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
2384 if (!wait_write_ptr
)
2385 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
2388 * At this point the frame is "transmitted" successfully
2389 * and we will get a TX status notification eventually.
2391 spin_unlock(&txq
->lock
);
2394 spin_unlock(&txq
->lock
);