1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
48 #include "iwl-eeprom.h"
50 #include "iwl-helpers.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
75 const struct iwl3945_rate_info iwl3945_rates
[IWL_RATE_COUNT_3945
] = {
76 IWL_DECLARE_RATE_INFO(1, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
90 /* 1 = enable the iwl3945_disable_events() function */
91 #define IWL_EVT_DISABLE (0)
92 #define IWL_EVT_DISABLE_SIZE (1532/32)
95 * iwl3945_disable_events - Disable selected events in uCode event log
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
103 void iwl3945_disable_events(struct iwl_priv
*priv
)
106 u32 base
; /* SRAM address of event log header */
107 u32 disable_ptr
; /* SRAM address of event-disable bitmap array */
108 u32 array_size
; /* # of u32 entries in array */
109 u32 evt_disable
[IWL_EVT_DISABLE_SIZE
] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
159 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
160 if (!iwl3945_hw_valid_rtc_data_addr(base
)) {
161 IWL_ERR(priv
, "Invalid event log pointer 0x%08X\n", base
);
165 disable_ptr
= iwl_read_targ_mem(priv
, base
+ (4 * sizeof(u32
)));
166 array_size
= iwl_read_targ_mem(priv
, base
+ (5 * sizeof(u32
)));
168 if (IWL_EVT_DISABLE
&& (array_size
== IWL_EVT_DISABLE_SIZE
)) {
169 IWL_DEBUG_INFO(priv
, "Disabling selected uCode log events at 0x%x\n",
171 for (i
= 0; i
< IWL_EVT_DISABLE_SIZE
; i
++)
172 iwl_write_targ_mem(priv
,
173 disable_ptr
+ (i
* sizeof(u32
)),
177 IWL_DEBUG_INFO(priv
, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv
, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv
, " in SRAM at 0x%x, size %d u32s\n",
180 disable_ptr
, array_size
);
185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp
)
189 for (idx
= 0; idx
< IWL_RATE_COUNT_3945
; idx
++)
190 if (iwl3945_rates
[idx
].plcp
== plcp
)
195 #ifdef CONFIG_IWLWIFI_DEBUG
196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
198 static const char *iwl3945_get_tx_fail_reason(u32 status
)
200 switch (status
& TX_STATUS_MSK
) {
201 case TX_3945_STATUS_SUCCESS
:
203 TX_STATUS_ENTRY(SHORT_LIMIT
);
204 TX_STATUS_ENTRY(LONG_LIMIT
);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
206 TX_STATUS_ENTRY(MGMNT_ABORT
);
207 TX_STATUS_ENTRY(NEXT_FRAG
);
208 TX_STATUS_ENTRY(LIFE_EXPIRE
);
209 TX_STATUS_ENTRY(DEST_PS
);
210 TX_STATUS_ENTRY(ABORTED
);
211 TX_STATUS_ENTRY(BT_RETRY
);
212 TX_STATUS_ENTRY(STA_INVALID
);
213 TX_STATUS_ENTRY(FRAG_DROPPED
);
214 TX_STATUS_ENTRY(TID_DISABLE
);
215 TX_STATUS_ENTRY(FRAME_FLUSHED
);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
217 TX_STATUS_ENTRY(TX_LOCKED
);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
224 static inline const char *iwl3945_get_tx_fail_reason(u32 status
)
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
235 int iwl3945_rs_next_rate(struct iwl_priv
*priv
, int rate
)
237 int next_rate
= iwl3945_get_prev_ieee_rate(rate
);
239 switch (priv
->band
) {
240 case IEEE80211_BAND_5GHZ
:
241 if (rate
== IWL_RATE_12M_INDEX
)
242 next_rate
= IWL_RATE_9M_INDEX
;
243 else if (rate
== IWL_RATE_6M_INDEX
)
244 next_rate
= IWL_RATE_6M_INDEX
;
246 case IEEE80211_BAND_2GHZ
:
247 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
248 iwl_is_associated(priv
)) {
249 if (rate
== IWL_RATE_11M_INDEX
)
250 next_rate
= IWL_RATE_5M_INDEX
;
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
269 static void iwl3945_tx_queue_reclaim(struct iwl_priv
*priv
,
270 int txq_id
, int index
)
272 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
273 struct iwl_queue
*q
= &txq
->q
;
274 struct iwl_tx_info
*tx_info
;
276 BUG_ON(txq_id
== IWL_CMD_QUEUE_NUM
);
278 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
279 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
281 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
282 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
283 tx_info
->skb
[0] = NULL
;
284 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
287 if (iwl_queue_space(q
) > q
->low_mark
&& (txq_id
>= 0) &&
288 (txq_id
!= IWL_CMD_QUEUE_NUM
) &&
289 priv
->mac80211_registered
)
290 iwl_wake_queue(priv
, txq_id
);
294 * iwl3945_rx_reply_tx - Handle Tx response
296 static void iwl3945_rx_reply_tx(struct iwl_priv
*priv
,
297 struct iwl_rx_mem_buffer
*rxb
)
299 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
300 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
301 int txq_id
= SEQ_TO_QUEUE(sequence
);
302 int index
= SEQ_TO_INDEX(sequence
);
303 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
304 struct ieee80211_tx_info
*info
;
305 struct iwl3945_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
306 u32 status
= le32_to_cpu(tx_resp
->status
);
310 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
311 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
312 "is out of range [0-%d] %d %d\n", txq_id
,
313 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
318 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
319 ieee80211_tx_info_clear_status(info
);
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx
= iwl3945_hwrate_to_plcp_idx(tx_resp
->rate
);
323 if (info
->band
== IEEE80211_BAND_5GHZ
)
324 rate_idx
-= IWL_FIRST_OFDM_RATE
;
326 fail
= tx_resp
->failure_frame
;
328 info
->status
.rates
[0].idx
= rate_idx
;
329 info
->status
.rates
[0].count
= fail
+ 1; /* add final attempt */
331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
332 info
->flags
|= ((status
& TX_STATUS_MSK
) == TX_STATUS_SUCCESS
) ?
333 IEEE80211_TX_STAT_ACK
: 0;
335 IWL_DEBUG_TX(priv
, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
336 txq_id
, iwl3945_get_tx_fail_reason(status
), status
,
337 tx_resp
->rate
, tx_resp
->failure_frame
);
339 IWL_DEBUG_TX_REPLY(priv
, "Tx queue reclaim %d\n", index
);
340 iwl3945_tx_queue_reclaim(priv
, txq_id
, index
);
342 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
343 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
348 /*****************************************************************************
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
352 * RX handler implementations
354 *****************************************************************************/
355 #ifdef CONFIG_IWLWIFI_DEBUGFS
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
361 static void iwl3945_accumulative_statistics(struct iwl_priv
*priv
,
367 u32
*delta
, *max_delta
;
369 prev_stats
= (__le32
*)&priv
->_3945
.statistics
;
370 accum_stats
= (u32
*)&priv
->_3945
.accum_statistics
;
371 delta
= (u32
*)&priv
->_3945
.delta_statistics
;
372 max_delta
= (u32
*)&priv
->_3945
.max_delta
;
374 for (i
= sizeof(__le32
); i
< sizeof(struct iwl3945_notif_statistics
);
375 i
+= sizeof(__le32
), stats
++, prev_stats
++, delta
++,
376 max_delta
++, accum_stats
++) {
377 if (le32_to_cpu(*stats
) > le32_to_cpu(*prev_stats
)) {
378 *delta
= (le32_to_cpu(*stats
) -
379 le32_to_cpu(*prev_stats
));
380 *accum_stats
+= *delta
;
381 if (*delta
> *max_delta
)
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv
->_3945
.accum_statistics
.general
.temperature
=
388 priv
->_3945
.statistics
.general
.temperature
;
389 priv
->_3945
.accum_statistics
.general
.ttl_timestamp
=
390 priv
->_3945
.statistics
.general
.ttl_timestamp
;
395 * iwl3945_good_plcp_health - checks for plcp error.
397 * When the plcp error is exceeding the thresholds, reset the radio
398 * to improve the throughput.
400 static bool iwl3945_good_plcp_health(struct iwl_priv
*priv
,
401 struct iwl_rx_packet
*pkt
)
404 struct iwl3945_notif_statistics current_stat
;
405 int combined_plcp_delta
;
406 unsigned int plcp_msec
;
407 unsigned long plcp_received_jiffies
;
409 memcpy(¤t_stat
, pkt
->u
.raw
, sizeof(struct
410 iwl3945_notif_statistics
));
412 * check for plcp_err and trigger radio reset if it exceeds
413 * the plcp error threshold plcp_delta.
415 plcp_received_jiffies
= jiffies
;
416 plcp_msec
= jiffies_to_msecs((long) plcp_received_jiffies
-
417 (long) priv
->plcp_jiffies
);
418 priv
->plcp_jiffies
= plcp_received_jiffies
;
420 * check to make sure plcp_msec is not 0 to prevent division
424 combined_plcp_delta
=
425 (le32_to_cpu(current_stat
.rx
.ofdm
.plcp_err
) -
426 le32_to_cpu(priv
->_3945
.statistics
.rx
.ofdm
.plcp_err
));
428 if ((combined_plcp_delta
> 0) &&
429 ((combined_plcp_delta
* 100) / plcp_msec
) >
430 priv
->cfg
->plcp_delta_threshold
) {
432 * if plcp_err exceed the threshold, the following
433 * data is printed in csv format:
434 * Text: plcp_err exceeded %d,
435 * Received ofdm.plcp_err,
436 * Current ofdm.plcp_err,
437 * combined_plcp_delta,
440 IWL_DEBUG_RADIO(priv
, "plcp_err exceeded %u, "
441 "%u, %d, %u mSecs\n",
442 priv
->cfg
->plcp_delta_threshold
,
443 le32_to_cpu(current_stat
.rx
.ofdm
.plcp_err
),
444 combined_plcp_delta
, plcp_msec
);
446 * Reset the RF radio due to the high plcp
455 void iwl3945_hw_rx_statistics(struct iwl_priv
*priv
,
456 struct iwl_rx_mem_buffer
*rxb
)
458 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
460 IWL_DEBUG_RX(priv
, "Statistics notification received (%d vs %d).\n",
461 (int)sizeof(struct iwl3945_notif_statistics
),
462 le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
);
463 #ifdef CONFIG_IWLWIFI_DEBUGFS
464 iwl3945_accumulative_statistics(priv
, (__le32
*)&pkt
->u
.raw
);
466 iwl_recover_from_statistics(priv
, pkt
);
468 memcpy(&priv
->_3945
.statistics
, pkt
->u
.raw
, sizeof(priv
->_3945
.statistics
));
471 void iwl3945_reply_statistics(struct iwl_priv
*priv
,
472 struct iwl_rx_mem_buffer
*rxb
)
474 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
475 __le32
*flag
= (__le32
*)&pkt
->u
.raw
;
477 if (le32_to_cpu(*flag
) & UCODE_STATISTICS_CLEAR_MSK
) {
478 #ifdef CONFIG_IWLWIFI_DEBUGFS
479 memset(&priv
->_3945
.accum_statistics
, 0,
480 sizeof(struct iwl3945_notif_statistics
));
481 memset(&priv
->_3945
.delta_statistics
, 0,
482 sizeof(struct iwl3945_notif_statistics
));
483 memset(&priv
->_3945
.max_delta
, 0,
484 sizeof(struct iwl3945_notif_statistics
));
486 IWL_DEBUG_RX(priv
, "Statistics have been cleared\n");
488 iwl3945_hw_rx_statistics(priv
, rxb
);
492 /******************************************************************************
494 * Misc. internal state and helper functions
496 ******************************************************************************/
498 /* This is necessary only for a number of statistics, see the caller. */
499 static int iwl3945_is_network_packet(struct iwl_priv
*priv
,
500 struct ieee80211_hdr
*header
)
502 /* Filter incoming packets to determine if they are targeted toward
503 * this network, discarding packets coming from ourselves */
504 switch (priv
->iw_mode
) {
505 case NL80211_IFTYPE_ADHOC
: /* Header: Dest. | Source | BSSID */
506 /* packets to our IBSS update information */
507 return !compare_ether_addr(header
->addr3
, priv
->bssid
);
508 case NL80211_IFTYPE_STATION
: /* Header: Dest. | AP{BSSID} | Source */
509 /* packets to our IBSS update information */
510 return !compare_ether_addr(header
->addr2
, priv
->bssid
);
516 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv
*priv
,
517 struct iwl_rx_mem_buffer
*rxb
,
518 struct ieee80211_rx_status
*stats
)
520 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
521 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
522 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
523 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
524 u16 len
= le16_to_cpu(rx_hdr
->len
);
526 __le16 fc
= hdr
->frame_control
;
528 /* We received data from the HW, so stop the watchdog */
529 if (unlikely(len
+ IWL39_RX_FRAME_SIZE
>
530 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
)) {
531 IWL_DEBUG_DROP(priv
, "Corruption detected!\n");
535 /* We only process data packets if the interface is open */
536 if (unlikely(!priv
->is_open
)) {
537 IWL_DEBUG_DROP_LIMIT(priv
,
538 "Dropping packet while interface is not open.\n");
542 skb
= dev_alloc_skb(128);
544 IWL_ERR(priv
, "dev_alloc_skb failed\n");
548 if (!iwl3945_mod_params
.sw_crypto
)
549 iwl_set_decrypted_flag(priv
,
550 (struct ieee80211_hdr
*)rxb_addr(rxb
),
551 le32_to_cpu(rx_end
->status
), stats
);
553 skb_add_rx_frag(skb
, 0, rxb
->page
,
554 (void *)rx_hdr
->payload
- (void *)pkt
, len
);
556 iwl_update_stats(priv
, false, fc
, len
);
557 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
559 ieee80211_rx(priv
->hw
, skb
);
560 priv
->alloc_rxb_page
--;
564 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
566 static void iwl3945_rx_reply_rx(struct iwl_priv
*priv
,
567 struct iwl_rx_mem_buffer
*rxb
)
569 struct ieee80211_hdr
*header
;
570 struct ieee80211_rx_status rx_status
;
571 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
572 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
573 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
574 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
575 u16 rx_stats_sig_avg __maybe_unused
= le16_to_cpu(rx_stats
->sig_avg
);
576 u16 rx_stats_noise_diff __maybe_unused
= le16_to_cpu(rx_stats
->noise_diff
);
580 rx_status
.mactime
= le64_to_cpu(rx_end
->timestamp
);
582 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr
->channel
));
583 rx_status
.band
= (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
584 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
586 rx_status
.rate_idx
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
587 if (rx_status
.band
== IEEE80211_BAND_5GHZ
)
588 rx_status
.rate_idx
-= IWL_FIRST_OFDM_RATE
;
590 rx_status
.antenna
= (le16_to_cpu(rx_hdr
->phy_flags
) &
591 RX_RES_PHY_FLAGS_ANTENNA_MSK
) >> 4;
593 /* set the preamble flag if appropriate */
594 if (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
595 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
597 if ((unlikely(rx_stats
->phy_count
> 20))) {
598 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
599 rx_stats
->phy_count
);
603 if (!(rx_end
->status
& RX_RES_STATUS_NO_CRC32_ERROR
)
604 || !(rx_end
->status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
605 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n", rx_end
->status
);
611 /* Convert 3945's rssi indicator to dBm */
612 rx_status
.signal
= rx_stats
->rssi
- IWL39_RSSI_OFFSET
;
614 IWL_DEBUG_STATS(priv
, "Rssi %d sig_avg %d noise_diff %d\n",
615 rx_status
.signal
, rx_stats_sig_avg
,
616 rx_stats_noise_diff
);
618 header
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
620 network_packet
= iwl3945_is_network_packet(priv
, header
);
622 IWL_DEBUG_STATS_LIMIT(priv
, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
623 network_packet
? '*' : ' ',
624 le16_to_cpu(rx_hdr
->channel
),
625 rx_status
.signal
, rx_status
.signal
,
628 iwl_dbg_log_rx_data_frame(priv
, le16_to_cpu(rx_hdr
->len
), header
);
630 if (network_packet
) {
631 priv
->_3945
.last_beacon_time
=
632 le32_to_cpu(rx_end
->beacon_timestamp
);
633 priv
->_3945
.last_tsf
= le64_to_cpu(rx_end
->timestamp
);
634 priv
->_3945
.last_rx_rssi
= rx_status
.signal
;
637 iwl3945_pass_packet_to_mac80211(priv
, rxb
, &rx_status
);
640 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
641 struct iwl_tx_queue
*txq
,
642 dma_addr_t addr
, u16 len
, u8 reset
, u8 pad
)
646 struct iwl3945_tfd
*tfd
, *tfd_tmp
;
649 tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
650 tfd
= &tfd_tmp
[q
->write_ptr
];
653 memset(tfd
, 0, sizeof(*tfd
));
655 count
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
657 if ((count
>= NUM_TFD_CHUNKS
) || (count
< 0)) {
658 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
663 tfd
->tbs
[count
].addr
= cpu_to_le32(addr
);
664 tfd
->tbs
[count
].len
= cpu_to_le32(len
);
668 tfd
->control_flags
= cpu_to_le32(TFD_CTL_COUNT_SET(count
) |
669 TFD_CTL_PAD_SET(pad
));
675 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
677 * Does NOT advance any indexes
679 void iwl3945_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
681 struct iwl3945_tfd
*tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
682 int index
= txq
->q
.read_ptr
;
683 struct iwl3945_tfd
*tfd
= &tfd_tmp
[index
];
684 struct pci_dev
*dev
= priv
->pci_dev
;
689 counter
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
690 if (counter
> NUM_TFD_CHUNKS
) {
691 IWL_ERR(priv
, "Too many chunks: %i\n", counter
);
692 /* @todo issue fatal error, it is quite serious situation */
698 pci_unmap_single(dev
,
699 dma_unmap_addr(&txq
->meta
[index
], mapping
),
700 dma_unmap_len(&txq
->meta
[index
], len
),
703 /* unmap chunks if any */
705 for (i
= 1; i
< counter
; i
++) {
706 pci_unmap_single(dev
, le32_to_cpu(tfd
->tbs
[i
].addr
),
707 le32_to_cpu(tfd
->tbs
[i
].len
), PCI_DMA_TODEVICE
);
708 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
709 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[0];
710 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
711 /* Can be called from interrupt context */
712 dev_kfree_skb_any(skb
);
713 txq
->txb
[txq
->q
.read_ptr
].skb
[0] = NULL
;
721 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
724 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv
*priv
,
725 struct iwl_device_cmd
*cmd
,
726 struct ieee80211_tx_info
*info
,
727 struct ieee80211_hdr
*hdr
,
728 int sta_id
, int tx_id
)
730 u16 hw_value
= ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
;
731 u16 rate_index
= min(hw_value
& 0xffff, IWL_RATE_COUNT_3945
);
737 __le16 fc
= hdr
->frame_control
;
738 struct iwl3945_tx_cmd
*tx_cmd
= (struct iwl3945_tx_cmd
*)cmd
->cmd
.payload
;
740 rate
= iwl3945_rates
[rate_index
].plcp
;
741 tx_flags
= tx_cmd
->tx_flags
;
743 /* We need to figure out how to get the sta->supp_rates while
744 * in this running context */
745 rate_mask
= IWL_RATES_MASK
;
748 /* Set retry limit on DATA packets and Probe Responses*/
749 if (ieee80211_is_probe_resp(fc
))
750 data_retry_limit
= 3;
752 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
753 tx_cmd
->data_retry_limit
= data_retry_limit
;
755 if (tx_id
>= IWL_CMD_QUEUE_NUM
)
760 if (data_retry_limit
< rts_retry_limit
)
761 rts_retry_limit
= data_retry_limit
;
762 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
764 if (ieee80211_is_mgmt(fc
)) {
765 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
766 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
767 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
768 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
769 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
770 if (tx_flags
& TX_CMD_FLG_RTS_MSK
) {
771 tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
772 tx_flags
|= TX_CMD_FLG_CTS_MSK
;
781 tx_cmd
->tx_flags
= tx_flags
;
784 tx_cmd
->supp_rates
[0] =
785 ((rate_mask
& IWL_OFDM_RATES_MASK
) >> IWL_FIRST_OFDM_RATE
) & 0xFF;
788 tx_cmd
->supp_rates
[1] = (rate_mask
& 0xF);
790 IWL_DEBUG_RATE(priv
, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
791 "cck/ofdm mask: 0x%x/0x%x\n", sta_id
,
792 tx_cmd
->rate
, le32_to_cpu(tx_cmd
->tx_flags
),
793 tx_cmd
->supp_rates
[1], tx_cmd
->supp_rates
[0]);
796 static u8
iwl3945_sync_sta(struct iwl_priv
*priv
, int sta_id
, u16 tx_rate
)
798 unsigned long flags_spin
;
799 struct iwl_station_entry
*station
;
801 if (sta_id
== IWL_INVALID_STATION
)
802 return IWL_INVALID_STATION
;
804 spin_lock_irqsave(&priv
->sta_lock
, flags_spin
);
805 station
= &priv
->stations
[sta_id
];
807 station
->sta
.sta
.modify_mask
= STA_MODIFY_TX_RATE_MSK
;
808 station
->sta
.rate_n_flags
= cpu_to_le16(tx_rate
);
809 station
->sta
.mode
= STA_CONTROL_MODIFY_MSK
;
810 iwl_send_add_sta(priv
, &station
->sta
, CMD_ASYNC
);
811 spin_unlock_irqrestore(&priv
->sta_lock
, flags_spin
);
813 IWL_DEBUG_RATE(priv
, "SCALE sync station %d to rate %d\n",
818 static int iwl3945_set_pwr_src(struct iwl_priv
*priv
, enum iwl_pwr_src src
)
820 if (src
== IWL_PWR_SRC_VAUX
) {
821 if (pci_pme_capable(priv
->pci_dev
, PCI_D3cold
)) {
822 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
823 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
824 ~APMG_PS_CTRL_MSK_PWR_SRC
);
826 iwl_poll_bit(priv
, CSR_GPIO_IN
,
827 CSR_GPIO_IN_VAL_VAUX_PWR_SRC
,
828 CSR_GPIO_IN_BIT_AUX_POWER
, 5000);
831 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
832 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
833 ~APMG_PS_CTRL_MSK_PWR_SRC
);
835 iwl_poll_bit(priv
, CSR_GPIO_IN
, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC
,
836 CSR_GPIO_IN_BIT_AUX_POWER
, 5000); /* uS */
842 static int iwl3945_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
844 iwl_write_direct32(priv
, FH39_RCSR_RBD_BASE(0), rxq
->dma_addr
);
845 iwl_write_direct32(priv
, FH39_RCSR_RPTR_ADDR(0), rxq
->rb_stts_dma
);
846 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), 0);
847 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0),
848 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE
|
849 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE
|
850 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN
|
851 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128
|
852 (RX_QUEUE_SIZE_LOG
<< FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE
) |
853 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST
|
854 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH
) |
855 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH
);
857 /* fake read to flush all prev I/O */
858 iwl_read_direct32(priv
, FH39_RSSR_CTRL
);
863 static int iwl3945_tx_reset(struct iwl_priv
*priv
)
867 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0x2);
870 iwl_write_prph(priv
, ALM_SCD_ARASTAT_REG
, 0x01);
872 /* all 6 fifo are active */
873 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0x3f);
875 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_1_REG
, 0x010000);
876 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_2_REG
, 0x030002);
877 iwl_write_prph(priv
, ALM_SCD_TXF4MF_REG
, 0x000004);
878 iwl_write_prph(priv
, ALM_SCD_TXF5MF_REG
, 0x000005);
880 iwl_write_direct32(priv
, FH39_TSSR_CBB_BASE
,
881 priv
->_3945
.shared_phys
);
883 iwl_write_direct32(priv
, FH39_TSSR_MSG_CONFIG
,
884 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON
|
885 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON
|
886 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B
|
887 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON
|
888 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON
|
889 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH
|
890 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH
);
897 * iwl3945_txq_ctx_reset - Reset TX queue context
899 * Destroys all DMA structures and initialize them again
901 static int iwl3945_txq_ctx_reset(struct iwl_priv
*priv
)
904 int txq_id
, slots_num
;
906 iwl3945_hw_txq_ctx_free(priv
);
908 /* allocate tx queue structure */
909 rc
= iwl_alloc_txq_mem(priv
);
914 rc
= iwl3945_tx_reset(priv
);
919 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
920 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
921 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
922 rc
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
925 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
933 iwl3945_hw_txq_ctx_free(priv
);
939 * Start up 3945's basic functionality after it has been reset
940 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
941 * NOTE: This does not load uCode nor start the embedded processor
943 static int iwl3945_apm_init(struct iwl_priv
*priv
)
945 int ret
= iwl_apm_init(priv
);
947 /* Clear APMG (NIC's internal power management) interrupts */
948 iwl_write_prph(priv
, APMG_RTC_INT_MSK_REG
, 0x0);
949 iwl_write_prph(priv
, APMG_RTC_INT_STT_REG
, 0xFFFFFFFF);
951 /* Reset radio chip */
952 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
954 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
959 static void iwl3945_nic_config(struct iwl_priv
*priv
)
961 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
965 spin_lock_irqsave(&priv
->lock
, flags
);
967 /* Determine HW type */
968 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &rev_id
);
970 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", rev_id
);
972 if (rev_id
& PCI_CFG_REV_ID_BIT_RTP
)
973 IWL_DEBUG_INFO(priv
, "RTP type\n");
974 else if (rev_id
& PCI_CFG_REV_ID_BIT_BASIC_SKU
) {
975 IWL_DEBUG_INFO(priv
, "3945 RADIO-MB type\n");
976 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
977 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB
);
979 IWL_DEBUG_INFO(priv
, "3945 RADIO-MM type\n");
980 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
981 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM
);
984 if (EEPROM_SKU_CAP_OP_MODE_MRC
== eeprom
->sku_cap
) {
985 IWL_DEBUG_INFO(priv
, "SKU OP mode is mrc\n");
986 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
987 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC
);
989 IWL_DEBUG_INFO(priv
, "SKU OP mode is basic\n");
991 if ((eeprom
->board_revision
& 0xF0) == 0xD0) {
992 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
993 eeprom
->board_revision
);
994 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
995 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
997 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
998 eeprom
->board_revision
);
999 iwl_clear_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1000 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1003 if (eeprom
->almgor_m_version
<= 1) {
1004 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1005 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A
);
1006 IWL_DEBUG_INFO(priv
, "Card M type A version is 0x%X\n",
1007 eeprom
->almgor_m_version
);
1009 IWL_DEBUG_INFO(priv
, "Card M type B version is 0x%X\n",
1010 eeprom
->almgor_m_version
);
1011 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1012 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B
);
1014 spin_unlock_irqrestore(&priv
->lock
, flags
);
1016 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_SW_RF_KILL_ENABLE
)
1017 IWL_DEBUG_RF_KILL(priv
, "SW RF KILL supported in EEPROM.\n");
1019 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_HW_RF_KILL_ENABLE
)
1020 IWL_DEBUG_RF_KILL(priv
, "HW RF KILL supported in EEPROM.\n");
1023 int iwl3945_hw_nic_init(struct iwl_priv
*priv
)
1026 unsigned long flags
;
1027 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
1029 spin_lock_irqsave(&priv
->lock
, flags
);
1030 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
1031 spin_unlock_irqrestore(&priv
->lock
, flags
);
1033 rc
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
1037 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
1039 /* Allocate the RX queue, or reset if it is already allocated */
1041 rc
= iwl_rx_queue_alloc(priv
);
1043 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
1047 iwl3945_rx_queue_reset(priv
, rxq
);
1049 iwl3945_rx_replenish(priv
);
1051 iwl3945_rx_init(priv
, rxq
);
1054 /* Look at using this instead:
1055 rxq->need_update = 1;
1056 iwl_rx_queue_update_write_ptr(priv, rxq);
1059 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), rxq
->write
& ~7);
1061 rc
= iwl3945_txq_ctx_reset(priv
);
1065 set_bit(STATUS_INIT
, &priv
->status
);
1071 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1073 * Destroy all TX DMA queues and structures
1075 void iwl3945_hw_txq_ctx_free(struct iwl_priv
*priv
)
1081 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
;
1083 if (txq_id
== IWL_CMD_QUEUE_NUM
)
1084 iwl_cmd_queue_free(priv
);
1086 iwl_tx_queue_free(priv
, txq_id
);
1088 /* free tx queue structure */
1089 iwl_free_txq_mem(priv
);
1092 void iwl3945_hw_txq_ctx_stop(struct iwl_priv
*priv
)
1097 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0);
1098 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0);
1100 /* reset TFD queues */
1101 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
1102 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
), 0x0);
1103 iwl_poll_direct_bit(priv
, FH39_TSSR_TX_STATUS
,
1104 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id
),
1108 iwl3945_hw_txq_ctx_free(priv
);
1112 * iwl3945_hw_reg_adjust_power_by_temp
1113 * return index delta into power gain settings table
1115 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading
, int old_reading
)
1117 return (new_reading
- old_reading
) * (-11) / 100;
1121 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1123 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature
)
1125 return ((temperature
< -260) || (temperature
> 25)) ? 1 : 0;
1128 int iwl3945_hw_get_temperature(struct iwl_priv
*priv
)
1130 return iwl_read32(priv
, CSR_UCODE_DRV_GP2
);
1134 * iwl3945_hw_reg_txpower_get_temperature
1135 * get the current temperature by reading from NIC
1137 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv
*priv
)
1139 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1142 temperature
= iwl3945_hw_get_temperature(priv
);
1144 /* driver's okay range is -260 to +25.
1145 * human readable okay range is 0 to +285 */
1146 IWL_DEBUG_INFO(priv
, "Temperature: %d\n", temperature
+ IWL_TEMP_CONVERT
);
1148 /* handle insane temp reading */
1149 if (iwl3945_hw_reg_temp_out_of_range(temperature
)) {
1150 IWL_ERR(priv
, "Error bad temperature value %d\n", temperature
);
1152 /* if really really hot(?),
1153 * substitute the 3rd band/group's temp measured at factory */
1154 if (priv
->last_temperature
> 100)
1155 temperature
= eeprom
->groups
[2].temperature
;
1156 else /* else use most recent "sane" value from driver */
1157 temperature
= priv
->last_temperature
;
1160 return temperature
; /* raw, not "human readable" */
1163 /* Adjust Txpower only if temperature variance is greater than threshold.
1165 * Both are lower than older versions' 9 degrees */
1166 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1169 * is_temp_calib_needed - determines if new calibration is needed
1171 * records new temperature in tx_mgr->temperature.
1172 * replaces tx_mgr->last_temperature *only* if calib needed
1173 * (assumes caller will actually do the calibration!). */
1174 static int is_temp_calib_needed(struct iwl_priv
*priv
)
1178 priv
->temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
1179 temp_diff
= priv
->temperature
- priv
->last_temperature
;
1181 /* get absolute value */
1182 if (temp_diff
< 0) {
1183 IWL_DEBUG_POWER(priv
, "Getting cooler, delta %d,\n", temp_diff
);
1184 temp_diff
= -temp_diff
;
1185 } else if (temp_diff
== 0)
1186 IWL_DEBUG_POWER(priv
, "Same temp,\n");
1188 IWL_DEBUG_POWER(priv
, "Getting warmer, delta %d,\n", temp_diff
);
1190 /* if we don't need calibration, *don't* update last_temperature */
1191 if (temp_diff
< IWL_TEMPERATURE_LIMIT_TIMER
) {
1192 IWL_DEBUG_POWER(priv
, "Timed thermal calib not needed\n");
1196 IWL_DEBUG_POWER(priv
, "Timed thermal calib needed\n");
1198 /* assume that caller will actually do calib ...
1199 * update the "last temperature" value */
1200 priv
->last_temperature
= priv
->temperature
;
1204 #define IWL_MAX_GAIN_ENTRIES 78
1205 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1206 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1208 /* radio and DSP power table, each step is 1/2 dB.
1209 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1210 static struct iwl3945_tx_power power_gain_table
[2][IWL_MAX_GAIN_ENTRIES
] = {
1212 {251, 127}, /* 2.4 GHz, highest power */
1289 {3, 95} }, /* 2.4 GHz, lowest power */
1291 {251, 127}, /* 5.x GHz, highest power */
1368 {3, 120} } /* 5.x GHz, lowest power */
1371 static inline u8
iwl3945_hw_reg_fix_power_index(int index
)
1375 if (index
>= IWL_MAX_GAIN_ENTRIES
)
1376 return IWL_MAX_GAIN_ENTRIES
- 1;
1380 /* Kick off thermal recalibration check every 60 seconds */
1381 #define REG_RECALIB_PERIOD (60)
1384 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1386 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1387 * or 6 Mbit (OFDM) rates.
1389 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv
*priv
, u32 scan_tbl_index
,
1390 s32 rate_index
, const s8
*clip_pwrs
,
1391 struct iwl_channel_info
*ch_info
,
1394 struct iwl3945_scan_power_info
*scan_power_info
;
1398 scan_power_info
= &ch_info
->scan_pwr_info
[scan_tbl_index
];
1400 /* use this channel group's 6Mbit clipping/saturation pwr,
1401 * but cap at regulatory scan power restriction (set during init
1402 * based on eeprom channel data) for this channel. */
1403 power
= min(ch_info
->scan_power
, clip_pwrs
[IWL_RATE_6M_INDEX_TABLE
]);
1405 /* further limit to user's max power preference.
1406 * FIXME: Other spectrum management power limitations do not
1407 * seem to apply?? */
1408 power
= min(power
, priv
->tx_power_user_lmt
);
1409 scan_power_info
->requested_power
= power
;
1411 /* find difference between new scan *power* and current "normal"
1412 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1413 * current "normal" temperature-compensated Tx power *index* for
1414 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1416 power_index
= ch_info
->power_info
[rate_index
].power_table_index
1417 - (power
- ch_info
->power_info
1418 [IWL_RATE_6M_INDEX_TABLE
].requested_power
) * 2;
1420 /* store reference index that we use when adjusting *all* scan
1421 * powers. So we can accommodate user (all channel) or spectrum
1422 * management (single channel) power changes "between" temperature
1423 * feedback compensation procedures.
1424 * don't force fit this reference index into gain table; it may be a
1425 * negative number. This will help avoid errors when we're at
1426 * the lower bounds (highest gains, for warmest temperatures)
1429 /* don't exceed table bounds for "real" setting */
1430 power_index
= iwl3945_hw_reg_fix_power_index(power_index
);
1432 scan_power_info
->power_table_index
= power_index
;
1433 scan_power_info
->tpc
.tx_gain
=
1434 power_gain_table
[band_index
][power_index
].tx_gain
;
1435 scan_power_info
->tpc
.dsp_atten
=
1436 power_gain_table
[band_index
][power_index
].dsp_atten
;
1440 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1442 * Configures power settings for all rates for the current channel,
1443 * using values from channel info struct, and send to NIC
1445 static int iwl3945_send_tx_power(struct iwl_priv
*priv
)
1448 const struct iwl_channel_info
*ch_info
= NULL
;
1449 struct iwl3945_txpowertable_cmd txpower
= {
1450 .channel
= priv
->active_rxon
.channel
,
1453 txpower
.band
= (priv
->band
== IEEE80211_BAND_5GHZ
) ? 0 : 1;
1454 ch_info
= iwl_get_channel_info(priv
,
1456 le16_to_cpu(priv
->active_rxon
.channel
));
1459 "Failed to get channel info for channel %d [%d]\n",
1460 le16_to_cpu(priv
->active_rxon
.channel
), priv
->band
);
1464 if (!is_channel_valid(ch_info
)) {
1465 IWL_DEBUG_POWER(priv
, "Not calling TX_PWR_TABLE_CMD on "
1466 "non-Tx channel.\n");
1470 /* fill cmd with power settings for all rates for current channel */
1471 /* Fill OFDM rate */
1472 for (rate_idx
= IWL_FIRST_OFDM_RATE
, i
= 0;
1473 rate_idx
<= IWL39_LAST_OFDM_RATE
; rate_idx
++, i
++) {
1475 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1476 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1478 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1479 le16_to_cpu(txpower
.channel
),
1481 txpower
.power
[i
].tpc
.tx_gain
,
1482 txpower
.power
[i
].tpc
.dsp_atten
,
1483 txpower
.power
[i
].rate
);
1485 /* Fill CCK rates */
1486 for (rate_idx
= IWL_FIRST_CCK_RATE
;
1487 rate_idx
<= IWL_LAST_CCK_RATE
; rate_idx
++, i
++) {
1488 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1489 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1491 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1492 le16_to_cpu(txpower
.channel
),
1494 txpower
.power
[i
].tpc
.tx_gain
,
1495 txpower
.power
[i
].tpc
.dsp_atten
,
1496 txpower
.power
[i
].rate
);
1499 return iwl_send_cmd_pdu(priv
, REPLY_TX_PWR_TABLE_CMD
,
1500 sizeof(struct iwl3945_txpowertable_cmd
),
1506 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1507 * @ch_info: Channel to update. Uses power_info.requested_power.
1509 * Replace requested_power and base_power_index ch_info fields for
1512 * Called if user or spectrum management changes power preferences.
1513 * Takes into account h/w and modulation limitations (clip power).
1515 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1517 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1518 * properly fill out the scan powers, and actual h/w gain settings,
1519 * and send changes to NIC
1521 static int iwl3945_hw_reg_set_new_power(struct iwl_priv
*priv
,
1522 struct iwl_channel_info
*ch_info
)
1524 struct iwl3945_channel_power_info
*power_info
;
1525 int power_changed
= 0;
1527 const s8
*clip_pwrs
;
1530 /* Get this chnlgrp's rate-to-max/clip-powers table */
1531 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1533 /* Get this channel's rate-to-current-power settings table */
1534 power_info
= ch_info
->power_info
;
1536 /* update OFDM Txpower settings */
1537 for (i
= IWL_RATE_6M_INDEX_TABLE
; i
<= IWL_RATE_54M_INDEX_TABLE
;
1538 i
++, ++power_info
) {
1541 /* limit new power to be no more than h/w capability */
1542 power
= min(ch_info
->curr_txpow
, clip_pwrs
[i
]);
1543 if (power
== power_info
->requested_power
)
1546 /* find difference between old and new requested powers,
1547 * update base (non-temp-compensated) power index */
1548 delta_idx
= (power
- power_info
->requested_power
) * 2;
1549 power_info
->base_power_index
-= delta_idx
;
1551 /* save new requested power value */
1552 power_info
->requested_power
= power
;
1557 /* update CCK Txpower settings, based on OFDM 12M setting ...
1558 * ... all CCK power settings for a given channel are the *same*. */
1559 if (power_changed
) {
1561 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1562 requested_power
+ IWL_CCK_FROM_OFDM_POWER_DIFF
;
1564 /* do all CCK rates' iwl3945_channel_power_info structures */
1565 for (i
= IWL_RATE_1M_INDEX_TABLE
; i
<= IWL_RATE_11M_INDEX_TABLE
; i
++) {
1566 power_info
->requested_power
= power
;
1567 power_info
->base_power_index
=
1568 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1569 base_power_index
+ IWL_CCK_FROM_OFDM_INDEX_DIFF
;
1578 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1580 * NOTE: Returned power limit may be less (but not more) than requested,
1581 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1582 * (no consideration for h/w clipping limitations).
1584 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info
*ch_info
)
1589 /* if we're using TGd limits, use lower of TGd or EEPROM */
1590 if (ch_info
->tgd_data
.max_power
!= 0)
1591 max_power
= min(ch_info
->tgd_data
.max_power
,
1592 ch_info
->eeprom
.max_power_avg
);
1594 /* else just use EEPROM limits */
1597 max_power
= ch_info
->eeprom
.max_power_avg
;
1599 return min(max_power
, ch_info
->max_power_avg
);
1603 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1605 * Compensate txpower settings of *all* channels for temperature.
1606 * This only accounts for the difference between current temperature
1607 * and the factory calibration temperatures, and bases the new settings
1608 * on the channel's base_power_index.
1610 * If RxOn is "associated", this sends the new Txpower to NIC!
1612 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv
*priv
)
1614 struct iwl_channel_info
*ch_info
= NULL
;
1615 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1617 const s8
*clip_pwrs
; /* array of h/w max power levels for each rate */
1623 int temperature
= priv
->temperature
;
1625 if (priv
->disable_tx_power_cal
||
1626 test_bit(STATUS_SCANNING
, &priv
->status
)) {
1627 /* do not perform tx power calibration */
1630 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1631 for (i
= 0; i
< priv
->channel_count
; i
++) {
1632 ch_info
= &priv
->channel_info
[i
];
1633 a_band
= is_channel_a_band(ch_info
);
1635 /* Get this chnlgrp's factory calibration temperature */
1636 ref_temp
= (s16
)eeprom
->groups
[ch_info
->group_index
].
1639 /* get power index adjustment based on current and factory
1641 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
1644 /* set tx power value for all rates, OFDM and CCK */
1645 for (rate_index
= 0; rate_index
< IWL_RATE_COUNT
;
1648 ch_info
->power_info
[rate_index
].base_power_index
;
1650 /* temperature compensate */
1651 power_idx
+= delta_index
;
1653 /* stay within table range */
1654 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
1655 ch_info
->power_info
[rate_index
].
1656 power_table_index
= (u8
) power_idx
;
1657 ch_info
->power_info
[rate_index
].tpc
=
1658 power_gain_table
[a_band
][power_idx
];
1661 /* Get this chnlgrp's rate-to-max/clip-powers table */
1662 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1664 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1665 for (scan_tbl_index
= 0;
1666 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
1667 s32 actual_index
= (scan_tbl_index
== 0) ?
1668 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
1669 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
1670 actual_index
, clip_pwrs
,
1675 /* send Txpower command for current channel to ucode */
1676 return priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1679 int iwl3945_hw_reg_set_txpower(struct iwl_priv
*priv
, s8 power
)
1681 struct iwl_channel_info
*ch_info
;
1686 if (priv
->tx_power_user_lmt
== power
) {
1687 IWL_DEBUG_POWER(priv
, "Requested Tx power same as current "
1688 "limit: %ddBm.\n", power
);
1692 IWL_DEBUG_POWER(priv
, "Setting upper limit clamp to %ddBm.\n", power
);
1693 priv
->tx_power_user_lmt
= power
;
1695 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1697 for (i
= 0; i
< priv
->channel_count
; i
++) {
1698 ch_info
= &priv
->channel_info
[i
];
1699 a_band
= is_channel_a_band(ch_info
);
1701 /* find minimum power of all user and regulatory constraints
1702 * (does not consider h/w clipping limitations) */
1703 max_power
= iwl3945_hw_reg_get_ch_txpower_limit(ch_info
);
1704 max_power
= min(power
, max_power
);
1705 if (max_power
!= ch_info
->curr_txpow
) {
1706 ch_info
->curr_txpow
= max_power
;
1708 /* this considers the h/w clipping limitations */
1709 iwl3945_hw_reg_set_new_power(priv
, ch_info
);
1713 /* update txpower settings for all channels,
1714 * send to NIC if associated. */
1715 is_temp_calib_needed(priv
);
1716 iwl3945_hw_reg_comp_txpower_temp(priv
);
1721 static int iwl3945_send_rxon_assoc(struct iwl_priv
*priv
)
1724 struct iwl_rx_packet
*pkt
;
1725 struct iwl3945_rxon_assoc_cmd rxon_assoc
;
1726 struct iwl_host_cmd cmd
= {
1727 .id
= REPLY_RXON_ASSOC
,
1728 .len
= sizeof(rxon_assoc
),
1729 .flags
= CMD_WANT_SKB
,
1730 .data
= &rxon_assoc
,
1732 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1733 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1735 if ((rxon1
->flags
== rxon2
->flags
) &&
1736 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1737 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1738 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1739 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1743 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1744 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1745 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1746 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1747 rxon_assoc
.reserved
= 0;
1749 rc
= iwl_send_cmd_sync(priv
, &cmd
);
1753 pkt
= (struct iwl_rx_packet
*)cmd
.reply_page
;
1754 if (pkt
->hdr
.flags
& IWL_CMD_FAILED_MSK
) {
1755 IWL_ERR(priv
, "Bad return from REPLY_RXON_ASSOC command\n");
1759 iwl_free_pages(priv
, cmd
.reply_page
);
1765 * iwl3945_commit_rxon - commit staging_rxon to hardware
1767 * The RXON command in staging_rxon is committed to the hardware and
1768 * the active_rxon structure is updated with the new data. This
1769 * function correctly transitions out of the RXON_ASSOC_MSK state if
1770 * a HW tune is required based on the RXON structure changes.
1772 static int iwl3945_commit_rxon(struct iwl_priv
*priv
)
1774 /* cast away the const for active_rxon in this function */
1775 struct iwl3945_rxon_cmd
*active_rxon
= (void *)&priv
->active_rxon
;
1776 struct iwl3945_rxon_cmd
*staging_rxon
= (void *)&priv
->staging_rxon
;
1779 !!(priv
->staging_rxon
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
1781 if (!iwl_is_alive(priv
))
1784 /* always get timestamp with Rx frame */
1785 staging_rxon
->flags
|= RXON_FLG_TSF2HOST_MSK
;
1787 /* select antenna */
1788 staging_rxon
->flags
&=
1789 ~(RXON_FLG_DIS_DIV_MSK
| RXON_FLG_ANT_SEL_MSK
);
1790 staging_rxon
->flags
|= iwl3945_get_antenna_flags(priv
);
1792 rc
= iwl_check_rxon_cmd(priv
);
1794 IWL_ERR(priv
, "Invalid RXON configuration. Not committing.\n");
1798 /* If we don't need to send a full RXON, we can use
1799 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1800 * and other flags for the current radio configuration. */
1801 if (!iwl_full_rxon_required(priv
)) {
1802 rc
= iwl_send_rxon_assoc(priv
);
1804 IWL_ERR(priv
, "Error setting RXON_ASSOC "
1805 "configuration (%d).\n", rc
);
1809 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1814 /* If we are currently associated and the new config requires
1815 * an RXON_ASSOC and the new config wants the associated mask enabled,
1816 * we must clear the associated from the active configuration
1817 * before we apply the new config */
1818 if (iwl_is_associated(priv
) && new_assoc
) {
1819 IWL_DEBUG_INFO(priv
, "Toggling associated bit on current RXON\n");
1820 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
1823 * reserved4 and 5 could have been filled by the iwlcore code.
1824 * Let's clear them before pushing to the 3945.
1826 active_rxon
->reserved4
= 0;
1827 active_rxon
->reserved5
= 0;
1828 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1829 sizeof(struct iwl3945_rxon_cmd
),
1830 &priv
->active_rxon
);
1832 /* If the mask clearing failed then we set
1833 * active_rxon back to what it was previously */
1835 active_rxon
->filter_flags
|= RXON_FILTER_ASSOC_MSK
;
1836 IWL_ERR(priv
, "Error clearing ASSOC_MSK on current "
1837 "configuration (%d).\n", rc
);
1840 iwl_clear_ucode_stations(priv
);
1841 iwl_restore_stations(priv
);
1844 IWL_DEBUG_INFO(priv
, "Sending RXON\n"
1845 "* with%s RXON_FILTER_ASSOC_MSK\n"
1848 (new_assoc
? "" : "out"),
1849 le16_to_cpu(staging_rxon
->channel
),
1850 staging_rxon
->bssid_addr
);
1853 * reserved4 and 5 could have been filled by the iwlcore code.
1854 * Let's clear them before pushing to the 3945.
1856 staging_rxon
->reserved4
= 0;
1857 staging_rxon
->reserved5
= 0;
1859 iwl_set_rxon_hwcrypto(priv
, !iwl3945_mod_params
.sw_crypto
);
1861 /* Apply the new configuration */
1862 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1863 sizeof(struct iwl3945_rxon_cmd
),
1866 IWL_ERR(priv
, "Error setting new configuration (%d).\n", rc
);
1870 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1873 iwl_clear_ucode_stations(priv
);
1874 iwl_restore_stations(priv
);
1877 /* If we issue a new RXON command which required a tune then we must
1878 * send a new TXPOWER command or we won't be able to Tx any frames */
1879 rc
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1881 IWL_ERR(priv
, "Error setting Tx power (%d).\n", rc
);
1885 /* Init the hardware's rate fallback order based on the band */
1886 rc
= iwl3945_init_hw_rate_table(priv
);
1888 IWL_ERR(priv
, "Error setting HW rate table: %02X\n", rc
);
1896 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1898 * -- reset periodic timer
1899 * -- see if temp has changed enough to warrant re-calibration ... if so:
1900 * -- correct coeffs for temp (can reset temp timer)
1901 * -- save this temp as "last",
1902 * -- send new set of gain settings to NIC
1903 * NOTE: This should continue working, even when we're not associated,
1904 * so we can keep our internal table of scan powers current. */
1905 void iwl3945_reg_txpower_periodic(struct iwl_priv
*priv
)
1907 /* This will kick in the "brute force"
1908 * iwl3945_hw_reg_comp_txpower_temp() below */
1909 if (!is_temp_calib_needed(priv
))
1912 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1913 * This is based *only* on current temperature,
1914 * ignoring any previous power measurements */
1915 iwl3945_hw_reg_comp_txpower_temp(priv
);
1918 queue_delayed_work(priv
->workqueue
,
1919 &priv
->_3945
.thermal_periodic
, REG_RECALIB_PERIOD
* HZ
);
1922 static void iwl3945_bg_reg_txpower_periodic(struct work_struct
*work
)
1924 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
1925 _3945
.thermal_periodic
.work
);
1927 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
1930 mutex_lock(&priv
->mutex
);
1931 iwl3945_reg_txpower_periodic(priv
);
1932 mutex_unlock(&priv
->mutex
);
1936 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1939 * This function is used when initializing channel-info structs.
1941 * NOTE: These channel groups do *NOT* match the bands above!
1942 * These channel groups are based on factory-tested channels;
1943 * on A-band, EEPROM's "group frequency" entries represent the top
1944 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1946 static u16
iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv
*priv
,
1947 const struct iwl_channel_info
*ch_info
)
1949 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1950 struct iwl3945_eeprom_txpower_group
*ch_grp
= &eeprom
->groups
[0];
1952 u16 group_index
= 0; /* based on factory calib frequencies */
1955 /* Find the group index for the channel ... don't use index 1(?) */
1956 if (is_channel_a_band(ch_info
)) {
1957 for (group
= 1; group
< 5; group
++) {
1958 grp_channel
= ch_grp
[group
].group_channel
;
1959 if (ch_info
->channel
<= grp_channel
) {
1960 group_index
= group
;
1964 /* group 4 has a few channels *above* its factory cal freq */
1968 group_index
= 0; /* 2.4 GHz, group 0 */
1970 IWL_DEBUG_POWER(priv
, "Chnl %d mapped to grp %d\n", ch_info
->channel
,
1976 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1978 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1979 * into radio/DSP gain settings table for requested power.
1981 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv
*priv
,
1983 s32 setting_index
, s32
*new_index
)
1985 const struct iwl3945_eeprom_txpower_group
*chnl_grp
= NULL
;
1986 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1988 s32 power
= 2 * requested_power
;
1990 const struct iwl3945_eeprom_txpower_sample
*samples
;
1995 chnl_grp
= &eeprom
->groups
[setting_index
];
1996 samples
= chnl_grp
->samples
;
1997 for (i
= 0; i
< 5; i
++) {
1998 if (power
== samples
[i
].power
) {
1999 *new_index
= samples
[i
].gain_index
;
2004 if (power
> samples
[1].power
) {
2007 } else if (power
> samples
[2].power
) {
2010 } else if (power
> samples
[3].power
) {
2018 denominator
= (s32
) samples
[index1
].power
- (s32
) samples
[index0
].power
;
2019 if (denominator
== 0)
2021 gains0
= (s32
) samples
[index0
].gain_index
* (1 << 19);
2022 gains1
= (s32
) samples
[index1
].gain_index
* (1 << 19);
2023 res
= gains0
+ (gains1
- gains0
) *
2024 ((s32
) power
- (s32
) samples
[index0
].power
) / denominator
+
2026 *new_index
= res
>> 19;
2030 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv
*priv
)
2034 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2035 const struct iwl3945_eeprom_txpower_group
*group
;
2037 IWL_DEBUG_POWER(priv
, "Initializing factory calib info from EEPROM\n");
2039 for (i
= 0; i
< IWL_NUM_TX_CALIB_GROUPS
; i
++) {
2040 s8
*clip_pwrs
; /* table of power levels for each rate */
2041 s8 satur_pwr
; /* saturation power for each chnl group */
2042 group
= &eeprom
->groups
[i
];
2044 /* sanity check on factory saturation power value */
2045 if (group
->saturation_power
< 40) {
2046 IWL_WARN(priv
, "Error: saturation power is %d, "
2047 "less than minimum expected 40\n",
2048 group
->saturation_power
);
2053 * Derive requested power levels for each rate, based on
2054 * hardware capabilities (saturation power for band).
2055 * Basic value is 3dB down from saturation, with further
2056 * power reductions for highest 3 data rates. These
2057 * backoffs provide headroom for high rate modulation
2058 * power peaks, without too much distortion (clipping).
2060 /* we'll fill in this array with h/w max power levels */
2061 clip_pwrs
= (s8
*) priv
->_3945
.clip_groups
[i
].clip_powers
;
2063 /* divide factory saturation power by 2 to find -3dB level */
2064 satur_pwr
= (s8
) (group
->saturation_power
>> 1);
2066 /* fill in channel group's nominal powers for each rate */
2067 for (rate_index
= 0;
2068 rate_index
< IWL_RATE_COUNT_3945
; rate_index
++, clip_pwrs
++) {
2069 switch (rate_index
) {
2070 case IWL_RATE_36M_INDEX_TABLE
:
2071 if (i
== 0) /* B/G */
2072 *clip_pwrs
= satur_pwr
;
2074 *clip_pwrs
= satur_pwr
- 5;
2076 case IWL_RATE_48M_INDEX_TABLE
:
2078 *clip_pwrs
= satur_pwr
- 7;
2080 *clip_pwrs
= satur_pwr
- 10;
2082 case IWL_RATE_54M_INDEX_TABLE
:
2084 *clip_pwrs
= satur_pwr
- 9;
2086 *clip_pwrs
= satur_pwr
- 12;
2089 *clip_pwrs
= satur_pwr
;
2097 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2099 * Second pass (during init) to set up priv->channel_info
2101 * Set up Tx-power settings in our channel info database for each VALID
2102 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2103 * and current temperature.
2105 * Since this is based on current temperature (at init time), these values may
2106 * not be valid for very long, but it gives us a starting/default point,
2107 * and allows us to active (i.e. using Tx) scan.
2109 * This does *not* write values to NIC, just sets up our internal table.
2111 int iwl3945_txpower_set_from_eeprom(struct iwl_priv
*priv
)
2113 struct iwl_channel_info
*ch_info
= NULL
;
2114 struct iwl3945_channel_power_info
*pwr_info
;
2115 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2119 const s8
*clip_pwrs
; /* array of power levels for each rate */
2122 u8 pwr_index
, base_pwr_index
, a_band
;
2126 /* save temperature reference,
2127 * so we can determine next time to calibrate */
2128 temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
2129 priv
->last_temperature
= temperature
;
2131 iwl3945_hw_reg_init_channel_groups(priv
);
2133 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2134 for (i
= 0, ch_info
= priv
->channel_info
; i
< priv
->channel_count
;
2136 a_band
= is_channel_a_band(ch_info
);
2137 if (!is_channel_valid(ch_info
))
2140 /* find this channel's channel group (*not* "band") index */
2141 ch_info
->group_index
=
2142 iwl3945_hw_reg_get_ch_grp_index(priv
, ch_info
);
2144 /* Get this chnlgrp's rate->max/clip-powers table */
2145 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
2147 /* calculate power index *adjustment* value according to
2148 * diff between current temperature and factory temperature */
2149 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
2150 eeprom
->groups
[ch_info
->group_index
].
2153 IWL_DEBUG_POWER(priv
, "Delta index for channel %d: %d [%d]\n",
2154 ch_info
->channel
, delta_index
, temperature
+
2157 /* set tx power value for all OFDM rates */
2158 for (rate_index
= 0; rate_index
< IWL_OFDM_RATES
;
2160 s32
uninitialized_var(power_idx
);
2163 /* use channel group's clip-power table,
2164 * but don't exceed channel's max power */
2165 s8 pwr
= min(ch_info
->max_power_avg
,
2166 clip_pwrs
[rate_index
]);
2168 pwr_info
= &ch_info
->power_info
[rate_index
];
2170 /* get base (i.e. at factory-measured temperature)
2171 * power table index for this rate's power */
2172 rc
= iwl3945_hw_reg_get_matched_power_index(priv
, pwr
,
2173 ch_info
->group_index
,
2176 IWL_ERR(priv
, "Invalid power index\n");
2179 pwr_info
->base_power_index
= (u8
) power_idx
;
2181 /* temperature compensate */
2182 power_idx
+= delta_index
;
2184 /* stay within range of gain table */
2185 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
2187 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2188 pwr_info
->requested_power
= pwr
;
2189 pwr_info
->power_table_index
= (u8
) power_idx
;
2190 pwr_info
->tpc
.tx_gain
=
2191 power_gain_table
[a_band
][power_idx
].tx_gain
;
2192 pwr_info
->tpc
.dsp_atten
=
2193 power_gain_table
[a_band
][power_idx
].dsp_atten
;
2196 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2197 pwr_info
= &ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
];
2198 power
= pwr_info
->requested_power
+
2199 IWL_CCK_FROM_OFDM_POWER_DIFF
;
2200 pwr_index
= pwr_info
->power_table_index
+
2201 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2202 base_pwr_index
= pwr_info
->base_power_index
+
2203 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2205 /* stay within table range */
2206 pwr_index
= iwl3945_hw_reg_fix_power_index(pwr_index
);
2207 gain
= power_gain_table
[a_band
][pwr_index
].tx_gain
;
2208 dsp_atten
= power_gain_table
[a_band
][pwr_index
].dsp_atten
;
2210 /* fill each CCK rate's iwl3945_channel_power_info structure
2211 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2212 * NOTE: CCK rates start at end of OFDM rates! */
2213 for (rate_index
= 0;
2214 rate_index
< IWL_CCK_RATES
; rate_index
++) {
2215 pwr_info
= &ch_info
->power_info
[rate_index
+IWL_OFDM_RATES
];
2216 pwr_info
->requested_power
= power
;
2217 pwr_info
->power_table_index
= pwr_index
;
2218 pwr_info
->base_power_index
= base_pwr_index
;
2219 pwr_info
->tpc
.tx_gain
= gain
;
2220 pwr_info
->tpc
.dsp_atten
= dsp_atten
;
2223 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2224 for (scan_tbl_index
= 0;
2225 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
2226 s32 actual_index
= (scan_tbl_index
== 0) ?
2227 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
2228 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
2229 actual_index
, clip_pwrs
, ch_info
, a_band
);
2236 int iwl3945_hw_rxq_stop(struct iwl_priv
*priv
)
2240 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0), 0);
2241 rc
= iwl_poll_direct_bit(priv
, FH39_RSSR_STATUS
,
2242 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
2244 IWL_ERR(priv
, "Can't stop Rx DMA.\n");
2249 int iwl3945_hw_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
2251 int txq_id
= txq
->q
.id
;
2253 struct iwl3945_shared
*shared_data
= priv
->_3945
.shared_virt
;
2255 shared_data
->tx_base_ptr
[txq_id
] = cpu_to_le32((u32
)txq
->q
.dma_addr
);
2257 iwl_write_direct32(priv
, FH39_CBCC_CTRL(txq_id
), 0);
2258 iwl_write_direct32(priv
, FH39_CBCC_BASE(txq_id
), 0);
2260 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
),
2261 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
|
2262 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
|
2263 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
|
2264 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
2265 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
);
2267 /* fake read to flush all prev. writes */
2268 iwl_read32(priv
, FH39_TSSR_CBB_BASE
);
2276 static u16
iwl3945_get_hcmd_size(u8 cmd_id
, u16 len
)
2280 return sizeof(struct iwl3945_rxon_cmd
);
2281 case POWER_TABLE_CMD
:
2282 return sizeof(struct iwl3945_powertable_cmd
);
2289 static u16
iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
2291 struct iwl3945_addsta_cmd
*addsta
= (struct iwl3945_addsta_cmd
*)data
;
2292 addsta
->mode
= cmd
->mode
;
2293 memcpy(&addsta
->sta
, &cmd
->sta
, sizeof(struct sta_id_modify
));
2294 memcpy(&addsta
->key
, &cmd
->key
, sizeof(struct iwl4965_keyinfo
));
2295 addsta
->station_flags
= cmd
->station_flags
;
2296 addsta
->station_flags_msk
= cmd
->station_flags_msk
;
2297 addsta
->tid_disable_tx
= cpu_to_le16(0);
2298 addsta
->rate_n_flags
= cmd
->rate_n_flags
;
2299 addsta
->add_immediate_ba_tid
= cmd
->add_immediate_ba_tid
;
2300 addsta
->remove_immediate_ba_tid
= cmd
->remove_immediate_ba_tid
;
2301 addsta
->add_immediate_ba_ssn
= cmd
->add_immediate_ba_ssn
;
2303 return (u16
)sizeof(struct iwl3945_addsta_cmd
);
2306 static int iwl3945_manage_ibss_station(struct iwl_priv
*priv
,
2307 struct ieee80211_vif
*vif
, bool add
)
2309 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
2313 ret
= iwl_add_bssid_station(priv
, vif
->bss_conf
.bssid
, false,
2314 &vif_priv
->ibss_bssid_sta_id
);
2318 iwl3945_sync_sta(priv
, vif_priv
->ibss_bssid_sta_id
,
2319 (priv
->band
== IEEE80211_BAND_5GHZ
) ?
2320 IWL_RATE_6M_PLCP
: IWL_RATE_1M_PLCP
);
2321 iwl3945_rate_scale_init(priv
->hw
, vif_priv
->ibss_bssid_sta_id
);
2326 return iwl_remove_station(priv
, vif_priv
->ibss_bssid_sta_id
,
2327 vif
->bss_conf
.bssid
);
2331 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2333 int iwl3945_init_hw_rate_table(struct iwl_priv
*priv
)
2335 int rc
, i
, index
, prev_index
;
2336 struct iwl3945_rate_scaling_cmd rate_cmd
= {
2337 .reserved
= {0, 0, 0},
2339 struct iwl3945_rate_scaling_info
*table
= rate_cmd
.table
;
2341 for (i
= 0; i
< ARRAY_SIZE(iwl3945_rates
); i
++) {
2342 index
= iwl3945_rates
[i
].table_rs_index
;
2344 table
[index
].rate_n_flags
=
2345 iwl3945_hw_set_rate_n_flags(iwl3945_rates
[i
].plcp
, 0);
2346 table
[index
].try_cnt
= priv
->retry_rate
;
2347 prev_index
= iwl3945_get_prev_ieee_rate(i
);
2348 table
[index
].next_rate_index
=
2349 iwl3945_rates
[prev_index
].table_rs_index
;
2352 switch (priv
->band
) {
2353 case IEEE80211_BAND_5GHZ
:
2354 IWL_DEBUG_RATE(priv
, "Select A mode rate scale\n");
2355 /* If one of the following CCK rates is used,
2356 * have it fall back to the 6M OFDM rate */
2357 for (i
= IWL_RATE_1M_INDEX_TABLE
;
2358 i
<= IWL_RATE_11M_INDEX_TABLE
; i
++)
2359 table
[i
].next_rate_index
=
2360 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2362 /* Don't fall back to CCK rates */
2363 table
[IWL_RATE_12M_INDEX_TABLE
].next_rate_index
=
2364 IWL_RATE_9M_INDEX_TABLE
;
2366 /* Don't drop out of OFDM rates */
2367 table
[IWL_RATE_6M_INDEX_TABLE
].next_rate_index
=
2368 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2371 case IEEE80211_BAND_2GHZ
:
2372 IWL_DEBUG_RATE(priv
, "Select B/G mode rate scale\n");
2373 /* If an OFDM rate is used, have it fall back to the
2376 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
2377 iwl_is_associated(priv
)) {
2379 index
= IWL_FIRST_CCK_RATE
;
2380 for (i
= IWL_RATE_6M_INDEX_TABLE
;
2381 i
<= IWL_RATE_54M_INDEX_TABLE
; i
++)
2382 table
[i
].next_rate_index
=
2383 iwl3945_rates
[index
].table_rs_index
;
2385 index
= IWL_RATE_11M_INDEX_TABLE
;
2386 /* CCK shouldn't fall back to OFDM... */
2387 table
[index
].next_rate_index
= IWL_RATE_5M_INDEX_TABLE
;
2396 /* Update the rate scaling for control frame Tx */
2397 rate_cmd
.table_id
= 0;
2398 rc
= iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2403 /* Update the rate scaling for data frame Tx */
2404 rate_cmd
.table_id
= 1;
2405 return iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2409 /* Called when initializing driver */
2410 int iwl3945_hw_set_hw_params(struct iwl_priv
*priv
)
2412 memset((void *)&priv
->hw_params
, 0,
2413 sizeof(struct iwl_hw_params
));
2415 priv
->_3945
.shared_virt
=
2416 dma_alloc_coherent(&priv
->pci_dev
->dev
,
2417 sizeof(struct iwl3945_shared
),
2418 &priv
->_3945
.shared_phys
, GFP_KERNEL
);
2419 if (!priv
->_3945
.shared_virt
) {
2420 IWL_ERR(priv
, "failed to allocate pci memory\n");
2424 /* Assign number of Usable TX queues */
2425 priv
->hw_params
.max_txq_num
= priv
->cfg
->num_of_queues
;
2427 priv
->hw_params
.tfd_size
= sizeof(struct iwl3945_tfd
);
2428 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_3K
);
2429 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
2430 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
2431 priv
->hw_params
.max_stations
= IWL3945_STATION_COUNT
;
2432 priv
->hw_params
.bcast_sta_id
= IWL3945_BROADCAST_ID
;
2434 priv
->hw_params
.rx_wrt_ptr_reg
= FH39_RSCSR_CHNL0_WPTR
;
2435 priv
->hw_params
.max_beacon_itrvl
= IWL39_MAX_UCODE_BEACON_INTERVAL
;
2436 priv
->hw_params
.beacon_time_tsf_bits
= IWL3945_EXT_BEACON_TIME_POS
;
2441 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv
*priv
,
2442 struct iwl3945_frame
*frame
, u8 rate
)
2444 struct iwl3945_tx_beacon_cmd
*tx_beacon_cmd
;
2445 unsigned int frame_size
;
2447 tx_beacon_cmd
= (struct iwl3945_tx_beacon_cmd
*)&frame
->u
;
2448 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
2450 tx_beacon_cmd
->tx
.sta_id
= priv
->hw_params
.bcast_sta_id
;
2451 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
2453 frame_size
= iwl3945_fill_beacon_frame(priv
,
2454 tx_beacon_cmd
->frame
,
2455 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
2457 BUG_ON(frame_size
> MAX_MPDU_SIZE
);
2458 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
2460 tx_beacon_cmd
->tx
.rate
= rate
;
2461 tx_beacon_cmd
->tx
.tx_flags
= (TX_CMD_FLG_SEQ_CTL_MSK
|
2462 TX_CMD_FLG_TSF_MSK
);
2464 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2465 tx_beacon_cmd
->tx
.supp_rates
[0] =
2466 (IWL_OFDM_BASIC_RATES_MASK
>> IWL_FIRST_OFDM_RATE
) & 0xFF;
2468 tx_beacon_cmd
->tx
.supp_rates
[1] =
2469 (IWL_CCK_BASIC_RATES_MASK
& 0xF);
2471 return sizeof(struct iwl3945_tx_beacon_cmd
) + frame_size
;
2474 void iwl3945_hw_rx_handler_setup(struct iwl_priv
*priv
)
2476 priv
->rx_handlers
[REPLY_TX
] = iwl3945_rx_reply_tx
;
2477 priv
->rx_handlers
[REPLY_3945_RX
] = iwl3945_rx_reply_rx
;
2480 void iwl3945_hw_setup_deferred_work(struct iwl_priv
*priv
)
2482 INIT_DELAYED_WORK(&priv
->_3945
.thermal_periodic
,
2483 iwl3945_bg_reg_txpower_periodic
);
2486 void iwl3945_hw_cancel_deferred_work(struct iwl_priv
*priv
)
2488 cancel_delayed_work(&priv
->_3945
.thermal_periodic
);
2491 /* check contents of special bootstrap uCode SRAM */
2492 static int iwl3945_verify_bsm(struct iwl_priv
*priv
)
2494 __le32
*image
= priv
->ucode_boot
.v_addr
;
2495 u32 len
= priv
->ucode_boot
.len
;
2499 IWL_DEBUG_INFO(priv
, "Begin verify bsm\n");
2501 /* verify BSM SRAM contents */
2502 val
= iwl_read_prph(priv
, BSM_WR_DWCOUNT_REG
);
2503 for (reg
= BSM_SRAM_LOWER_BOUND
;
2504 reg
< BSM_SRAM_LOWER_BOUND
+ len
;
2505 reg
+= sizeof(u32
), image
++) {
2506 val
= iwl_read_prph(priv
, reg
);
2507 if (val
!= le32_to_cpu(*image
)) {
2508 IWL_ERR(priv
, "BSM uCode verification failed at "
2509 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2510 BSM_SRAM_LOWER_BOUND
,
2511 reg
- BSM_SRAM_LOWER_BOUND
, len
,
2512 val
, le32_to_cpu(*image
));
2517 IWL_DEBUG_INFO(priv
, "BSM bootstrap uCode image OK\n");
2523 /******************************************************************************
2525 * EEPROM related functions
2527 ******************************************************************************/
2530 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2531 * embedded controller) as EEPROM reader; each read is a series of pulses
2532 * to/from the EEPROM chip, not a single event, so even reads could conflict
2533 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2534 * simply claims ownership, which should be safe when this function is called
2535 * (i.e. before loading uCode!).
2537 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv
*priv
)
2539 _iwl_clear_bit(priv
, CSR_EEPROM_GP
, CSR_EEPROM_GP_IF_OWNER_MSK
);
2544 static void iwl3945_eeprom_release_semaphore(struct iwl_priv
*priv
)
2550 * iwl3945_load_bsm - Load bootstrap instructions
2554 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2555 * in special SRAM that does not power down during RFKILL. When powering back
2556 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2557 * the bootstrap program into the on-board processor, and starts it.
2559 * The bootstrap program loads (via DMA) instructions and data for a new
2560 * program from host DRAM locations indicated by the host driver in the
2561 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2564 * When initializing the NIC, the host driver points the BSM to the
2565 * "initialize" uCode image. This uCode sets up some internal data, then
2566 * notifies host via "initialize alive" that it is complete.
2568 * The host then replaces the BSM_DRAM_* pointer values to point to the
2569 * normal runtime uCode instructions and a backup uCode data cache buffer
2570 * (filled initially with starting data values for the on-board processor),
2571 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2572 * which begins normal operation.
2574 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2575 * the backup data cache in DRAM before SRAM is powered down.
2577 * When powering back up, the BSM loads the bootstrap program. This reloads
2578 * the runtime uCode instructions and the backup data cache into SRAM,
2579 * and re-launches the runtime uCode from where it left off.
2581 static int iwl3945_load_bsm(struct iwl_priv
*priv
)
2583 __le32
*image
= priv
->ucode_boot
.v_addr
;
2584 u32 len
= priv
->ucode_boot
.len
;
2594 IWL_DEBUG_INFO(priv
, "Begin load bsm\n");
2596 /* make sure bootstrap program is no larger than BSM's SRAM size */
2597 if (len
> IWL39_MAX_BSM_SIZE
)
2600 /* Tell bootstrap uCode where to find the "Initialize" uCode
2601 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2602 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2603 * after the "initialize" uCode has run, to point to
2604 * runtime/protocol instructions and backup data cache. */
2605 pinst
= priv
->ucode_init
.p_addr
;
2606 pdata
= priv
->ucode_init_data
.p_addr
;
2607 inst_len
= priv
->ucode_init
.len
;
2608 data_len
= priv
->ucode_init_data
.len
;
2610 iwl_write_prph(priv
, BSM_DRAM_INST_PTR_REG
, pinst
);
2611 iwl_write_prph(priv
, BSM_DRAM_DATA_PTR_REG
, pdata
);
2612 iwl_write_prph(priv
, BSM_DRAM_INST_BYTECOUNT_REG
, inst_len
);
2613 iwl_write_prph(priv
, BSM_DRAM_DATA_BYTECOUNT_REG
, data_len
);
2615 /* Fill BSM memory with bootstrap instructions */
2616 for (reg_offset
= BSM_SRAM_LOWER_BOUND
;
2617 reg_offset
< BSM_SRAM_LOWER_BOUND
+ len
;
2618 reg_offset
+= sizeof(u32
), image
++)
2619 _iwl_write_prph(priv
, reg_offset
,
2620 le32_to_cpu(*image
));
2622 rc
= iwl3945_verify_bsm(priv
);
2626 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2627 iwl_write_prph(priv
, BSM_WR_MEM_SRC_REG
, 0x0);
2628 iwl_write_prph(priv
, BSM_WR_MEM_DST_REG
,
2629 IWL39_RTC_INST_LOWER_BOUND
);
2630 iwl_write_prph(priv
, BSM_WR_DWCOUNT_REG
, len
/ sizeof(u32
));
2632 /* Load bootstrap code into instruction SRAM now,
2633 * to prepare to load "initialize" uCode */
2634 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2635 BSM_WR_CTRL_REG_BIT_START
);
2637 /* Wait for load of bootstrap uCode to finish */
2638 for (i
= 0; i
< 100; i
++) {
2639 done
= iwl_read_prph(priv
, BSM_WR_CTRL_REG
);
2640 if (!(done
& BSM_WR_CTRL_REG_BIT_START
))
2645 IWL_DEBUG_INFO(priv
, "BSM write complete, poll %d iterations\n", i
);
2647 IWL_ERR(priv
, "BSM write did not complete!\n");
2651 /* Enable future boot loads whenever power management unit triggers it
2652 * (e.g. when powering back up after power-save shutdown) */
2653 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2654 BSM_WR_CTRL_REG_BIT_START_EN
);
2659 static struct iwl_hcmd_ops iwl3945_hcmd
= {
2660 .rxon_assoc
= iwl3945_send_rxon_assoc
,
2661 .commit_rxon
= iwl3945_commit_rxon
,
2662 .send_bt_config
= iwl_send_bt_config
,
2665 static struct iwl_lib_ops iwl3945_lib
= {
2666 .txq_attach_buf_to_tfd
= iwl3945_hw_txq_attach_buf_to_tfd
,
2667 .txq_free_tfd
= iwl3945_hw_txq_free_tfd
,
2668 .txq_init
= iwl3945_hw_tx_queue_init
,
2669 .load_ucode
= iwl3945_load_bsm
,
2670 .dump_nic_event_log
= iwl3945_dump_nic_event_log
,
2671 .dump_nic_error_log
= iwl3945_dump_nic_error_log
,
2673 .init
= iwl3945_apm_init
,
2674 .stop
= iwl_apm_stop
,
2675 .config
= iwl3945_nic_config
,
2676 .set_pwr_src
= iwl3945_set_pwr_src
,
2679 .regulatory_bands
= {
2680 EEPROM_REGULATORY_BAND_1_CHANNELS
,
2681 EEPROM_REGULATORY_BAND_2_CHANNELS
,
2682 EEPROM_REGULATORY_BAND_3_CHANNELS
,
2683 EEPROM_REGULATORY_BAND_4_CHANNELS
,
2684 EEPROM_REGULATORY_BAND_5_CHANNELS
,
2685 EEPROM_REGULATORY_BAND_NO_HT40
,
2686 EEPROM_REGULATORY_BAND_NO_HT40
,
2688 .verify_signature
= iwlcore_eeprom_verify_signature
,
2689 .acquire_semaphore
= iwl3945_eeprom_acquire_semaphore
,
2690 .release_semaphore
= iwl3945_eeprom_release_semaphore
,
2691 .query_addr
= iwlcore_eeprom_query_addr
,
2693 .send_tx_power
= iwl3945_send_tx_power
,
2694 .is_valid_rtc_data_addr
= iwl3945_hw_valid_rtc_data_addr
,
2695 .post_associate
= iwl3945_post_associate
,
2696 .isr
= iwl_isr_legacy
,
2697 .config_ap
= iwl3945_config_ap
,
2698 .manage_ibss_station
= iwl3945_manage_ibss_station
,
2699 .check_plcp_health
= iwl3945_good_plcp_health
,
2702 .rx_stats_read
= iwl3945_ucode_rx_stats_read
,
2703 .tx_stats_read
= iwl3945_ucode_tx_stats_read
,
2704 .general_stats_read
= iwl3945_ucode_general_stats_read
,
2708 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils
= {
2709 .get_hcmd_size
= iwl3945_get_hcmd_size
,
2710 .build_addsta_hcmd
= iwl3945_build_addsta_hcmd
,
2711 .rts_tx_cmd_flag
= iwlcore_rts_tx_cmd_flag
,
2712 .request_scan
= iwl3945_request_scan
,
2715 static const struct iwl_ops iwl3945_ops
= {
2716 .lib
= &iwl3945_lib
,
2717 .hcmd
= &iwl3945_hcmd
,
2718 .utils
= &iwl3945_hcmd_utils
,
2719 .led
= &iwl3945_led_ops
,
2722 static struct iwl_cfg iwl3945_bg_cfg
= {
2724 .fw_name_pre
= IWL3945_FW_PRE
,
2725 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2726 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2728 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2729 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2730 .ops
= &iwl3945_ops
,
2731 .num_of_queues
= IWL39_NUM_QUEUES
,
2732 .mod_params
= &iwl3945_mod_params
,
2733 .pll_cfg_val
= CSR39_ANA_PLL_CFG_VAL
,
2736 .use_isr_legacy
= true,
2737 .ht_greenfield_support
= false,
2738 .led_compensation
= 64,
2739 .broken_powersave
= true,
2740 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
2741 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2742 .max_event_log_size
= 512,
2743 .tx_power_by_driver
= true,
2746 static struct iwl_cfg iwl3945_abg_cfg
= {
2748 .fw_name_pre
= IWL3945_FW_PRE
,
2749 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2750 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2751 .sku
= IWL_SKU_A
|IWL_SKU_G
,
2752 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2753 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2754 .ops
= &iwl3945_ops
,
2755 .num_of_queues
= IWL39_NUM_QUEUES
,
2756 .mod_params
= &iwl3945_mod_params
,
2757 .use_isr_legacy
= true,
2758 .ht_greenfield_support
= false,
2759 .led_compensation
= 64,
2760 .broken_powersave
= true,
2761 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
2762 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2763 .max_event_log_size
= 512,
2764 .tx_power_by_driver
= true,
2767 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids
) = {
2768 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg
)},
2769 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg
)},
2770 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg
)},
2771 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg
)},
2772 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2773 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2777 MODULE_DEVICE_TABLE(pci
, iwl3945_hw_card_ids
);