1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
47 #include "iwl-eeprom.h"
49 #include "iwl-helpers.h"
51 #include "iwl-3945-led.h"
52 #include "iwl-3945-debugfs.h"
54 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
55 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
56 IWL_RATE_##r##M_IEEE, \
57 IWL_RATE_##ip##M_INDEX, \
58 IWL_RATE_##in##M_INDEX, \
59 IWL_RATE_##rp##M_INDEX, \
60 IWL_RATE_##rn##M_INDEX, \
61 IWL_RATE_##pp##M_INDEX, \
62 IWL_RATE_##np##M_INDEX, \
63 IWL_RATE_##r##M_INDEX_TABLE, \
64 IWL_RATE_##ip##M_INDEX_TABLE }
68 * rate, prev rate, next rate, prev tgg rate, next tgg rate
70 * If there isn't a valid next or previous rate then INV is used which
71 * maps to IWL_RATE_INVALID
74 const struct iwl3945_rate_info iwl3945_rates
[IWL_RATE_COUNT_3945
] = {
75 IWL_DECLARE_RATE_INFO(1, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
76 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
77 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
78 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
79 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
80 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
81 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
82 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
83 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
84 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
85 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
86 IWL_DECLARE_RATE_INFO(54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
89 /* 1 = enable the iwl3945_disable_events() function */
90 #define IWL_EVT_DISABLE (0)
91 #define IWL_EVT_DISABLE_SIZE (1532/32)
94 * iwl3945_disable_events - Disable selected events in uCode event log
96 * Disable an event by writing "1"s into "disable"
97 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
98 * Default values of 0 enable uCode events to be logged.
99 * Use for only special debugging. This function is just a placeholder as-is,
100 * you'll need to provide the special bits! ...
101 * ... and set IWL_EVT_DISABLE to 1. */
102 void iwl3945_disable_events(struct iwl_priv
*priv
)
105 u32 base
; /* SRAM address of event log header */
106 u32 disable_ptr
; /* SRAM address of event-disable bitmap array */
107 u32 array_size
; /* # of u32 entries in array */
108 u32 evt_disable
[IWL_EVT_DISABLE_SIZE
] = {
109 0x00000000, /* 31 - 0 Event id numbers */
110 0x00000000, /* 63 - 32 */
111 0x00000000, /* 95 - 64 */
112 0x00000000, /* 127 - 96 */
113 0x00000000, /* 159 - 128 */
114 0x00000000, /* 191 - 160 */
115 0x00000000, /* 223 - 192 */
116 0x00000000, /* 255 - 224 */
117 0x00000000, /* 287 - 256 */
118 0x00000000, /* 319 - 288 */
119 0x00000000, /* 351 - 320 */
120 0x00000000, /* 383 - 352 */
121 0x00000000, /* 415 - 384 */
122 0x00000000, /* 447 - 416 */
123 0x00000000, /* 479 - 448 */
124 0x00000000, /* 511 - 480 */
125 0x00000000, /* 543 - 512 */
126 0x00000000, /* 575 - 544 */
127 0x00000000, /* 607 - 576 */
128 0x00000000, /* 639 - 608 */
129 0x00000000, /* 671 - 640 */
130 0x00000000, /* 703 - 672 */
131 0x00000000, /* 735 - 704 */
132 0x00000000, /* 767 - 736 */
133 0x00000000, /* 799 - 768 */
134 0x00000000, /* 831 - 800 */
135 0x00000000, /* 863 - 832 */
136 0x00000000, /* 895 - 864 */
137 0x00000000, /* 927 - 896 */
138 0x00000000, /* 959 - 928 */
139 0x00000000, /* 991 - 960 */
140 0x00000000, /* 1023 - 992 */
141 0x00000000, /* 1055 - 1024 */
142 0x00000000, /* 1087 - 1056 */
143 0x00000000, /* 1119 - 1088 */
144 0x00000000, /* 1151 - 1120 */
145 0x00000000, /* 1183 - 1152 */
146 0x00000000, /* 1215 - 1184 */
147 0x00000000, /* 1247 - 1216 */
148 0x00000000, /* 1279 - 1248 */
149 0x00000000, /* 1311 - 1280 */
150 0x00000000, /* 1343 - 1312 */
151 0x00000000, /* 1375 - 1344 */
152 0x00000000, /* 1407 - 1376 */
153 0x00000000, /* 1439 - 1408 */
154 0x00000000, /* 1471 - 1440 */
155 0x00000000, /* 1503 - 1472 */
158 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
159 if (!iwl3945_hw_valid_rtc_data_addr(base
)) {
160 IWL_ERR(priv
, "Invalid event log pointer 0x%08X\n", base
);
164 disable_ptr
= iwl_read_targ_mem(priv
, base
+ (4 * sizeof(u32
)));
165 array_size
= iwl_read_targ_mem(priv
, base
+ (5 * sizeof(u32
)));
167 if (IWL_EVT_DISABLE
&& (array_size
== IWL_EVT_DISABLE_SIZE
)) {
168 IWL_DEBUG_INFO(priv
, "Disabling selected uCode log events at 0x%x\n",
170 for (i
= 0; i
< IWL_EVT_DISABLE_SIZE
; i
++)
171 iwl_write_targ_mem(priv
,
172 disable_ptr
+ (i
* sizeof(u32
)),
176 IWL_DEBUG_INFO(priv
, "Selected uCode log events may be disabled\n");
177 IWL_DEBUG_INFO(priv
, " by writing \"1\"s into disable bitmap\n");
178 IWL_DEBUG_INFO(priv
, " in SRAM at 0x%x, size %d u32s\n",
179 disable_ptr
, array_size
);
184 static int iwl3945_hwrate_to_plcp_idx(u8 plcp
)
188 for (idx
= 0; idx
< IWL_RATE_COUNT_3945
; idx
++)
189 if (iwl3945_rates
[idx
].plcp
== plcp
)
194 #ifdef CONFIG_IWLWIFI_DEBUG
195 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
197 static const char *iwl3945_get_tx_fail_reason(u32 status
)
199 switch (status
& TX_STATUS_MSK
) {
200 case TX_3945_STATUS_SUCCESS
:
202 TX_STATUS_ENTRY(SHORT_LIMIT
);
203 TX_STATUS_ENTRY(LONG_LIMIT
);
204 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
205 TX_STATUS_ENTRY(MGMNT_ABORT
);
206 TX_STATUS_ENTRY(NEXT_FRAG
);
207 TX_STATUS_ENTRY(LIFE_EXPIRE
);
208 TX_STATUS_ENTRY(DEST_PS
);
209 TX_STATUS_ENTRY(ABORTED
);
210 TX_STATUS_ENTRY(BT_RETRY
);
211 TX_STATUS_ENTRY(STA_INVALID
);
212 TX_STATUS_ENTRY(FRAG_DROPPED
);
213 TX_STATUS_ENTRY(TID_DISABLE
);
214 TX_STATUS_ENTRY(FRAME_FLUSHED
);
215 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
216 TX_STATUS_ENTRY(TX_LOCKED
);
217 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
223 static inline const char *iwl3945_get_tx_fail_reason(u32 status
)
230 * get ieee prev rate from rate scale table.
231 * for A and B mode we need to overright prev
234 int iwl3945_rs_next_rate(struct iwl_priv
*priv
, int rate
)
236 int next_rate
= iwl3945_get_prev_ieee_rate(rate
);
238 switch (priv
->band
) {
239 case IEEE80211_BAND_5GHZ
:
240 if (rate
== IWL_RATE_12M_INDEX
)
241 next_rate
= IWL_RATE_9M_INDEX
;
242 else if (rate
== IWL_RATE_6M_INDEX
)
243 next_rate
= IWL_RATE_6M_INDEX
;
245 case IEEE80211_BAND_2GHZ
:
246 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
247 iwl_is_associated(priv
)) {
248 if (rate
== IWL_RATE_11M_INDEX
)
249 next_rate
= IWL_RATE_5M_INDEX
;
262 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
264 * When FW advances 'R' index, all entries between old and new 'R' index
265 * need to be reclaimed. As result, some free space forms. If there is
266 * enough free space (> low mark), wake the stack that feeds us.
268 static void iwl3945_tx_queue_reclaim(struct iwl_priv
*priv
,
269 int txq_id
, int index
)
271 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
272 struct iwl_queue
*q
= &txq
->q
;
273 struct iwl_tx_info
*tx_info
;
275 BUG_ON(txq_id
== IWL_CMD_QUEUE_NUM
);
277 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
278 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
280 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
281 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
282 tx_info
->skb
[0] = NULL
;
283 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
286 if (iwl_queue_space(q
) > q
->low_mark
&& (txq_id
>= 0) &&
287 (txq_id
!= IWL_CMD_QUEUE_NUM
) &&
288 priv
->mac80211_registered
)
289 iwl_wake_queue(priv
, txq_id
);
293 * iwl3945_rx_reply_tx - Handle Tx response
295 static void iwl3945_rx_reply_tx(struct iwl_priv
*priv
,
296 struct iwl_rx_mem_buffer
*rxb
)
298 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
299 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
300 int txq_id
= SEQ_TO_QUEUE(sequence
);
301 int index
= SEQ_TO_INDEX(sequence
);
302 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
303 struct ieee80211_tx_info
*info
;
304 struct iwl3945_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
305 u32 status
= le32_to_cpu(tx_resp
->status
);
309 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
310 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
311 "is out of range [0-%d] %d %d\n", txq_id
,
312 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
317 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
318 ieee80211_tx_info_clear_status(info
);
320 /* Fill the MRR chain with some info about on-chip retransmissions */
321 rate_idx
= iwl3945_hwrate_to_plcp_idx(tx_resp
->rate
);
322 if (info
->band
== IEEE80211_BAND_5GHZ
)
323 rate_idx
-= IWL_FIRST_OFDM_RATE
;
325 fail
= tx_resp
->failure_frame
;
327 info
->status
.rates
[0].idx
= rate_idx
;
328 info
->status
.rates
[0].count
= fail
+ 1; /* add final attempt */
330 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
331 info
->flags
|= ((status
& TX_STATUS_MSK
) == TX_STATUS_SUCCESS
) ?
332 IEEE80211_TX_STAT_ACK
: 0;
334 IWL_DEBUG_TX(priv
, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
335 txq_id
, iwl3945_get_tx_fail_reason(status
), status
,
336 tx_resp
->rate
, tx_resp
->failure_frame
);
338 IWL_DEBUG_TX_REPLY(priv
, "Tx queue reclaim %d\n", index
);
339 iwl3945_tx_queue_reclaim(priv
, txq_id
, index
);
341 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
342 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
347 /*****************************************************************************
349 * Intel PRO/Wireless 3945ABG/BG Network Connection
351 * RX handler implementations
353 *****************************************************************************/
354 #ifdef CONFIG_IWLWIFI_DEBUG
356 * based on the assumption of all statistics counter are in DWORD
357 * FIXME: This function is for debugging, do not deal with
358 * the case of counters roll-over.
360 static void iwl3945_accumulative_statistics(struct iwl_priv
*priv
,
366 u32
*delta
, *max_delta
;
368 prev_stats
= (__le32
*)&priv
->_3945
.statistics
;
369 accum_stats
= (u32
*)&priv
->_3945
.accum_statistics
;
370 delta
= (u32
*)&priv
->_3945
.delta_statistics
;
371 max_delta
= (u32
*)&priv
->_3945
.max_delta
;
373 for (i
= sizeof(__le32
); i
< sizeof(struct iwl3945_notif_statistics
);
374 i
+= sizeof(__le32
), stats
++, prev_stats
++, delta
++,
375 max_delta
++, accum_stats
++) {
376 if (le32_to_cpu(*stats
) > le32_to_cpu(*prev_stats
)) {
377 *delta
= (le32_to_cpu(*stats
) -
378 le32_to_cpu(*prev_stats
));
379 *accum_stats
+= *delta
;
380 if (*delta
> *max_delta
)
385 /* reset accumulative statistics for "no-counter" type statistics */
386 priv
->_3945
.accum_statistics
.general
.temperature
=
387 priv
->_3945
.statistics
.general
.temperature
;
388 priv
->_3945
.accum_statistics
.general
.ttl_timestamp
=
389 priv
->_3945
.statistics
.general
.ttl_timestamp
;
393 void iwl3945_hw_rx_statistics(struct iwl_priv
*priv
,
394 struct iwl_rx_mem_buffer
*rxb
)
396 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
398 IWL_DEBUG_RX(priv
, "Statistics notification received (%d vs %d).\n",
399 (int)sizeof(struct iwl3945_notif_statistics
),
400 le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
);
401 #ifdef CONFIG_IWLWIFI_DEBUG
402 iwl3945_accumulative_statistics(priv
, (__le32
*)&pkt
->u
.raw
);
405 memcpy(&priv
->_3945
.statistics
, pkt
->u
.raw
, sizeof(priv
->_3945
.statistics
));
408 void iwl3945_reply_statistics(struct iwl_priv
*priv
,
409 struct iwl_rx_mem_buffer
*rxb
)
411 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
412 __le32
*flag
= (__le32
*)&pkt
->u
.raw
;
414 if (le32_to_cpu(*flag
) & UCODE_STATISTICS_CLEAR_MSK
) {
415 #ifdef CONFIG_IWLWIFI_DEBUG
416 memset(&priv
->_3945
.accum_statistics
, 0,
417 sizeof(struct iwl3945_notif_statistics
));
418 memset(&priv
->_3945
.delta_statistics
, 0,
419 sizeof(struct iwl3945_notif_statistics
));
420 memset(&priv
->_3945
.max_delta
, 0,
421 sizeof(struct iwl3945_notif_statistics
));
423 IWL_DEBUG_RX(priv
, "Statistics have been cleared\n");
425 iwl3945_hw_rx_statistics(priv
, rxb
);
429 /******************************************************************************
431 * Misc. internal state and helper functions
433 ******************************************************************************/
434 #ifdef CONFIG_IWLWIFI_DEBUG
437 * iwl3945_report_frame - dump frame to syslog during debug sessions
439 * You may hack this function to show different aspects of received frames,
440 * including selective frame dumps.
441 * group100 parameter selects whether to show 1 out of 100 good frames.
443 static void _iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
444 struct iwl_rx_packet
*pkt
,
445 struct ieee80211_hdr
*header
, int group100
)
448 u32 print_summary
= 0;
449 u32 print_dump
= 0; /* set to 1 to dump all frames' contents */
465 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
466 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
467 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
468 u8
*data
= IWL_RX_DATA(pkt
);
471 fc
= header
->frame_control
;
472 seq_ctl
= le16_to_cpu(header
->seq_ctrl
);
475 channel
= le16_to_cpu(rx_hdr
->channel
);
476 phy_flags
= le16_to_cpu(rx_hdr
->phy_flags
);
477 length
= le16_to_cpu(rx_hdr
->len
);
479 /* end-of-frame status and timestamp */
480 status
= le32_to_cpu(rx_end
->status
);
481 bcn_tmr
= le32_to_cpu(rx_end
->beacon_timestamp
);
482 tsf_low
= le64_to_cpu(rx_end
->timestamp
) & 0x0ffffffff;
483 tsf
= le64_to_cpu(rx_end
->timestamp
);
485 /* signal statistics */
486 rssi
= rx_stats
->rssi
;
488 sig_avg
= le16_to_cpu(rx_stats
->sig_avg
);
489 noise_diff
= le16_to_cpu(rx_stats
->noise_diff
);
491 to_us
= !compare_ether_addr(header
->addr1
, priv
->mac_addr
);
493 /* if data frame is to us and all is good,
494 * (optionally) print summary for only 1 out of every 100 */
495 if (to_us
&& (fc
& ~cpu_to_le16(IEEE80211_FCTL_PROTECTED
)) ==
496 cpu_to_le16(IEEE80211_FCTL_FROMDS
| IEEE80211_FTYPE_DATA
)) {
499 print_summary
= 1; /* print each frame */
500 else if (priv
->framecnt_to_us
< 100) {
501 priv
->framecnt_to_us
++;
504 priv
->framecnt_to_us
= 0;
509 /* print summary for all other frames */
519 else if (ieee80211_has_retry(fc
))
521 else if (ieee80211_is_assoc_resp(fc
))
523 else if (ieee80211_is_reassoc_resp(fc
))
525 else if (ieee80211_is_probe_resp(fc
)) {
527 print_dump
= 1; /* dump frame contents */
528 } else if (ieee80211_is_beacon(fc
)) {
530 print_dump
= 1; /* dump frame contents */
531 } else if (ieee80211_is_atim(fc
))
533 else if (ieee80211_is_auth(fc
))
535 else if (ieee80211_is_deauth(fc
))
537 else if (ieee80211_is_disassoc(fc
))
542 rate
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
546 rate
= iwl3945_rates
[rate
].ieee
/ 2;
548 /* print frame summary.
549 * MAC addresses show just the last byte (for brevity),
550 * but you can hack it to show more, if you'd like to. */
552 IWL_DEBUG_RX(priv
, "%s: mhd=0x%04x, dst=0x%02x, "
553 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
554 title
, le16_to_cpu(fc
), header
->addr1
[5],
555 length
, rssi
, channel
, rate
);
557 /* src/dst addresses assume managed mode */
558 IWL_DEBUG_RX(priv
, "%s: 0x%04x, dst=0x%02x, "
559 "src=0x%02x, rssi=%u, tim=%lu usec, "
560 "phy=0x%02x, chnl=%d\n",
561 title
, le16_to_cpu(fc
), header
->addr1
[5],
562 header
->addr3
[5], rssi
,
563 tsf_low
- priv
->scan_start_tsf
,
568 iwl_print_hex_dump(priv
, IWL_DL_RX
, data
, length
);
571 static void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
572 struct iwl_rx_packet
*pkt
,
573 struct ieee80211_hdr
*header
, int group100
)
575 if (iwl_get_debug_level(priv
) & IWL_DL_RX
)
576 _iwl3945_dbg_report_frame(priv
, pkt
, header
, group100
);
580 static inline void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
581 struct iwl_rx_packet
*pkt
,
582 struct ieee80211_hdr
*header
, int group100
)
587 /* This is necessary only for a number of statistics, see the caller. */
588 static int iwl3945_is_network_packet(struct iwl_priv
*priv
,
589 struct ieee80211_hdr
*header
)
591 /* Filter incoming packets to determine if they are targeted toward
592 * this network, discarding packets coming from ourselves */
593 switch (priv
->iw_mode
) {
594 case NL80211_IFTYPE_ADHOC
: /* Header: Dest. | Source | BSSID */
595 /* packets to our IBSS update information */
596 return !compare_ether_addr(header
->addr3
, priv
->bssid
);
597 case NL80211_IFTYPE_STATION
: /* Header: Dest. | AP{BSSID} | Source */
598 /* packets to our IBSS update information */
599 return !compare_ether_addr(header
->addr2
, priv
->bssid
);
605 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv
*priv
,
606 struct iwl_rx_mem_buffer
*rxb
,
607 struct ieee80211_rx_status
*stats
)
609 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
610 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
611 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
612 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
613 u16 len
= le16_to_cpu(rx_hdr
->len
);
615 __le16 fc
= hdr
->frame_control
;
617 /* We received data from the HW, so stop the watchdog */
618 if (unlikely(len
+ IWL39_RX_FRAME_SIZE
>
619 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
)) {
620 IWL_DEBUG_DROP(priv
, "Corruption detected!\n");
624 /* We only process data packets if the interface is open */
625 if (unlikely(!priv
->is_open
)) {
626 IWL_DEBUG_DROP_LIMIT(priv
,
627 "Dropping packet while interface is not open.\n");
631 skb
= dev_alloc_skb(128);
633 IWL_ERR(priv
, "dev_alloc_skb failed\n");
637 if (!iwl3945_mod_params
.sw_crypto
)
638 iwl_set_decrypted_flag(priv
,
639 (struct ieee80211_hdr
*)rxb_addr(rxb
),
640 le32_to_cpu(rx_end
->status
), stats
);
642 skb_add_rx_frag(skb
, 0, rxb
->page
,
643 (void *)rx_hdr
->payload
- (void *)pkt
, len
);
645 iwl_update_stats(priv
, false, fc
, len
);
646 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
648 ieee80211_rx(priv
->hw
, skb
);
649 priv
->alloc_rxb_page
--;
653 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
655 static void iwl3945_rx_reply_rx(struct iwl_priv
*priv
,
656 struct iwl_rx_mem_buffer
*rxb
)
658 struct ieee80211_hdr
*header
;
659 struct ieee80211_rx_status rx_status
;
660 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
661 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
662 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
663 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
664 u16 rx_stats_sig_avg __maybe_unused
= le16_to_cpu(rx_stats
->sig_avg
);
665 u16 rx_stats_noise_diff __maybe_unused
= le16_to_cpu(rx_stats
->noise_diff
);
669 rx_status
.mactime
= le64_to_cpu(rx_end
->timestamp
);
671 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr
->channel
));
672 rx_status
.band
= (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
673 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
675 rx_status
.rate_idx
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
676 if (rx_status
.band
== IEEE80211_BAND_5GHZ
)
677 rx_status
.rate_idx
-= IWL_FIRST_OFDM_RATE
;
679 rx_status
.antenna
= (le16_to_cpu(rx_hdr
->phy_flags
) &
680 RX_RES_PHY_FLAGS_ANTENNA_MSK
) >> 4;
682 /* set the preamble flag if appropriate */
683 if (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
684 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
686 if ((unlikely(rx_stats
->phy_count
> 20))) {
687 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
688 rx_stats
->phy_count
);
692 if (!(rx_end
->status
& RX_RES_STATUS_NO_CRC32_ERROR
)
693 || !(rx_end
->status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
694 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n", rx_end
->status
);
700 /* Convert 3945's rssi indicator to dBm */
701 rx_status
.signal
= rx_stats
->rssi
- IWL39_RSSI_OFFSET
;
703 IWL_DEBUG_STATS(priv
, "Rssi %d sig_avg %d noise_diff %d\n",
704 rx_status
.signal
, rx_stats_sig_avg
,
705 rx_stats_noise_diff
);
707 header
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
709 network_packet
= iwl3945_is_network_packet(priv
, header
);
711 IWL_DEBUG_STATS_LIMIT(priv
, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
712 network_packet
? '*' : ' ',
713 le16_to_cpu(rx_hdr
->channel
),
714 rx_status
.signal
, rx_status
.signal
,
717 /* Set "1" to report good data frames in groups of 100 */
718 iwl3945_dbg_report_frame(priv
, pkt
, header
, 1);
719 iwl_dbg_log_rx_data_frame(priv
, le16_to_cpu(rx_hdr
->len
), header
);
721 if (network_packet
) {
722 priv
->_3945
.last_beacon_time
=
723 le32_to_cpu(rx_end
->beacon_timestamp
);
724 priv
->_3945
.last_tsf
= le64_to_cpu(rx_end
->timestamp
);
725 priv
->_3945
.last_rx_rssi
= rx_status
.signal
;
728 iwl3945_pass_packet_to_mac80211(priv
, rxb
, &rx_status
);
731 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
732 struct iwl_tx_queue
*txq
,
733 dma_addr_t addr
, u16 len
, u8 reset
, u8 pad
)
737 struct iwl3945_tfd
*tfd
, *tfd_tmp
;
740 tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
741 tfd
= &tfd_tmp
[q
->write_ptr
];
744 memset(tfd
, 0, sizeof(*tfd
));
746 count
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
748 if ((count
>= NUM_TFD_CHUNKS
) || (count
< 0)) {
749 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
754 tfd
->tbs
[count
].addr
= cpu_to_le32(addr
);
755 tfd
->tbs
[count
].len
= cpu_to_le32(len
);
759 tfd
->control_flags
= cpu_to_le32(TFD_CTL_COUNT_SET(count
) |
760 TFD_CTL_PAD_SET(pad
));
766 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
768 * Does NOT advance any indexes
770 void iwl3945_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
772 struct iwl3945_tfd
*tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
773 int index
= txq
->q
.read_ptr
;
774 struct iwl3945_tfd
*tfd
= &tfd_tmp
[index
];
775 struct pci_dev
*dev
= priv
->pci_dev
;
780 counter
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
781 if (counter
> NUM_TFD_CHUNKS
) {
782 IWL_ERR(priv
, "Too many chunks: %i\n", counter
);
783 /* @todo issue fatal error, it is quite serious situation */
789 pci_unmap_single(dev
,
790 pci_unmap_addr(&txq
->meta
[index
], mapping
),
791 pci_unmap_len(&txq
->meta
[index
], len
),
794 /* unmap chunks if any */
796 for (i
= 1; i
< counter
; i
++) {
797 pci_unmap_single(dev
, le32_to_cpu(tfd
->tbs
[i
].addr
),
798 le32_to_cpu(tfd
->tbs
[i
].len
), PCI_DMA_TODEVICE
);
799 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
800 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[0];
801 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
802 /* Can be called from interrupt context */
803 dev_kfree_skb_any(skb
);
804 txq
->txb
[txq
->q
.read_ptr
].skb
[0] = NULL
;
812 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
815 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv
*priv
,
816 struct iwl_device_cmd
*cmd
,
817 struct ieee80211_tx_info
*info
,
818 struct ieee80211_hdr
*hdr
,
819 int sta_id
, int tx_id
)
821 u16 hw_value
= ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
;
822 u16 rate_index
= min(hw_value
& 0xffff, IWL_RATE_COUNT_3945
);
828 __le16 fc
= hdr
->frame_control
;
829 struct iwl3945_tx_cmd
*tx_cmd
= (struct iwl3945_tx_cmd
*)cmd
->cmd
.payload
;
831 rate
= iwl3945_rates
[rate_index
].plcp
;
832 tx_flags
= tx_cmd
->tx_flags
;
834 /* We need to figure out how to get the sta->supp_rates while
835 * in this running context */
836 rate_mask
= IWL_RATES_MASK
;
839 /* Set retry limit on DATA packets and Probe Responses*/
840 if (ieee80211_is_probe_resp(fc
))
841 data_retry_limit
= 3;
843 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
844 tx_cmd
->data_retry_limit
= data_retry_limit
;
846 if (tx_id
>= IWL_CMD_QUEUE_NUM
)
851 if (data_retry_limit
< rts_retry_limit
)
852 rts_retry_limit
= data_retry_limit
;
853 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
855 if (ieee80211_is_mgmt(fc
)) {
856 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
857 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
858 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
859 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
860 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
861 if (tx_flags
& TX_CMD_FLG_RTS_MSK
) {
862 tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
863 tx_flags
|= TX_CMD_FLG_CTS_MSK
;
872 tx_cmd
->tx_flags
= tx_flags
;
875 tx_cmd
->supp_rates
[0] =
876 ((rate_mask
& IWL_OFDM_RATES_MASK
) >> IWL_FIRST_OFDM_RATE
) & 0xFF;
879 tx_cmd
->supp_rates
[1] = (rate_mask
& 0xF);
881 IWL_DEBUG_RATE(priv
, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
882 "cck/ofdm mask: 0x%x/0x%x\n", sta_id
,
883 tx_cmd
->rate
, le32_to_cpu(tx_cmd
->tx_flags
),
884 tx_cmd
->supp_rates
[1], tx_cmd
->supp_rates
[0]);
887 u8
iwl3945_sync_sta(struct iwl_priv
*priv
, int sta_id
, u16 tx_rate
, u8 flags
)
889 unsigned long flags_spin
;
890 struct iwl_station_entry
*station
;
892 if (sta_id
== IWL_INVALID_STATION
)
893 return IWL_INVALID_STATION
;
895 spin_lock_irqsave(&priv
->sta_lock
, flags_spin
);
896 station
= &priv
->stations
[sta_id
];
898 station
->sta
.sta
.modify_mask
= STA_MODIFY_TX_RATE_MSK
;
899 station
->sta
.rate_n_flags
= cpu_to_le16(tx_rate
);
900 station
->sta
.mode
= STA_CONTROL_MODIFY_MSK
;
902 spin_unlock_irqrestore(&priv
->sta_lock
, flags_spin
);
904 iwl_send_add_sta(priv
, &station
->sta
, flags
);
905 IWL_DEBUG_RATE(priv
, "SCALE sync station %d to rate %d\n",
910 static int iwl3945_set_pwr_src(struct iwl_priv
*priv
, enum iwl_pwr_src src
)
912 if (src
== IWL_PWR_SRC_VAUX
) {
913 if (pci_pme_capable(priv
->pci_dev
, PCI_D3cold
)) {
914 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
915 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
916 ~APMG_PS_CTRL_MSK_PWR_SRC
);
918 iwl_poll_bit(priv
, CSR_GPIO_IN
,
919 CSR_GPIO_IN_VAL_VAUX_PWR_SRC
,
920 CSR_GPIO_IN_BIT_AUX_POWER
, 5000);
923 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
924 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
925 ~APMG_PS_CTRL_MSK_PWR_SRC
);
927 iwl_poll_bit(priv
, CSR_GPIO_IN
, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC
,
928 CSR_GPIO_IN_BIT_AUX_POWER
, 5000); /* uS */
934 static int iwl3945_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
936 iwl_write_direct32(priv
, FH39_RCSR_RBD_BASE(0), rxq
->dma_addr
);
937 iwl_write_direct32(priv
, FH39_RCSR_RPTR_ADDR(0), rxq
->rb_stts_dma
);
938 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), 0);
939 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0),
940 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE
|
941 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE
|
942 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN
|
943 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128
|
944 (RX_QUEUE_SIZE_LOG
<< FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE
) |
945 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST
|
946 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH
) |
947 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH
);
949 /* fake read to flush all prev I/O */
950 iwl_read_direct32(priv
, FH39_RSSR_CTRL
);
955 static int iwl3945_tx_reset(struct iwl_priv
*priv
)
959 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0x2);
962 iwl_write_prph(priv
, ALM_SCD_ARASTAT_REG
, 0x01);
964 /* all 6 fifo are active */
965 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0x3f);
967 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_1_REG
, 0x010000);
968 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_2_REG
, 0x030002);
969 iwl_write_prph(priv
, ALM_SCD_TXF4MF_REG
, 0x000004);
970 iwl_write_prph(priv
, ALM_SCD_TXF5MF_REG
, 0x000005);
972 iwl_write_direct32(priv
, FH39_TSSR_CBB_BASE
,
973 priv
->_3945
.shared_phys
);
975 iwl_write_direct32(priv
, FH39_TSSR_MSG_CONFIG
,
976 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON
|
977 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON
|
978 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B
|
979 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON
|
980 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON
|
981 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH
|
982 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH
);
989 * iwl3945_txq_ctx_reset - Reset TX queue context
991 * Destroys all DMA structures and initialize them again
993 static int iwl3945_txq_ctx_reset(struct iwl_priv
*priv
)
996 int txq_id
, slots_num
;
998 iwl3945_hw_txq_ctx_free(priv
);
1000 /* allocate tx queue structure */
1001 rc
= iwl_alloc_txq_mem(priv
);
1006 rc
= iwl3945_tx_reset(priv
);
1011 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
1012 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
1013 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
1014 rc
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
1017 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
1025 iwl3945_hw_txq_ctx_free(priv
);
1031 * Start up 3945's basic functionality after it has been reset
1032 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1033 * NOTE: This does not load uCode nor start the embedded processor
1035 static int iwl3945_apm_init(struct iwl_priv
*priv
)
1037 int ret
= iwl_apm_init(priv
);
1039 /* Clear APMG (NIC's internal power management) interrupts */
1040 iwl_write_prph(priv
, APMG_RTC_INT_MSK_REG
, 0x0);
1041 iwl_write_prph(priv
, APMG_RTC_INT_STT_REG
, 0xFFFFFFFF);
1043 /* Reset radio chip */
1044 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
1046 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
1051 static void iwl3945_nic_config(struct iwl_priv
*priv
)
1053 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1054 unsigned long flags
;
1057 spin_lock_irqsave(&priv
->lock
, flags
);
1059 /* Determine HW type */
1060 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &rev_id
);
1062 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", rev_id
);
1064 if (rev_id
& PCI_CFG_REV_ID_BIT_RTP
)
1065 IWL_DEBUG_INFO(priv
, "RTP type\n");
1066 else if (rev_id
& PCI_CFG_REV_ID_BIT_BASIC_SKU
) {
1067 IWL_DEBUG_INFO(priv
, "3945 RADIO-MB type\n");
1068 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1069 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB
);
1071 IWL_DEBUG_INFO(priv
, "3945 RADIO-MM type\n");
1072 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1073 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM
);
1076 if (EEPROM_SKU_CAP_OP_MODE_MRC
== eeprom
->sku_cap
) {
1077 IWL_DEBUG_INFO(priv
, "SKU OP mode is mrc\n");
1078 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1079 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC
);
1081 IWL_DEBUG_INFO(priv
, "SKU OP mode is basic\n");
1083 if ((eeprom
->board_revision
& 0xF0) == 0xD0) {
1084 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1085 eeprom
->board_revision
);
1086 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1087 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1089 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1090 eeprom
->board_revision
);
1091 iwl_clear_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1092 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1095 if (eeprom
->almgor_m_version
<= 1) {
1096 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1097 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A
);
1098 IWL_DEBUG_INFO(priv
, "Card M type A version is 0x%X\n",
1099 eeprom
->almgor_m_version
);
1101 IWL_DEBUG_INFO(priv
, "Card M type B version is 0x%X\n",
1102 eeprom
->almgor_m_version
);
1103 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1104 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B
);
1106 spin_unlock_irqrestore(&priv
->lock
, flags
);
1108 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_SW_RF_KILL_ENABLE
)
1109 IWL_DEBUG_RF_KILL(priv
, "SW RF KILL supported in EEPROM.\n");
1111 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_HW_RF_KILL_ENABLE
)
1112 IWL_DEBUG_RF_KILL(priv
, "HW RF KILL supported in EEPROM.\n");
1115 int iwl3945_hw_nic_init(struct iwl_priv
*priv
)
1118 unsigned long flags
;
1119 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
1121 spin_lock_irqsave(&priv
->lock
, flags
);
1122 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
1123 spin_unlock_irqrestore(&priv
->lock
, flags
);
1125 rc
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
1129 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
1131 /* Allocate the RX queue, or reset if it is already allocated */
1133 rc
= iwl_rx_queue_alloc(priv
);
1135 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
1139 iwl3945_rx_queue_reset(priv
, rxq
);
1141 iwl3945_rx_replenish(priv
);
1143 iwl3945_rx_init(priv
, rxq
);
1146 /* Look at using this instead:
1147 rxq->need_update = 1;
1148 iwl_rx_queue_update_write_ptr(priv, rxq);
1151 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), rxq
->write
& ~7);
1153 rc
= iwl3945_txq_ctx_reset(priv
);
1157 set_bit(STATUS_INIT
, &priv
->status
);
1163 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1165 * Destroy all TX DMA queues and structures
1167 void iwl3945_hw_txq_ctx_free(struct iwl_priv
*priv
)
1173 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
;
1175 if (txq_id
== IWL_CMD_QUEUE_NUM
)
1176 iwl_cmd_queue_free(priv
);
1178 iwl_tx_queue_free(priv
, txq_id
);
1180 /* free tx queue structure */
1181 iwl_free_txq_mem(priv
);
1184 void iwl3945_hw_txq_ctx_stop(struct iwl_priv
*priv
)
1189 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0);
1190 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0);
1192 /* reset TFD queues */
1193 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
1194 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
), 0x0);
1195 iwl_poll_direct_bit(priv
, FH39_TSSR_TX_STATUS
,
1196 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id
),
1200 iwl3945_hw_txq_ctx_free(priv
);
1204 * iwl3945_hw_reg_adjust_power_by_temp
1205 * return index delta into power gain settings table
1207 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading
, int old_reading
)
1209 return (new_reading
- old_reading
) * (-11) / 100;
1213 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1215 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature
)
1217 return ((temperature
< -260) || (temperature
> 25)) ? 1 : 0;
1220 int iwl3945_hw_get_temperature(struct iwl_priv
*priv
)
1222 return iwl_read32(priv
, CSR_UCODE_DRV_GP2
);
1226 * iwl3945_hw_reg_txpower_get_temperature
1227 * get the current temperature by reading from NIC
1229 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv
*priv
)
1231 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1234 temperature
= iwl3945_hw_get_temperature(priv
);
1236 /* driver's okay range is -260 to +25.
1237 * human readable okay range is 0 to +285 */
1238 IWL_DEBUG_INFO(priv
, "Temperature: %d\n", temperature
+ IWL_TEMP_CONVERT
);
1240 /* handle insane temp reading */
1241 if (iwl3945_hw_reg_temp_out_of_range(temperature
)) {
1242 IWL_ERR(priv
, "Error bad temperature value %d\n", temperature
);
1244 /* if really really hot(?),
1245 * substitute the 3rd band/group's temp measured at factory */
1246 if (priv
->last_temperature
> 100)
1247 temperature
= eeprom
->groups
[2].temperature
;
1248 else /* else use most recent "sane" value from driver */
1249 temperature
= priv
->last_temperature
;
1252 return temperature
; /* raw, not "human readable" */
1255 /* Adjust Txpower only if temperature variance is greater than threshold.
1257 * Both are lower than older versions' 9 degrees */
1258 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1261 * is_temp_calib_needed - determines if new calibration is needed
1263 * records new temperature in tx_mgr->temperature.
1264 * replaces tx_mgr->last_temperature *only* if calib needed
1265 * (assumes caller will actually do the calibration!). */
1266 static int is_temp_calib_needed(struct iwl_priv
*priv
)
1270 priv
->temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
1271 temp_diff
= priv
->temperature
- priv
->last_temperature
;
1273 /* get absolute value */
1274 if (temp_diff
< 0) {
1275 IWL_DEBUG_POWER(priv
, "Getting cooler, delta %d,\n", temp_diff
);
1276 temp_diff
= -temp_diff
;
1277 } else if (temp_diff
== 0)
1278 IWL_DEBUG_POWER(priv
, "Same temp,\n");
1280 IWL_DEBUG_POWER(priv
, "Getting warmer, delta %d,\n", temp_diff
);
1282 /* if we don't need calibration, *don't* update last_temperature */
1283 if (temp_diff
< IWL_TEMPERATURE_LIMIT_TIMER
) {
1284 IWL_DEBUG_POWER(priv
, "Timed thermal calib not needed\n");
1288 IWL_DEBUG_POWER(priv
, "Timed thermal calib needed\n");
1290 /* assume that caller will actually do calib ...
1291 * update the "last temperature" value */
1292 priv
->last_temperature
= priv
->temperature
;
1296 #define IWL_MAX_GAIN_ENTRIES 78
1297 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1298 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1300 /* radio and DSP power table, each step is 1/2 dB.
1301 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1302 static struct iwl3945_tx_power power_gain_table
[2][IWL_MAX_GAIN_ENTRIES
] = {
1304 {251, 127}, /* 2.4 GHz, highest power */
1381 {3, 95} }, /* 2.4 GHz, lowest power */
1383 {251, 127}, /* 5.x GHz, highest power */
1460 {3, 120} } /* 5.x GHz, lowest power */
1463 static inline u8
iwl3945_hw_reg_fix_power_index(int index
)
1467 if (index
>= IWL_MAX_GAIN_ENTRIES
)
1468 return IWL_MAX_GAIN_ENTRIES
- 1;
1472 /* Kick off thermal recalibration check every 60 seconds */
1473 #define REG_RECALIB_PERIOD (60)
1476 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1478 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1479 * or 6 Mbit (OFDM) rates.
1481 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv
*priv
, u32 scan_tbl_index
,
1482 s32 rate_index
, const s8
*clip_pwrs
,
1483 struct iwl_channel_info
*ch_info
,
1486 struct iwl3945_scan_power_info
*scan_power_info
;
1490 scan_power_info
= &ch_info
->scan_pwr_info
[scan_tbl_index
];
1492 /* use this channel group's 6Mbit clipping/saturation pwr,
1493 * but cap at regulatory scan power restriction (set during init
1494 * based on eeprom channel data) for this channel. */
1495 power
= min(ch_info
->scan_power
, clip_pwrs
[IWL_RATE_6M_INDEX_TABLE
]);
1497 /* further limit to user's max power preference.
1498 * FIXME: Other spectrum management power limitations do not
1499 * seem to apply?? */
1500 power
= min(power
, priv
->tx_power_user_lmt
);
1501 scan_power_info
->requested_power
= power
;
1503 /* find difference between new scan *power* and current "normal"
1504 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1505 * current "normal" temperature-compensated Tx power *index* for
1506 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1508 power_index
= ch_info
->power_info
[rate_index
].power_table_index
1509 - (power
- ch_info
->power_info
1510 [IWL_RATE_6M_INDEX_TABLE
].requested_power
) * 2;
1512 /* store reference index that we use when adjusting *all* scan
1513 * powers. So we can accommodate user (all channel) or spectrum
1514 * management (single channel) power changes "between" temperature
1515 * feedback compensation procedures.
1516 * don't force fit this reference index into gain table; it may be a
1517 * negative number. This will help avoid errors when we're at
1518 * the lower bounds (highest gains, for warmest temperatures)
1521 /* don't exceed table bounds for "real" setting */
1522 power_index
= iwl3945_hw_reg_fix_power_index(power_index
);
1524 scan_power_info
->power_table_index
= power_index
;
1525 scan_power_info
->tpc
.tx_gain
=
1526 power_gain_table
[band_index
][power_index
].tx_gain
;
1527 scan_power_info
->tpc
.dsp_atten
=
1528 power_gain_table
[band_index
][power_index
].dsp_atten
;
1532 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1534 * Configures power settings for all rates for the current channel,
1535 * using values from channel info struct, and send to NIC
1537 static int iwl3945_send_tx_power(struct iwl_priv
*priv
)
1540 const struct iwl_channel_info
*ch_info
= NULL
;
1541 struct iwl3945_txpowertable_cmd txpower
= {
1542 .channel
= priv
->active_rxon
.channel
,
1545 txpower
.band
= (priv
->band
== IEEE80211_BAND_5GHZ
) ? 0 : 1;
1546 ch_info
= iwl_get_channel_info(priv
,
1548 le16_to_cpu(priv
->active_rxon
.channel
));
1551 "Failed to get channel info for channel %d [%d]\n",
1552 le16_to_cpu(priv
->active_rxon
.channel
), priv
->band
);
1556 if (!is_channel_valid(ch_info
)) {
1557 IWL_DEBUG_POWER(priv
, "Not calling TX_PWR_TABLE_CMD on "
1558 "non-Tx channel.\n");
1562 /* fill cmd with power settings for all rates for current channel */
1563 /* Fill OFDM rate */
1564 for (rate_idx
= IWL_FIRST_OFDM_RATE
, i
= 0;
1565 rate_idx
<= IWL39_LAST_OFDM_RATE
; rate_idx
++, i
++) {
1567 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1568 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1570 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1571 le16_to_cpu(txpower
.channel
),
1573 txpower
.power
[i
].tpc
.tx_gain
,
1574 txpower
.power
[i
].tpc
.dsp_atten
,
1575 txpower
.power
[i
].rate
);
1577 /* Fill CCK rates */
1578 for (rate_idx
= IWL_FIRST_CCK_RATE
;
1579 rate_idx
<= IWL_LAST_CCK_RATE
; rate_idx
++, i
++) {
1580 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1581 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1583 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1584 le16_to_cpu(txpower
.channel
),
1586 txpower
.power
[i
].tpc
.tx_gain
,
1587 txpower
.power
[i
].tpc
.dsp_atten
,
1588 txpower
.power
[i
].rate
);
1591 return iwl_send_cmd_pdu(priv
, REPLY_TX_PWR_TABLE_CMD
,
1592 sizeof(struct iwl3945_txpowertable_cmd
),
1598 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1599 * @ch_info: Channel to update. Uses power_info.requested_power.
1601 * Replace requested_power and base_power_index ch_info fields for
1604 * Called if user or spectrum management changes power preferences.
1605 * Takes into account h/w and modulation limitations (clip power).
1607 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1609 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1610 * properly fill out the scan powers, and actual h/w gain settings,
1611 * and send changes to NIC
1613 static int iwl3945_hw_reg_set_new_power(struct iwl_priv
*priv
,
1614 struct iwl_channel_info
*ch_info
)
1616 struct iwl3945_channel_power_info
*power_info
;
1617 int power_changed
= 0;
1619 const s8
*clip_pwrs
;
1622 /* Get this chnlgrp's rate-to-max/clip-powers table */
1623 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1625 /* Get this channel's rate-to-current-power settings table */
1626 power_info
= ch_info
->power_info
;
1628 /* update OFDM Txpower settings */
1629 for (i
= IWL_RATE_6M_INDEX_TABLE
; i
<= IWL_RATE_54M_INDEX_TABLE
;
1630 i
++, ++power_info
) {
1633 /* limit new power to be no more than h/w capability */
1634 power
= min(ch_info
->curr_txpow
, clip_pwrs
[i
]);
1635 if (power
== power_info
->requested_power
)
1638 /* find difference between old and new requested powers,
1639 * update base (non-temp-compensated) power index */
1640 delta_idx
= (power
- power_info
->requested_power
) * 2;
1641 power_info
->base_power_index
-= delta_idx
;
1643 /* save new requested power value */
1644 power_info
->requested_power
= power
;
1649 /* update CCK Txpower settings, based on OFDM 12M setting ...
1650 * ... all CCK power settings for a given channel are the *same*. */
1651 if (power_changed
) {
1653 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1654 requested_power
+ IWL_CCK_FROM_OFDM_POWER_DIFF
;
1656 /* do all CCK rates' iwl3945_channel_power_info structures */
1657 for (i
= IWL_RATE_1M_INDEX_TABLE
; i
<= IWL_RATE_11M_INDEX_TABLE
; i
++) {
1658 power_info
->requested_power
= power
;
1659 power_info
->base_power_index
=
1660 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1661 base_power_index
+ IWL_CCK_FROM_OFDM_INDEX_DIFF
;
1670 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1672 * NOTE: Returned power limit may be less (but not more) than requested,
1673 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1674 * (no consideration for h/w clipping limitations).
1676 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info
*ch_info
)
1681 /* if we're using TGd limits, use lower of TGd or EEPROM */
1682 if (ch_info
->tgd_data
.max_power
!= 0)
1683 max_power
= min(ch_info
->tgd_data
.max_power
,
1684 ch_info
->eeprom
.max_power_avg
);
1686 /* else just use EEPROM limits */
1689 max_power
= ch_info
->eeprom
.max_power_avg
;
1691 return min(max_power
, ch_info
->max_power_avg
);
1695 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1697 * Compensate txpower settings of *all* channels for temperature.
1698 * This only accounts for the difference between current temperature
1699 * and the factory calibration temperatures, and bases the new settings
1700 * on the channel's base_power_index.
1702 * If RxOn is "associated", this sends the new Txpower to NIC!
1704 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv
*priv
)
1706 struct iwl_channel_info
*ch_info
= NULL
;
1707 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1709 const s8
*clip_pwrs
; /* array of h/w max power levels for each rate */
1715 int temperature
= priv
->temperature
;
1717 if (priv
->disable_tx_power_cal
||
1718 test_bit(STATUS_SCANNING
, &priv
->status
)) {
1719 /* do not perform tx power calibration */
1722 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1723 for (i
= 0; i
< priv
->channel_count
; i
++) {
1724 ch_info
= &priv
->channel_info
[i
];
1725 a_band
= is_channel_a_band(ch_info
);
1727 /* Get this chnlgrp's factory calibration temperature */
1728 ref_temp
= (s16
)eeprom
->groups
[ch_info
->group_index
].
1731 /* get power index adjustment based on current and factory
1733 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
1736 /* set tx power value for all rates, OFDM and CCK */
1737 for (rate_index
= 0; rate_index
< IWL_RATE_COUNT
;
1740 ch_info
->power_info
[rate_index
].base_power_index
;
1742 /* temperature compensate */
1743 power_idx
+= delta_index
;
1745 /* stay within table range */
1746 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
1747 ch_info
->power_info
[rate_index
].
1748 power_table_index
= (u8
) power_idx
;
1749 ch_info
->power_info
[rate_index
].tpc
=
1750 power_gain_table
[a_band
][power_idx
];
1753 /* Get this chnlgrp's rate-to-max/clip-powers table */
1754 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1756 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1757 for (scan_tbl_index
= 0;
1758 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
1759 s32 actual_index
= (scan_tbl_index
== 0) ?
1760 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
1761 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
1762 actual_index
, clip_pwrs
,
1767 /* send Txpower command for current channel to ucode */
1768 return priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1771 int iwl3945_hw_reg_set_txpower(struct iwl_priv
*priv
, s8 power
)
1773 struct iwl_channel_info
*ch_info
;
1778 if (priv
->tx_power_user_lmt
== power
) {
1779 IWL_DEBUG_POWER(priv
, "Requested Tx power same as current "
1780 "limit: %ddBm.\n", power
);
1784 IWL_DEBUG_POWER(priv
, "Setting upper limit clamp to %ddBm.\n", power
);
1785 priv
->tx_power_user_lmt
= power
;
1787 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1789 for (i
= 0; i
< priv
->channel_count
; i
++) {
1790 ch_info
= &priv
->channel_info
[i
];
1791 a_band
= is_channel_a_band(ch_info
);
1793 /* find minimum power of all user and regulatory constraints
1794 * (does not consider h/w clipping limitations) */
1795 max_power
= iwl3945_hw_reg_get_ch_txpower_limit(ch_info
);
1796 max_power
= min(power
, max_power
);
1797 if (max_power
!= ch_info
->curr_txpow
) {
1798 ch_info
->curr_txpow
= max_power
;
1800 /* this considers the h/w clipping limitations */
1801 iwl3945_hw_reg_set_new_power(priv
, ch_info
);
1805 /* update txpower settings for all channels,
1806 * send to NIC if associated. */
1807 is_temp_calib_needed(priv
);
1808 iwl3945_hw_reg_comp_txpower_temp(priv
);
1813 static int iwl3945_send_rxon_assoc(struct iwl_priv
*priv
)
1816 struct iwl_rx_packet
*pkt
;
1817 struct iwl3945_rxon_assoc_cmd rxon_assoc
;
1818 struct iwl_host_cmd cmd
= {
1819 .id
= REPLY_RXON_ASSOC
,
1820 .len
= sizeof(rxon_assoc
),
1821 .flags
= CMD_WANT_SKB
,
1822 .data
= &rxon_assoc
,
1824 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1825 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1827 if ((rxon1
->flags
== rxon2
->flags
) &&
1828 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1829 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1830 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1831 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1835 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1836 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1837 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1838 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1839 rxon_assoc
.reserved
= 0;
1841 rc
= iwl_send_cmd_sync(priv
, &cmd
);
1845 pkt
= (struct iwl_rx_packet
*)cmd
.reply_page
;
1846 if (pkt
->hdr
.flags
& IWL_CMD_FAILED_MSK
) {
1847 IWL_ERR(priv
, "Bad return from REPLY_RXON_ASSOC command\n");
1851 iwl_free_pages(priv
, cmd
.reply_page
);
1857 * iwl3945_commit_rxon - commit staging_rxon to hardware
1859 * The RXON command in staging_rxon is committed to the hardware and
1860 * the active_rxon structure is updated with the new data. This
1861 * function correctly transitions out of the RXON_ASSOC_MSK state if
1862 * a HW tune is required based on the RXON structure changes.
1864 static int iwl3945_commit_rxon(struct iwl_priv
*priv
)
1866 /* cast away the const for active_rxon in this function */
1867 struct iwl3945_rxon_cmd
*active_rxon
= (void *)&priv
->active_rxon
;
1868 struct iwl3945_rxon_cmd
*staging_rxon
= (void *)&priv
->staging_rxon
;
1871 !!(priv
->staging_rxon
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
1873 if (!iwl_is_alive(priv
))
1876 /* always get timestamp with Rx frame */
1877 staging_rxon
->flags
|= RXON_FLG_TSF2HOST_MSK
;
1879 /* select antenna */
1880 staging_rxon
->flags
&=
1881 ~(RXON_FLG_DIS_DIV_MSK
| RXON_FLG_ANT_SEL_MSK
);
1882 staging_rxon
->flags
|= iwl3945_get_antenna_flags(priv
);
1884 rc
= iwl_check_rxon_cmd(priv
);
1886 IWL_ERR(priv
, "Invalid RXON configuration. Not committing.\n");
1890 /* If we don't need to send a full RXON, we can use
1891 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1892 * and other flags for the current radio configuration. */
1893 if (!iwl_full_rxon_required(priv
)) {
1894 rc
= iwl_send_rxon_assoc(priv
);
1896 IWL_ERR(priv
, "Error setting RXON_ASSOC "
1897 "configuration (%d).\n", rc
);
1901 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1906 /* If we are currently associated and the new config requires
1907 * an RXON_ASSOC and the new config wants the associated mask enabled,
1908 * we must clear the associated from the active configuration
1909 * before we apply the new config */
1910 if (iwl_is_associated(priv
) && new_assoc
) {
1911 IWL_DEBUG_INFO(priv
, "Toggling associated bit on current RXON\n");
1912 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
1915 * reserved4 and 5 could have been filled by the iwlcore code.
1916 * Let's clear them before pushing to the 3945.
1918 active_rxon
->reserved4
= 0;
1919 active_rxon
->reserved5
= 0;
1920 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1921 sizeof(struct iwl3945_rxon_cmd
),
1922 &priv
->active_rxon
);
1924 /* If the mask clearing failed then we set
1925 * active_rxon back to what it was previously */
1927 active_rxon
->filter_flags
|= RXON_FILTER_ASSOC_MSK
;
1928 IWL_ERR(priv
, "Error clearing ASSOC_MSK on current "
1929 "configuration (%d).\n", rc
);
1932 iwl_clear_ucode_stations(priv
, false);
1933 iwl_restore_stations(priv
);
1936 IWL_DEBUG_INFO(priv
, "Sending RXON\n"
1937 "* with%s RXON_FILTER_ASSOC_MSK\n"
1940 (new_assoc
? "" : "out"),
1941 le16_to_cpu(staging_rxon
->channel
),
1942 staging_rxon
->bssid_addr
);
1945 * reserved4 and 5 could have been filled by the iwlcore code.
1946 * Let's clear them before pushing to the 3945.
1948 staging_rxon
->reserved4
= 0;
1949 staging_rxon
->reserved5
= 0;
1951 iwl_set_rxon_hwcrypto(priv
, !iwl3945_mod_params
.sw_crypto
);
1953 /* Apply the new configuration */
1954 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1955 sizeof(struct iwl3945_rxon_cmd
),
1958 IWL_ERR(priv
, "Error setting new configuration (%d).\n", rc
);
1962 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1965 iwl_clear_ucode_stations(priv
, false);
1966 iwl_restore_stations(priv
);
1969 /* If we issue a new RXON command which required a tune then we must
1970 * send a new TXPOWER command or we won't be able to Tx any frames */
1971 rc
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1973 IWL_ERR(priv
, "Error setting Tx power (%d).\n", rc
);
1977 /* Init the hardware's rate fallback order based on the band */
1978 rc
= iwl3945_init_hw_rate_table(priv
);
1980 IWL_ERR(priv
, "Error setting HW rate table: %02X\n", rc
);
1988 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1990 * -- reset periodic timer
1991 * -- see if temp has changed enough to warrant re-calibration ... if so:
1992 * -- correct coeffs for temp (can reset temp timer)
1993 * -- save this temp as "last",
1994 * -- send new set of gain settings to NIC
1995 * NOTE: This should continue working, even when we're not associated,
1996 * so we can keep our internal table of scan powers current. */
1997 void iwl3945_reg_txpower_periodic(struct iwl_priv
*priv
)
1999 /* This will kick in the "brute force"
2000 * iwl3945_hw_reg_comp_txpower_temp() below */
2001 if (!is_temp_calib_needed(priv
))
2004 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2005 * This is based *only* on current temperature,
2006 * ignoring any previous power measurements */
2007 iwl3945_hw_reg_comp_txpower_temp(priv
);
2010 queue_delayed_work(priv
->workqueue
,
2011 &priv
->_3945
.thermal_periodic
, REG_RECALIB_PERIOD
* HZ
);
2014 static void iwl3945_bg_reg_txpower_periodic(struct work_struct
*work
)
2016 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
2017 _3945
.thermal_periodic
.work
);
2019 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2022 mutex_lock(&priv
->mutex
);
2023 iwl3945_reg_txpower_periodic(priv
);
2024 mutex_unlock(&priv
->mutex
);
2028 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2031 * This function is used when initializing channel-info structs.
2033 * NOTE: These channel groups do *NOT* match the bands above!
2034 * These channel groups are based on factory-tested channels;
2035 * on A-band, EEPROM's "group frequency" entries represent the top
2036 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2038 static u16
iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv
*priv
,
2039 const struct iwl_channel_info
*ch_info
)
2041 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2042 struct iwl3945_eeprom_txpower_group
*ch_grp
= &eeprom
->groups
[0];
2044 u16 group_index
= 0; /* based on factory calib frequencies */
2047 /* Find the group index for the channel ... don't use index 1(?) */
2048 if (is_channel_a_band(ch_info
)) {
2049 for (group
= 1; group
< 5; group
++) {
2050 grp_channel
= ch_grp
[group
].group_channel
;
2051 if (ch_info
->channel
<= grp_channel
) {
2052 group_index
= group
;
2056 /* group 4 has a few channels *above* its factory cal freq */
2060 group_index
= 0; /* 2.4 GHz, group 0 */
2062 IWL_DEBUG_POWER(priv
, "Chnl %d mapped to grp %d\n", ch_info
->channel
,
2068 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2070 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2071 * into radio/DSP gain settings table for requested power.
2073 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv
*priv
,
2075 s32 setting_index
, s32
*new_index
)
2077 const struct iwl3945_eeprom_txpower_group
*chnl_grp
= NULL
;
2078 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2080 s32 power
= 2 * requested_power
;
2082 const struct iwl3945_eeprom_txpower_sample
*samples
;
2087 chnl_grp
= &eeprom
->groups
[setting_index
];
2088 samples
= chnl_grp
->samples
;
2089 for (i
= 0; i
< 5; i
++) {
2090 if (power
== samples
[i
].power
) {
2091 *new_index
= samples
[i
].gain_index
;
2096 if (power
> samples
[1].power
) {
2099 } else if (power
> samples
[2].power
) {
2102 } else if (power
> samples
[3].power
) {
2110 denominator
= (s32
) samples
[index1
].power
- (s32
) samples
[index0
].power
;
2111 if (denominator
== 0)
2113 gains0
= (s32
) samples
[index0
].gain_index
* (1 << 19);
2114 gains1
= (s32
) samples
[index1
].gain_index
* (1 << 19);
2115 res
= gains0
+ (gains1
- gains0
) *
2116 ((s32
) power
- (s32
) samples
[index0
].power
) / denominator
+
2118 *new_index
= res
>> 19;
2122 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv
*priv
)
2126 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2127 const struct iwl3945_eeprom_txpower_group
*group
;
2129 IWL_DEBUG_POWER(priv
, "Initializing factory calib info from EEPROM\n");
2131 for (i
= 0; i
< IWL_NUM_TX_CALIB_GROUPS
; i
++) {
2132 s8
*clip_pwrs
; /* table of power levels for each rate */
2133 s8 satur_pwr
; /* saturation power for each chnl group */
2134 group
= &eeprom
->groups
[i
];
2136 /* sanity check on factory saturation power value */
2137 if (group
->saturation_power
< 40) {
2138 IWL_WARN(priv
, "Error: saturation power is %d, "
2139 "less than minimum expected 40\n",
2140 group
->saturation_power
);
2145 * Derive requested power levels for each rate, based on
2146 * hardware capabilities (saturation power for band).
2147 * Basic value is 3dB down from saturation, with further
2148 * power reductions for highest 3 data rates. These
2149 * backoffs provide headroom for high rate modulation
2150 * power peaks, without too much distortion (clipping).
2152 /* we'll fill in this array with h/w max power levels */
2153 clip_pwrs
= (s8
*) priv
->_3945
.clip_groups
[i
].clip_powers
;
2155 /* divide factory saturation power by 2 to find -3dB level */
2156 satur_pwr
= (s8
) (group
->saturation_power
>> 1);
2158 /* fill in channel group's nominal powers for each rate */
2159 for (rate_index
= 0;
2160 rate_index
< IWL_RATE_COUNT_3945
; rate_index
++, clip_pwrs
++) {
2161 switch (rate_index
) {
2162 case IWL_RATE_36M_INDEX_TABLE
:
2163 if (i
== 0) /* B/G */
2164 *clip_pwrs
= satur_pwr
;
2166 *clip_pwrs
= satur_pwr
- 5;
2168 case IWL_RATE_48M_INDEX_TABLE
:
2170 *clip_pwrs
= satur_pwr
- 7;
2172 *clip_pwrs
= satur_pwr
- 10;
2174 case IWL_RATE_54M_INDEX_TABLE
:
2176 *clip_pwrs
= satur_pwr
- 9;
2178 *clip_pwrs
= satur_pwr
- 12;
2181 *clip_pwrs
= satur_pwr
;
2189 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2191 * Second pass (during init) to set up priv->channel_info
2193 * Set up Tx-power settings in our channel info database for each VALID
2194 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2195 * and current temperature.
2197 * Since this is based on current temperature (at init time), these values may
2198 * not be valid for very long, but it gives us a starting/default point,
2199 * and allows us to active (i.e. using Tx) scan.
2201 * This does *not* write values to NIC, just sets up our internal table.
2203 int iwl3945_txpower_set_from_eeprom(struct iwl_priv
*priv
)
2205 struct iwl_channel_info
*ch_info
= NULL
;
2206 struct iwl3945_channel_power_info
*pwr_info
;
2207 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2211 const s8
*clip_pwrs
; /* array of power levels for each rate */
2214 u8 pwr_index
, base_pwr_index
, a_band
;
2218 /* save temperature reference,
2219 * so we can determine next time to calibrate */
2220 temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
2221 priv
->last_temperature
= temperature
;
2223 iwl3945_hw_reg_init_channel_groups(priv
);
2225 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2226 for (i
= 0, ch_info
= priv
->channel_info
; i
< priv
->channel_count
;
2228 a_band
= is_channel_a_band(ch_info
);
2229 if (!is_channel_valid(ch_info
))
2232 /* find this channel's channel group (*not* "band") index */
2233 ch_info
->group_index
=
2234 iwl3945_hw_reg_get_ch_grp_index(priv
, ch_info
);
2236 /* Get this chnlgrp's rate->max/clip-powers table */
2237 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
2239 /* calculate power index *adjustment* value according to
2240 * diff between current temperature and factory temperature */
2241 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
2242 eeprom
->groups
[ch_info
->group_index
].
2245 IWL_DEBUG_POWER(priv
, "Delta index for channel %d: %d [%d]\n",
2246 ch_info
->channel
, delta_index
, temperature
+
2249 /* set tx power value for all OFDM rates */
2250 for (rate_index
= 0; rate_index
< IWL_OFDM_RATES
;
2252 s32
uninitialized_var(power_idx
);
2255 /* use channel group's clip-power table,
2256 * but don't exceed channel's max power */
2257 s8 pwr
= min(ch_info
->max_power_avg
,
2258 clip_pwrs
[rate_index
]);
2260 pwr_info
= &ch_info
->power_info
[rate_index
];
2262 /* get base (i.e. at factory-measured temperature)
2263 * power table index for this rate's power */
2264 rc
= iwl3945_hw_reg_get_matched_power_index(priv
, pwr
,
2265 ch_info
->group_index
,
2268 IWL_ERR(priv
, "Invalid power index\n");
2271 pwr_info
->base_power_index
= (u8
) power_idx
;
2273 /* temperature compensate */
2274 power_idx
+= delta_index
;
2276 /* stay within range of gain table */
2277 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
2279 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2280 pwr_info
->requested_power
= pwr
;
2281 pwr_info
->power_table_index
= (u8
) power_idx
;
2282 pwr_info
->tpc
.tx_gain
=
2283 power_gain_table
[a_band
][power_idx
].tx_gain
;
2284 pwr_info
->tpc
.dsp_atten
=
2285 power_gain_table
[a_band
][power_idx
].dsp_atten
;
2288 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2289 pwr_info
= &ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
];
2290 power
= pwr_info
->requested_power
+
2291 IWL_CCK_FROM_OFDM_POWER_DIFF
;
2292 pwr_index
= pwr_info
->power_table_index
+
2293 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2294 base_pwr_index
= pwr_info
->base_power_index
+
2295 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2297 /* stay within table range */
2298 pwr_index
= iwl3945_hw_reg_fix_power_index(pwr_index
);
2299 gain
= power_gain_table
[a_band
][pwr_index
].tx_gain
;
2300 dsp_atten
= power_gain_table
[a_band
][pwr_index
].dsp_atten
;
2302 /* fill each CCK rate's iwl3945_channel_power_info structure
2303 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2304 * NOTE: CCK rates start at end of OFDM rates! */
2305 for (rate_index
= 0;
2306 rate_index
< IWL_CCK_RATES
; rate_index
++) {
2307 pwr_info
= &ch_info
->power_info
[rate_index
+IWL_OFDM_RATES
];
2308 pwr_info
->requested_power
= power
;
2309 pwr_info
->power_table_index
= pwr_index
;
2310 pwr_info
->base_power_index
= base_pwr_index
;
2311 pwr_info
->tpc
.tx_gain
= gain
;
2312 pwr_info
->tpc
.dsp_atten
= dsp_atten
;
2315 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2316 for (scan_tbl_index
= 0;
2317 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
2318 s32 actual_index
= (scan_tbl_index
== 0) ?
2319 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
2320 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
2321 actual_index
, clip_pwrs
, ch_info
, a_band
);
2328 int iwl3945_hw_rxq_stop(struct iwl_priv
*priv
)
2332 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0), 0);
2333 rc
= iwl_poll_direct_bit(priv
, FH39_RSSR_STATUS
,
2334 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
2336 IWL_ERR(priv
, "Can't stop Rx DMA.\n");
2341 int iwl3945_hw_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
2343 int txq_id
= txq
->q
.id
;
2345 struct iwl3945_shared
*shared_data
= priv
->_3945
.shared_virt
;
2347 shared_data
->tx_base_ptr
[txq_id
] = cpu_to_le32((u32
)txq
->q
.dma_addr
);
2349 iwl_write_direct32(priv
, FH39_CBCC_CTRL(txq_id
), 0);
2350 iwl_write_direct32(priv
, FH39_CBCC_BASE(txq_id
), 0);
2352 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
),
2353 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
|
2354 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
|
2355 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
|
2356 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
2357 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
);
2359 /* fake read to flush all prev. writes */
2360 iwl_read32(priv
, FH39_TSSR_CBB_BASE
);
2368 static u16
iwl3945_get_hcmd_size(u8 cmd_id
, u16 len
)
2372 return sizeof(struct iwl3945_rxon_cmd
);
2373 case POWER_TABLE_CMD
:
2374 return sizeof(struct iwl3945_powertable_cmd
);
2381 static u16
iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
2383 struct iwl3945_addsta_cmd
*addsta
= (struct iwl3945_addsta_cmd
*)data
;
2384 addsta
->mode
= cmd
->mode
;
2385 memcpy(&addsta
->sta
, &cmd
->sta
, sizeof(struct sta_id_modify
));
2386 memcpy(&addsta
->key
, &cmd
->key
, sizeof(struct iwl4965_keyinfo
));
2387 addsta
->station_flags
= cmd
->station_flags
;
2388 addsta
->station_flags_msk
= cmd
->station_flags_msk
;
2389 addsta
->tid_disable_tx
= cpu_to_le16(0);
2390 addsta
->rate_n_flags
= cmd
->rate_n_flags
;
2391 addsta
->add_immediate_ba_tid
= cmd
->add_immediate_ba_tid
;
2392 addsta
->remove_immediate_ba_tid
= cmd
->remove_immediate_ba_tid
;
2393 addsta
->add_immediate_ba_ssn
= cmd
->add_immediate_ba_ssn
;
2395 return (u16
)sizeof(struct iwl3945_addsta_cmd
);
2400 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2402 int iwl3945_init_hw_rate_table(struct iwl_priv
*priv
)
2404 int rc
, i
, index
, prev_index
;
2405 struct iwl3945_rate_scaling_cmd rate_cmd
= {
2406 .reserved
= {0, 0, 0},
2408 struct iwl3945_rate_scaling_info
*table
= rate_cmd
.table
;
2410 for (i
= 0; i
< ARRAY_SIZE(iwl3945_rates
); i
++) {
2411 index
= iwl3945_rates
[i
].table_rs_index
;
2413 table
[index
].rate_n_flags
=
2414 iwl3945_hw_set_rate_n_flags(iwl3945_rates
[i
].plcp
, 0);
2415 table
[index
].try_cnt
= priv
->retry_rate
;
2416 prev_index
= iwl3945_get_prev_ieee_rate(i
);
2417 table
[index
].next_rate_index
=
2418 iwl3945_rates
[prev_index
].table_rs_index
;
2421 switch (priv
->band
) {
2422 case IEEE80211_BAND_5GHZ
:
2423 IWL_DEBUG_RATE(priv
, "Select A mode rate scale\n");
2424 /* If one of the following CCK rates is used,
2425 * have it fall back to the 6M OFDM rate */
2426 for (i
= IWL_RATE_1M_INDEX_TABLE
;
2427 i
<= IWL_RATE_11M_INDEX_TABLE
; i
++)
2428 table
[i
].next_rate_index
=
2429 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2431 /* Don't fall back to CCK rates */
2432 table
[IWL_RATE_12M_INDEX_TABLE
].next_rate_index
=
2433 IWL_RATE_9M_INDEX_TABLE
;
2435 /* Don't drop out of OFDM rates */
2436 table
[IWL_RATE_6M_INDEX_TABLE
].next_rate_index
=
2437 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2440 case IEEE80211_BAND_2GHZ
:
2441 IWL_DEBUG_RATE(priv
, "Select B/G mode rate scale\n");
2442 /* If an OFDM rate is used, have it fall back to the
2445 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
2446 iwl_is_associated(priv
)) {
2448 index
= IWL_FIRST_CCK_RATE
;
2449 for (i
= IWL_RATE_6M_INDEX_TABLE
;
2450 i
<= IWL_RATE_54M_INDEX_TABLE
; i
++)
2451 table
[i
].next_rate_index
=
2452 iwl3945_rates
[index
].table_rs_index
;
2454 index
= IWL_RATE_11M_INDEX_TABLE
;
2455 /* CCK shouldn't fall back to OFDM... */
2456 table
[index
].next_rate_index
= IWL_RATE_5M_INDEX_TABLE
;
2465 /* Update the rate scaling for control frame Tx */
2466 rate_cmd
.table_id
= 0;
2467 rc
= iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2472 /* Update the rate scaling for data frame Tx */
2473 rate_cmd
.table_id
= 1;
2474 return iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2478 /* Called when initializing driver */
2479 int iwl3945_hw_set_hw_params(struct iwl_priv
*priv
)
2481 memset((void *)&priv
->hw_params
, 0,
2482 sizeof(struct iwl_hw_params
));
2484 priv
->_3945
.shared_virt
=
2485 dma_alloc_coherent(&priv
->pci_dev
->dev
,
2486 sizeof(struct iwl3945_shared
),
2487 &priv
->_3945
.shared_phys
, GFP_KERNEL
);
2488 if (!priv
->_3945
.shared_virt
) {
2489 IWL_ERR(priv
, "failed to allocate pci memory\n");
2493 /* Assign number of Usable TX queues */
2494 priv
->hw_params
.max_txq_num
= priv
->cfg
->num_of_queues
;
2496 priv
->hw_params
.tfd_size
= sizeof(struct iwl3945_tfd
);
2497 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_3K
);
2498 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
2499 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
2500 priv
->hw_params
.max_stations
= IWL3945_STATION_COUNT
;
2501 priv
->hw_params
.bcast_sta_id
= IWL3945_BROADCAST_ID
;
2503 priv
->hw_params
.rx_wrt_ptr_reg
= FH39_RSCSR_CHNL0_WPTR
;
2504 priv
->hw_params
.max_beacon_itrvl
= IWL39_MAX_UCODE_BEACON_INTERVAL
;
2509 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv
*priv
,
2510 struct iwl3945_frame
*frame
, u8 rate
)
2512 struct iwl3945_tx_beacon_cmd
*tx_beacon_cmd
;
2513 unsigned int frame_size
;
2515 tx_beacon_cmd
= (struct iwl3945_tx_beacon_cmd
*)&frame
->u
;
2516 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
2518 tx_beacon_cmd
->tx
.sta_id
= priv
->hw_params
.bcast_sta_id
;
2519 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
2521 frame_size
= iwl3945_fill_beacon_frame(priv
,
2522 tx_beacon_cmd
->frame
,
2523 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
2525 BUG_ON(frame_size
> MAX_MPDU_SIZE
);
2526 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
2528 tx_beacon_cmd
->tx
.rate
= rate
;
2529 tx_beacon_cmd
->tx
.tx_flags
= (TX_CMD_FLG_SEQ_CTL_MSK
|
2530 TX_CMD_FLG_TSF_MSK
);
2532 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2533 tx_beacon_cmd
->tx
.supp_rates
[0] =
2534 (IWL_OFDM_BASIC_RATES_MASK
>> IWL_FIRST_OFDM_RATE
) & 0xFF;
2536 tx_beacon_cmd
->tx
.supp_rates
[1] =
2537 (IWL_CCK_BASIC_RATES_MASK
& 0xF);
2539 return sizeof(struct iwl3945_tx_beacon_cmd
) + frame_size
;
2542 void iwl3945_hw_rx_handler_setup(struct iwl_priv
*priv
)
2544 priv
->rx_handlers
[REPLY_TX
] = iwl3945_rx_reply_tx
;
2545 priv
->rx_handlers
[REPLY_3945_RX
] = iwl3945_rx_reply_rx
;
2548 void iwl3945_hw_setup_deferred_work(struct iwl_priv
*priv
)
2550 INIT_DELAYED_WORK(&priv
->_3945
.thermal_periodic
,
2551 iwl3945_bg_reg_txpower_periodic
);
2554 void iwl3945_hw_cancel_deferred_work(struct iwl_priv
*priv
)
2556 cancel_delayed_work(&priv
->_3945
.thermal_periodic
);
2559 /* check contents of special bootstrap uCode SRAM */
2560 static int iwl3945_verify_bsm(struct iwl_priv
*priv
)
2562 __le32
*image
= priv
->ucode_boot
.v_addr
;
2563 u32 len
= priv
->ucode_boot
.len
;
2567 IWL_DEBUG_INFO(priv
, "Begin verify bsm\n");
2569 /* verify BSM SRAM contents */
2570 val
= iwl_read_prph(priv
, BSM_WR_DWCOUNT_REG
);
2571 for (reg
= BSM_SRAM_LOWER_BOUND
;
2572 reg
< BSM_SRAM_LOWER_BOUND
+ len
;
2573 reg
+= sizeof(u32
), image
++) {
2574 val
= iwl_read_prph(priv
, reg
);
2575 if (val
!= le32_to_cpu(*image
)) {
2576 IWL_ERR(priv
, "BSM uCode verification failed at "
2577 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2578 BSM_SRAM_LOWER_BOUND
,
2579 reg
- BSM_SRAM_LOWER_BOUND
, len
,
2580 val
, le32_to_cpu(*image
));
2585 IWL_DEBUG_INFO(priv
, "BSM bootstrap uCode image OK\n");
2591 /******************************************************************************
2593 * EEPROM related functions
2595 ******************************************************************************/
2598 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2599 * embedded controller) as EEPROM reader; each read is a series of pulses
2600 * to/from the EEPROM chip, not a single event, so even reads could conflict
2601 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2602 * simply claims ownership, which should be safe when this function is called
2603 * (i.e. before loading uCode!).
2605 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv
*priv
)
2607 _iwl_clear_bit(priv
, CSR_EEPROM_GP
, CSR_EEPROM_GP_IF_OWNER_MSK
);
2612 static void iwl3945_eeprom_release_semaphore(struct iwl_priv
*priv
)
2618 * iwl3945_load_bsm - Load bootstrap instructions
2622 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2623 * in special SRAM that does not power down during RFKILL. When powering back
2624 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2625 * the bootstrap program into the on-board processor, and starts it.
2627 * The bootstrap program loads (via DMA) instructions and data for a new
2628 * program from host DRAM locations indicated by the host driver in the
2629 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2632 * When initializing the NIC, the host driver points the BSM to the
2633 * "initialize" uCode image. This uCode sets up some internal data, then
2634 * notifies host via "initialize alive" that it is complete.
2636 * The host then replaces the BSM_DRAM_* pointer values to point to the
2637 * normal runtime uCode instructions and a backup uCode data cache buffer
2638 * (filled initially with starting data values for the on-board processor),
2639 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2640 * which begins normal operation.
2642 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2643 * the backup data cache in DRAM before SRAM is powered down.
2645 * When powering back up, the BSM loads the bootstrap program. This reloads
2646 * the runtime uCode instructions and the backup data cache into SRAM,
2647 * and re-launches the runtime uCode from where it left off.
2649 static int iwl3945_load_bsm(struct iwl_priv
*priv
)
2651 __le32
*image
= priv
->ucode_boot
.v_addr
;
2652 u32 len
= priv
->ucode_boot
.len
;
2662 IWL_DEBUG_INFO(priv
, "Begin load bsm\n");
2664 /* make sure bootstrap program is no larger than BSM's SRAM size */
2665 if (len
> IWL39_MAX_BSM_SIZE
)
2668 /* Tell bootstrap uCode where to find the "Initialize" uCode
2669 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2670 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2671 * after the "initialize" uCode has run, to point to
2672 * runtime/protocol instructions and backup data cache. */
2673 pinst
= priv
->ucode_init
.p_addr
;
2674 pdata
= priv
->ucode_init_data
.p_addr
;
2675 inst_len
= priv
->ucode_init
.len
;
2676 data_len
= priv
->ucode_init_data
.len
;
2678 iwl_write_prph(priv
, BSM_DRAM_INST_PTR_REG
, pinst
);
2679 iwl_write_prph(priv
, BSM_DRAM_DATA_PTR_REG
, pdata
);
2680 iwl_write_prph(priv
, BSM_DRAM_INST_BYTECOUNT_REG
, inst_len
);
2681 iwl_write_prph(priv
, BSM_DRAM_DATA_BYTECOUNT_REG
, data_len
);
2683 /* Fill BSM memory with bootstrap instructions */
2684 for (reg_offset
= BSM_SRAM_LOWER_BOUND
;
2685 reg_offset
< BSM_SRAM_LOWER_BOUND
+ len
;
2686 reg_offset
+= sizeof(u32
), image
++)
2687 _iwl_write_prph(priv
, reg_offset
,
2688 le32_to_cpu(*image
));
2690 rc
= iwl3945_verify_bsm(priv
);
2694 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2695 iwl_write_prph(priv
, BSM_WR_MEM_SRC_REG
, 0x0);
2696 iwl_write_prph(priv
, BSM_WR_MEM_DST_REG
,
2697 IWL39_RTC_INST_LOWER_BOUND
);
2698 iwl_write_prph(priv
, BSM_WR_DWCOUNT_REG
, len
/ sizeof(u32
));
2700 /* Load bootstrap code into instruction SRAM now,
2701 * to prepare to load "initialize" uCode */
2702 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2703 BSM_WR_CTRL_REG_BIT_START
);
2705 /* Wait for load of bootstrap uCode to finish */
2706 for (i
= 0; i
< 100; i
++) {
2707 done
= iwl_read_prph(priv
, BSM_WR_CTRL_REG
);
2708 if (!(done
& BSM_WR_CTRL_REG_BIT_START
))
2713 IWL_DEBUG_INFO(priv
, "BSM write complete, poll %d iterations\n", i
);
2715 IWL_ERR(priv
, "BSM write did not complete!\n");
2719 /* Enable future boot loads whenever power management unit triggers it
2720 * (e.g. when powering back up after power-save shutdown) */
2721 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2722 BSM_WR_CTRL_REG_BIT_START_EN
);
2727 #define IWL3945_UCODE_GET(item) \
2728 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2731 return le32_to_cpu(ucode->u.v1.item); \
2734 static u32
iwl3945_ucode_get_header_size(u32 api_ver
)
2736 return UCODE_HEADER_SIZE(1);
2738 static u32
iwl3945_ucode_get_build(const struct iwl_ucode_header
*ucode
,
2743 static u8
*iwl3945_ucode_get_data(const struct iwl_ucode_header
*ucode
,
2746 return (u8
*) ucode
->u
.v1
.data
;
2749 IWL3945_UCODE_GET(inst_size
);
2750 IWL3945_UCODE_GET(data_size
);
2751 IWL3945_UCODE_GET(init_size
);
2752 IWL3945_UCODE_GET(init_data_size
);
2753 IWL3945_UCODE_GET(boot_size
);
2755 static struct iwl_hcmd_ops iwl3945_hcmd
= {
2756 .rxon_assoc
= iwl3945_send_rxon_assoc
,
2757 .commit_rxon
= iwl3945_commit_rxon
,
2758 .send_bt_config
= iwl_send_bt_config
,
2761 static struct iwl_ucode_ops iwl3945_ucode
= {
2762 .get_header_size
= iwl3945_ucode_get_header_size
,
2763 .get_build
= iwl3945_ucode_get_build
,
2764 .get_inst_size
= iwl3945_ucode_get_inst_size
,
2765 .get_data_size
= iwl3945_ucode_get_data_size
,
2766 .get_init_size
= iwl3945_ucode_get_init_size
,
2767 .get_init_data_size
= iwl3945_ucode_get_init_data_size
,
2768 .get_boot_size
= iwl3945_ucode_get_boot_size
,
2769 .get_data
= iwl3945_ucode_get_data
,
2772 static struct iwl_lib_ops iwl3945_lib
= {
2773 .txq_attach_buf_to_tfd
= iwl3945_hw_txq_attach_buf_to_tfd
,
2774 .txq_free_tfd
= iwl3945_hw_txq_free_tfd
,
2775 .txq_init
= iwl3945_hw_tx_queue_init
,
2776 .load_ucode
= iwl3945_load_bsm
,
2777 .dump_nic_event_log
= iwl3945_dump_nic_event_log
,
2778 .dump_nic_error_log
= iwl3945_dump_nic_error_log
,
2780 .init
= iwl3945_apm_init
,
2781 .stop
= iwl_apm_stop
,
2782 .config
= iwl3945_nic_config
,
2783 .set_pwr_src
= iwl3945_set_pwr_src
,
2786 .regulatory_bands
= {
2787 EEPROM_REGULATORY_BAND_1_CHANNELS
,
2788 EEPROM_REGULATORY_BAND_2_CHANNELS
,
2789 EEPROM_REGULATORY_BAND_3_CHANNELS
,
2790 EEPROM_REGULATORY_BAND_4_CHANNELS
,
2791 EEPROM_REGULATORY_BAND_5_CHANNELS
,
2792 EEPROM_REGULATORY_BAND_NO_HT40
,
2793 EEPROM_REGULATORY_BAND_NO_HT40
,
2795 .verify_signature
= iwlcore_eeprom_verify_signature
,
2796 .acquire_semaphore
= iwl3945_eeprom_acquire_semaphore
,
2797 .release_semaphore
= iwl3945_eeprom_release_semaphore
,
2798 .query_addr
= iwlcore_eeprom_query_addr
,
2800 .send_tx_power
= iwl3945_send_tx_power
,
2801 .is_valid_rtc_data_addr
= iwl3945_hw_valid_rtc_data_addr
,
2802 .post_associate
= iwl3945_post_associate
,
2803 .isr
= iwl_isr_legacy
,
2804 .config_ap
= iwl3945_config_ap
,
2805 .add_bcast_station
= iwl3945_add_bcast_station
,
2808 .rx_stats_read
= iwl3945_ucode_rx_stats_read
,
2809 .tx_stats_read
= iwl3945_ucode_tx_stats_read
,
2810 .general_stats_read
= iwl3945_ucode_general_stats_read
,
2814 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils
= {
2815 .get_hcmd_size
= iwl3945_get_hcmd_size
,
2816 .build_addsta_hcmd
= iwl3945_build_addsta_hcmd
,
2817 .rts_tx_cmd_flag
= iwlcore_rts_tx_cmd_flag
,
2818 .request_scan
= iwl3945_request_scan
,
2821 static const struct iwl_ops iwl3945_ops
= {
2822 .ucode
= &iwl3945_ucode
,
2823 .lib
= &iwl3945_lib
,
2824 .hcmd
= &iwl3945_hcmd
,
2825 .utils
= &iwl3945_hcmd_utils
,
2826 .led
= &iwl3945_led_ops
,
2829 static struct iwl_cfg iwl3945_bg_cfg
= {
2831 .fw_name_pre
= IWL3945_FW_PRE
,
2832 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2833 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2835 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2836 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2837 .ops
= &iwl3945_ops
,
2838 .num_of_queues
= IWL39_NUM_QUEUES
,
2839 .mod_params
= &iwl3945_mod_params
,
2840 .pll_cfg_val
= CSR39_ANA_PLL_CFG_VAL
,
2843 .use_isr_legacy
= true,
2844 .ht_greenfield_support
= false,
2845 .led_compensation
= 64,
2846 .broken_powersave
= true,
2847 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2848 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2849 .max_event_log_size
= 512,
2850 .tx_power_by_driver
= true,
2853 static struct iwl_cfg iwl3945_abg_cfg
= {
2855 .fw_name_pre
= IWL3945_FW_PRE
,
2856 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2857 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2858 .sku
= IWL_SKU_A
|IWL_SKU_G
,
2859 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2860 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2861 .ops
= &iwl3945_ops
,
2862 .num_of_queues
= IWL39_NUM_QUEUES
,
2863 .mod_params
= &iwl3945_mod_params
,
2864 .use_isr_legacy
= true,
2865 .ht_greenfield_support
= false,
2866 .led_compensation
= 64,
2867 .broken_powersave
= true,
2868 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2869 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2870 .max_event_log_size
= 512,
2871 .tx_power_by_driver
= true,
2874 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids
) = {
2875 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg
)},
2876 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg
)},
2877 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg
)},
2878 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg
)},
2879 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2880 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2884 MODULE_DEVICE_TABLE(pci
, iwl3945_hw_card_ids
);