1 /******************************************************************************
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28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
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62 *****************************************************************************/
64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions.
65 * Use iwl-4965-commands.h for uCode API definitions.
66 * Use iwl-4965.h for driver implementation definitions.
69 #ifndef __iwl_4965_hw_h__
70 #define __iwl_4965_hw_h__
73 #define IWL4965_EEPROM_IMG_SIZE 1024
76 * uCode queue management definitions ...
77 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
78 * The first queue used for block-ack aggregation is #7 (4965 only).
79 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
81 #define IWL_CMD_QUEUE_NUM 4
82 #define IWL_CMD_FIFO_NUM 4
83 #define IWL_BACK_QUEUE_FIRST_ID 7
86 #define IWL_CCK_RATES 4
87 #define IWL_OFDM_RATES 8
88 #define IWL_HT_RATES 16
89 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
92 #define SHORT_SLOT_TIME 9
93 #define LONG_SLOT_TIME 20
96 #define IWL_RSSI_OFFSET 44
99 #include "iwl-4965-commands.h"
101 #define PCI_LINK_CTRL 0x0F0
102 #define PCI_POWER_SOURCE 0x0C8
103 #define PCI_REG_WUM8 0x0E8
104 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
106 #define TFD_QUEUE_SIZE_MAX (256)
108 #define IWL_NUM_SCAN_RATES (2)
110 #define IWL_DEFAULT_TX_RETRY 15
112 #define RX_QUEUE_SIZE 256
113 #define RX_QUEUE_MASK 255
114 #define RX_QUEUE_SIZE_LOG 8
116 #define TFD_TX_CMD_SLOTS 256
117 #define TFD_CMD_SLOTS 32
120 * RX related structures and functions
122 #define RX_FREE_BUFFERS 64
123 #define RX_LOW_WATERMARK 8
125 /* Size of one Rx buffer in host DRAM */
126 #define IWL_RX_BUF_SIZE_4K (4 * 1024)
127 #define IWL_RX_BUF_SIZE_8K (8 * 1024)
129 /* Sizes and addresses for instruction and data memory (SRAM) in
130 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
131 #define RTC_INST_LOWER_BOUND (0x000000)
132 #define IWL49_RTC_INST_UPPER_BOUND (0x018000)
134 #define RTC_DATA_LOWER_BOUND (0x800000)
135 #define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
137 #define IWL49_RTC_INST_SIZE (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
138 #define IWL49_RTC_DATA_SIZE (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
140 #define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
141 #define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
143 /* Size of uCode instruction memory in bootstrap state machine */
144 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
146 static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr
)
148 return (addr
>= RTC_DATA_LOWER_BOUND
) &&
149 (addr
< IWL49_RTC_DATA_UPPER_BOUND
);
152 /********************* START TEMPERATURE *************************************/
155 * 4965 temperature calculation.
157 * The driver must calculate the device temperature before calculating
158 * a txpower setting (amplifier gain is temperature dependent). The
159 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
160 * values used for the life of the driver, and one of which (R4) is the
161 * real-time temperature indicator.
163 * uCode provides all 4 values to the driver via the "initialize alive"
164 * notification (see struct iwl4965_init_alive_resp). After the runtime uCode
165 * image loads, uCode updates the R4 value via statistics notifications
166 * (see STATISTICS_NOTIFICATION), which occur after each received beacon
167 * when associated, or can be requested via REPLY_STATISTICS_CMD.
169 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
170 * must sign-extend to 32 bits before applying formula below.
174 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
176 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
177 * an additional correction, which should be centered around 0 degrees
178 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
179 * centering the 97/100 correction around 0 degrees K.
181 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
182 * temperature with factory-measured temperatures when calculating txpower
185 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
186 #define TEMPERATURE_CALIB_A_VAL 259
188 /* Limit range of calculated temperature to be between these Kelvin values */
189 #define IWL_TX_POWER_TEMPERATURE_MIN (263)
190 #define IWL_TX_POWER_TEMPERATURE_MAX (410)
192 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
193 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
194 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
196 /********************* END TEMPERATURE ***************************************/
198 /********************* START TXPOWER *****************************************/
201 * 4965 txpower calculations rely on information from three sources:
204 * 2) "initialize" alive notification
205 * 3) statistics notifications
207 * EEPROM data consists of:
209 * 1) Regulatory information (max txpower and channel usage flags) is provided
210 * separately for each channel that can possibly supported by 4965.
211 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz
214 * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom
215 * for locations in EEPROM.
217 * 2) Factory txpower calibration information is provided separately for
218 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
219 * but 5 GHz has several sub-bands.
221 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
223 * See struct iwl4965_eeprom_calib_info (and the tree of structures
224 * contained within it) for format, and struct iwl4965_eeprom for
225 * locations in EEPROM.
227 * "Initialization alive" notification (see struct iwl4965_init_alive_resp)
230 * 1) Temperature calculation parameters.
232 * 2) Power supply voltage measurement.
234 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
236 * Statistics notifications deliver:
238 * 1) Current values for temperature param R4.
242 * To calculate a txpower setting for a given desired target txpower, channel,
243 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
244 * support MIMO and transmit diversity), driver must do the following:
246 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
247 * Do not exceed regulatory limit; reduce target txpower if necessary.
249 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
250 * 2 transmitters will be used simultaneously; driver must reduce the
251 * regulatory limit by 3 dB (half-power) for each transmitter, so the
252 * combined total output of the 2 transmitters is within regulatory limits.
255 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
256 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
257 * reduce target txpower if necessary.
259 * Backoff values below are in 1/2 dB units (equivalent to steps in
260 * txpower gain tables):
262 * OFDM 6 - 36 MBit: 10 steps (5 dB)
263 * OFDM 48 MBit: 15 steps (7.5 dB)
264 * OFDM 54 MBit: 17 steps (8.5 dB)
265 * OFDM 60 MBit: 20 steps (10 dB)
266 * CCK all rates: 10 steps (5 dB)
268 * Backoff values apply to saturation txpower on a per-transmitter basis;
269 * when using MIMO (2 transmitters), each transmitter uses the same
270 * saturation level provided in EEPROM, and the same backoff values;
271 * no reduction (such as with regulatory txpower limits) is required.
273 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
274 * widths and 40 Mhz (.11n fat) channel widths; there is no separate
275 * factory measurement for fat channels.
277 * The result of this step is the final target txpower. The rest of
278 * the steps figure out the proper settings for the device to achieve
279 * that target txpower.
282 * 3) Determine (EEPROM) calibration subband for the target channel, by
283 * comparing against first and last channels in each subband
284 * (see struct iwl4965_eeprom_calib_subband_info).
287 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
288 * referencing the 2 factory-measured (sample) channels within the subband.
290 * Interpolation is based on difference between target channel's frequency
291 * and the sample channels' frequencies. Since channel numbers are based
292 * on frequency (5 MHz between each channel number), this is equivalent
293 * to interpolating based on channel number differences.
295 * Note that the sample channels may or may not be the channels at the
296 * edges of the subband. The target channel may be "outside" of the
297 * span of the sampled channels.
299 * Driver may choose the pair (for 2 Tx chains) of measurements (see
300 * struct iwl4965_eeprom_calib_ch_info) for which the actual measured
301 * txpower comes closest to the desired txpower. Usually, though,
302 * the middle set of measurements is closest to the regulatory limits,
303 * and is therefore a good choice for all txpower calculations (this
304 * assumes that high accuracy is needed for maximizing legal txpower,
305 * while lower txpower configurations do not need as much accuracy).
307 * Driver should interpolate both members of the chosen measurement pair,
308 * i.e. for both Tx chains (radio transmitters), unless the driver knows
309 * that only one of the chains will be used (e.g. only one tx antenna
310 * connected, but this should be unusual). The rate scaling algorithm
311 * switches antennas to find best performance, so both Tx chains will
312 * be used (although only one at a time) even for non-MIMO transmissions.
314 * Driver should interpolate factory values for temperature, gain table
315 * index, and actual power. The power amplifier detector values are
316 * not used by the driver.
318 * Sanity check: If the target channel happens to be one of the sample
319 * channels, the results should agree with the sample channel's
323 * 5) Find difference between desired txpower and (interpolated)
324 * factory-measured txpower. Using (interpolated) factory gain table index
325 * (shown elsewhere) as a starting point, adjust this index lower to
326 * increase txpower, or higher to decrease txpower, until the target
327 * txpower is reached. Each step in the gain table is 1/2 dB.
329 * For example, if factory measured txpower is 16 dBm, and target txpower
330 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower
334 * 6) Find difference between current device temperature and (interpolated)
335 * factory-measured temperature for sub-band. Factory values are in
336 * degrees Celsius. To calculate current temperature, see comments for
337 * "4965 temperature calculation".
339 * If current temperature is higher than factory temperature, driver must
340 * increase gain (lower gain table index), and vice versa.
342 * Temperature affects gain differently for different channels:
344 * 2.4 GHz all channels: 3.5 degrees per half-dB step
345 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
346 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
348 * NOTE: Temperature can increase rapidly when transmitting, especially
349 * with heavy traffic at high txpowers. Driver should update
350 * temperature calculations often under these conditions to
351 * maintain strong txpower in the face of rising temperature.
354 * 7) Find difference between current power supply voltage indicator
355 * (from "initialize alive") and factory-measured power supply voltage
356 * indicator (EEPROM).
358 * If the current voltage is higher (indicator is lower) than factory
359 * voltage, gain should be reduced (gain table index increased) by:
361 * (eeprom - current) / 7
363 * If the current voltage is lower (indicator is higher) than factory
364 * voltage, gain should be increased (gain table index decreased) by:
366 * 2 * (current - eeprom) / 7
368 * If number of index steps in either direction turns out to be > 2,
369 * something is wrong ... just use 0.
371 * NOTE: Voltage compensation is independent of band/channel.
373 * NOTE: "Initialize" uCode measures current voltage, which is assumed
374 * to be constant after this initial measurement. Voltage
375 * compensation for txpower (number of steps in gain table)
376 * may be calculated once and used until the next uCode bootload.
379 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
380 * adjust txpower for each transmitter chain, so txpower is balanced
381 * between the two chains. There are 5 pairs of tx_atten[group][chain]
382 * values in "initialize alive", one pair for each of 5 channel ranges:
384 * Group 0: 5 GHz channel 34-43
385 * Group 1: 5 GHz channel 44-70
386 * Group 2: 5 GHz channel 71-124
387 * Group 3: 5 GHz channel 125-200
388 * Group 4: 2.4 GHz all channels
390 * Add the tx_atten[group][chain] value to the index for the target chain.
391 * The values are signed, but are in pairs of 0 and a non-negative number,
392 * so as to reduce gain (if necessary) of the "hotter" channel. This
393 * avoids any need to double-check for regulatory compliance after
397 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
398 * value to the index:
400 * Hardware rev B: 9 steps (4.5 dB)
401 * Hardware rev C: 5 steps (2.5 dB)
403 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
404 * bits [3:2], 1 = B, 2 = C.
406 * NOTE: This compensation is in addition to any saturation backoff that
407 * might have been applied in an earlier step.
410 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
412 * Limit the adjusted index to stay within the table!
415 * 11) Read gain table entries for DSP and radio gain, place into appropriate
416 * location(s) in command (struct iwl4965_txpowertable_cmd).
419 /* Limit range of txpower output target to be between these values */
420 #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
421 #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
424 * When MIMO is used (2 transmitters operating simultaneously), driver should
425 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
426 * for the device. That is, use half power for each transmitter, so total
427 * txpower is within regulatory limits.
429 * The value "6" represents number of steps in gain table to reduce power 3 dB.
430 * Each step is 1/2 dB.
432 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
435 * CCK gain compensation.
437 * When calculating txpowers for CCK, after making sure that the target power
438 * is within regulatory and saturation limits, driver must additionally
439 * back off gain by adding these values to the gain table index.
441 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
442 * bits [3:2], 1 = B, 2 = C.
444 #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
445 #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
448 * 4965 power supply voltage compensation for txpower
450 #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7)
455 * The following tables contain pair of values for setting txpower, i.e.
456 * gain settings for the output of the device's digital signal processor (DSP),
457 * and for the analog gain structure of the transmitter.
459 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
460 * are *relative* steps, not indications of absolute output power. Output
461 * power varies with temperature, voltage, and channel frequency, and also
462 * requires consideration of average power (to satisfy regulatory constraints),
463 * and peak power (to avoid distortion of the output signal).
465 * Each entry contains two values:
466 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
467 * linear value that multiplies the output of the digital signal processor,
468 * before being sent to the analog radio.
469 * 2) Radio gain. This sets the analog gain of the radio Tx path.
470 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
472 * EEPROM contains factory calibration data for txpower. This maps actual
473 * measured txpower levels to gain settings in the "well known" tables
474 * below ("well-known" means here that both factory calibration *and* the
475 * driver work with the same table).
477 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
478 * has an extension (into negative indexes), in case the driver needs to
479 * boost power setting for high device temperatures (higher than would be
480 * present during factory calibration). A 5 Ghz EEPROM index of "40"
481 * corresponds to the 49th entry in the table used by the driver.
483 #define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */
484 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
489 * Index Dsp gain Radio gain
490 * 0 110 0x3f (highest gain)
594 * Index Dsp gain Radio gain
595 * -9 123 0x3F (highest gain)
707 * Sanity checks and default values for EEPROM regulatory levels.
708 * If EEPROM values fall outside MIN/MAX range, use default values.
710 * Regulatory limits refer to the maximum average txpower allowed by
711 * regulatory agencies in the geographies in which the device is meant
712 * to be operated. These limits are SKU-specific (i.e. geography-specific),
713 * and channel-specific; each channel has an individual regulatory limit
714 * listed in the EEPROM.
716 * Units are in half-dBm (i.e. "34" means 17 dBm).
718 #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
719 #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
720 #define IWL_TX_POWER_REGULATORY_MIN (0)
721 #define IWL_TX_POWER_REGULATORY_MAX (34)
724 * Sanity checks and default values for EEPROM saturation levels.
725 * If EEPROM values fall outside MIN/MAX range, use default values.
727 * Saturation is the highest level that the output power amplifier can produce
728 * without significant clipping distortion. This is a "peak" power level.
729 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
730 * require differing amounts of backoff, relative to their average power output,
731 * in order to avoid clipping distortion.
733 * Driver must make sure that it is violating neither the saturation limit,
734 * nor the regulatory limit, when calculating Tx power settings for various
737 * Units are in half-dBm (i.e. "38" means 19 dBm).
739 #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
740 #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
741 #define IWL_TX_POWER_SATURATION_MIN (20)
742 #define IWL_TX_POWER_SATURATION_MAX (50)
745 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
746 * and thermal Txpower calibration.
748 * When calculating txpower, driver must compensate for current device
749 * temperature; higher temperature requires higher gain. Driver must calculate
750 * current temperature (see "4965 temperature calculation"), then compare vs.
751 * factory calibration temperature in EEPROM; if current temperature is higher
752 * than factory temperature, driver must *increase* gain by proportions shown
753 * in table below. If current temperature is lower than factory, driver must
756 * Different frequency ranges require different compensation, as shown below.
758 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
759 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
760 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
762 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
763 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
764 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
766 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
767 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
768 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
770 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
771 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
772 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
774 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
775 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
776 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
779 CALIB_CH_GROUP_1
= 0,
780 CALIB_CH_GROUP_2
= 1,
781 CALIB_CH_GROUP_3
= 2,
782 CALIB_CH_GROUP_4
= 3,
783 CALIB_CH_GROUP_5
= 4,
787 /********************* END TXPOWER *****************************************/
789 /****************************/
790 /* Flow Handler Definitions */
791 /****************************/
794 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
795 * Addresses are offsets from device's PCI hardware base address.
797 #define FH_MEM_LOWER_BOUND (0x1000)
798 #define FH_MEM_UPPER_BOUND (0x1EF0)
801 * Keep-Warm (KW) buffer base address.
803 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
804 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
805 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
806 * from going into a power-savings mode that would cause higher DRAM latency,
807 * and possible data over/under-runs, before all Tx/Rx is complete.
809 * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
810 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
811 * automatically invokes keep-warm accesses when normal accesses might not
812 * be sufficient to maintain fast DRAM response.
815 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
817 #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
821 * TFD Circular Buffers Base (CBBC) addresses
823 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
824 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
825 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
826 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
827 * aligned (address bits 0-7 must be 0).
829 * Bit fields in each pointer register:
830 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
832 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
833 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
835 /* Find TFD CB base pointer for given queue (range 0-15). */
836 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
840 * Rx SRAM Control and Status Registers (RSCSR)
842 * These registers provide handshake between driver and 4965 for the Rx queue
843 * (this queue handles *all* command responses, notifications, Rx data, etc.
844 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
845 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
846 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
847 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
848 * mapping between RBDs and RBs.
850 * Driver must allocate host DRAM memory for the following, and set the
851 * physical address of each into 4965 registers:
853 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
854 * entries (although any power of 2, up to 4096, is selectable by driver).
855 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
856 * (typically 4K, although 8K or 16K are also selectable by driver).
857 * Driver sets up RB size and number of RBDs in the CB via Rx config
858 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
860 * Bit fields within one RBD:
861 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
863 * Driver sets physical address [35:8] of base of RBD circular buffer
864 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
866 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
867 * (RBs) have been filled, via a "write pointer", actually the index of
868 * the RB's corresponding RBD within the circular buffer. Driver sets
869 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
871 * Bit fields in lower dword of Rx status buffer (upper dword not used
872 * by driver; see struct iwl4965_shared, val0):
873 * 31-12: Not used by driver
874 * 11- 0: Index of last filled Rx buffer descriptor
875 * (4965 writes, driver reads this value)
877 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
878 * enter pointers to these RBs into contiguous RBD circular buffer entries,
879 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
881 * This "write" index corresponds to the *next* RBD that the driver will make
882 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
883 * the circular buffer. This value should initially be 0 (before preparing any
884 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
885 * wrap back to 0 at the end of the circular buffer (but don't wrap before
886 * "read" index has advanced past 1! See below).
887 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
889 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
890 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
891 * to tell the driver the index of the latest filled RBD. The driver must
892 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
894 * The driver must also internally keep track of a third index, which is the
895 * next RBD to process. When receiving an Rx interrupt, driver should process
896 * all filled but unprocessed RBs up to, but not including, the RB
897 * corresponding to the "read" index. For example, if "read" index becomes "1",
898 * driver may process the RB pointed to by RBD 0. Depending on volume of
899 * traffic, there may be many RBs to process.
901 * If read index == write index, 4965 thinks there is no room to put new data.
902 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
903 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
904 * and "read" indexes; that is, make sure that there are no more than 254
905 * buffers waiting to be filled.
907 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
908 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
909 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
912 * Physical base address of 8-byte Rx Status buffer.
914 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
916 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
919 * Physical base address of Rx Buffer Descriptor Circular Buffer.
921 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
923 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
926 * Rx write pointer (index, really!).
928 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
929 * NOTE: For 256-entry circular buffer, use only bits [7:0].
931 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
932 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
936 * Rx Config/Status Registers (RCSR)
937 * Rx Config Reg for channel 0 (only channel used)
939 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
940 * normal operation (see bit fields).
942 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
943 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
944 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
947 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
948 * '10' operate normally
950 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
951 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
953 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
954 * '10' 12K, '11' 16K.
956 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
957 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
958 * typical value 0x10 (about 1/2 msec)
961 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
962 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
963 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
965 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
967 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
968 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
969 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
970 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
971 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
972 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
974 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
975 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
976 #define RX_RB_TIMEOUT (0x10)
978 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
979 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
980 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
982 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
983 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
984 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
985 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
987 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
988 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
992 * Rx Shared Status Registers (RSSR)
994 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
995 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
998 * 24: 1 = Channel 0 is idle
1000 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain
1001 * default values that should not be altered by the driver.
1003 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
1004 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1006 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
1007 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
1008 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
1010 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1014 * Transmit DMA Channel Control/Status Registers (TCSR)
1016 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1017 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1018 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1020 * To use a Tx DMA channel, driver must initialize its
1021 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1023 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1024 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1026 * All other bits should be 0.
1029 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1030 * '10' operate normally
1031 * 29- 4: Reserved, set to "0"
1032 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1033 * 2- 0: Reserved, set to "0"
1035 #define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1036 #define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
1038 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1039 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1040 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
1042 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1043 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1045 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1046 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1047 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1050 * Tx Shared Status Registers (TSSR)
1052 * After stopping Tx DMA channel (writing 0 to
1053 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1054 * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1055 * (channel's buffers empty | no pending requests).
1058 * 31-24: 1 = Channel buffers empty (channel 7:0)
1059 * 23-16: 1 = No pending requests (channel 7:0)
1061 #define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
1062 #define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
1064 #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
1066 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1067 ((1 << (_chnl)) << 24)
1068 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1069 ((1 << (_chnl)) << 16)
1071 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1072 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1073 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1075 static inline u8
iwl4965_hw_get_rate(__le32 rate_n_flags
)
1077 return le32_to_cpu(rate_n_flags
) & 0xFF;
1079 static inline u32
iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags
)
1081 return le32_to_cpu(rate_n_flags
) & 0x1FFFF;
1083 static inline __le32
iwl4965_hw_set_rate_n_flags(u8 rate
, u16 flags
)
1085 return cpu_to_le32(flags
|(u16
)rate
);
1092 * Most communication between driver and 4965 is via queues of data buffers.
1093 * For example, all commands that the driver issues to device's embedded
1094 * controller (uCode) are via the command queue (one of the Tx queues). All
1095 * uCode command responses/replies/notifications, including Rx frames, are
1096 * conveyed from uCode to driver via the Rx queue.
1098 * Most support for these queues, including handshake support, resides in
1099 * structures in host DRAM, shared between the driver and the device. When
1100 * allocating this memory, the driver must make sure that data written by
1101 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
1102 * cache memory), so DRAM and cache are consistent, and the device can
1103 * immediately see changes made by the driver.
1105 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
1106 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
1107 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
1109 #define IWL49_MAX_WIN_SIZE 64
1110 #define IWL49_QUEUE_SIZE 256
1111 #define IWL49_NUM_FIFOS 7
1112 #define IWL49_CMD_FIFO_NUM 4
1113 #define IWL49_NUM_QUEUES 16
1116 * struct iwl4965_tfd_frame_data
1118 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame.
1119 * Each buffer must be on dword boundary.
1120 * Up to 10 iwl_tfd_frame_data structures, describing up to 20 buffers,
1121 * may be filled within a TFD (iwl_tfd_frame).
1123 * Bit fields in tb1_addr:
1124 * 31- 0: Tx buffer 1 address bits [31:0]
1126 * Bit fields in val1:
1127 * 31-16: Tx buffer 2 address bits [15:0]
1128 * 15- 4: Tx buffer 1 length (bytes)
1129 * 3- 0: Tx buffer 1 address bits [32:32]
1131 * Bit fields in val2:
1132 * 31-20: Tx buffer 2 length (bytes)
1133 * 19- 0: Tx buffer 2 address bits [35:16]
1135 struct iwl4965_tfd_frame_data
{
1139 /* __le32 ptb1_32_35:4; */
1140 #define IWL_tb1_addr_hi_POS 0
1141 #define IWL_tb1_addr_hi_LEN 4
1142 #define IWL_tb1_addr_hi_SYM val1
1143 /* __le32 tb_len1:12; */
1144 #define IWL_tb1_len_POS 4
1145 #define IWL_tb1_len_LEN 12
1146 #define IWL_tb1_len_SYM val1
1147 /* __le32 ptb2_0_15:16; */
1148 #define IWL_tb2_addr_lo16_POS 16
1149 #define IWL_tb2_addr_lo16_LEN 16
1150 #define IWL_tb2_addr_lo16_SYM val1
1153 /* __le32 ptb2_16_35:20; */
1154 #define IWL_tb2_addr_hi20_POS 0
1155 #define IWL_tb2_addr_hi20_LEN 20
1156 #define IWL_tb2_addr_hi20_SYM val2
1157 /* __le32 tb_len2:12; */
1158 #define IWL_tb2_len_POS 20
1159 #define IWL_tb2_len_LEN 12
1160 #define IWL_tb2_len_SYM val2
1161 } __attribute__ ((packed
));
1165 * struct iwl4965_tfd_frame
1167 * Transmit Frame Descriptor (TFD)
1169 * 4965 supports up to 16 Tx queues resident in host DRAM.
1170 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1171 * Both driver and device share these circular buffers, each of which must be
1172 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes for 4965.
1174 * Driver must indicate the physical address of the base of each
1175 * circular buffer via the 4965's FH_MEM_CBBC_QUEUE registers.
1177 * Each TFD contains pointer/size information for up to 20 data buffers
1178 * in host DRAM. These buffers collectively contain the (one) frame described
1179 * by the TFD. Each buffer must be a single contiguous block of memory within
1180 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1181 * of (4K - 4). The 4965 concatenates all of a TFD's buffers into a single
1182 * Tx frame, up to 8 KBytes in size.
1184 * Bit fields in the control dword (val0):
1185 * 31-30: # dwords (0-3) of padding required at end of frame for 16-byte bound
1187 * 28-24: # Transmit Buffer Descriptors in TFD
1190 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1192 struct iwl4965_tfd_frame
{
1194 /* __le32 rsvd1:24; */
1195 /* __le32 num_tbs:5; */
1196 #define IWL_num_tbs_POS 24
1197 #define IWL_num_tbs_LEN 5
1198 #define IWL_num_tbs_SYM val0
1199 /* __le32 rsvd2:1; */
1200 /* __le32 padding:2; */
1201 struct iwl4965_tfd_frame_data pa
[10];
1203 } __attribute__ ((packed
));
1207 * struct iwl4965_queue_byte_cnt_entry
1209 * Byte Count Table Entry
1213 * 11- 0: total to-be-transmitted byte count of frame (does not include command)
1215 struct iwl4965_queue_byte_cnt_entry
{
1217 /* __le16 byte_cnt:12; */
1218 #define IWL_byte_cnt_POS 0
1219 #define IWL_byte_cnt_LEN 12
1220 #define IWL_byte_cnt_SYM val
1221 /* __le16 rsvd:4; */
1222 } __attribute__ ((packed
));
1226 * struct iwl4965_sched_queue_byte_cnt_tbl
1230 * Each Tx queue uses a byte-count table containing 320 entries:
1231 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
1232 * duplicate the first 64 entries (to avoid wrap-around within a Tx window;
1233 * max Tx window is 64 TFDs).
1235 * When driver sets up a new TFD, it must also enter the total byte count
1236 * of the frame to be transmitted into the corresponding entry in the byte
1237 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver
1238 * must duplicate the byte count entry in corresponding index 256-319.
1240 * "dont_care" padding puts each byte count table on a 1024-byte boundary;
1241 * 4965 assumes tables are separated by 1024 bytes.
1243 struct iwl4965_sched_queue_byte_cnt_tbl
{
1244 struct iwl4965_queue_byte_cnt_entry tfd_offset
[IWL49_QUEUE_SIZE
+
1245 IWL49_MAX_WIN_SIZE
];
1247 (IWL49_QUEUE_SIZE
+ IWL49_MAX_WIN_SIZE
) *
1249 } __attribute__ ((packed
));
1253 * struct iwl4965_shared - handshake area for Tx and Rx
1255 * For convenience in allocating memory, this structure combines 2 areas of
1256 * DRAM which must be shared between driver and 4965. These do not need to
1257 * be combined, if better allocation would result from keeping them separate:
1259 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for
1260 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find
1261 * the first of these tables. 4965 assumes tables are 1024 bytes apart.
1263 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses
1264 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area.
1265 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD)
1266 * that has been filled by the 4965.
1270 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads)
1275 struct iwl4965_shared
{
1276 struct iwl4965_sched_queue_byte_cnt_tbl
1277 queues_byte_cnt_tbls
[IWL49_NUM_QUEUES
];
1280 /* __le32 rb_closed_stts_rb_num:12; */
1281 #define IWL_rb_closed_stts_rb_num_POS 0
1282 #define IWL_rb_closed_stts_rb_num_LEN 12
1283 #define IWL_rb_closed_stts_rb_num_SYM rb_closed
1284 /* __le32 rsrv1:4; */
1285 /* __le32 rb_closed_stts_rx_frame_num:12; */
1286 #define IWL_rb_closed_stts_rx_frame_num_POS 16
1287 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
1288 #define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
1289 /* __le32 rsrv2:4; */
1291 __le32 frm_finished
;
1292 /* __le32 frame_finished_stts_rb_num:12; */
1293 #define IWL_frame_finished_stts_rb_num_POS 0
1294 #define IWL_frame_finished_stts_rb_num_LEN 12
1295 #define IWL_frame_finished_stts_rb_num_SYM frm_finished
1296 /* __le32 rsrv3:4; */
1297 /* __le32 frame_finished_stts_rx_frame_num:12; */
1298 #define IWL_frame_finished_stts_rx_frame_num_POS 16
1299 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
1300 #define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
1301 /* __le32 rsrv4:4; */
1303 __le32 padding1
; /* so that allocation will be aligned to 16B */
1305 } __attribute__ ((packed
));
1307 #endif /* __iwl4965_4965_hw_h__ */