1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
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15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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62 *****************************************************************************/
64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions.
65 * Use iwl-4965-commands.h for uCode API definitions.
66 * Use iwl-4965.h for driver implementation definitions.
69 #ifndef __iwl_4965_hw_h__
70 #define __iwl_4965_hw_h__
75 #define IWL4965_EEPROM_IMG_SIZE 1024
78 * uCode queue management definitions ...
79 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
80 * The first queue used for block-ack aggregation is #7 (4965 only).
81 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
83 #define IWL_CMD_QUEUE_NUM 4
84 #define IWL_CMD_FIFO_NUM 4
85 #define IWL_BACK_QUEUE_FIRST_ID 7
88 #define IWL_CCK_RATES 4
89 #define IWL_OFDM_RATES 8
90 #define IWL_HT_RATES 16
91 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
94 #define SHORT_SLOT_TIME 9
95 #define LONG_SLOT_TIME 20
98 #define IWL_RSSI_OFFSET 44
101 #include "iwl-4965-commands.h"
103 #define PCI_LINK_CTRL 0x0F0
104 #define PCI_POWER_SOURCE 0x0C8
105 #define PCI_REG_WUM8 0x0E8
106 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
108 #define TFD_QUEUE_SIZE_MAX (256)
110 #define IWL_NUM_SCAN_RATES (2)
112 #define IWL_DEFAULT_TX_RETRY 15
114 #define RX_QUEUE_SIZE 256
115 #define RX_QUEUE_MASK 255
116 #define RX_QUEUE_SIZE_LOG 8
118 #define TFD_TX_CMD_SLOTS 256
119 #define TFD_CMD_SLOTS 32
122 * RX related structures and functions
124 #define RX_FREE_BUFFERS 64
125 #define RX_LOW_WATERMARK 8
127 /* Size of one Rx buffer in host DRAM */
128 #define IWL_RX_BUF_SIZE_4K (4 * 1024)
129 #define IWL_RX_BUF_SIZE_8K (8 * 1024)
131 /* Sizes and addresses for instruction and data memory (SRAM) in
132 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
133 #define RTC_INST_LOWER_BOUND (0x000000)
134 #define IWL49_RTC_INST_UPPER_BOUND (0x018000)
136 #define RTC_DATA_LOWER_BOUND (0x800000)
137 #define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
139 #define IWL49_RTC_INST_SIZE (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
140 #define IWL49_RTC_DATA_SIZE (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
142 #define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
143 #define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
145 /* Size of uCode instruction memory in bootstrap state machine */
146 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
148 static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr
)
150 return (addr
>= RTC_DATA_LOWER_BOUND
) &&
151 (addr
< IWL49_RTC_DATA_UPPER_BOUND
);
154 /********************* START TEMPERATURE *************************************/
157 * 4965 temperature calculation.
159 * The driver must calculate the device temperature before calculating
160 * a txpower setting (amplifier gain is temperature dependent). The
161 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
162 * values used for the life of the driver, and one of which (R4) is the
163 * real-time temperature indicator.
165 * uCode provides all 4 values to the driver via the "initialize alive"
166 * notification (see struct iwl4965_init_alive_resp). After the runtime uCode
167 * image loads, uCode updates the R4 value via statistics notifications
168 * (see STATISTICS_NOTIFICATION), which occur after each received beacon
169 * when associated, or can be requested via REPLY_STATISTICS_CMD.
171 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
172 * must sign-extend to 32 bits before applying formula below.
176 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
178 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
179 * an additional correction, which should be centered around 0 degrees
180 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
181 * centering the 97/100 correction around 0 degrees K.
183 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
184 * temperature with factory-measured temperatures when calculating txpower
187 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
188 #define TEMPERATURE_CALIB_A_VAL 259
190 /* Limit range of calculated temperature to be between these Kelvin values */
191 #define IWL_TX_POWER_TEMPERATURE_MIN (263)
192 #define IWL_TX_POWER_TEMPERATURE_MAX (410)
194 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
195 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
196 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
198 /********************* END TEMPERATURE ***************************************/
200 /********************* START TXPOWER *****************************************/
203 * 4965 txpower calculations rely on information from three sources:
206 * 2) "initialize" alive notification
207 * 3) statistics notifications
209 * EEPROM data consists of:
211 * 1) Regulatory information (max txpower and channel usage flags) is provided
212 * separately for each channel that can possibly supported by 4965.
213 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz
216 * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom
217 * for locations in EEPROM.
219 * 2) Factory txpower calibration information is provided separately for
220 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
221 * but 5 GHz has several sub-bands.
223 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
225 * See struct iwl4965_eeprom_calib_info (and the tree of structures
226 * contained within it) for format, and struct iwl4965_eeprom for
227 * locations in EEPROM.
229 * "Initialization alive" notification (see struct iwl4965_init_alive_resp)
232 * 1) Temperature calculation parameters.
234 * 2) Power supply voltage measurement.
236 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
238 * Statistics notifications deliver:
240 * 1) Current values for temperature param R4.
244 * To calculate a txpower setting for a given desired target txpower, channel,
245 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
246 * support MIMO and transmit diversity), driver must do the following:
248 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
249 * Do not exceed regulatory limit; reduce target txpower if necessary.
251 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
252 * 2 transmitters will be used simultaneously; driver must reduce the
253 * regulatory limit by 3 dB (half-power) for each transmitter, so the
254 * combined total output of the 2 transmitters is within regulatory limits.
257 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
258 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
259 * reduce target txpower if necessary.
261 * Backoff values below are in 1/2 dB units (equivalent to steps in
262 * txpower gain tables):
264 * OFDM 6 - 36 MBit: 10 steps (5 dB)
265 * OFDM 48 MBit: 15 steps (7.5 dB)
266 * OFDM 54 MBit: 17 steps (8.5 dB)
267 * OFDM 60 MBit: 20 steps (10 dB)
268 * CCK all rates: 10 steps (5 dB)
270 * Backoff values apply to saturation txpower on a per-transmitter basis;
271 * when using MIMO (2 transmitters), each transmitter uses the same
272 * saturation level provided in EEPROM, and the same backoff values;
273 * no reduction (such as with regulatory txpower limits) is required.
275 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
276 * widths and 40 Mhz (.11n fat) channel widths; there is no separate
277 * factory measurement for fat channels.
279 * The result of this step is the final target txpower. The rest of
280 * the steps figure out the proper settings for the device to achieve
281 * that target txpower.
284 * 3) Determine (EEPROM) calibration subband for the target channel, by
285 * comparing against first and last channels in each subband
286 * (see struct iwl4965_eeprom_calib_subband_info).
289 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
290 * referencing the 2 factory-measured (sample) channels within the subband.
292 * Interpolation is based on difference between target channel's frequency
293 * and the sample channels' frequencies. Since channel numbers are based
294 * on frequency (5 MHz between each channel number), this is equivalent
295 * to interpolating based on channel number differences.
297 * Note that the sample channels may or may not be the channels at the
298 * edges of the subband. The target channel may be "outside" of the
299 * span of the sampled channels.
301 * Driver may choose the pair (for 2 Tx chains) of measurements (see
302 * struct iwl4965_eeprom_calib_ch_info) for which the actual measured
303 * txpower comes closest to the desired txpower. Usually, though,
304 * the middle set of measurements is closest to the regulatory limits,
305 * and is therefore a good choice for all txpower calculations (this
306 * assumes that high accuracy is needed for maximizing legal txpower,
307 * while lower txpower configurations do not need as much accuracy).
309 * Driver should interpolate both members of the chosen measurement pair,
310 * i.e. for both Tx chains (radio transmitters), unless the driver knows
311 * that only one of the chains will be used (e.g. only one tx antenna
312 * connected, but this should be unusual). The rate scaling algorithm
313 * switches antennas to find best performance, so both Tx chains will
314 * be used (although only one at a time) even for non-MIMO transmissions.
316 * Driver should interpolate factory values for temperature, gain table
317 * index, and actual power. The power amplifier detector values are
318 * not used by the driver.
320 * Sanity check: If the target channel happens to be one of the sample
321 * channels, the results should agree with the sample channel's
325 * 5) Find difference between desired txpower and (interpolated)
326 * factory-measured txpower. Using (interpolated) factory gain table index
327 * (shown elsewhere) as a starting point, adjust this index lower to
328 * increase txpower, or higher to decrease txpower, until the target
329 * txpower is reached. Each step in the gain table is 1/2 dB.
331 * For example, if factory measured txpower is 16 dBm, and target txpower
332 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower
336 * 6) Find difference between current device temperature and (interpolated)
337 * factory-measured temperature for sub-band. Factory values are in
338 * degrees Celsius. To calculate current temperature, see comments for
339 * "4965 temperature calculation".
341 * If current temperature is higher than factory temperature, driver must
342 * increase gain (lower gain table index), and vice versa.
344 * Temperature affects gain differently for different channels:
346 * 2.4 GHz all channels: 3.5 degrees per half-dB step
347 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
348 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
350 * NOTE: Temperature can increase rapidly when transmitting, especially
351 * with heavy traffic at high txpowers. Driver should update
352 * temperature calculations often under these conditions to
353 * maintain strong txpower in the face of rising temperature.
356 * 7) Find difference between current power supply voltage indicator
357 * (from "initialize alive") and factory-measured power supply voltage
358 * indicator (EEPROM).
360 * If the current voltage is higher (indicator is lower) than factory
361 * voltage, gain should be reduced (gain table index increased) by:
363 * (eeprom - current) / 7
365 * If the current voltage is lower (indicator is higher) than factory
366 * voltage, gain should be increased (gain table index decreased) by:
368 * 2 * (current - eeprom) / 7
370 * If number of index steps in either direction turns out to be > 2,
371 * something is wrong ... just use 0.
373 * NOTE: Voltage compensation is independent of band/channel.
375 * NOTE: "Initialize" uCode measures current voltage, which is assumed
376 * to be constant after this initial measurement. Voltage
377 * compensation for txpower (number of steps in gain table)
378 * may be calculated once and used until the next uCode bootload.
381 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
382 * adjust txpower for each transmitter chain, so txpower is balanced
383 * between the two chains. There are 5 pairs of tx_atten[group][chain]
384 * values in "initialize alive", one pair for each of 5 channel ranges:
386 * Group 0: 5 GHz channel 34-43
387 * Group 1: 5 GHz channel 44-70
388 * Group 2: 5 GHz channel 71-124
389 * Group 3: 5 GHz channel 125-200
390 * Group 4: 2.4 GHz all channels
392 * Add the tx_atten[group][chain] value to the index for the target chain.
393 * The values are signed, but are in pairs of 0 and a non-negative number,
394 * so as to reduce gain (if necessary) of the "hotter" channel. This
395 * avoids any need to double-check for regulatory compliance after
399 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
400 * value to the index:
402 * Hardware rev B: 9 steps (4.5 dB)
403 * Hardware rev C: 5 steps (2.5 dB)
405 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
406 * bits [3:2], 1 = B, 2 = C.
408 * NOTE: This compensation is in addition to any saturation backoff that
409 * might have been applied in an earlier step.
412 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
414 * Limit the adjusted index to stay within the table!
417 * 11) Read gain table entries for DSP and radio gain, place into appropriate
418 * location(s) in command (struct iwl4965_txpowertable_cmd).
421 /* Limit range of txpower output target to be between these values */
422 #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
423 #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
426 * When MIMO is used (2 transmitters operating simultaneously), driver should
427 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
428 * for the device. That is, use half power for each transmitter, so total
429 * txpower is within regulatory limits.
431 * The value "6" represents number of steps in gain table to reduce power 3 dB.
432 * Each step is 1/2 dB.
434 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
437 * CCK gain compensation.
439 * When calculating txpowers for CCK, after making sure that the target power
440 * is within regulatory and saturation limits, driver must additionally
441 * back off gain by adding these values to the gain table index.
443 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
444 * bits [3:2], 1 = B, 2 = C.
446 #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
447 #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
450 * 4965 power supply voltage compensation for txpower
452 #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7)
457 * The following tables contain pair of values for setting txpower, i.e.
458 * gain settings for the output of the device's digital signal processor (DSP),
459 * and for the analog gain structure of the transmitter.
461 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
462 * are *relative* steps, not indications of absolute output power. Output
463 * power varies with temperature, voltage, and channel frequency, and also
464 * requires consideration of average power (to satisfy regulatory constraints),
465 * and peak power (to avoid distortion of the output signal).
467 * Each entry contains two values:
468 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
469 * linear value that multiplies the output of the digital signal processor,
470 * before being sent to the analog radio.
471 * 2) Radio gain. This sets the analog gain of the radio Tx path.
472 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
474 * EEPROM contains factory calibration data for txpower. This maps actual
475 * measured txpower levels to gain settings in the "well known" tables
476 * below ("well-known" means here that both factory calibration *and* the
477 * driver work with the same table).
479 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
480 * has an extension (into negative indexes), in case the driver needs to
481 * boost power setting for high device temperatures (higher than would be
482 * present during factory calibration). A 5 Ghz EEPROM index of "40"
483 * corresponds to the 49th entry in the table used by the driver.
485 #define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */
486 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
491 * Index Dsp gain Radio gain
492 * 0 110 0x3f (highest gain)
596 * Index Dsp gain Radio gain
597 * -9 123 0x3F (highest gain)
709 * Sanity checks and default values for EEPROM regulatory levels.
710 * If EEPROM values fall outside MIN/MAX range, use default values.
712 * Regulatory limits refer to the maximum average txpower allowed by
713 * regulatory agencies in the geographies in which the device is meant
714 * to be operated. These limits are SKU-specific (i.e. geography-specific),
715 * and channel-specific; each channel has an individual regulatory limit
716 * listed in the EEPROM.
718 * Units are in half-dBm (i.e. "34" means 17 dBm).
720 #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
721 #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
722 #define IWL_TX_POWER_REGULATORY_MIN (0)
723 #define IWL_TX_POWER_REGULATORY_MAX (34)
726 * Sanity checks and default values for EEPROM saturation levels.
727 * If EEPROM values fall outside MIN/MAX range, use default values.
729 * Saturation is the highest level that the output power amplifier can produce
730 * without significant clipping distortion. This is a "peak" power level.
731 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
732 * require differing amounts of backoff, relative to their average power output,
733 * in order to avoid clipping distortion.
735 * Driver must make sure that it is violating neither the saturation limit,
736 * nor the regulatory limit, when calculating Tx power settings for various
739 * Units are in half-dBm (i.e. "38" means 19 dBm).
741 #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
742 #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
743 #define IWL_TX_POWER_SATURATION_MIN (20)
744 #define IWL_TX_POWER_SATURATION_MAX (50)
747 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
748 * and thermal Txpower calibration.
750 * When calculating txpower, driver must compensate for current device
751 * temperature; higher temperature requires higher gain. Driver must calculate
752 * current temperature (see "4965 temperature calculation"), then compare vs.
753 * factory calibration temperature in EEPROM; if current temperature is higher
754 * than factory temperature, driver must *increase* gain by proportions shown
755 * in table below. If current temperature is lower than factory, driver must
758 * Different frequency ranges require different compensation, as shown below.
760 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
761 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
762 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
764 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
765 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
766 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
768 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
769 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
770 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
772 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
773 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
774 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
776 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
777 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
778 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
781 CALIB_CH_GROUP_1
= 0,
782 CALIB_CH_GROUP_2
= 1,
783 CALIB_CH_GROUP_3
= 2,
784 CALIB_CH_GROUP_4
= 3,
785 CALIB_CH_GROUP_5
= 4,
789 /********************* END TXPOWER *****************************************/
791 static inline u8
iwl4965_hw_get_rate(__le32 rate_n_flags
)
793 return le32_to_cpu(rate_n_flags
) & 0xFF;
795 static inline u32
iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags
)
797 return le32_to_cpu(rate_n_flags
) & 0x1FFFF;
799 static inline __le32
iwl4965_hw_set_rate_n_flags(u8 rate
, u16 flags
)
801 return cpu_to_le32(flags
|(u16
)rate
);
808 * Most communication between driver and 4965 is via queues of data buffers.
809 * For example, all commands that the driver issues to device's embedded
810 * controller (uCode) are via the command queue (one of the Tx queues). All
811 * uCode command responses/replies/notifications, including Rx frames, are
812 * conveyed from uCode to driver via the Rx queue.
814 * Most support for these queues, including handshake support, resides in
815 * structures in host DRAM, shared between the driver and the device. When
816 * allocating this memory, the driver must make sure that data written by
817 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
818 * cache memory), so DRAM and cache are consistent, and the device can
819 * immediately see changes made by the driver.
821 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
822 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
823 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
825 #define IWL49_MAX_WIN_SIZE 64
826 #define IWL49_QUEUE_SIZE 256
827 #define IWL49_NUM_FIFOS 7
828 #define IWL49_CMD_FIFO_NUM 4
829 #define IWL49_NUM_QUEUES 16
832 * struct iwl4965_tfd_frame_data
834 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame.
835 * Each buffer must be on dword boundary.
836 * Up to 10 iwl_tfd_frame_data structures, describing up to 20 buffers,
837 * may be filled within a TFD (iwl_tfd_frame).
839 * Bit fields in tb1_addr:
840 * 31- 0: Tx buffer 1 address bits [31:0]
842 * Bit fields in val1:
843 * 31-16: Tx buffer 2 address bits [15:0]
844 * 15- 4: Tx buffer 1 length (bytes)
845 * 3- 0: Tx buffer 1 address bits [32:32]
847 * Bit fields in val2:
848 * 31-20: Tx buffer 2 length (bytes)
849 * 19- 0: Tx buffer 2 address bits [35:16]
851 struct iwl4965_tfd_frame_data
{
855 /* __le32 ptb1_32_35:4; */
856 #define IWL_tb1_addr_hi_POS 0
857 #define IWL_tb1_addr_hi_LEN 4
858 #define IWL_tb1_addr_hi_SYM val1
859 /* __le32 tb_len1:12; */
860 #define IWL_tb1_len_POS 4
861 #define IWL_tb1_len_LEN 12
862 #define IWL_tb1_len_SYM val1
863 /* __le32 ptb2_0_15:16; */
864 #define IWL_tb2_addr_lo16_POS 16
865 #define IWL_tb2_addr_lo16_LEN 16
866 #define IWL_tb2_addr_lo16_SYM val1
869 /* __le32 ptb2_16_35:20; */
870 #define IWL_tb2_addr_hi20_POS 0
871 #define IWL_tb2_addr_hi20_LEN 20
872 #define IWL_tb2_addr_hi20_SYM val2
873 /* __le32 tb_len2:12; */
874 #define IWL_tb2_len_POS 20
875 #define IWL_tb2_len_LEN 12
876 #define IWL_tb2_len_SYM val2
877 } __attribute__ ((packed
));
881 * struct iwl4965_tfd_frame
883 * Transmit Frame Descriptor (TFD)
885 * 4965 supports up to 16 Tx queues resident in host DRAM.
886 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
887 * Both driver and device share these circular buffers, each of which must be
888 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes for 4965.
890 * Driver must indicate the physical address of the base of each
891 * circular buffer via the 4965's FH_MEM_CBBC_QUEUE registers.
893 * Each TFD contains pointer/size information for up to 20 data buffers
894 * in host DRAM. These buffers collectively contain the (one) frame described
895 * by the TFD. Each buffer must be a single contiguous block of memory within
896 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
897 * of (4K - 4). The 4965 concatenates all of a TFD's buffers into a single
898 * Tx frame, up to 8 KBytes in size.
900 * Bit fields in the control dword (val0):
901 * 31-30: # dwords (0-3) of padding required at end of frame for 16-byte bound
903 * 28-24: # Transmit Buffer Descriptors in TFD
906 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
908 struct iwl4965_tfd_frame
{
910 /* __le32 rsvd1:24; */
911 /* __le32 num_tbs:5; */
912 #define IWL_num_tbs_POS 24
913 #define IWL_num_tbs_LEN 5
914 #define IWL_num_tbs_SYM val0
915 /* __le32 rsvd2:1; */
916 /* __le32 padding:2; */
917 struct iwl4965_tfd_frame_data pa
[10];
919 } __attribute__ ((packed
));
923 * struct iwl4965_queue_byte_cnt_entry
925 * Byte Count Table Entry
929 * 11- 0: total to-be-transmitted byte count of frame (does not include command)
931 struct iwl4965_queue_byte_cnt_entry
{
933 /* __le16 byte_cnt:12; */
934 #define IWL_byte_cnt_POS 0
935 #define IWL_byte_cnt_LEN 12
936 #define IWL_byte_cnt_SYM val
938 } __attribute__ ((packed
));
942 * struct iwl4965_sched_queue_byte_cnt_tbl
946 * Each Tx queue uses a byte-count table containing 320 entries:
947 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
948 * duplicate the first 64 entries (to avoid wrap-around within a Tx window;
949 * max Tx window is 64 TFDs).
951 * When driver sets up a new TFD, it must also enter the total byte count
952 * of the frame to be transmitted into the corresponding entry in the byte
953 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver
954 * must duplicate the byte count entry in corresponding index 256-319.
956 * "dont_care" padding puts each byte count table on a 1024-byte boundary;
957 * 4965 assumes tables are separated by 1024 bytes.
959 struct iwl4965_sched_queue_byte_cnt_tbl
{
960 struct iwl4965_queue_byte_cnt_entry tfd_offset
[IWL49_QUEUE_SIZE
+
963 (IWL49_QUEUE_SIZE
+ IWL49_MAX_WIN_SIZE
) *
965 } __attribute__ ((packed
));
969 * struct iwl4965_shared - handshake area for Tx and Rx
971 * For convenience in allocating memory, this structure combines 2 areas of
972 * DRAM which must be shared between driver and 4965. These do not need to
973 * be combined, if better allocation would result from keeping them separate:
975 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for
976 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find
977 * the first of these tables. 4965 assumes tables are 1024 bytes apart.
979 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses
980 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area.
981 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD)
982 * that has been filled by the 4965.
986 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads)
991 struct iwl4965_shared
{
992 struct iwl4965_sched_queue_byte_cnt_tbl
993 queues_byte_cnt_tbls
[IWL49_NUM_QUEUES
];
996 /* __le32 rb_closed_stts_rb_num:12; */
997 #define IWL_rb_closed_stts_rb_num_POS 0
998 #define IWL_rb_closed_stts_rb_num_LEN 12
999 #define IWL_rb_closed_stts_rb_num_SYM rb_closed
1000 /* __le32 rsrv1:4; */
1001 /* __le32 rb_closed_stts_rx_frame_num:12; */
1002 #define IWL_rb_closed_stts_rx_frame_num_POS 16
1003 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
1004 #define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
1005 /* __le32 rsrv2:4; */
1007 __le32 frm_finished
;
1008 /* __le32 frame_finished_stts_rb_num:12; */
1009 #define IWL_frame_finished_stts_rb_num_POS 0
1010 #define IWL_frame_finished_stts_rb_num_LEN 12
1011 #define IWL_frame_finished_stts_rb_num_SYM frm_finished
1012 /* __le32 rsrv3:4; */
1013 /* __le32 frame_finished_stts_rx_frame_num:12; */
1014 #define IWL_frame_finished_stts_rx_frame_num_POS 16
1015 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
1016 #define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
1017 /* __le32 rsrv4:4; */
1019 __le32 padding1
; /* so that allocation will be aligned to 16B */
1021 } __attribute__ ((packed
));
1023 #endif /* __iwl4965_4965_hw_h__ */