drivers/net/wireless/iwlwifi/iwl-4965-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63
  64 #ifndef __iwl_4965_hw_h__
  65 #define __iwl_4965_hw_h__
  66
  67 /*
  68  * uCode queue management definitions ...
  69  * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
  70  * The first queue used for block-ack aggregation is #7 (4965 only).
  71  * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
  72  */
  73 #define IWL_CMD_QUEUE_NUM       4
  74 #define IWL_CMD_FIFO_NUM        4
  75 #define IWL_BACK_QUEUE_FIRST_ID 7
  76
  77 /* Tx rates */
  78 #define IWL_CCK_RATES 4
  79 #define IWL_OFDM_RATES 8
  80
  81 #define IWL_HT_RATES 16
  82
  83 #define IWL_MAX_RATES  (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
  84
  85 /* Time constants */
  86 #define SHORT_SLOT_TIME 9
  87 #define LONG_SLOT_TIME 20
  88
  89 /* RSSI to dBm */
  90 #define IWL_RSSI_OFFSET 44
  91
  92 /*
  93  * EEPROM related constants, enums, and structures.
  94  */
  95
  96 /*
  97  * EEPROM access time values:
  98  *
  99  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
 100  *   then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
 101  *   CSR_EEPROM_REG_BIT_CMD (0x2).
 102  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
 103  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
 104  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
 105  */
 106 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
 107 #define IWL_EEPROM_ACCESS_DELAY         10   /* uSec */
 108
 109 /*
 110  * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
 111  *
 112  * IBSS and/or AP operation is allowed *only* on those channels with
 113  * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
 114  * RADAR detection is not supported by the 4965 driver, but is a
 115  * requirement for establishing a new network for legal operation on channels
 116  * requiring RADAR detection or restricting ACTIVE scanning.
 117  *
 118  * NOTE:  "WIDE" flag does not indicate anything about "FAT" 40 MHz channels.
 119  *        It only indicates that 20 MHz channel use is supported; FAT channel
 120  *        usage is indicated by a separate set of regulatory flags for each
 121  *        FAT channel pair.
 122  *
 123  * NOTE:  Using a channel inappropriately will result in a uCode error!
 124  */
 125 enum {
 126         EEPROM_CHANNEL_VALID = (1 << 0),        /* usable for this SKU/geo */
 127         EEPROM_CHANNEL_IBSS = (1 << 1),         /* usable as an IBSS channel */
 128         /* Bit 2 Reserved */
 129         EEPROM_CHANNEL_ACTIVE = (1 << 3),       /* active scanning allowed */
 130         EEPROM_CHANNEL_RADAR = (1 << 4),        /* radar detection required */
 131         EEPROM_CHANNEL_WIDE = (1 << 5),         /* 20 MHz channel okay */
 132         EEPROM_CHANNEL_NARROW = (1 << 6),       /* 10 MHz channel (not used) */
 133         EEPROM_CHANNEL_DFS = (1 << 7),  /* dynamic freq selection candidate */
 134 };
 135
 136 /* SKU Capabilities */
 137 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 138 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 139
 140 /* *regulatory* channel data format in eeprom, one for each channel.
 141  * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */
 142 struct iwl4965_eeprom_channel {
 143         u8 flags;               /* EEPROM_CHANNEL_* flags copied from EEPROM */
 144         s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 145 } __attribute__ ((packed));
 146
 147 /* 4965 has two radio transmitters (and 3 radio receivers) */
 148 #define EEPROM_TX_POWER_TX_CHAINS      (2)
 149
 150 /* 4965 has room for up to 8 sets of txpower calibration data */
 151 #define EEPROM_TX_POWER_BANDS          (8)
 152
 153 /* 4965 factory calibration measures txpower gain settings for
 154  * each of 3 target output levels */
 155 #define EEPROM_TX_POWER_MEASUREMENTS   (3)
 156
 157 /* 4965 driver does not work with txpower calibration version < 5.
 158  * Look for this in calib_version member of struct iwl4965_eeprom. */
 159 #define EEPROM_TX_POWER_VERSION_NEW    (5)
 160
 161
 162 /*
 163  * 4965 factory calibration data for one txpower level, on one channel,
 164  * measured on one of the 2 tx chains (radio transmitter and associated
 165  * antenna).  EEPROM contains:
 166  *
 167  * 1)  Temperature (degrees Celsius) of device when measurement was made.
 168  *
 169  * 2)  Gain table index used to achieve the target measurement power.
 170  *     This refers to the "well-known" gain tables (see iwl-4965-hw.h).
 171  *
 172  * 3)  Actual measured output power, in half-dBm ("34" = 17 dBm).
 173  *
 174  * 4)  RF power amplifier detector level measurement (not used).
 175  */
 176 struct iwl4965_eeprom_calib_measure {
 177         u8 temperature;         /* Device temperature (Celsius) */
 178         u8 gain_idx;            /* Index into gain table */
 179         u8 actual_pow;          /* Measured RF output power, half-dBm */
 180         s8 pa_det;              /* Power amp detector level (not used) */
 181 } __attribute__ ((packed));
 182
 183
 184 /*
 185  * 4965 measurement set for one channel.  EEPROM contains:
 186  *
 187  * 1)  Channel number measured
 188  *
 189  * 2)  Measurements for each of 3 power levels for each of 2 radio transmitters
 190  *     (a.k.a. "tx chains") (6 measurements altogether)
 191  */
 192 struct iwl4965_eeprom_calib_ch_info {
 193         u8 ch_num;
 194         struct iwl4965_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
 195                 [EEPROM_TX_POWER_MEASUREMENTS];
 196 } __attribute__ ((packed));
 197
 198 /*
 199  * 4965 txpower subband info.
 200  *
 201  * For each frequency subband, EEPROM contains the following:
 202  *
 203  * 1)  First and last channels within range of the subband.  "0" values
 204  *     indicate that this sample set is not being used.
 205  *
 206  * 2)  Sample measurement sets for 2 channels close to the range endpoints.
 207  */
 208 struct iwl4965_eeprom_calib_subband_info {
 209         u8 ch_from;     /* channel number of lowest channel in subband */
 210         u8 ch_to;       /* channel number of highest channel in subband */
 211         struct iwl4965_eeprom_calib_ch_info ch1;
 212         struct iwl4965_eeprom_calib_ch_info ch2;
 213 } __attribute__ ((packed));
 214
 215
 216 /*
 217  * 4965 txpower calibration info.  EEPROM contains:
 218  *
 219  * 1)  Factory-measured saturation power levels (maximum levels at which
 220  *     tx power amplifier can output a signal without too much distortion).
 221  *     There is one level for 2.4 GHz band and one for 5 GHz band.  These
 222  *     values apply to all channels within each of the bands.
 223  *
 224  * 2)  Factory-measured power supply voltage level.  This is assumed to be
 225  *     constant (i.e. same value applies to all channels/bands) while the
 226  *     factory measurements are being made.
 227  *
 228  * 3)  Up to 8 sets of factory-measured txpower calibration values.
 229  *     These are for different frequency ranges, since txpower gain
 230  *     characteristics of the analog radio circuitry vary with frequency.
 231  *
 232  *     Not all sets need to be filled with data;
 233  *     struct iwl4965_eeprom_calib_subband_info contains range of channels
 234  *     (0 if unused) for each set of data.
 235  */
 236 struct iwl4965_eeprom_calib_info {
 237         u8 saturation_power24;  /* half-dBm (e.g. "34" = 17 dBm) */
 238         u8 saturation_power52;  /* half-dBm */
 239         s16 voltage;            /* signed */
 240         struct iwl4965_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
 241 } __attribute__ ((packed));
 242
 243
 244 /*
 245  * 4965 EEPROM map
 246  */
 247 struct iwl4965_eeprom {
 248         u8 reserved0[16];
 249 #define EEPROM_DEVICE_ID                    (2*0x08)    /* 2 bytes */
 250         u16 device_id;          /* abs.ofs: 16 */
 251         u8 reserved1[2];
 252 #define EEPROM_PMC                          (2*0x0A)    /* 2 bytes */
 253         u16 pmc;                /* abs.ofs: 20 */
 254         u8 reserved2[20];
 255 #define EEPROM_MAC_ADDRESS                  (2*0x15)    /* 6  bytes */
 256         u8 mac_address[6];      /* abs.ofs: 42 */
 257         u8 reserved3[58];
 258 #define EEPROM_BOARD_REVISION               (2*0x35)    /* 2  bytes */
 259         u16 board_revision;     /* abs.ofs: 106 */
 260         u8 reserved4[11];
 261 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)  /* 9  bytes */
 262         u8 board_pba_number[9]; /* abs.ofs: 119 */
 263         u8 reserved5[8];
 264 #define EEPROM_VERSION                      (2*0x44)    /* 2  bytes */
 265         u16 version;            /* abs.ofs: 136 */
 266 #define EEPROM_SKU_CAP                      (2*0x45)    /* 1  bytes */
 267         u8 sku_cap;             /* abs.ofs: 138 */
 268 #define EEPROM_LEDS_MODE                    (2*0x45+1)  /* 1  bytes */
 269         u8 leds_mode;           /* abs.ofs: 139 */
 270 #define EEPROM_OEM_MODE                     (2*0x46)    /* 2  bytes */
 271         u16 oem_mode;
 272 #define EEPROM_WOWLAN_MODE                  (2*0x47)    /* 2  bytes */
 273         u16 wowlan_mode;        /* abs.ofs: 142 */
 274 #define EEPROM_LEDS_TIME_INTERVAL           (2*0x48)    /* 2  bytes */
 275         u16 leds_time_interval; /* abs.ofs: 144 */
 276 #define EEPROM_LEDS_OFF_TIME                (2*0x49)    /* 1  bytes */
 277         u8 leds_off_time;       /* abs.ofs: 146 */
 278 #define EEPROM_LEDS_ON_TIME                 (2*0x49+1)  /* 1  bytes */
 279         u8 leds_on_time;        /* abs.ofs: 147 */
 280 #define EEPROM_ALMGOR_M_VERSION             (2*0x4A)    /* 1  bytes */
 281         u8 almgor_m_version;    /* abs.ofs: 148 */
 282 #define EEPROM_ANTENNA_SWITCH_TYPE          (2*0x4A+1)  /* 1  bytes */
 283         u8 antenna_switch_type; /* abs.ofs: 149 */
 284         u8 reserved6[8];
 285 #define EEPROM_4965_BOARD_REVISION          (2*0x4F)    /* 2 bytes */
 286         u16 board_revision_4965;        /* abs.ofs: 158 */
 287         u8 reserved7[13];
 288 #define EEPROM_4965_BOARD_PBA               (2*0x56+1)  /* 9 bytes */
 289         u8 board_pba_number_4965[9];    /* abs.ofs: 173 */
 290         u8 reserved8[10];
 291 #define EEPROM_REGULATORY_SKU_ID            (2*0x60)    /* 4  bytes */
 292         u8 sku_id[4];           /* abs.ofs: 192 */
 293
 294 /*
 295  * Per-channel regulatory data.
 296  *
 297  * Each channel that *might* be supported by 3945 or 4965 has a fixed location
 298  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 299  * txpower (MSB).
 300  *
 301  * Entries immediately below are for 20 MHz channel width.  FAT (40 MHz)
 302  * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
 303  *
 304  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 305  */
 306 #define EEPROM_REGULATORY_BAND_1            (2*0x62)    /* 2  bytes */
 307         u16 band_1_count;       /* abs.ofs: 196 */
 308 #define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)    /* 28 bytes */
 309         struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
 310
 311 /*
 312  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 313  * 5.0 GHz channels 7, 8, 11, 12, 16
 314  * (4915-5080MHz) (none of these is ever supported)
 315  */
 316 #define EEPROM_REGULATORY_BAND_2            (2*0x71)    /* 2  bytes */
 317         u16 band_2_count;       /* abs.ofs: 226 */
 318 #define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)    /* 26 bytes */
 319         struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
 320
 321 /*
 322  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 323  * (5170-5320MHz)
 324  */
 325 #define EEPROM_REGULATORY_BAND_3            (2*0x7F)    /* 2  bytes */
 326         u16 band_3_count;       /* abs.ofs: 254 */
 327 #define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)    /* 24 bytes */
 328         struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
 329
 330 /*
 331  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 332  * (5500-5700MHz)
 333  */
 334 #define EEPROM_REGULATORY_BAND_4            (2*0x8C)    /* 2  bytes */
 335         u16 band_4_count;       /* abs.ofs: 280 */
 336 #define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)    /* 22 bytes */
 337         struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
 338
 339 /*
 340  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 341  * (5725-5825MHz)
 342  */
 343 #define EEPROM_REGULATORY_BAND_5            (2*0x98)    /* 2  bytes */
 344         u16 band_5_count;       /* abs.ofs: 304 */
 345 #define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)    /* 12 bytes */
 346         struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
 347
 348         u8 reserved10[2];
 349
 350
 351 /*
 352  * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
 353  *
 354  * The channel listed is the center of the lower 20 MHz half of the channel.
 355  * The overall center frequency is actually 2 channels (10 MHz) above that,
 356  * and the upper half of each FAT channel is centered 4 channels (20 MHz) away
 357  * from the lower half; e.g. the upper half of FAT channel 1 is channel 5,
 358  * and the overall FAT channel width centers on channel 3.
 359  *
 360  * NOTE:  The RXON command uses 20 MHz channel numbers to specify the
 361  *        control channel to which to tune.  RXON also specifies whether the
 362  *        control channel is the upper or lower half of a FAT channel.
 363  *
 364  * NOTE:  4965 does not support FAT channels on 2.4 GHz.
 365  */
 366 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
 367         struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
 368         u8 reserved11[2];
 369
 370 /*
 371  * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64),
 372  * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
 373  */
 374 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
 375         struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
 376         u8 reserved12[6];
 377
 378 /*
 379  * 4965 driver requires txpower calibration format version 5 or greater.
 380  * Driver does not work with txpower calibration version < 5.
 381  * This value is simply a 16-bit number, no major/minor versions here.
 382  */
 383 #define EEPROM_CALIB_VERSION_OFFSET            (2*0xB6) /* 2 bytes */
 384         u16 calib_version;      /* abs.ofs: 364 */
 385         u8 reserved13[2];
 386         u8 reserved14[96];      /* abs.ofs: 368 */
 387
 388 /*
 389  * 4965 Txpower calibration data.
 390  */
 391 #define EEPROM_IWL_CALIB_TXPOWER_OFFSET        (2*0xE8) /* 48  bytes */
 392         struct iwl4965_eeprom_calib_info calib_info;    /* abs.ofs: 464 */
 393
 394         u8 reserved16[140];     /* fill out to full 1024 byte block */
 395
 396
 397 } __attribute__ ((packed));
 398
 399 #define IWL_EEPROM_IMAGE_SIZE 1024
 400
 401 /* End of EEPROM */
 402
 403 #include "iwl-4965-commands.h"
 404
 405 #define PCI_LINK_CTRL      0x0F0
 406 #define PCI_POWER_SOURCE   0x0C8
 407 #define PCI_REG_WUM8       0x0E8
 408 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)
 409
 410 /*=== CSR (control and status registers) ===*/
 411 #define CSR_BASE    (0x000)
 412
 413 #define CSR_SW_VER              (CSR_BASE+0x000)
 414 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
 415 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
 416 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
 417 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
 418 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
 419 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
 420 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
 421 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
 422
 423 /*
 424  * Hardware revision info
 425  * Bit fields:
 426  * 31-8:  Reserved
 427  *  7-4:  Type of device:  0x0 = 4965, 0xd = 3945
 428  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 429  *  1-0:  "Dash" value, as in A-1, etc.
 430  *
 431  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
 432  */
 433 #define CSR_HW_REV              (CSR_BASE+0x028)
 434
 435 /* EEPROM reads */
 436 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 437 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 438 #define CSR_GP_UCODE            (CSR_BASE+0x044)
 439 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 440 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 441 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 442 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 443 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 444
 445 /*
 446  * Indicates hardware rev, to determine CCK backoff for txpower calculation.
 447  * Bit fields:
 448  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 449  */
 450 #define CSR_HW_REV_WA_REG       (CSR_BASE+0x22C)
 451
 452 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM     (0x00200000)
 453
 454 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 455  * acknowledged (reset) by host writing "1" to flagged bits. */
 456 #define CSR_INT_BIT_FH_RX        (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 457 #define CSR_INT_BIT_HW_ERR       (1<<29) /* DMA hardware error FH_INT[31] */
 458 #define CSR_INT_BIT_DNLD         (1<<28) /* uCode Download */
 459 #define CSR_INT_BIT_FH_TX        (1<<27) /* Tx DMA FH_INT[1:0] */
 460 #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
 461 #define CSR_INT_BIT_SW_ERR       (1<<25) /* uCode error */
 462 #define CSR_INT_BIT_RF_KILL      (1<<7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 463 #define CSR_INT_BIT_CT_KILL      (1<<6)  /* Critical temp (chip too hot) rfkill */
 464 #define CSR_INT_BIT_SW_RX        (1<<3)  /* Rx, command responses, 3945 */
 465 #define CSR_INT_BIT_WAKEUP       (1<<1)  /* NIC controller waking up (pwr mgmt) */
 466 #define CSR_INT_BIT_ALIVE        (1<<0)  /* uCode interrupts once it initializes */
 467
 468 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 469                                  CSR_INT_BIT_HW_ERR  | \
 470                                  CSR_INT_BIT_FH_TX   | \
 471                                  CSR_INT_BIT_SW_ERR  | \
 472                                  CSR_INT_BIT_RF_KILL | \
 473                                  CSR_INT_BIT_SW_RX   | \
 474                                  CSR_INT_BIT_WAKEUP  | \
 475                                  CSR_INT_BIT_ALIVE)
 476
 477 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 478 #define CSR_FH_INT_BIT_ERR       (1<<31) /* Error */
 479 #define CSR_FH_INT_BIT_HI_PRIOR  (1<<30) /* High priority Rx, bypass coalescing */
 480 #define CSR_FH_INT_BIT_RX_CHNL1  (1<<17) /* Rx channel 1 */
 481 #define CSR_FH_INT_BIT_RX_CHNL0  (1<<16) /* Rx channel 0 */
 482 #define CSR_FH_INT_BIT_TX_CHNL1  (1<<1)  /* Tx channel 1 */
 483 #define CSR_FH_INT_BIT_TX_CHNL0  (1<<0)  /* Tx channel 0 */
 484
 485 #define CSR_FH_INT_RX_MASK      (CSR_FH_INT_BIT_HI_PRIOR | \
 486                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 487                                  CSR_FH_INT_BIT_RX_CHNL0)
 488
 489 #define CSR_FH_INT_TX_MASK      (CSR_FH_INT_BIT_TX_CHNL1 | \
 490                                  CSR_FH_INT_BIT_TX_CHNL0)
 491
 492
 493 /* RESET */
 494 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 495 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 496 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 497 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 498 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 499
 500 /* GP (general purpose) CONTROL */
 501 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 502 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 503 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 504 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 505
 506 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 507
 508 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 509 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 510 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 511
 512
 513 /* EEPROM REG */
 514 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 515 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 516
 517 /* EEPROM GP */
 518 #define CSR_EEPROM_GP_VALID_MSK         (0x00000006)
 519 #define CSR_EEPROM_GP_BAD_SIGNATURE     (0x00000000)
 520 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 521
 522 /* UCODE DRV GP */
 523 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 524 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 525 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 526 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 527
 528 /* GPIO */
 529 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 530 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 531 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC           CSR_GPIO_IN_BIT_AUX_POWER
 532
 533 /* GI Chicken Bits */
 534 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 535 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 536
 537 /*=== HBUS (Host-side Bus) ===*/
 538 #define HBUS_BASE       (0x400)
 539
 540 /*
 541  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 542  * structures, error log, event log, verifying uCode load).
 543  * First write to address register, then read from or write to data register
 544  * to complete the job.  Once the address register is set up, accesses to
 545  * data registers auto-increment the address by one dword.
 546  * Bit usage for address registers (read or write):
 547  *  0-31:  memory address within device
 548  */
 549 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 550 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 551 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 552 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 553
 554 /*
 555  * Registers for accessing device's internal peripheral registers
 556  * (e.g. SCD, BSM, etc.).  First write to address register,
 557  * then read from or write to data register to complete the job.
 558  * Bit usage for address registers (read or write):
 559  *  0-15:  register address (offset) within device
 560  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 561  */
 562 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 563 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 564 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 565 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 566
 567 /*
 568  * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
 569  * Indicates index to next TFD that driver will fill (1 past latest filled).
 570  * Bit usage:
 571  *  0-7:  queue write index (0-255)
 572  * 11-8:  queue selector (0-15)
 573  */
 574 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 575
 576 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 577
 578 /*=== FH (data Flow Handler) ===*/
 579 #define FH_BASE     (0x800)
 580
 581 #define FH_RSCSR_CHNL0_WPTR        (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
 582
 583 /* RSSR */
 584 #define FH_RSSR_CTRL            (FH_RSSR_TABLE+0x000)
 585 #define FH_RSSR_STATUS          (FH_RSSR_TABLE+0x004)
 586 /* TCSR */
 587 #define FH_TCSR(_channel)           (FH_TCSR_TABLE+(_channel)*0x20)
 588 #define FH_TCSR_CONFIG(_channel)    (FH_TCSR(_channel)+0x00)
 589 #define FH_TCSR_CREDIT(_channel)    (FH_TCSR(_channel)+0x04)
 590 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
 591 /* TSSR */
 592 #define FH_TSSR_CBB_BASE        (FH_TSSR_TABLE+0x000)
 593 #define FH_TSSR_MSG_CONFIG      (FH_TSSR_TABLE+0x008)
 594 #define FH_TSSR_TX_STATUS       (FH_TSSR_TABLE+0x010)
 595 /* 18 - reserved */
 596
 597 /* card static random access memory (SRAM) for processor data and instructs */
 598 #define RTC_INST_LOWER_BOUND                    (0x000000)
 599 #define RTC_DATA_LOWER_BOUND                    (0x800000)
 600
 601 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 602
 603 #define TFD_QUEUE_SIZE_MAX      (256)
 604
 605 /* spectrum and channel data structures */
 606 #define IWL_NUM_SCAN_RATES         (2)
 607
 608 #define IWL_DEFAULT_TX_RETRY  15
 609
 610 #define RX_QUEUE_SIZE                         256
 611 #define RX_QUEUE_MASK                         255
 612 #define RX_QUEUE_SIZE_LOG                     8
 613
 614 #define TFD_TX_CMD_SLOTS 256
 615 #define TFD_CMD_SLOTS 32
 616
 617 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \
 618                               sizeof(struct iwl4965_cmd_meta))
 619
 620 /*
 621  * RX related structures and functions
 622  */
 623 #define RX_FREE_BUFFERS 64
 624 #define RX_LOW_WATERMARK 8
 625
 626
 627 #define IWL_RX_BUF_SIZE (4 * 1024)
 628 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
 629 #define KDR_RTC_INST_UPPER_BOUND                (0x018000)
 630 #define KDR_RTC_DATA_UPPER_BOUND                (0x80A000)
 631 #define KDR_RTC_INST_SIZE    (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
 632 #define KDR_RTC_DATA_SIZE    (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
 633
 634 #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
 635 #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
 636
 637 static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
 638 {
 639         return (addr >= RTC_DATA_LOWER_BOUND) &&
 640                (addr < KDR_RTC_DATA_UPPER_BOUND);
 641 }
 642
 643 /********************* START TXPOWER *****************************************/
 644 enum {
 645         HT_IE_EXT_CHANNEL_NONE = 0,
 646         HT_IE_EXT_CHANNEL_ABOVE,
 647         HT_IE_EXT_CHANNEL_INVALID,
 648         HT_IE_EXT_CHANNEL_BELOW,
 649         HT_IE_EXT_CHANNEL_MAX
 650 };
 651
 652 enum {
 653         CALIB_CH_GROUP_1 = 0,
 654         CALIB_CH_GROUP_2 = 1,
 655         CALIB_CH_GROUP_3 = 2,
 656         CALIB_CH_GROUP_4 = 3,
 657         CALIB_CH_GROUP_5 = 4,
 658         CALIB_CH_GROUP_MAX
 659 };
 660
 661 /* Temperature calibration offset is 3% 0C in Kelvin */
 662 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
 663 #define TEMPERATURE_CALIB_A_VAL 259
 664
 665 #define IWL_TX_POWER_TEMPERATURE_MIN  (263)
 666 #define IWL_TX_POWER_TEMPERATURE_MAX  (410)
 667
 668 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
 669         (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
 670          ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
 671
 672 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
 673
 674 #define IWL_TX_POWER_TARGET_POWER_MIN       (0) /* 0 dBm = 1 milliwatt */
 675 #define IWL_TX_POWER_TARGET_POWER_MAX      (16) /* 16 dBm */
 676
 677 #define MIN_TX_GAIN_INDEX               (0)
 678 #define MIN_TX_GAIN_INDEX_52GHZ_EXT     (-9)
 679
 680 #define IWL_TX_POWER_DEFAULT_REGULATORY_24   (34)
 681 #define IWL_TX_POWER_DEFAULT_REGULATORY_52   (34)
 682 #define IWL_TX_POWER_REGULATORY_MIN          (0)
 683 #define IWL_TX_POWER_REGULATORY_MAX          (34)
 684 #define IWL_TX_POWER_DEFAULT_SATURATION_24   (38)
 685 #define IWL_TX_POWER_DEFAULT_SATURATION_52   (38)
 686 #define IWL_TX_POWER_SATURATION_MIN          (20)
 687 #define IWL_TX_POWER_SATURATION_MAX          (50)
 688
 689 /* First and last channels of all groups */
 690 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
 691 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
 692 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
 693 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
 694 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
 695 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
 696 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
 697 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
 698 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
 699 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
 700
 701 /********************* END TXPOWER *****************************************/
 702
 703 /* Flow Handler Definitions */
 704
 705 /**********************/
 706 /*     Addresses      */
 707 /**********************/
 708
 709 #define FH_MEM_LOWER_BOUND                   (0x1000)
 710 #define FH_MEM_UPPER_BOUND                   (0x1EF0)
 711
 712 #define IWL_FH_REGS_LOWER_BOUND              (0x1000)
 713 #define IWL_FH_REGS_UPPER_BOUND              (0x2000)
 714
 715 #define IWL_FH_KW_MEM_ADDR_REG               (FH_MEM_LOWER_BOUND + 0x97C)
 716
 717 /* CBBC Area - Circular buffers base address cache pointers table */
 718 #define FH_MEM_CBBC_LOWER_BOUND              (FH_MEM_LOWER_BOUND + 0x9D0)
 719 #define FH_MEM_CBBC_UPPER_BOUND              (FH_MEM_LOWER_BOUND + 0xA10)
 720 /* queues 0 - 15 */
 721 #define FH_MEM_CBBC_QUEUE(x)  (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
 722
 723 /* RSCSR Area */
 724 #define FH_MEM_RSCSR_LOWER_BOUND        (FH_MEM_LOWER_BOUND + 0xBC0)
 725 #define FH_MEM_RSCSR_UPPER_BOUND        (FH_MEM_LOWER_BOUND + 0xC00)
 726 #define FH_MEM_RSCSR_CHNL0              (FH_MEM_RSCSR_LOWER_BOUND)
 727
 728 #define FH_RSCSR_CHNL0_STTS_WPTR_REG            (FH_MEM_RSCSR_CHNL0)
 729 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG           (FH_MEM_RSCSR_CHNL0 + 0x004)
 730 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG           (FH_MEM_RSCSR_CHNL0 + 0x008)
 731
 732 /* RCSR Area - Registers address map */
 733 #define FH_MEM_RCSR_LOWER_BOUND      (FH_MEM_LOWER_BOUND + 0xC00)
 734 #define FH_MEM_RCSR_UPPER_BOUND      (FH_MEM_LOWER_BOUND + 0xCC0)
 735 #define FH_MEM_RCSR_CHNL0            (FH_MEM_RCSR_LOWER_BOUND)
 736
 737 #define FH_MEM_RCSR_CHNL0_CONFIG_REG    (FH_MEM_RCSR_CHNL0)
 738
 739 /* RSSR Area - Rx shared ctrl & status registers */
 740 #define FH_MEM_RSSR_LOWER_BOUND                 (FH_MEM_LOWER_BOUND + 0xC40)
 741 #define FH_MEM_RSSR_UPPER_BOUND                 (FH_MEM_LOWER_BOUND + 0xD00)
 742 #define FH_MEM_RSSR_SHARED_CTRL_REG             (FH_MEM_RSSR_LOWER_BOUND)
 743 #define FH_MEM_RSSR_RX_STATUS_REG       (FH_MEM_RSSR_LOWER_BOUND + 0x004)
 744 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV  (FH_MEM_RSSR_LOWER_BOUND + 0x008)
 745
 746 /* TCSR */
 747 #define IWL_FH_TCSR_LOWER_BOUND  (IWL_FH_REGS_LOWER_BOUND + 0xD00)
 748 #define IWL_FH_TCSR_UPPER_BOUND  (IWL_FH_REGS_LOWER_BOUND + 0xE60)
 749
 750 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
 751         (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
 752
 753 /* TSSR Area - Tx shared status registers */
 754 /* TSSR */
 755 #define IWL_FH_TSSR_LOWER_BOUND         (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
 756 #define IWL_FH_TSSR_UPPER_BOUND         (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
 757
 758 #define IWL_FH_TSSR_TX_STATUS_REG       (IWL_FH_TSSR_LOWER_BOUND + 0x010)
 759
 760 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
 761         ((1 << (_chnl)) << 24)
 762 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
 763         ((1 << (_chnl)) << 16)
 764
 765 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
 766         (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
 767         IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
 768
 769 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL     (0x00000008)
 770
 771 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE           (0x80000000)
 772
 773 /* RCSR:  channel 0 rx_config register defines */
 774
 775 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT       (20)
 776
 777 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL        (0x80000000)
 778
 779 #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K    (0x00000000)
 780
 781 /* RCSR channel 0 config register values */
 782 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL     (0x00001000)
 783
 784 #define SCD_WIN_SIZE                            64
 785 #define SCD_FRAME_LIMIT                         64
 786
 787 /* SRAM structures */
 788 #define SCD_CONTEXT_DATA_OFFSET                 0x380
 789 #define SCD_TX_STTS_BITMAP_OFFSET               0x400
 790 #define SCD_TRANSLATE_TBL_OFFSET                0x500
 791 #define SCD_CONTEXT_QUEUE_OFFSET(x)     (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
 792 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
 793         ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
 794
 795 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
 796        ((1<<(hi))|((1<<(hi))-(1<<(lo))))
 797
 798 #define SCD_QUEUE_STTS_REG_POS_ACTIVE           (0)
 799 #define SCD_QUEUE_STTS_REG_POS_TXF              (1)
 800 #define SCD_QUEUE_STTS_REG_POS_WSL              (5)
 801 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK          (8)
 802 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN       (10)
 803 #define SCD_QUEUE_STTS_REG_MSK                  (0x0007FC00)
 804
 805 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS         (0)
 806 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK         (0x0000007F)
 807
 808 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS      (16)
 809 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK      (0x007F0000)
 810
 811 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R       (0x00000010)
 812 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 813 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 814 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 815
 816 static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
 817 {
 818         return le32_to_cpu(rate_n_flags) & 0xFF;
 819 }
 820 static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags)
 821 {
 822         return le32_to_cpu(rate_n_flags) & 0xFFFF;
 823 }
 824 static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
 825 {
 826         return cpu_to_le32(flags|(u16)rate);
 827 }
 828
 829 struct iwl4965_tfd_frame_data {
 830         __le32 tb1_addr;
 831
 832         __le32 val1;
 833         /* __le32 ptb1_32_35:4; */
 834 #define IWL_tb1_addr_hi_POS 0
 835 #define IWL_tb1_addr_hi_LEN 4
 836 #define IWL_tb1_addr_hi_SYM val1
 837         /* __le32 tb_len1:12; */
 838 #define IWL_tb1_len_POS 4
 839 #define IWL_tb1_len_LEN 12
 840 #define IWL_tb1_len_SYM val1
 841         /* __le32 ptb2_0_15:16; */
 842 #define IWL_tb2_addr_lo16_POS 16
 843 #define IWL_tb2_addr_lo16_LEN 16
 844 #define IWL_tb2_addr_lo16_SYM val1
 845
 846         __le32 val2;
 847         /* __le32 ptb2_16_35:20; */
 848 #define IWL_tb2_addr_hi20_POS 0
 849 #define IWL_tb2_addr_hi20_LEN 20
 850 #define IWL_tb2_addr_hi20_SYM val2
 851         /* __le32 tb_len2:12; */
 852 #define IWL_tb2_len_POS 20
 853 #define IWL_tb2_len_LEN 12
 854 #define IWL_tb2_len_SYM val2
 855 } __attribute__ ((packed));
 856
 857 struct iwl4965_tfd_frame {
 858         __le32 val0;
 859         /* __le32 rsvd1:24; */
 860         /* __le32 num_tbs:5; */
 861 #define IWL_num_tbs_POS 24
 862 #define IWL_num_tbs_LEN 5
 863 #define IWL_num_tbs_SYM val0
 864         /* __le32 rsvd2:1; */
 865         /* __le32 padding:2; */
 866         struct iwl4965_tfd_frame_data pa[10];
 867         __le32 reserved;
 868 } __attribute__ ((packed));
 869
 870 #define IWL4965_MAX_WIN_SIZE              64
 871 #define IWL4965_QUEUE_SIZE               256
 872 #define IWL4965_NUM_FIFOS                  7
 873 #define IWL_MAX_NUM_QUEUES                16
 874
 875 struct iwl4965_queue_byte_cnt_entry {
 876         __le16 val;
 877         /* __le16 byte_cnt:12; */
 878 #define IWL_byte_cnt_POS 0
 879 #define IWL_byte_cnt_LEN 12
 880 #define IWL_byte_cnt_SYM val
 881         /* __le16 rsvd:4; */
 882 } __attribute__ ((packed));
 883
 884 struct iwl4965_sched_queue_byte_cnt_tbl {
 885         struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
 886                                                        IWL4965_MAX_WIN_SIZE];
 887         u8 dont_care[1024 -
 888                      (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) *
 889                      sizeof(__le16)];
 890 } __attribute__ ((packed));
 891
 892 /* Base physical address of iwl4965_shared is provided to KDR_SCD_DRAM_BASE_ADDR
 893  * and &iwl4965_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
 894 struct iwl4965_shared {
 895         struct iwl4965_sched_queue_byte_cnt_tbl
 896          queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
 897         __le32 val0;
 898
 899         /* __le32 rb_closed_stts_rb_num:12; */
 900 #define IWL_rb_closed_stts_rb_num_POS 0
 901 #define IWL_rb_closed_stts_rb_num_LEN 12
 902 #define IWL_rb_closed_stts_rb_num_SYM val0
 903         /* __le32 rsrv1:4; */
 904         /* __le32 rb_closed_stts_rx_frame_num:12; */
 905 #define IWL_rb_closed_stts_rx_frame_num_POS 16
 906 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
 907 #define IWL_rb_closed_stts_rx_frame_num_SYM val0
 908         /* __le32 rsrv2:4; */
 909
 910         __le32 val1;
 911         /* __le32 frame_finished_stts_rb_num:12; */
 912 #define IWL_frame_finished_stts_rb_num_POS 0
 913 #define IWL_frame_finished_stts_rb_num_LEN 12
 914 #define IWL_frame_finished_stts_rb_num_SYM val1
 915         /* __le32 rsrv3:4; */
 916         /* __le32 frame_finished_stts_rx_frame_num:12; */
 917 #define IWL_frame_finished_stts_rx_frame_num_POS 16
 918 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
 919 #define IWL_frame_finished_stts_rx_frame_num_SYM val1
 920         /* __le32 rsrv4:4; */
 921
 922         __le32 padding1;  /* so that allocation will be aligned to 16B */
 923         __le32 padding2;
 924 } __attribute__ ((packed));
 925
 926 #endif /* __iwl4965_4965_hw_h__ */