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iwlwifi: Partially clean-up, add comments to iwl-*-hw.h
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965-hw.h
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64 #ifndef __iwl_4965_hw_h__
65 #define __iwl_4965_hw_h__
66
67 /*
68 * uCode queue management definitions ...
69 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
70 * The first queue used for block-ack aggregation is #7 (4965 only).
71 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
72 */
73 #define IWL_CMD_QUEUE_NUM 4
74 #define IWL_CMD_FIFO_NUM 4
75 #define IWL_BACK_QUEUE_FIRST_ID 7
76
77 /* Tx rates */
78 #define IWL_CCK_RATES 4
79 #define IWL_OFDM_RATES 8
80
81 #define IWL_HT_RATES 16
82
83 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
84
85 /* Time constants */
86 #define SHORT_SLOT_TIME 9
87 #define LONG_SLOT_TIME 20
88
89 /* RSSI to dBm */
90 #define IWL_RSSI_OFFSET 44
91
92 /*
93 * EEPROM related constants, enums, and structures.
94 */
95
96 /*
97 * EEPROM access time values:
98 *
99 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
100 * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
101 * CSR_EEPROM_REG_BIT_CMD (0x2).
102 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
103 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
104 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
105 */
106 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
107 #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
108
109 /* EEPROM field values */
110 #define ANTENNA_SWITCH_NORMAL 0
111 #define ANTENNA_SWITCH_INVERSE 1
112
113 /*
114 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
115 *
116 * IBSS and/or AP operation is allowed *only* on those channels with
117 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
118 * RADAR detection is not supported by the 4965 driver, but is a
119 * requirement for establishing a new network for legal operation on channels
120 * requiring RADAR detection or restricting ACTIVE scanning.
121 *
122 * NOTE: "WIDE" flag does not indicate anything about "FAT" 40 MHz channels.
123 * It only indicates that 20 MHz channel use is supported; FAT channel
124 * usage is indicated by a separate set of regulatory flags for each
125 * FAT channel pair.
126 *
127 * NOTE: Using a channel inappropriately will result in a uCode error!
128 */
129 enum {
130 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
131 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
132 /* Bit 2 Reserved */
133 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
134 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
135 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
136 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel, not used */
137 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
138 };
139
140 /* EEPROM field lengths */
141 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
142
143 /* EEPROM field lengths */
144 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
145 #define EEPROM_REGULATORY_SKU_ID_LENGTH 4
146 #define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
147 #define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
148 #define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
149 #define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
150 #define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
151
152 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH 7
153 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH 11
154 #define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
155 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
156 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
157 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
158 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
159 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH + \
160 EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH + \
161 EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH)
162
163 #define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
164
165 /* SKU Capabilities */
166 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
167 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
168 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
169
170 /* *regulatory* channel data format in eeprom, one for each channel.
171 * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */
172 struct iwl4965_eeprom_channel {
173 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
174 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
175 } __attribute__ ((packed));
176
177 /* 4965 has two radio transmitters (and 3 radio receivers) */
178 #define EEPROM_TX_POWER_TX_CHAINS (2)
179
180 /* 4965 has room for up to 8 sets of txpower calibration data */
181 #define EEPROM_TX_POWER_BANDS (8)
182
183 /* 4965 factory calibration measures txpower gain settings for
184 * each of 3 target output levels */
185 #define EEPROM_TX_POWER_MEASUREMENTS (3)
186
187 /* 4965 driver does not work with txpower calibration version < 5.
188 * Look for this in calib_version member of struct iwl4965_eeprom. */
189 #define EEPROM_TX_POWER_VERSION_NEW (5)
190
191
192 /*
193 * 4965 factory calibration data for one txpower level, on one channel,
194 * measured on one of the 2 tx chains (radio transmitter and associated
195 * antenna). EEPROM contains:
196 *
197 * 1) Temperature (degrees Celsius) of device when measurement was made.
198 *
199 * 2) Gain table index used to achieve the target measurement power.
200 * This refers to the "well-known" gain tables (see iwl-4965-hw.h).
201 *
202 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
203 *
204 * 4) RF power amplifier detector level measurement (not used).
205 */
206 struct iwl4965_eeprom_calib_measure {
207 u8 temperature; /* Device temperature (Celsius) */
208 u8 gain_idx; /* Index into gain table */
209 u8 actual_pow; /* Measured RF output power, half-dBm */
210 s8 pa_det; /* Power amp detector level (not used) */
211 } __attribute__ ((packed));
212
213
214 /*
215 * 4965 measurement set for one channel. EEPROM contains:
216 *
217 * 1) Channel number measured
218 *
219 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
220 * (a.k.a. "tx chains") (6 measurements altogether)
221 */
222 struct iwl4965_eeprom_calib_ch_info {
223 u8 ch_num;
224 struct iwl4965_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
225 [EEPROM_TX_POWER_MEASUREMENTS];
226 } __attribute__ ((packed));
227
228 /*
229 * 4965 txpower subband info.
230 *
231 * For each frequency subband, EEPROM contains the following:
232 *
233 * 1) First and last channels within range of the subband. "0" values
234 * indicate that this sample set is not being used.
235 *
236 * 2) Sample measurement sets for 2 channels close to the range endpoints.
237 */
238 struct iwl4965_eeprom_calib_subband_info {
239 u8 ch_from; /* channel number of lowest channel in subband */
240 u8 ch_to; /* channel number of highest channel in subband */
241 struct iwl4965_eeprom_calib_ch_info ch1;
242 struct iwl4965_eeprom_calib_ch_info ch2;
243 } __attribute__ ((packed));
244
245
246 /*
247 * 4965 txpower calibration info. EEPROM contains:
248 *
249 * 1) Factory-measured saturation power levels (maximum levels at which
250 * tx power amplifier can output a signal without too much distortion).
251 * There is one level for 2.4 GHz band and one for 5 GHz band. These
252 * values apply to all channels within each of the bands.
253 *
254 * 2) Factory-measured power supply voltage level. This is assumed to be
255 * constant (i.e. same value applies to all channels/bands) while the
256 * factory measurements are being made.
257 *
258 * 3) Up to 8 sets of factory-measured txpower calibration values.
259 * These are for different frequency ranges, since txpower gain
260 * characteristics of the analog radio circuitry vary with frequency.
261 *
262 * Not all sets need to be filled with data;
263 * struct iwl4965_eeprom_calib_subband_info contains range of channels
264 * (0 if unused) for each set of data.
265 */
266 struct iwl4965_eeprom_calib_info {
267 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
268 u8 saturation_power52; /* half-dBm */
269 s16 voltage; /* signed */
270 struct iwl4965_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
271 } __attribute__ ((packed));
272
273
274 /*
275 * 4965 EEPROM map
276 */
277 struct iwl4965_eeprom {
278 u8 reserved0[16];
279 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
280 u16 device_id; /* abs.ofs: 16 */
281 u8 reserved1[2];
282 #define EEPROM_PMC (2*0x0A) /* 2 bytes */
283 u16 pmc; /* abs.ofs: 20 */
284 u8 reserved2[20];
285 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
286 u8 mac_address[6]; /* abs.ofs: 42 */
287 u8 reserved3[58];
288 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
289 u16 board_revision; /* abs.ofs: 106 */
290 u8 reserved4[11];
291 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
292 u8 board_pba_number[9]; /* abs.ofs: 119 */
293 u8 reserved5[8];
294 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
295 u16 version; /* abs.ofs: 136 */
296 #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
297 u8 sku_cap; /* abs.ofs: 138 */
298 #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
299 u8 leds_mode; /* abs.ofs: 139 */
300 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
301 u16 oem_mode;
302 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
303 u16 wowlan_mode; /* abs.ofs: 142 */
304 #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
305 u16 leds_time_interval; /* abs.ofs: 144 */
306 #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
307 u8 leds_off_time; /* abs.ofs: 146 */
308 #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
309 u8 leds_on_time; /* abs.ofs: 147 */
310 #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
311 u8 almgor_m_version; /* abs.ofs: 148 */
312 #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
313 u8 antenna_switch_type; /* abs.ofs: 149 */
314 u8 reserved6[8];
315 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
316 u16 board_revision_4965; /* abs.ofs: 158 */
317 u8 reserved7[13];
318 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
319 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */
320 u8 reserved8[10];
321 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
322 u8 sku_id[4]; /* abs.ofs: 192 */
323
324 /*
325 * Per-channel regulatory data.
326 *
327 * Each channel that *might* be supported by 3945 or 4965 has a fixed location
328 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
329 * txpower (MSB).
330 *
331 * Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
332 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
333 *
334 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
335 */
336 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
337 u16 band_1_count; /* abs.ofs: 196 */
338 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
339 struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
340
341 /*
342 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
343 * 5.0 GHz channels 7, 8, 11, 12, 16
344 * (4915-5080MHz) (none of these is ever supported)
345 */
346 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
347 u16 band_2_count; /* abs.ofs: 226 */
348 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
349 struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
350
351 /*
352 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
353 * (5170-5320MHz)
354 */
355 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
356 u16 band_3_count; /* abs.ofs: 254 */
357 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
358 struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
359
360 /*
361 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
362 * (5500-5700MHz)
363 */
364 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
365 u16 band_4_count; /* abs.ofs: 280 */
366 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
367 struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
368
369 /*
370 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
371 * (5725-5825MHz)
372 */
373 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
374 u16 band_5_count; /* abs.ofs: 304 */
375 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
376 struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
377
378 u8 reserved10[2];
379
380
381 /*
382 * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
383 *
384 * The channel listed is the center of the lower 20 MHz half of the channel.
385 * The overall center frequency is actually 2 channels (10 MHz) above that,
386 * and the upper half of each FAT channel is centered 4 channels (20 MHz) away
387 * from the lower half; e.g. the upper half of FAT channel 1 is channel 5,
388 * and the overall FAT channel width centers on channel 3.
389 *
390 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
391 * control channel to which to tune. RXON also specifies whether the
392 * control channel is the upper or lower half of a FAT channel.
393 *
394 * NOTE: 4965 does not support FAT channels on 2.4 GHz.
395 */
396 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
397 struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
398 u8 reserved11[2];
399
400 /*
401 * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64),
402 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
403 */
404 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
405 struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
406 u8 reserved12[6];
407
408 /*
409 * 4965 driver requires txpower calibration format version 5 or greater.
410 * Driver does not work with txpower calibration version < 5.
411 * This value is simply a 16-bit number, no major/minor versions here.
412 */
413 #define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
414 u16 calib_version; /* abs.ofs: 364 */
415 u8 reserved13[2];
416 u8 reserved14[96]; /* abs.ofs: 368 */
417
418 /*
419 * 4965 Txpower calibration data.
420 */
421 #define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
422 struct iwl4965_eeprom_calib_info calib_info; /* abs.ofs: 464 */
423
424 u8 reserved16[140]; /* fill out to full 1024 byte block */
425
426
427 } __attribute__ ((packed));
428
429 #define IWL_EEPROM_IMAGE_SIZE 1024
430
431 /* End of EEPROM */
432
433 #include "iwl-4965-commands.h"
434
435 #define PCI_LINK_CTRL 0x0F0
436 #define PCI_POWER_SOURCE 0x0C8
437 #define PCI_REG_WUM8 0x0E8
438 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
439
440 /*=== CSR (control and status registers) ===*/
441 #define CSR_BASE (0x000)
442
443 #define CSR_SW_VER (CSR_BASE+0x000)
444 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
445 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
446 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
447 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
448 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
449 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
450 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
451 #define CSR_GP_CNTRL (CSR_BASE+0x024)
452
453 /*
454 * Hardware revision info
455 * Bit fields:
456 * 31-8: Reserved
457 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
458 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
459 * 1-0: "Dash" value, as in A-1, etc.
460 *
461 * NOTE: Revision step affects calculation of CCK txpower for 4965.
462 */
463 #define CSR_HW_REV (CSR_BASE+0x028)
464
465 /* EEPROM reads */
466 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
467 #define CSR_EEPROM_GP (CSR_BASE+0x030)
468 #define CSR_GP_UCODE (CSR_BASE+0x044)
469 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
470 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
471 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
472 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
473 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
474
475 /*
476 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
477 * Bit fields:
478 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
479 */
480 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
481
482 /* HW I/F configuration */
483 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
484 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
485 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
486 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
487 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
488 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
489 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
490
491 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
492 * acknowledged (reset) by host writing "1" to flagged bits. */
493 #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
494 #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
495 #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
496 #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
497 #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
498 #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
499 #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
500 #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
501 #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
502 #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
503 #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
504
505 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
506 CSR_INT_BIT_HW_ERR | \
507 CSR_INT_BIT_FH_TX | \
508 CSR_INT_BIT_SW_ERR | \
509 CSR_INT_BIT_RF_KILL | \
510 CSR_INT_BIT_SW_RX | \
511 CSR_INT_BIT_WAKEUP | \
512 CSR_INT_BIT_ALIVE)
513
514 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
515 #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
516 #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
517 #define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
518 #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
519 #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
520 #define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
521 #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
522 #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
523
524 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
525 CSR_FH_INT_BIT_RX_CHNL2 | \
526 CSR_FH_INT_BIT_RX_CHNL1 | \
527 CSR_FH_INT_BIT_RX_CHNL0)
528
529 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
530 CSR_FH_INT_BIT_TX_CHNL1 | \
531 CSR_FH_INT_BIT_TX_CHNL0)
532
533
534 /* RESET */
535 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
536 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
537 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
538 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
539 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
540
541 /* GP (general purpose) CONTROL */
542 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
543 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
544 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
545 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
546
547 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
548
549 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
550 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
551 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
552
553
554 /* EEPROM REG */
555 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
556 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
557
558 /* EEPROM GP */
559 #define CSR_EEPROM_GP_VALID_MSK (0x00000006)
560 #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
561 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
562
563 /* UCODE DRV GP */
564 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
565 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
566 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
567 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
568
569 /* GPIO */
570 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
571 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
572 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
573
574 /* GI Chicken Bits */
575 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
576 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
577
578 /*=== HBUS (Host-side Bus) ===*/
579 #define HBUS_BASE (0x400)
580
581 /*
582 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
583 * structures, error log, event log, verifying uCode load).
584 * First write to address register, then read from or write to data register
585 * to complete the job. Once the address register is set up, accesses to
586 * data registers auto-increment the address by one dword.
587 * Bit usage for address registers (read or write):
588 * 0-31: memory address within device
589 */
590 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
591 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
592 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
593 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
594
595 /*
596 * Registers for accessing device's internal peripheral registers
597 * (e.g. SCD, BSM, etc.). First write to address register,
598 * then read from or write to data register to complete the job.
599 * Bit usage for address registers (read or write):
600 * 0-15: register address (offset) within device
601 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
602 */
603 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
604 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
605 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
606 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
607
608 /*
609 * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
610 * Indicates index to next TFD that driver will fill (1 past latest filled).
611 * Bit usage:
612 * 0-7: queue write index (0-255)
613 * 11-8: queue selector (0-15)
614 */
615 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
616
617 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
618
619 /*=== FH (data Flow Handler) ===*/
620 #define FH_BASE (0x800)
621
622 #define FH_CBCC_TABLE (FH_BASE+0x140)
623 #define FH_TFDB_TABLE (FH_BASE+0x180)
624 #define FH_RCSR_TABLE (FH_BASE+0x400)
625 #define FH_RSSR_TABLE (FH_BASE+0x4c0)
626 #define FH_TCSR_TABLE (FH_BASE+0x500)
627 #define FH_TSSR_TABLE (FH_BASE+0x680)
628
629 /* TFDB (Transmit Frame Buffer Descriptor) */
630 #define FH_TFDB(_channel, buf) \
631 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
632 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
633 (FH_TFDB_TABLE + 0x50 * _channel)
634 /* CBCC _channel is [0,2] */
635 #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
636 #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
637 #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
638
639 /* RCSR _channel is [0,2] */
640 #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
641 #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
642 #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
643 #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
644 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
645
646 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
647
648 /* RSSR */
649 #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
650 #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
651 /* TCSR */
652 #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
653 #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
654 #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
655 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
656 /* TSSR */
657 #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
658 #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
659 #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
660 /* 18 - reserved */
661
662 /* card static random access memory (SRAM) for processor data and instructs */
663 #define RTC_INST_LOWER_BOUND (0x000000)
664 #define RTC_DATA_LOWER_BOUND (0x800000)
665
666
667 /* DBM */
668
669 #define ALM_FH_SRVC_CHNL (6)
670
671 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
672 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
673
674 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
675
676 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
677
678 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
679
680 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
681
682 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
683
684 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
685
686 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
687 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
688
689 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
690 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
691
692 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
693
694 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
695
696 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
697 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
698
699 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
700
701 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
702
703 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
704 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
705
706 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
707
708 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
709 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
710
711 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
712 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
713
714 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
715
716 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
717 ((1LU << _channel) << 24)
718 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
719 ((1LU << _channel) << 16)
720
721 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
722 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
723 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
724 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
725 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
726
727 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
728
729 #define TFD_QUEUE_MIN 0
730 #define TFD_QUEUE_MAX 6
731 #define TFD_QUEUE_SIZE_MAX (256)
732
733 /* spectrum and channel data structures */
734 #define IWL_NUM_SCAN_RATES (2)
735
736 #define IWL_SCAN_FLAG_24GHZ (1<<0)
737 #define IWL_SCAN_FLAG_52GHZ (1<<1)
738 #define IWL_SCAN_FLAG_ACTIVE (1<<2)
739 #define IWL_SCAN_FLAG_DIRECT (1<<3)
740
741 #define IWL_MAX_CMD_SIZE 1024
742
743 #define IWL_DEFAULT_TX_RETRY 15
744 #define IWL_MAX_TX_RETRY 16
745
746 /*********************************************/
747
748 #define RFD_SIZE 4
749 #define NUM_TFD_CHUNKS 4
750
751 #define RX_QUEUE_SIZE 256
752 #define RX_QUEUE_MASK 255
753 #define RX_QUEUE_SIZE_LOG 8
754
755 /* QoS definitions */
756
757 #define CW_MIN_OFDM 15
758 #define CW_MAX_OFDM 1023
759 #define CW_MIN_CCK 31
760 #define CW_MAX_CCK 1023
761
762 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
763 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
764 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
765 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
766
767 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
768 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
769 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
770 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
771
772 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
773 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
774 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
775 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
776
777 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
778 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
779 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
780 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
781
782 #define QOS_TX0_AIFS 3
783 #define QOS_TX1_AIFS 7
784 #define QOS_TX2_AIFS 2
785 #define QOS_TX3_AIFS 2
786
787 #define QOS_TX0_ACM 0
788 #define QOS_TX1_ACM 0
789 #define QOS_TX2_ACM 0
790 #define QOS_TX3_ACM 0
791
792 #define QOS_TX0_TXOP_LIMIT_CCK 0
793 #define QOS_TX1_TXOP_LIMIT_CCK 0
794 #define QOS_TX2_TXOP_LIMIT_CCK 6016
795 #define QOS_TX3_TXOP_LIMIT_CCK 3264
796
797 #define QOS_TX0_TXOP_LIMIT_OFDM 0
798 #define QOS_TX1_TXOP_LIMIT_OFDM 0
799 #define QOS_TX2_TXOP_LIMIT_OFDM 3008
800 #define QOS_TX3_TXOP_LIMIT_OFDM 1504
801
802 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
803 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
804 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
805 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
806
807 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
808 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
809 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
810 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
811
812 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
813 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
814 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
815 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
816
817 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
818 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
819 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
820 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
821
822 #define DEF_TX0_AIFS (2)
823 #define DEF_TX1_AIFS (2)
824 #define DEF_TX2_AIFS (2)
825 #define DEF_TX3_AIFS (2)
826
827 #define DEF_TX0_ACM 0
828 #define DEF_TX1_ACM 0
829 #define DEF_TX2_ACM 0
830 #define DEF_TX3_ACM 0
831
832 #define DEF_TX0_TXOP_LIMIT_CCK 0
833 #define DEF_TX1_TXOP_LIMIT_CCK 0
834 #define DEF_TX2_TXOP_LIMIT_CCK 0
835 #define DEF_TX3_TXOP_LIMIT_CCK 0
836
837 #define DEF_TX0_TXOP_LIMIT_OFDM 0
838 #define DEF_TX1_TXOP_LIMIT_OFDM 0
839 #define DEF_TX2_TXOP_LIMIT_OFDM 0
840 #define DEF_TX3_TXOP_LIMIT_OFDM 0
841
842 #define QOS_QOS_SETS 3
843 #define QOS_PARAM_SET_ACTIVE 0
844 #define QOS_PARAM_SET_DEF_CCK 1
845 #define QOS_PARAM_SET_DEF_OFDM 2
846
847 #define CTRL_QOS_NO_ACK (0x0020)
848 #define DCT_FLAG_EXT_QOS_ENABLED (0x10)
849
850 #define U32_PAD(n) ((4-(n))&0x3)
851
852 /*
853 * Generic queue structure
854 *
855 * Contains common data for Rx and Tx queues
856 */
857 #define TFD_CTL_COUNT_SET(n) (n<<24)
858 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
859 #define TFD_CTL_PAD_SET(n) (n<<28)
860 #define TFD_CTL_PAD_GET(ctl) (ctl>>28)
861
862 #define TFD_TX_CMD_SLOTS 256
863 #define TFD_CMD_SLOTS 32
864
865 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \
866 sizeof(struct iwl4965_cmd_meta))
867
868 /*
869 * RX related structures and functions
870 */
871 #define RX_FREE_BUFFERS 64
872 #define RX_LOW_WATERMARK 8
873
874
875 #define IWL_RX_BUF_SIZE (4 * 1024)
876 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
877 #define KDR_RTC_INST_UPPER_BOUND (0x018000)
878 #define KDR_RTC_DATA_UPPER_BOUND (0x80A000)
879 #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
880 #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
881
882 #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
883 #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
884
885 static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
886 {
887 return (addr >= RTC_DATA_LOWER_BOUND) &&
888 (addr < KDR_RTC_DATA_UPPER_BOUND);
889 }
890
891 /********************* START TXPOWER *****************************************/
892 enum {
893 HT_IE_EXT_CHANNEL_NONE = 0,
894 HT_IE_EXT_CHANNEL_ABOVE,
895 HT_IE_EXT_CHANNEL_INVALID,
896 HT_IE_EXT_CHANNEL_BELOW,
897 HT_IE_EXT_CHANNEL_MAX
898 };
899
900 enum {
901 CALIB_CH_GROUP_1 = 0,
902 CALIB_CH_GROUP_2 = 1,
903 CALIB_CH_GROUP_3 = 2,
904 CALIB_CH_GROUP_4 = 3,
905 CALIB_CH_GROUP_5 = 4,
906 CALIB_CH_GROUP_MAX
907 };
908
909 /* Temperature calibration offset is 3% 0C in Kelvin */
910 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
911 #define TEMPERATURE_CALIB_A_VAL 259
912
913 #define IWL_TX_POWER_TEMPERATURE_MIN (263)
914 #define IWL_TX_POWER_TEMPERATURE_MAX (410)
915
916 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
917 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
918 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
919
920 #define IWL_TX_POWER_ILLEGAL_TEMPERATURE (300)
921
922 #define IWL_TX_POWER_TEMPERATURE_DIFFERENCE (2)
923
924 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
925
926 #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
927 #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
928
929 /* timeout equivalent to 3 minutes */
930 #define IWL_TX_POWER_TIMELIMIT_NOCALIB 1800000000
931
932 #define IWL_TX_POWER_CCK_COMPENSATION (9)
933
934 #define MIN_TX_GAIN_INDEX (0)
935 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9)
936 #define MAX_TX_GAIN_INDEX_52GHZ (98)
937 #define MIN_TX_GAIN_52GHZ (98)
938 #define MAX_TX_GAIN_INDEX_24GHZ (98)
939 #define MIN_TX_GAIN_24GHZ (98)
940 #define MAX_TX_GAIN (0)
941 #define MAX_TX_GAIN_52GHZ_EXT (-9)
942
943 #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
944 #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
945 #define IWL_TX_POWER_REGULATORY_MIN (0)
946 #define IWL_TX_POWER_REGULATORY_MAX (34)
947 #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
948 #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
949 #define IWL_TX_POWER_SATURATION_MIN (20)
950 #define IWL_TX_POWER_SATURATION_MAX (50)
951
952 /* dv *0.4 = dt; so that 5 degrees temperature diff equals
953 * 12.5 in voltage diff */
954 #define IWL_TX_TEMPERATURE_UPDATE_LIMIT 9
955
956 #define IWL_INVALID_CHANNEL (0xffffffff)
957 #define IWL_TX_POWER_REGITRY_BIT (2)
958
959 #define MIN_IWL_TX_POWER_CALIB_DUR (100)
960 #define IWL_CCK_FROM_OFDM_POWER_DIFF (-5)
961 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (9)
962
963 /* Number of entries in the gain table */
964 #define POWER_GAIN_NUM_ENTRIES 78
965 #define TX_POW_MAX_SESSION_NUM 5
966 /* timeout equivalent to 3 minutes */
967 #define TX_IWL_TIMELIMIT_NOCALIB 1800000000
968
969 /* Kedron TX_CALIB_STATES */
970 #define IWL_TX_CALIB_STATE_SEND_TX 0x00000001
971 #define IWL_TX_CALIB_WAIT_TX_RESPONSE 0x00000002
972 #define IWL_TX_CALIB_ENABLED 0x00000004
973 #define IWL_TX_CALIB_XVT_ON 0x00000008
974 #define IWL_TX_CALIB_TEMPERATURE_CORRECT 0x00000010
975 #define IWL_TX_CALIB_WORKING_WITH_XVT 0x00000020
976 #define IWL_TX_CALIB_XVT_PERIODICAL 0x00000040
977
978 #define NUM_IWL_TX_CALIB_SETTINS 5 /* Number of tx correction groups */
979
980 #define IWL_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */
981 #define IWL_MAX_POWER_IN_VP_TABLE 40 /* 20dBm - multiplied by 2 (because
982 * entries are for each 0.5dBm) */
983 #define IWL_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */
984 #define IWL_NUM_POINTS_IN_VPTABLE \
985 (1 + IWL_MAX_POWER_IN_VP_TABLE - IWL_MIN_POWER_IN_VP_TABLE)
986
987 #define MIN_TX_GAIN_INDEX (0)
988 #define MAX_TX_GAIN_INDEX_52GHZ (98)
989 #define MIN_TX_GAIN_52GHZ (98)
990 #define MAX_TX_GAIN_INDEX_24GHZ (98)
991 #define MIN_TX_GAIN_24GHZ (98)
992 #define MAX_TX_GAIN (0)
993
994 /* First and last channels of all groups */
995 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
996 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
997 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
998 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
999 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
1000 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
1001 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
1002 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
1003 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
1004 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
1005
1006
1007 union iwl4965_tx_power_dual_stream {
1008 struct {
1009 u8 radio_tx_gain[2];
1010 u8 dsp_predis_atten[2];
1011 } s;
1012 u32 dw;
1013 };
1014
1015 /********************* END TXPOWER *****************************************/
1016
1017 /* HT flags */
1018 #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
1019 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK __constant_cpu_to_le32(0x1<<22)
1020
1021 #define RXON_FLG_HT_OPERATING_MODE_POS (23)
1022
1023 #define RXON_FLG_HT_PROT_MSK __constant_cpu_to_le32(0x1<<23)
1024 #define RXON_FLG_FAT_PROT_MSK __constant_cpu_to_le32(0x2<<23)
1025
1026 #define RXON_FLG_CHANNEL_MODE_POS (25)
1027 #define RXON_FLG_CHANNEL_MODE_MSK __constant_cpu_to_le32(0x3<<25)
1028 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK __constant_cpu_to_le32(0x1<<25)
1029 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK __constant_cpu_to_le32(0x2<<25)
1030
1031 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK __constant_cpu_to_le16(0x1<<0)
1032 #define RXON_RX_CHAIN_VALID_MSK __constant_cpu_to_le16(0x7<<1)
1033 #define RXON_RX_CHAIN_VALID_POS (1)
1034 #define RXON_RX_CHAIN_FORCE_SEL_MSK __constant_cpu_to_le16(0x7<<4)
1035 #define RXON_RX_CHAIN_FORCE_SEL_POS (4)
1036 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK __constant_cpu_to_le16(0x7<<7)
1037 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
1038 #define RXON_RX_CHAIN_CNT_MSK __constant_cpu_to_le16(0x3<<10)
1039 #define RXON_RX_CHAIN_CNT_POS (10)
1040 #define RXON_RX_CHAIN_MIMO_CNT_MSK __constant_cpu_to_le16(0x3<<12)
1041 #define RXON_RX_CHAIN_MIMO_CNT_POS (12)
1042 #define RXON_RX_CHAIN_MIMO_FORCE_MSK __constant_cpu_to_le16(0x1<<14)
1043 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
1044
1045
1046 #define MCS_DUP_6M_PLCP 0x20
1047
1048 /* OFDM HT rate masks */
1049 /* ***************************************** */
1050 #define R_MCS_6M_MSK 0x1
1051 #define R_MCS_12M_MSK 0x2
1052 #define R_MCS_18M_MSK 0x4
1053 #define R_MCS_24M_MSK 0x8
1054 #define R_MCS_36M_MSK 0x10
1055 #define R_MCS_48M_MSK 0x20
1056 #define R_MCS_54M_MSK 0x40
1057 #define R_MCS_60M_MSK 0x80
1058 #define R_MCS_12M_DUAL_MSK 0x100
1059 #define R_MCS_24M_DUAL_MSK 0x200
1060 #define R_MCS_36M_DUAL_MSK 0x400
1061 #define R_MCS_48M_DUAL_MSK 0x800
1062
1063 /* Flow Handler Definitions */
1064
1065 /**********************/
1066 /* Addresses */
1067 /**********************/
1068
1069 #define FH_MEM_LOWER_BOUND (0x1000)
1070 #define FH_MEM_UPPER_BOUND (0x1EF0)
1071
1072 #define IWL_FH_REGS_LOWER_BOUND (0x1000)
1073 #define IWL_FH_REGS_UPPER_BOUND (0x2000)
1074
1075 #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
1076
1077 /* CBBC Area - Circular buffers base address cache pointers table */
1078 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
1079 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
1080 /* queues 0 - 15 */
1081 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
1082
1083 /* RSCSR Area */
1084 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
1085 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
1086 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
1087
1088 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
1089 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
1090 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
1091
1092 /* RCSR Area - Registers address map */
1093 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
1094 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
1095 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
1096
1097 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
1098
1099 /* RSSR Area - Rx shared ctrl & status registers */
1100 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
1101 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1102 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
1103 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
1104 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
1105
1106 /* TCSR */
1107 #define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00)
1108 #define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60)
1109
1110 #define IWL_FH_TCSR_CHNL_NUM (7)
1111 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1112 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
1113
1114 /* TSSR Area - Tx shared status registers */
1115 /* TSSR */
1116 #define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
1117 #define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
1118
1119 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG (IWL_FH_TSSR_LOWER_BOUND + 0x008)
1120 #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
1121
1122 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
1123 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
1124
1125 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000)
1126 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
1127 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800)
1128 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00)
1129
1130 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
1131 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
1132
1133 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
1134 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
1135
1136 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1137 ((1 << (_chnl)) << 24)
1138 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1139 ((1 << (_chnl)) << 16)
1140
1141 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1142 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1143 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1144
1145 /* TCSR: tx_config register values */
1146 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1147 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
1148 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002)
1149
1150 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1151 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1152
1153 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1154 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1155 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1156
1157 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1158 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1159 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1160
1161 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1162 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1163 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1164
1165 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1166 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1167 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1168
1169 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
1170
1171 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1172 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1173
1174 /* RCSR: channel 0 rx_config register defines */
1175 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
1176 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
1177 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
1178 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
1179 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
1180 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
1181
1182 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
1183 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16)
1184
1185 /* RCSR: rx_config register values */
1186 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1187 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1188 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1189
1190 #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1191
1192 /* RCSR channel 0 config register values */
1193 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1194 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1195
1196 /* RSCSR: defs used in normal mode */
1197 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */
1198
1199 #define SCD_WIN_SIZE 64
1200 #define SCD_FRAME_LIMIT 64
1201
1202 /* SRAM structures */
1203 #define SCD_CONTEXT_DATA_OFFSET 0x380
1204 #define SCD_TX_STTS_BITMAP_OFFSET 0x400
1205 #define SCD_TRANSLATE_TBL_OFFSET 0x500
1206 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
1207 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
1208 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
1209
1210 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1211 ((1<<(hi))|((1<<(hi))-(1<<(lo))))
1212
1213
1214 #define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0)
1215 #define SCD_MODE_REG_BIT_SBYP_MODE (1<<1)
1216
1217 #define SCD_TXFIFO_POS_TID (0)
1218 #define SCD_TXFIFO_POS_RA (4)
1219 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
1220 #define SCD_QUEUE_STTS_REG_POS_TXF (1)
1221 #define SCD_QUEUE_STTS_REG_POS_WSL (5)
1222 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
1223 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
1224 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
1225
1226 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1227
1228 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
1229 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
1230 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1231 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1232 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1233 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1234 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1235 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1236
1237 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
1238 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
1239 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
1240 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
1241
1242 static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
1243 {
1244 return le32_to_cpu(rate_n_flags) & 0xFF;
1245 }
1246 static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags)
1247 {
1248 return le32_to_cpu(rate_n_flags) & 0xFFFF;
1249 }
1250 static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1251 {
1252 return cpu_to_le32(flags|(u16)rate);
1253 }
1254
1255 struct iwl4965_tfd_frame_data {
1256 __le32 tb1_addr;
1257
1258 __le32 val1;
1259 /* __le32 ptb1_32_35:4; */
1260 #define IWL_tb1_addr_hi_POS 0
1261 #define IWL_tb1_addr_hi_LEN 4
1262 #define IWL_tb1_addr_hi_SYM val1
1263 /* __le32 tb_len1:12; */
1264 #define IWL_tb1_len_POS 4
1265 #define IWL_tb1_len_LEN 12
1266 #define IWL_tb1_len_SYM val1
1267 /* __le32 ptb2_0_15:16; */
1268 #define IWL_tb2_addr_lo16_POS 16
1269 #define IWL_tb2_addr_lo16_LEN 16
1270 #define IWL_tb2_addr_lo16_SYM val1
1271
1272 __le32 val2;
1273 /* __le32 ptb2_16_35:20; */
1274 #define IWL_tb2_addr_hi20_POS 0
1275 #define IWL_tb2_addr_hi20_LEN 20
1276 #define IWL_tb2_addr_hi20_SYM val2
1277 /* __le32 tb_len2:12; */
1278 #define IWL_tb2_len_POS 20
1279 #define IWL_tb2_len_LEN 12
1280 #define IWL_tb2_len_SYM val2
1281 } __attribute__ ((packed));
1282
1283 struct iwl4965_tfd_frame {
1284 __le32 val0;
1285 /* __le32 rsvd1:24; */
1286 /* __le32 num_tbs:5; */
1287 #define IWL_num_tbs_POS 24
1288 #define IWL_num_tbs_LEN 5
1289 #define IWL_num_tbs_SYM val0
1290 /* __le32 rsvd2:1; */
1291 /* __le32 padding:2; */
1292 struct iwl4965_tfd_frame_data pa[10];
1293 __le32 reserved;
1294 } __attribute__ ((packed));
1295
1296 #define IWL4965_MAX_WIN_SIZE 64
1297 #define IWL4965_QUEUE_SIZE 256
1298 #define IWL4965_NUM_FIFOS 7
1299 #define IWL_MAX_NUM_QUEUES 16
1300
1301 struct iwl4965_queue_byte_cnt_entry {
1302 __le16 val;
1303 /* __le16 byte_cnt:12; */
1304 #define IWL_byte_cnt_POS 0
1305 #define IWL_byte_cnt_LEN 12
1306 #define IWL_byte_cnt_SYM val
1307 /* __le16 rsvd:4; */
1308 } __attribute__ ((packed));
1309
1310 struct iwl4965_sched_queue_byte_cnt_tbl {
1311 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
1312 IWL4965_MAX_WIN_SIZE];
1313 u8 dont_care[1024 -
1314 (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) *
1315 sizeof(__le16)];
1316 } __attribute__ ((packed));
1317
1318 /* Base physical address of iwl4965_shared is provided to KDR_SCD_DRAM_BASE_ADDR
1319 * and &iwl4965_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
1320 struct iwl4965_shared {
1321 struct iwl4965_sched_queue_byte_cnt_tbl
1322 queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
1323 __le32 val0;
1324
1325 /* __le32 rb_closed_stts_rb_num:12; */
1326 #define IWL_rb_closed_stts_rb_num_POS 0
1327 #define IWL_rb_closed_stts_rb_num_LEN 12
1328 #define IWL_rb_closed_stts_rb_num_SYM val0
1329 /* __le32 rsrv1:4; */
1330 /* __le32 rb_closed_stts_rx_frame_num:12; */
1331 #define IWL_rb_closed_stts_rx_frame_num_POS 16
1332 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
1333 #define IWL_rb_closed_stts_rx_frame_num_SYM val0
1334 /* __le32 rsrv2:4; */
1335
1336 __le32 val1;
1337 /* __le32 frame_finished_stts_rb_num:12; */
1338 #define IWL_frame_finished_stts_rb_num_POS 0
1339 #define IWL_frame_finished_stts_rb_num_LEN 12
1340 #define IWL_frame_finished_stts_rb_num_SYM val1
1341 /* __le32 rsrv3:4; */
1342 /* __le32 frame_finished_stts_rx_frame_num:12; */
1343 #define IWL_frame_finished_stts_rx_frame_num_POS 16
1344 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
1345 #define IWL_frame_finished_stts_rx_frame_num_SYM val1
1346 /* __le32 rsrv4:4; */
1347
1348 __le32 padding1; /* so that allocation will be aligned to 16B */
1349 __le32 padding2;
1350 } __attribute__ ((packed));
1351
1352 #endif /* __iwl4965_4965_hw_h__ */
Linux kernel - Deliverables
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