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iwlwifi: expanding HW parameters control
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-4965.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47
48 /* module parameters */
49 static struct iwl_mod_params iwl4965_mod_params = {
50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54 };
55
56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
57
58 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
61 IWL_RATE_MIMO_##s##M_PLCP, \
62 IWL_RATE_##r##M_IEEE, \
63 IWL_RATE_##ip##M_INDEX, \
64 IWL_RATE_##in##M_INDEX, \
65 IWL_RATE_##rp##M_INDEX, \
66 IWL_RATE_##rn##M_INDEX, \
67 IWL_RATE_##pp##M_INDEX, \
68 IWL_RATE_##np##M_INDEX }
69
70 /*
71 * Parameter order:
72 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
73 *
74 * If there isn't a valid next or previous rate then INV is used which
75 * maps to IWL_RATE_INVALID
76 *
77 */
78 const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
79 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
80 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
81 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
82 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
83 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
84 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
85 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
86 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
87 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
88 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
89 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
90 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
91 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
92 };
93
94 #ifdef CONFIG_IWL4965_HT
95
96 static const u16 default_tid_to_tx_fifo[] = {
97 IWL_TX_FIFO_AC1,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC0,
100 IWL_TX_FIFO_AC1,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC2,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_AC3,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_AC3
114 };
115
116 #endif /*CONFIG_IWL4965_HT */
117
118 /* check contents of special bootstrap uCode SRAM */
119 static int iwl4965_verify_bsm(struct iwl_priv *priv)
120 {
121 __le32 *image = priv->ucode_boot.v_addr;
122 u32 len = priv->ucode_boot.len;
123 u32 reg;
124 u32 val;
125
126 IWL_DEBUG_INFO("Begin verify bsm\n");
127
128 /* verify BSM SRAM contents */
129 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
130 for (reg = BSM_SRAM_LOWER_BOUND;
131 reg < BSM_SRAM_LOWER_BOUND + len;
132 reg += sizeof(u32), image++) {
133 val = iwl_read_prph(priv, reg);
134 if (val != le32_to_cpu(*image)) {
135 IWL_ERROR("BSM uCode verification failed at "
136 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
137 BSM_SRAM_LOWER_BOUND,
138 reg - BSM_SRAM_LOWER_BOUND, len,
139 val, le32_to_cpu(*image));
140 return -EIO;
141 }
142 }
143
144 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
145
146 return 0;
147 }
148
149 /**
150 * iwl4965_load_bsm - Load bootstrap instructions
151 *
152 * BSM operation:
153 *
154 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
155 * in special SRAM that does not power down during RFKILL. When powering back
156 * up after power-saving sleeps (or during initial uCode load), the BSM loads
157 * the bootstrap program into the on-board processor, and starts it.
158 *
159 * The bootstrap program loads (via DMA) instructions and data for a new
160 * program from host DRAM locations indicated by the host driver in the
161 * BSM_DRAM_* registers. Once the new program is loaded, it starts
162 * automatically.
163 *
164 * When initializing the NIC, the host driver points the BSM to the
165 * "initialize" uCode image. This uCode sets up some internal data, then
166 * notifies host via "initialize alive" that it is complete.
167 *
168 * The host then replaces the BSM_DRAM_* pointer values to point to the
169 * normal runtime uCode instructions and a backup uCode data cache buffer
170 * (filled initially with starting data values for the on-board processor),
171 * then triggers the "initialize" uCode to load and launch the runtime uCode,
172 * which begins normal operation.
173 *
174 * When doing a power-save shutdown, runtime uCode saves data SRAM into
175 * the backup data cache in DRAM before SRAM is powered down.
176 *
177 * When powering back up, the BSM loads the bootstrap program. This reloads
178 * the runtime uCode instructions and the backup data cache into SRAM,
179 * and re-launches the runtime uCode from where it left off.
180 */
181 static int iwl4965_load_bsm(struct iwl_priv *priv)
182 {
183 __le32 *image = priv->ucode_boot.v_addr;
184 u32 len = priv->ucode_boot.len;
185 dma_addr_t pinst;
186 dma_addr_t pdata;
187 u32 inst_len;
188 u32 data_len;
189 int i;
190 u32 done;
191 u32 reg_offset;
192 int ret;
193
194 IWL_DEBUG_INFO("Begin load bsm\n");
195
196 /* make sure bootstrap program is no larger than BSM's SRAM size */
197 if (len > IWL_MAX_BSM_SIZE)
198 return -EINVAL;
199
200 /* Tell bootstrap uCode where to find the "Initialize" uCode
201 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
202 * NOTE: iwl4965_initialize_alive_start() will replace these values,
203 * after the "initialize" uCode has run, to point to
204 * runtime/protocol instructions and backup data cache. */
205 pinst = priv->ucode_init.p_addr >> 4;
206 pdata = priv->ucode_init_data.p_addr >> 4;
207 inst_len = priv->ucode_init.len;
208 data_len = priv->ucode_init_data.len;
209
210 ret = iwl_grab_nic_access(priv);
211 if (ret)
212 return ret;
213
214 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
215 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
216 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
217 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
218
219 /* Fill BSM memory with bootstrap instructions */
220 for (reg_offset = BSM_SRAM_LOWER_BOUND;
221 reg_offset < BSM_SRAM_LOWER_BOUND + len;
222 reg_offset += sizeof(u32), image++)
223 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
224
225 ret = iwl4965_verify_bsm(priv);
226 if (ret) {
227 iwl_release_nic_access(priv);
228 return ret;
229 }
230
231 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
232 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
233 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
234 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
235
236 /* Load bootstrap code into instruction SRAM now,
237 * to prepare to load "initialize" uCode */
238 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
239
240 /* Wait for load of bootstrap uCode to finish */
241 for (i = 0; i < 100; i++) {
242 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
243 if (!(done & BSM_WR_CTRL_REG_BIT_START))
244 break;
245 udelay(10);
246 }
247 if (i < 100)
248 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
249 else {
250 IWL_ERROR("BSM write did not complete!\n");
251 return -EIO;
252 }
253
254 /* Enable future boot loads whenever power management unit triggers it
255 * (e.g. when powering back up after power-save shutdown) */
256 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
257
258 iwl_release_nic_access(priv);
259
260 return 0;
261 }
262
263 static int iwl4965_init_drv(struct iwl_priv *priv)
264 {
265 int ret;
266 int i;
267
268 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
269 priv->retry_rate = 1;
270 priv->ibss_beacon = NULL;
271
272 spin_lock_init(&priv->lock);
273 spin_lock_init(&priv->power_data.lock);
274 spin_lock_init(&priv->sta_lock);
275 spin_lock_init(&priv->hcmd_lock);
276 spin_lock_init(&priv->lq_mngr.lock);
277
278 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
279 sizeof(struct iwl4965_shared),
280 &priv->shared_phys);
281
282 if (!priv->shared_virt) {
283 ret = -ENOMEM;
284 goto err;
285 }
286
287 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
288
289
290 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
291 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
292
293 INIT_LIST_HEAD(&priv->free_frames);
294
295 mutex_init(&priv->mutex);
296
297 /* Clear the driver's (not device's) station table */
298 iwlcore_clear_stations_table(priv);
299
300 priv->data_retry_limit = -1;
301 priv->ieee_channels = NULL;
302 priv->ieee_rates = NULL;
303 priv->band = IEEE80211_BAND_2GHZ;
304
305 priv->iw_mode = IEEE80211_IF_TYPE_STA;
306
307 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
308 priv->valid_antenna = 0x7; /* assume all 3 connected */
309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350 err_free_geos:
351 iwl4965_free_geos(priv);
352 err_free_channel_map:
353 iwl_free_channel_map(priv);
354 err:
355 return ret;
356 }
357
358 static int is_fat_channel(__le32 rxon_flags)
359 {
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362 }
363
364 static u8 is_single_stream(struct iwl_priv *priv)
365 {
366 #ifdef CONFIG_IWL4965_HT
367 if (!priv->current_ht_config.is_ht ||
368 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
369 (priv->ps_mode == IWL_MIMO_PS_STATIC))
370 return 1;
371 #else
372 return 1;
373 #endif /*CONFIG_IWL4965_HT */
374 return 0;
375 }
376
377 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
378 {
379 int idx = 0;
380
381 /* 4965 HT rate format */
382 if (rate_n_flags & RATE_MCS_HT_MSK) {
383 idx = (rate_n_flags & 0xff);
384
385 if (idx >= IWL_RATE_MIMO_6M_PLCP)
386 idx = idx - IWL_RATE_MIMO_6M_PLCP;
387
388 idx += IWL_FIRST_OFDM_RATE;
389 /* skip 9M not supported in ht*/
390 if (idx >= IWL_RATE_9M_INDEX)
391 idx += 1;
392 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
393 return idx;
394
395 /* 4965 legacy rate format, search for match in table */
396 } else {
397 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
398 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
399 return idx;
400 }
401
402 return -1;
403 }
404
405 /**
406 * translate ucode response to mac80211 tx status control values
407 */
408 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
409 struct ieee80211_tx_control *control)
410 {
411 int rate_index;
412
413 control->antenna_sel_tx =
414 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS);
415 if (rate_n_flags & RATE_MCS_HT_MSK)
416 control->flags |= IEEE80211_TXCTL_OFDM_HT;
417 if (rate_n_flags & RATE_MCS_GF_MSK)
418 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
419 if (rate_n_flags & RATE_MCS_FAT_MSK)
420 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
421 if (rate_n_flags & RATE_MCS_DUP_MSK)
422 control->flags |= IEEE80211_TXCTL_DUP_DATA;
423 if (rate_n_flags & RATE_MCS_SGI_MSK)
424 control->flags |= IEEE80211_TXCTL_SHORT_GI;
425 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
426 * IEEE80211_BAND_2GHZ band as it contains all the rates */
427 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
428 if (rate_index == -1)
429 control->tx_rate = NULL;
430 else
431 control->tx_rate =
432 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
433 }
434
435 /*
436 * Determine how many receiver/antenna chains to use.
437 * More provides better reception via diversity. Fewer saves power.
438 * MIMO (dual stream) requires at least 2, but works better with 3.
439 * This does not determine *which* chains to use, just how many.
440 */
441 static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
442 u8 *idle_state, u8 *rx_state)
443 {
444 u8 is_single = is_single_stream(priv);
445 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
446
447 /* # of Rx chains to use when expecting MIMO. */
448 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
449 *rx_state = 2;
450 else
451 *rx_state = 3;
452
453 /* # Rx chains when idling and maybe trying to save power */
454 switch (priv->ps_mode) {
455 case IWL_MIMO_PS_STATIC:
456 case IWL_MIMO_PS_DYNAMIC:
457 *idle_state = (is_cam) ? 2 : 1;
458 break;
459 case IWL_MIMO_PS_NONE:
460 *idle_state = (is_cam) ? *rx_state : 1;
461 break;
462 default:
463 *idle_state = 1;
464 break;
465 }
466
467 return 0;
468 }
469
470 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
471 {
472 int rc;
473 unsigned long flags;
474
475 spin_lock_irqsave(&priv->lock, flags);
476 rc = iwl_grab_nic_access(priv);
477 if (rc) {
478 spin_unlock_irqrestore(&priv->lock, flags);
479 return rc;
480 }
481
482 /* stop Rx DMA */
483 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
484 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
485 (1 << 24), 1000);
486 if (rc < 0)
487 IWL_ERROR("Can't stop Rx DMA.\n");
488
489 iwl_release_nic_access(priv);
490 spin_unlock_irqrestore(&priv->lock, flags);
491
492 return 0;
493 }
494
495 int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
496 {
497 int ret;
498 unsigned long flags;
499
500 spin_lock_irqsave(&priv->lock, flags);
501 ret = iwl_grab_nic_access(priv);
502 if (ret) {
503 spin_unlock_irqrestore(&priv->lock, flags);
504 return ret;
505 }
506
507 if (src == IWL_PWR_SRC_VAUX) {
508 u32 val;
509 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
510 &val);
511
512 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
513 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
514 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
515 ~APMG_PS_CTRL_MSK_PWR_SRC);
516 }
517 } else {
518 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
519 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
520 ~APMG_PS_CTRL_MSK_PWR_SRC);
521 }
522
523 iwl_release_nic_access(priv);
524 spin_unlock_irqrestore(&priv->lock, flags);
525
526 return ret;
527 }
528
529 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
530 {
531 int ret;
532 unsigned long flags;
533 unsigned int rb_size;
534
535 spin_lock_irqsave(&priv->lock, flags);
536 ret = iwl_grab_nic_access(priv);
537 if (ret) {
538 spin_unlock_irqrestore(&priv->lock, flags);
539 return ret;
540 }
541
542 if (priv->cfg->mod_params->amsdu_size_8K)
543 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
544 else
545 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
546
547 /* Stop Rx DMA */
548 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
549
550 /* Reset driver's Rx queue write index */
551 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
552
553 /* Tell device where to find RBD circular buffer in DRAM */
554 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
555 rxq->dma_addr >> 8);
556
557 /* Tell device where in DRAM to update its Rx status */
558 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
559 (priv->shared_phys +
560 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
561
562 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
563 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
564 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
565 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
566 rb_size |
567 /* 0x10 << 4 | */
568 (RX_QUEUE_SIZE_LOG <<
569 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
570
571 /*
572 * iwl_write32(priv,CSR_INT_COAL_REG,0);
573 */
574
575 iwl_release_nic_access(priv);
576 spin_unlock_irqrestore(&priv->lock, flags);
577
578 return 0;
579 }
580
581 /* Tell 4965 where to find the "keep warm" buffer */
582 static int iwl4965_kw_init(struct iwl_priv *priv)
583 {
584 unsigned long flags;
585 int rc;
586
587 spin_lock_irqsave(&priv->lock, flags);
588 rc = iwl_grab_nic_access(priv);
589 if (rc)
590 goto out;
591
592 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
593 priv->kw.dma_addr >> 4);
594 iwl_release_nic_access(priv);
595 out:
596 spin_unlock_irqrestore(&priv->lock, flags);
597 return rc;
598 }
599
600 static int iwl4965_kw_alloc(struct iwl_priv *priv)
601 {
602 struct pci_dev *dev = priv->pci_dev;
603 struct iwl4965_kw *kw = &priv->kw;
604
605 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
606 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
607 if (!kw->v_addr)
608 return -ENOMEM;
609
610 return 0;
611 }
612
613 /**
614 * iwl4965_kw_free - Free the "keep warm" buffer
615 */
616 static void iwl4965_kw_free(struct iwl_priv *priv)
617 {
618 struct pci_dev *dev = priv->pci_dev;
619 struct iwl4965_kw *kw = &priv->kw;
620
621 if (kw->v_addr) {
622 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
623 memset(kw, 0, sizeof(*kw));
624 }
625 }
626
627 /**
628 * iwl4965_txq_ctx_reset - Reset TX queue context
629 * Destroys all DMA structures and initialise them again
630 *
631 * @param priv
632 * @return error code
633 */
634 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
635 {
636 int rc = 0;
637 int txq_id, slots_num;
638 unsigned long flags;
639
640 iwl4965_kw_free(priv);
641
642 /* Free all tx/cmd queues and keep-warm buffer */
643 iwl4965_hw_txq_ctx_free(priv);
644
645 /* Alloc keep-warm buffer */
646 rc = iwl4965_kw_alloc(priv);
647 if (rc) {
648 IWL_ERROR("Keep Warm allocation failed");
649 goto error_kw;
650 }
651
652 spin_lock_irqsave(&priv->lock, flags);
653
654 rc = iwl_grab_nic_access(priv);
655 if (unlikely(rc)) {
656 IWL_ERROR("TX reset failed");
657 spin_unlock_irqrestore(&priv->lock, flags);
658 goto error_reset;
659 }
660
661 /* Turn off all Tx DMA channels */
662 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
663 iwl_release_nic_access(priv);
664 spin_unlock_irqrestore(&priv->lock, flags);
665
666 /* Tell 4965 where to find the keep-warm buffer */
667 rc = iwl4965_kw_init(priv);
668 if (rc) {
669 IWL_ERROR("kw_init failed\n");
670 goto error_reset;
671 }
672
673 /* Alloc and init all (default 16) Tx queues,
674 * including the command queue (#4) */
675 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
676 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
677 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
678 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
679 txq_id);
680 if (rc) {
681 IWL_ERROR("Tx %d queue init failed\n", txq_id);
682 goto error;
683 }
684 }
685
686 return rc;
687
688 error:
689 iwl4965_hw_txq_ctx_free(priv);
690 error_reset:
691 iwl4965_kw_free(priv);
692 error_kw:
693 return rc;
694 }
695
696 int iwl4965_hw_nic_init(struct iwl_priv *priv)
697 {
698 int rc;
699 unsigned long flags;
700 struct iwl4965_rx_queue *rxq = &priv->rxq;
701 u8 rev_id;
702 u8 val_link;
703 u16 sku_cap;
704 u32 val;
705
706 /* nic_init */
707 spin_lock_irqsave(&priv->lock, flags);
708
709 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
710 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
711
712 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
713 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
714 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
715 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
716 if (rc < 0) {
717 spin_unlock_irqrestore(&priv->lock, flags);
718 IWL_DEBUG_INFO("Failed to init the card\n");
719 return rc;
720 }
721
722 rc = iwl_grab_nic_access(priv);
723 if (rc) {
724 spin_unlock_irqrestore(&priv->lock, flags);
725 return rc;
726 }
727
728 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
729
730 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
731 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
732 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
733
734 udelay(20);
735
736 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
737 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
738
739 iwl_release_nic_access(priv);
740 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
741 spin_unlock_irqrestore(&priv->lock, flags);
742
743 /* Determine HW type */
744 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
745 if (rc)
746 return rc;
747
748 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
749
750 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
751
752 spin_lock_irqsave(&priv->lock, flags);
753
754 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
755 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
756 /* Enable No Snoop field */
757 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
758 val & ~(1 << 11));
759 }
760
761 spin_unlock_irqrestore(&priv->lock, flags);
762
763 if (iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET) <
764 EEPROM_4965_TX_POWER_VERSION) {
765 IWL_ERROR("Older EEPROM detected! Aborting.\n");
766 return -EINVAL;
767 }
768
769 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
770
771 /* disable L1 entry -- workaround for pre-B1 */
772 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
773
774 spin_lock_irqsave(&priv->lock, flags);
775
776 /* set CSR_HW_CONFIG_REG for uCode use */
777
778 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
779 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
780 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
781 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
782
783 rc = iwl_grab_nic_access(priv);
784 if (rc < 0) {
785 spin_unlock_irqrestore(&priv->lock, flags);
786 IWL_DEBUG_INFO("Failed to init the card\n");
787 return rc;
788 }
789
790 iwl_read_prph(priv, APMG_PS_CTRL_REG);
791 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
792 udelay(5);
793 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
794
795 iwl_release_nic_access(priv);
796 spin_unlock_irqrestore(&priv->lock, flags);
797
798 iwl4965_hw_card_show_info(priv);
799
800 /* end nic_init */
801
802 /* Allocate the RX queue, or reset if it is already allocated */
803 if (!rxq->bd) {
804 rc = iwl4965_rx_queue_alloc(priv);
805 if (rc) {
806 IWL_ERROR("Unable to initialize Rx queue\n");
807 return -ENOMEM;
808 }
809 } else
810 iwl4965_rx_queue_reset(priv, rxq);
811
812 iwl4965_rx_replenish(priv);
813
814 iwl4965_rx_init(priv, rxq);
815
816 spin_lock_irqsave(&priv->lock, flags);
817
818 rxq->need_update = 1;
819 iwl4965_rx_queue_update_write_ptr(priv, rxq);
820
821 /* init the txpower calibration pointer */
822 priv->calib_info = (struct iwl_eeprom_calib_info *)
823 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
824
825 spin_unlock_irqrestore(&priv->lock, flags);
826
827 /* Allocate and init all Tx and Command queues */
828 rc = iwl4965_txq_ctx_reset(priv);
829 if (rc)
830 return rc;
831
832 sku_cap = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
833 if (sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
834 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
835
836 if (sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
837 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
838
839 set_bit(STATUS_INIT, &priv->status);
840
841 return 0;
842 }
843
844 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
845 {
846 int rc = 0;
847 u32 reg_val;
848 unsigned long flags;
849
850 spin_lock_irqsave(&priv->lock, flags);
851
852 /* set stop master bit */
853 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
854
855 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
856
857 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
858 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
859 IWL_DEBUG_INFO("Card in power save, master is already "
860 "stopped\n");
861 else {
862 rc = iwl_poll_bit(priv, CSR_RESET,
863 CSR_RESET_REG_FLAG_MASTER_DISABLED,
864 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
865 if (rc < 0) {
866 spin_unlock_irqrestore(&priv->lock, flags);
867 return rc;
868 }
869 }
870
871 spin_unlock_irqrestore(&priv->lock, flags);
872 IWL_DEBUG_INFO("stop master\n");
873
874 return rc;
875 }
876
877 /**
878 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
879 */
880 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
881 {
882
883 int txq_id;
884 unsigned long flags;
885
886 /* Stop each Tx DMA channel, and wait for it to be idle */
887 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
888 spin_lock_irqsave(&priv->lock, flags);
889 if (iwl_grab_nic_access(priv)) {
890 spin_unlock_irqrestore(&priv->lock, flags);
891 continue;
892 }
893
894 iwl_write_direct32(priv,
895 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
896 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
897 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
898 (txq_id), 200);
899 iwl_release_nic_access(priv);
900 spin_unlock_irqrestore(&priv->lock, flags);
901 }
902
903 /* Deallocate memory for all Tx queues */
904 iwl4965_hw_txq_ctx_free(priv);
905 }
906
907 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
908 {
909 int rc = 0;
910 unsigned long flags;
911
912 iwl4965_hw_nic_stop_master(priv);
913
914 spin_lock_irqsave(&priv->lock, flags);
915
916 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
917
918 udelay(10);
919
920 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
921 rc = iwl_poll_bit(priv, CSR_RESET,
922 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
923 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
924
925 udelay(10);
926
927 rc = iwl_grab_nic_access(priv);
928 if (!rc) {
929 iwl_write_prph(priv, APMG_CLK_EN_REG,
930 APMG_CLK_VAL_DMA_CLK_RQT |
931 APMG_CLK_VAL_BSM_CLK_RQT);
932
933 udelay(10);
934
935 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
936 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
937
938 iwl_release_nic_access(priv);
939 }
940
941 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
942 wake_up_interruptible(&priv->wait_command_queue);
943
944 spin_unlock_irqrestore(&priv->lock, flags);
945
946 return rc;
947
948 }
949
950 #define REG_RECALIB_PERIOD (60)
951
952 /**
953 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
954 *
955 * This callback is provided in order to send a statistics request.
956 *
957 * This timer function is continually reset to execute within
958 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
959 * was received. We need to ensure we receive the statistics in order
960 * to update the temperature used for calibrating the TXPOWER.
961 */
962 static void iwl4965_bg_statistics_periodic(unsigned long data)
963 {
964 struct iwl_priv *priv = (struct iwl_priv *)data;
965
966 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
967 return;
968
969 iwl_send_statistics_request(priv, CMD_ASYNC);
970 }
971
972 #define CT_LIMIT_CONST 259
973 #define TM_CT_KILL_THRESHOLD 110
974
975 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
976 {
977 struct iwl4965_ct_kill_config cmd;
978 u32 R1, R2, R3;
979 u32 temp_th;
980 u32 crit_temperature;
981 unsigned long flags;
982 int ret = 0;
983
984 spin_lock_irqsave(&priv->lock, flags);
985 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
986 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
987 spin_unlock_irqrestore(&priv->lock, flags);
988
989 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
990 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
991 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
992 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
993 } else {
994 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
995 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
996 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
997 }
998
999 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
1000
1001 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
1002 cmd.critical_temperature_R =
1003 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1004 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1005 sizeof(cmd), &cmd);
1006 if (ret)
1007 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1008 else
1009 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1010 }
1011
1012 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1013
1014 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1015 * Called after every association, but this runs only once!
1016 * ... once chain noise is calibrated the first time, it's good forever. */
1017 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1018 {
1019 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
1020
1021 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
1022 struct iwl4965_calibration_cmd cmd;
1023
1024 memset(&cmd, 0, sizeof(cmd));
1025 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1026 cmd.diff_gain_a = 0;
1027 cmd.diff_gain_b = 0;
1028 cmd.diff_gain_c = 0;
1029 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1030 sizeof(cmd), &cmd))
1031 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
1032 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1033 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1034 }
1035 }
1036
1037 static void iwl4965_gain_computation(struct iwl_priv *priv,
1038 u32 *average_noise,
1039 u16 min_average_noise_antenna_i,
1040 u32 min_average_noise)
1041 {
1042 int i, ret;
1043 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
1044
1045 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1046
1047 for (i = 0; i < NUM_RX_CHAINS; i++) {
1048 s32 delta_g = 0;
1049
1050 if (!(data->disconn_array[i]) &&
1051 (data->delta_gain_code[i] ==
1052 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1053 delta_g = average_noise[i] - min_average_noise;
1054 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1055 data->delta_gain_code[i] =
1056 min(data->delta_gain_code[i],
1057 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1058
1059 data->delta_gain_code[i] =
1060 (data->delta_gain_code[i] | (1 << 2));
1061 } else {
1062 data->delta_gain_code[i] = 0;
1063 }
1064 }
1065 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1066 data->delta_gain_code[0],
1067 data->delta_gain_code[1],
1068 data->delta_gain_code[2]);
1069
1070 /* Differential gain gets sent to uCode only once */
1071 if (!data->radio_write) {
1072 struct iwl4965_calibration_cmd cmd;
1073 data->radio_write = 1;
1074
1075 memset(&cmd, 0, sizeof(cmd));
1076 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1077 cmd.diff_gain_a = data->delta_gain_code[0];
1078 cmd.diff_gain_b = data->delta_gain_code[1];
1079 cmd.diff_gain_c = data->delta_gain_code[2];
1080 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1081 sizeof(cmd), &cmd);
1082 if (ret)
1083 IWL_DEBUG_CALIB("fail sending cmd "
1084 "REPLY_PHY_CALIBRATION_CMD \n");
1085
1086 /* TODO we might want recalculate
1087 * rx_chain in rxon cmd */
1088
1089 /* Mark so we run this algo only once! */
1090 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1091 }
1092 data->chain_noise_a = 0;
1093 data->chain_noise_b = 0;
1094 data->chain_noise_c = 0;
1095 data->chain_signal_a = 0;
1096 data->chain_signal_b = 0;
1097 data->chain_signal_c = 0;
1098 data->beacon_count = 0;
1099 }
1100
1101 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1102 {
1103 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1104 sensitivity_work);
1105
1106 mutex_lock(&priv->mutex);
1107
1108 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1109 test_bit(STATUS_SCANNING, &priv->status)) {
1110 mutex_unlock(&priv->mutex);
1111 return;
1112 }
1113
1114 if (priv->start_calib) {
1115 iwl_chain_noise_calibration(priv, &priv->statistics);
1116
1117 iwl_sensitivity_calibration(priv, &priv->statistics);
1118 }
1119
1120 mutex_unlock(&priv->mutex);
1121 return;
1122 }
1123 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
1124
1125 static void iwl4965_bg_txpower_work(struct work_struct *work)
1126 {
1127 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1128 txpower_work);
1129
1130 /* If a scan happened to start before we got here
1131 * then just return; the statistics notification will
1132 * kick off another scheduled work to compensate for
1133 * any temperature delta we missed here. */
1134 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1135 test_bit(STATUS_SCANNING, &priv->status))
1136 return;
1137
1138 mutex_lock(&priv->mutex);
1139
1140 /* Regardless of if we are assocaited, we must reconfigure the
1141 * TX power since frames can be sent on non-radar channels while
1142 * not associated */
1143 iwl4965_hw_reg_send_txpower(priv);
1144
1145 /* Update last_temperature to keep is_calib_needed from running
1146 * when it isn't needed... */
1147 priv->last_temperature = priv->temperature;
1148
1149 mutex_unlock(&priv->mutex);
1150 }
1151
1152 /*
1153 * Acquire priv->lock before calling this function !
1154 */
1155 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1156 {
1157 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1158 (index & 0xff) | (txq_id << 8));
1159 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
1160 }
1161
1162 /**
1163 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1164 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1165 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1166 *
1167 * NOTE: Acquire priv->lock before calling this function !
1168 */
1169 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1170 struct iwl4965_tx_queue *txq,
1171 int tx_fifo_id, int scd_retry)
1172 {
1173 int txq_id = txq->q.id;
1174
1175 /* Find out whether to activate Tx queue */
1176 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1177
1178 /* Set up and activate */
1179 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1180 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1181 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1182 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1183 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1184 SCD_QUEUE_STTS_REG_MSK);
1185
1186 txq->sched_retry = scd_retry;
1187
1188 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1189 active ? "Activate" : "Deactivate",
1190 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1191 }
1192
1193 static const u16 default_queue_to_tx_fifo[] = {
1194 IWL_TX_FIFO_AC3,
1195 IWL_TX_FIFO_AC2,
1196 IWL_TX_FIFO_AC1,
1197 IWL_TX_FIFO_AC0,
1198 IWL_CMD_FIFO_NUM,
1199 IWL_TX_FIFO_HCCA_1,
1200 IWL_TX_FIFO_HCCA_2
1201 };
1202
1203 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1204 {
1205 set_bit(txq_id, &priv->txq_ctx_active_msk);
1206 }
1207
1208 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1209 {
1210 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1211 }
1212
1213 int iwl4965_alive_notify(struct iwl_priv *priv)
1214 {
1215 u32 a;
1216 int i = 0;
1217 unsigned long flags;
1218 int ret;
1219
1220 spin_lock_irqsave(&priv->lock, flags);
1221
1222 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1223 memset(&(priv->sensitivity_data), 0,
1224 sizeof(struct iwl_sensitivity_data));
1225 memset(&(priv->chain_noise_data), 0,
1226 sizeof(struct iwl_chain_noise_data));
1227 for (i = 0; i < NUM_RX_CHAINS; i++)
1228 priv->chain_noise_data.delta_gain_code[i] =
1229 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1230 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1231 ret = iwl_grab_nic_access(priv);
1232 if (ret) {
1233 spin_unlock_irqrestore(&priv->lock, flags);
1234 return ret;
1235 }
1236
1237 /* Clear 4965's internal Tx Scheduler data base */
1238 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1239 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1240 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1241 iwl_write_targ_mem(priv, a, 0);
1242 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1243 iwl_write_targ_mem(priv, a, 0);
1244 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1245 iwl_write_targ_mem(priv, a, 0);
1246
1247 /* Tel 4965 where to find Tx byte count tables */
1248 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1249 (priv->shared_phys +
1250 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1251
1252 /* Disable chain mode for all queues */
1253 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1254
1255 /* Initialize each Tx queue (including the command queue) */
1256 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1257
1258 /* TFD circular buffer read/write indexes */
1259 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1260 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1261
1262 /* Max Tx Window size for Scheduler-ACK mode */
1263 iwl_write_targ_mem(priv, priv->scd_base_addr +
1264 SCD_CONTEXT_QUEUE_OFFSET(i),
1265 (SCD_WIN_SIZE <<
1266 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1267 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1268
1269 /* Frame limit */
1270 iwl_write_targ_mem(priv, priv->scd_base_addr +
1271 SCD_CONTEXT_QUEUE_OFFSET(i) +
1272 sizeof(u32),
1273 (SCD_FRAME_LIMIT <<
1274 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1275 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1276
1277 }
1278 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1279 (1 << priv->hw_params.max_txq_num) - 1);
1280
1281 /* Activate all Tx DMA/FIFO channels */
1282 iwl_write_prph(priv, IWL49_SCD_TXFACT,
1283 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1284
1285 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1286
1287 /* Map each Tx/cmd queue to its corresponding fifo */
1288 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1289 int ac = default_queue_to_tx_fifo[i];
1290 iwl4965_txq_ctx_activate(priv, i);
1291 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1292 }
1293
1294 iwl_release_nic_access(priv);
1295 spin_unlock_irqrestore(&priv->lock, flags);
1296
1297 /* Ask for statistics now, the uCode will send statistics notification
1298 * periodically after association */
1299 iwl_send_statistics_request(priv, CMD_ASYNC);
1300 return ret;
1301 }
1302
1303 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1304 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1305 .min_nrg_cck = 97,
1306 .max_nrg_cck = 0,
1307
1308 .auto_corr_min_ofdm = 85,
1309 .auto_corr_min_ofdm_mrc = 170,
1310 .auto_corr_min_ofdm_x1 = 105,
1311 .auto_corr_min_ofdm_mrc_x1 = 220,
1312
1313 .auto_corr_max_ofdm = 120,
1314 .auto_corr_max_ofdm_mrc = 210,
1315 .auto_corr_max_ofdm_x1 = 140,
1316 .auto_corr_max_ofdm_mrc_x1 = 270,
1317
1318 .auto_corr_min_cck = 125,
1319 .auto_corr_max_cck = 200,
1320 .auto_corr_min_cck_mrc = 200,
1321 .auto_corr_max_cck_mrc = 400,
1322
1323 .nrg_th_cck = 100,
1324 .nrg_th_ofdm = 100,
1325 };
1326 #endif
1327
1328 /**
1329 * iwl4965_hw_set_hw_params
1330 *
1331 * Called when initializing driver
1332 */
1333 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1334 {
1335
1336 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1337 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1338 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1339 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
1340 return -EINVAL;
1341 }
1342
1343 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1344 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1345 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1346 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1347 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1348 if (priv->cfg->mod_params->amsdu_size_8K)
1349 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1350 else
1351 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1352 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1353 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1354 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1355
1356 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1357 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1358 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1359 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1360
1361 priv->hw_params.tx_chains_num = 2;
1362 priv->hw_params.rx_chains_num = 2;
1363 priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1364 priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1365 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1366
1367 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1368 priv->hw_params.sens = &iwl4965_sensitivity;
1369 #endif
1370
1371 return 0;
1372 }
1373
1374 /**
1375 * iwl4965_hw_txq_ctx_free - Free TXQ Context
1376 *
1377 * Destroy all TX DMA queues and structures
1378 */
1379 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1380 {
1381 int txq_id;
1382
1383 /* Tx queues */
1384 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1385 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1386
1387 /* Keep-warm buffer */
1388 iwl4965_kw_free(priv);
1389 }
1390
1391 /**
1392 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1393 *
1394 * Does NOT advance any TFD circular buffer read/write indexes
1395 * Does NOT free the TFD itself (which is within circular buffer)
1396 */
1397 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1398 {
1399 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1400 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1401 struct pci_dev *dev = priv->pci_dev;
1402 int i;
1403 int counter = 0;
1404 int index, is_odd;
1405
1406 /* Host command buffers stay mapped in memory, nothing to clean */
1407 if (txq->q.id == IWL_CMD_QUEUE_NUM)
1408 return 0;
1409
1410 /* Sanity check on number of chunks */
1411 counter = IWL_GET_BITS(*bd, num_tbs);
1412 if (counter > MAX_NUM_OF_TBS) {
1413 IWL_ERROR("Too many chunks: %i\n", counter);
1414 /* @todo issue fatal error, it is quite serious situation */
1415 return 0;
1416 }
1417
1418 /* Unmap chunks, if any.
1419 * TFD info for odd chunks is different format than for even chunks. */
1420 for (i = 0; i < counter; i++) {
1421 index = i / 2;
1422 is_odd = i & 0x1;
1423
1424 if (is_odd)
1425 pci_unmap_single(
1426 dev,
1427 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1428 (IWL_GET_BITS(bd->pa[index],
1429 tb2_addr_hi20) << 16),
1430 IWL_GET_BITS(bd->pa[index], tb2_len),
1431 PCI_DMA_TODEVICE);
1432
1433 else if (i > 0)
1434 pci_unmap_single(dev,
1435 le32_to_cpu(bd->pa[index].tb1_addr),
1436 IWL_GET_BITS(bd->pa[index], tb1_len),
1437 PCI_DMA_TODEVICE);
1438
1439 /* Free SKB, if any, for this chunk */
1440 if (txq->txb[txq->q.read_ptr].skb[i]) {
1441 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1442
1443 dev_kfree_skb(skb);
1444 txq->txb[txq->q.read_ptr].skb[i] = NULL;
1445 }
1446 }
1447 return 0;
1448 }
1449
1450 /* set card power command */
1451 static int iwl4965_set_power(struct iwl_priv *priv,
1452 void *cmd)
1453 {
1454 int ret = 0;
1455
1456 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1457 sizeof(struct iwl4965_powertable_cmd),
1458 cmd, NULL);
1459 return ret;
1460 }
1461 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1462 {
1463 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1464 return -EINVAL;
1465 }
1466
1467 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1468 {
1469 s32 sign = 1;
1470
1471 if (num < 0) {
1472 sign = -sign;
1473 num = -num;
1474 }
1475 if (denom < 0) {
1476 sign = -sign;
1477 denom = -denom;
1478 }
1479 *res = 1;
1480 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1481
1482 return 1;
1483 }
1484
1485 /**
1486 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1487 *
1488 * Determines power supply voltage compensation for txpower calculations.
1489 * Returns number of 1/2-dB steps to subtract from gain table index,
1490 * to compensate for difference between power supply voltage during
1491 * factory measurements, vs. current power supply voltage.
1492 *
1493 * Voltage indication is higher for lower voltage.
1494 * Lower voltage requires more gain (lower gain table index).
1495 */
1496 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1497 s32 current_voltage)
1498 {
1499 s32 comp = 0;
1500
1501 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1502 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1503 return 0;
1504
1505 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1506 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1507
1508 if (current_voltage > eeprom_voltage)
1509 comp *= 2;
1510 if ((comp < -2) || (comp > 2))
1511 comp = 0;
1512
1513 return comp;
1514 }
1515
1516 static const struct iwl_channel_info *
1517 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1518 enum ieee80211_band band, u16 channel)
1519 {
1520 const struct iwl_channel_info *ch_info;
1521
1522 ch_info = iwl_get_channel_info(priv, band, channel);
1523
1524 if (!is_channel_valid(ch_info))
1525 return NULL;
1526
1527 return ch_info;
1528 }
1529
1530 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1531 {
1532 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1533 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1534 return CALIB_CH_GROUP_5;
1535
1536 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1537 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1538 return CALIB_CH_GROUP_1;
1539
1540 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1541 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1542 return CALIB_CH_GROUP_2;
1543
1544 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1545 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1546 return CALIB_CH_GROUP_3;
1547
1548 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1549 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1550 return CALIB_CH_GROUP_4;
1551
1552 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1553 return -1;
1554 }
1555
1556 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1557 {
1558 s32 b = -1;
1559
1560 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1561 if (priv->calib_info->band_info[b].ch_from == 0)
1562 continue;
1563
1564 if ((channel >= priv->calib_info->band_info[b].ch_from)
1565 && (channel <= priv->calib_info->band_info[b].ch_to))
1566 break;
1567 }
1568
1569 return b;
1570 }
1571
1572 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1573 {
1574 s32 val;
1575
1576 if (x2 == x1)
1577 return y1;
1578 else {
1579 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1580 return val + y2;
1581 }
1582 }
1583
1584 /**
1585 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1586 *
1587 * Interpolates factory measurements from the two sample channels within a
1588 * sub-band, to apply to channel of interest. Interpolation is proportional to
1589 * differences in channel frequencies, which is proportional to differences
1590 * in channel number.
1591 */
1592 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1593 struct iwl_eeprom_calib_ch_info *chan_info)
1594 {
1595 s32 s = -1;
1596 u32 c;
1597 u32 m;
1598 const struct iwl_eeprom_calib_measure *m1;
1599 const struct iwl_eeprom_calib_measure *m2;
1600 struct iwl_eeprom_calib_measure *omeas;
1601 u32 ch_i1;
1602 u32 ch_i2;
1603
1604 s = iwl4965_get_sub_band(priv, channel);
1605 if (s >= EEPROM_TX_POWER_BANDS) {
1606 IWL_ERROR("Tx Power can not find channel %d ", channel);
1607 return -1;
1608 }
1609
1610 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1611 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
1612 chan_info->ch_num = (u8) channel;
1613
1614 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1615 channel, s, ch_i1, ch_i2);
1616
1617 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1618 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1619 m1 = &(priv->calib_info->band_info[s].ch1.
1620 measurements[c][m]);
1621 m2 = &(priv->calib_info->band_info[s].ch2.
1622 measurements[c][m]);
1623 omeas = &(chan_info->measurements[c][m]);
1624
1625 omeas->actual_pow =
1626 (u8) iwl4965_interpolate_value(channel, ch_i1,
1627 m1->actual_pow,
1628 ch_i2,
1629 m2->actual_pow);
1630 omeas->gain_idx =
1631 (u8) iwl4965_interpolate_value(channel, ch_i1,
1632 m1->gain_idx, ch_i2,
1633 m2->gain_idx);
1634 omeas->temperature =
1635 (u8) iwl4965_interpolate_value(channel, ch_i1,
1636 m1->temperature,
1637 ch_i2,
1638 m2->temperature);
1639 omeas->pa_det =
1640 (s8) iwl4965_interpolate_value(channel, ch_i1,
1641 m1->pa_det, ch_i2,
1642 m2->pa_det);
1643
1644 IWL_DEBUG_TXPOWER
1645 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1646 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1647 IWL_DEBUG_TXPOWER
1648 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1649 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1650 IWL_DEBUG_TXPOWER
1651 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1652 m1->pa_det, m2->pa_det, omeas->pa_det);
1653 IWL_DEBUG_TXPOWER
1654 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1655 m1->temperature, m2->temperature,
1656 omeas->temperature);
1657 }
1658 }
1659
1660 return 0;
1661 }
1662
1663 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1664 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1665 static s32 back_off_table[] = {
1666 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1667 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1668 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1669 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1670 10 /* CCK */
1671 };
1672
1673 /* Thermal compensation values for txpower for various frequency ranges ...
1674 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1675 static struct iwl4965_txpower_comp_entry {
1676 s32 degrees_per_05db_a;
1677 s32 degrees_per_05db_a_denom;
1678 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1679 {9, 2}, /* group 0 5.2, ch 34-43 */
1680 {4, 1}, /* group 1 5.2, ch 44-70 */
1681 {4, 1}, /* group 2 5.2, ch 71-124 */
1682 {4, 1}, /* group 3 5.2, ch 125-200 */
1683 {3, 1} /* group 4 2.4, ch all */
1684 };
1685
1686 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1687 {
1688 if (!band) {
1689 if ((rate_power_index & 7) <= 4)
1690 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1691 }
1692 return MIN_TX_GAIN_INDEX;
1693 }
1694
1695 struct gain_entry {
1696 u8 dsp;
1697 u8 radio;
1698 };
1699
1700 static const struct gain_entry gain_table[2][108] = {
1701 /* 5.2GHz power gain index table */
1702 {
1703 {123, 0x3F}, /* highest txpower */
1704 {117, 0x3F},
1705 {110, 0x3F},
1706 {104, 0x3F},
1707 {98, 0x3F},
1708 {110, 0x3E},
1709 {104, 0x3E},
1710 {98, 0x3E},
1711 {110, 0x3D},
1712 {104, 0x3D},
1713 {98, 0x3D},
1714 {110, 0x3C},
1715 {104, 0x3C},
1716 {98, 0x3C},
1717 {110, 0x3B},
1718 {104, 0x3B},
1719 {98, 0x3B},
1720 {110, 0x3A},
1721 {104, 0x3A},
1722 {98, 0x3A},
1723 {110, 0x39},
1724 {104, 0x39},
1725 {98, 0x39},
1726 {110, 0x38},
1727 {104, 0x38},
1728 {98, 0x38},
1729 {110, 0x37},
1730 {104, 0x37},
1731 {98, 0x37},
1732 {110, 0x36},
1733 {104, 0x36},
1734 {98, 0x36},
1735 {110, 0x35},
1736 {104, 0x35},
1737 {98, 0x35},
1738 {110, 0x34},
1739 {104, 0x34},
1740 {98, 0x34},
1741 {110, 0x33},
1742 {104, 0x33},
1743 {98, 0x33},
1744 {110, 0x32},
1745 {104, 0x32},
1746 {98, 0x32},
1747 {110, 0x31},
1748 {104, 0x31},
1749 {98, 0x31},
1750 {110, 0x30},
1751 {104, 0x30},
1752 {98, 0x30},
1753 {110, 0x25},
1754 {104, 0x25},
1755 {98, 0x25},
1756 {110, 0x24},
1757 {104, 0x24},
1758 {98, 0x24},
1759 {110, 0x23},
1760 {104, 0x23},
1761 {98, 0x23},
1762 {110, 0x22},
1763 {104, 0x18},
1764 {98, 0x18},
1765 {110, 0x17},
1766 {104, 0x17},
1767 {98, 0x17},
1768 {110, 0x16},
1769 {104, 0x16},
1770 {98, 0x16},
1771 {110, 0x15},
1772 {104, 0x15},
1773 {98, 0x15},
1774 {110, 0x14},
1775 {104, 0x14},
1776 {98, 0x14},
1777 {110, 0x13},
1778 {104, 0x13},
1779 {98, 0x13},
1780 {110, 0x12},
1781 {104, 0x08},
1782 {98, 0x08},
1783 {110, 0x07},
1784 {104, 0x07},
1785 {98, 0x07},
1786 {110, 0x06},
1787 {104, 0x06},
1788 {98, 0x06},
1789 {110, 0x05},
1790 {104, 0x05},
1791 {98, 0x05},
1792 {110, 0x04},
1793 {104, 0x04},
1794 {98, 0x04},
1795 {110, 0x03},
1796 {104, 0x03},
1797 {98, 0x03},
1798 {110, 0x02},
1799 {104, 0x02},
1800 {98, 0x02},
1801 {110, 0x01},
1802 {104, 0x01},
1803 {98, 0x01},
1804 {110, 0x00},
1805 {104, 0x00},
1806 {98, 0x00},
1807 {93, 0x00},
1808 {88, 0x00},
1809 {83, 0x00},
1810 {78, 0x00},
1811 },
1812 /* 2.4GHz power gain index table */
1813 {
1814 {110, 0x3f}, /* highest txpower */
1815 {104, 0x3f},
1816 {98, 0x3f},
1817 {110, 0x3e},
1818 {104, 0x3e},
1819 {98, 0x3e},
1820 {110, 0x3d},
1821 {104, 0x3d},
1822 {98, 0x3d},
1823 {110, 0x3c},
1824 {104, 0x3c},
1825 {98, 0x3c},
1826 {110, 0x3b},
1827 {104, 0x3b},
1828 {98, 0x3b},
1829 {110, 0x3a},
1830 {104, 0x3a},
1831 {98, 0x3a},
1832 {110, 0x39},
1833 {104, 0x39},
1834 {98, 0x39},
1835 {110, 0x38},
1836 {104, 0x38},
1837 {98, 0x38},
1838 {110, 0x37},
1839 {104, 0x37},
1840 {98, 0x37},
1841 {110, 0x36},
1842 {104, 0x36},
1843 {98, 0x36},
1844 {110, 0x35},
1845 {104, 0x35},
1846 {98, 0x35},
1847 {110, 0x34},
1848 {104, 0x34},
1849 {98, 0x34},
1850 {110, 0x33},
1851 {104, 0x33},
1852 {98, 0x33},
1853 {110, 0x32},
1854 {104, 0x32},
1855 {98, 0x32},
1856 {110, 0x31},
1857 {104, 0x31},
1858 {98, 0x31},
1859 {110, 0x30},
1860 {104, 0x30},
1861 {98, 0x30},
1862 {110, 0x6},
1863 {104, 0x6},
1864 {98, 0x6},
1865 {110, 0x5},
1866 {104, 0x5},
1867 {98, 0x5},
1868 {110, 0x4},
1869 {104, 0x4},
1870 {98, 0x4},
1871 {110, 0x3},
1872 {104, 0x3},
1873 {98, 0x3},
1874 {110, 0x2},
1875 {104, 0x2},
1876 {98, 0x2},
1877 {110, 0x1},
1878 {104, 0x1},
1879 {98, 0x1},
1880 {110, 0x0},
1881 {104, 0x0},
1882 {98, 0x0},
1883 {97, 0},
1884 {96, 0},
1885 {95, 0},
1886 {94, 0},
1887 {93, 0},
1888 {92, 0},
1889 {91, 0},
1890 {90, 0},
1891 {89, 0},
1892 {88, 0},
1893 {87, 0},
1894 {86, 0},
1895 {85, 0},
1896 {84, 0},
1897 {83, 0},
1898 {82, 0},
1899 {81, 0},
1900 {80, 0},
1901 {79, 0},
1902 {78, 0},
1903 {77, 0},
1904 {76, 0},
1905 {75, 0},
1906 {74, 0},
1907 {73, 0},
1908 {72, 0},
1909 {71, 0},
1910 {70, 0},
1911 {69, 0},
1912 {68, 0},
1913 {67, 0},
1914 {66, 0},
1915 {65, 0},
1916 {64, 0},
1917 {63, 0},
1918 {62, 0},
1919 {61, 0},
1920 {60, 0},
1921 {59, 0},
1922 }
1923 };
1924
1925 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1926 u8 is_fat, u8 ctrl_chan_high,
1927 struct iwl4965_tx_power_db *tx_power_tbl)
1928 {
1929 u8 saturation_power;
1930 s32 target_power;
1931 s32 user_target_power;
1932 s32 power_limit;
1933 s32 current_temp;
1934 s32 reg_limit;
1935 s32 current_regulatory;
1936 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1937 int i;
1938 int c;
1939 const struct iwl_channel_info *ch_info = NULL;
1940 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1941 const struct iwl_eeprom_calib_measure *measurement;
1942 s16 voltage;
1943 s32 init_voltage;
1944 s32 voltage_compensation;
1945 s32 degrees_per_05db_num;
1946 s32 degrees_per_05db_denom;
1947 s32 factory_temp;
1948 s32 temperature_comp[2];
1949 s32 factory_gain_index[2];
1950 s32 factory_actual_pwr[2];
1951 s32 power_index;
1952
1953 /* Sanity check requested level (dBm) */
1954 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1955 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1956 priv->user_txpower_limit);
1957 return -EINVAL;
1958 }
1959 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1960 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1961 priv->user_txpower_limit);
1962 return -EINVAL;
1963 }
1964
1965 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1966 * are used for indexing into txpower table) */
1967 user_target_power = 2 * priv->user_txpower_limit;
1968
1969 /* Get current (RXON) channel, band, width */
1970 ch_info =
1971 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1972
1973 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1974 is_fat);
1975
1976 if (!ch_info)
1977 return -EINVAL;
1978
1979 /* get txatten group, used to select 1) thermal txpower adjustment
1980 * and 2) mimo txpower balance between Tx chains. */
1981 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1982 if (txatten_grp < 0)
1983 return -EINVAL;
1984
1985 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1986 channel, txatten_grp);
1987
1988 if (is_fat) {
1989 if (ctrl_chan_high)
1990 channel -= 2;
1991 else
1992 channel += 2;
1993 }
1994
1995 /* hardware txpower limits ...
1996 * saturation (clipping distortion) txpowers are in half-dBm */
1997 if (band)
1998 saturation_power = priv->calib_info->saturation_power24;
1999 else
2000 saturation_power = priv->calib_info->saturation_power52;
2001
2002 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2003 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2004 if (band)
2005 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2006 else
2007 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2008 }
2009
2010 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2011 * max_power_avg values are in dBm, convert * 2 */
2012 if (is_fat)
2013 reg_limit = ch_info->fat_max_power_avg * 2;
2014 else
2015 reg_limit = ch_info->max_power_avg * 2;
2016
2017 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2018 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2019 if (band)
2020 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2021 else
2022 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2023 }
2024
2025 /* Interpolate txpower calibration values for this channel,
2026 * based on factory calibration tests on spaced channels. */
2027 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2028
2029 /* calculate tx gain adjustment based on power supply voltage */
2030 voltage = priv->calib_info->voltage;
2031 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2032 voltage_compensation =
2033 iwl4965_get_voltage_compensation(voltage, init_voltage);
2034
2035 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2036 init_voltage,
2037 voltage, voltage_compensation);
2038
2039 /* get current temperature (Celsius) */
2040 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2041 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2042 current_temp = KELVIN_TO_CELSIUS(current_temp);
2043
2044 /* select thermal txpower adjustment params, based on channel group
2045 * (same frequency group used for mimo txatten adjustment) */
2046 degrees_per_05db_num =
2047 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2048 degrees_per_05db_denom =
2049 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2050
2051 /* get per-chain txpower values from factory measurements */
2052 for (c = 0; c < 2; c++) {
2053 measurement = &ch_eeprom_info.measurements[c][1];
2054
2055 /* txgain adjustment (in half-dB steps) based on difference
2056 * between factory and current temperature */
2057 factory_temp = measurement->temperature;
2058 iwl4965_math_div_round((current_temp - factory_temp) *
2059 degrees_per_05db_denom,
2060 degrees_per_05db_num,
2061 &temperature_comp[c]);
2062
2063 factory_gain_index[c] = measurement->gain_idx;
2064 factory_actual_pwr[c] = measurement->actual_pow;
2065
2066 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2067 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2068 "curr tmp %d, comp %d steps\n",
2069 factory_temp, current_temp,
2070 temperature_comp[c]);
2071
2072 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2073 factory_gain_index[c],
2074 factory_actual_pwr[c]);
2075 }
2076
2077 /* for each of 33 bit-rates (including 1 for CCK) */
2078 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2079 u8 is_mimo_rate;
2080 union iwl4965_tx_power_dual_stream tx_power;
2081
2082 /* for mimo, reduce each chain's txpower by half
2083 * (3dB, 6 steps), so total output power is regulatory
2084 * compliant. */
2085 if (i & 0x8) {
2086 current_regulatory = reg_limit -
2087 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2088 is_mimo_rate = 1;
2089 } else {
2090 current_regulatory = reg_limit;
2091 is_mimo_rate = 0;
2092 }
2093
2094 /* find txpower limit, either hardware or regulatory */
2095 power_limit = saturation_power - back_off_table[i];
2096 if (power_limit > current_regulatory)
2097 power_limit = current_regulatory;
2098
2099 /* reduce user's txpower request if necessary
2100 * for this rate on this channel */
2101 target_power = user_target_power;
2102 if (target_power > power_limit)
2103 target_power = power_limit;
2104
2105 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2106 i, saturation_power - back_off_table[i],
2107 current_regulatory, user_target_power,
2108 target_power);
2109
2110 /* for each of 2 Tx chains (radio transmitters) */
2111 for (c = 0; c < 2; c++) {
2112 s32 atten_value;
2113
2114 if (is_mimo_rate)
2115 atten_value =
2116 (s32)le32_to_cpu(priv->card_alive_init.
2117 tx_atten[txatten_grp][c]);
2118 else
2119 atten_value = 0;
2120
2121 /* calculate index; higher index means lower txpower */
2122 power_index = (u8) (factory_gain_index[c] -
2123 (target_power -
2124 factory_actual_pwr[c]) -
2125 temperature_comp[c] -
2126 voltage_compensation +
2127 atten_value);
2128
2129 /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2130 power_index); */
2131
2132 if (power_index < get_min_power_index(i, band))
2133 power_index = get_min_power_index(i, band);
2134
2135 /* adjust 5 GHz index to support negative indexes */
2136 if (!band)
2137 power_index += 9;
2138
2139 /* CCK, rate 32, reduce txpower for CCK */
2140 if (i == POWER_TABLE_CCK_ENTRY)
2141 power_index +=
2142 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2143
2144 /* stay within the table! */
2145 if (power_index > 107) {
2146 IWL_WARNING("txpower index %d > 107\n",
2147 power_index);
2148 power_index = 107;
2149 }
2150 if (power_index < 0) {
2151 IWL_WARNING("txpower index %d < 0\n",
2152 power_index);
2153 power_index = 0;
2154 }
2155
2156 /* fill txpower command for this rate/chain */
2157 tx_power.s.radio_tx_gain[c] =
2158 gain_table[band][power_index].radio;
2159 tx_power.s.dsp_predis_atten[c] =
2160 gain_table[band][power_index].dsp;
2161
2162 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2163 "gain 0x%02x dsp %d\n",
2164 c, atten_value, power_index,
2165 tx_power.s.radio_tx_gain[c],
2166 tx_power.s.dsp_predis_atten[c]);
2167 }/* for each chain */
2168
2169 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2170
2171 }/* for each rate */
2172
2173 return 0;
2174 }
2175
2176 /**
2177 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
2178 *
2179 * Uses the active RXON for channel, band, and characteristics (fat, high)
2180 * The power limit is taken from priv->user_txpower_limit.
2181 */
2182 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2183 {
2184 struct iwl4965_txpowertable_cmd cmd = { 0 };
2185 int ret;
2186 u8 band = 0;
2187 u8 is_fat = 0;
2188 u8 ctrl_chan_high = 0;
2189
2190 if (test_bit(STATUS_SCANNING, &priv->status)) {
2191 /* If this gets hit a lot, switch it to a BUG() and catch
2192 * the stack trace to find out who is calling this during
2193 * a scan. */
2194 IWL_WARNING("TX Power requested while scanning!\n");
2195 return -EAGAIN;
2196 }
2197
2198 band = priv->band == IEEE80211_BAND_2GHZ;
2199
2200 is_fat = is_fat_channel(priv->active_rxon.flags);
2201
2202 if (is_fat &&
2203 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2204 ctrl_chan_high = 1;
2205
2206 cmd.band = band;
2207 cmd.channel = priv->active_rxon.channel;
2208
2209 ret = iwl4965_fill_txpower_tbl(priv, band,
2210 le16_to_cpu(priv->active_rxon.channel),
2211 is_fat, ctrl_chan_high, &cmd.tx_power);
2212 if (ret)
2213 goto out;
2214
2215 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2216
2217 out:
2218 return ret;
2219 }
2220
2221 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2222 {
2223 int ret = 0;
2224 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2225 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2226 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2227
2228 if ((rxon1->flags == rxon2->flags) &&
2229 (rxon1->filter_flags == rxon2->filter_flags) &&
2230 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2231 (rxon1->ofdm_ht_single_stream_basic_rates ==
2232 rxon2->ofdm_ht_single_stream_basic_rates) &&
2233 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2234 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2235 (rxon1->rx_chain == rxon2->rx_chain) &&
2236 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2237 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2238 return 0;
2239 }
2240
2241 rxon_assoc.flags = priv->staging_rxon.flags;
2242 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2243 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2244 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2245 rxon_assoc.reserved = 0;
2246 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2247 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2248 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2249 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2250 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2251
2252 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2253 sizeof(rxon_assoc), &rxon_assoc, NULL);
2254 if (ret)
2255 return ret;
2256
2257 return ret;
2258 }
2259
2260
2261 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2262 {
2263 int rc;
2264 u8 band = 0;
2265 u8 is_fat = 0;
2266 u8 ctrl_chan_high = 0;
2267 struct iwl4965_channel_switch_cmd cmd = { 0 };
2268 const struct iwl_channel_info *ch_info;
2269
2270 band = priv->band == IEEE80211_BAND_2GHZ;
2271
2272 ch_info = iwl_get_channel_info(priv, priv->band, channel);
2273
2274 is_fat = is_fat_channel(priv->staging_rxon.flags);
2275
2276 if (is_fat &&
2277 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2278 ctrl_chan_high = 1;
2279
2280 cmd.band = band;
2281 cmd.expect_beacon = 0;
2282 cmd.channel = cpu_to_le16(channel);
2283 cmd.rxon_flags = priv->active_rxon.flags;
2284 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2285 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2286 if (ch_info)
2287 cmd.expect_beacon = is_channel_radar(ch_info);
2288 else
2289 cmd.expect_beacon = 1;
2290
2291 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2292 ctrl_chan_high, &cmd.tx_power);
2293 if (rc) {
2294 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2295 return rc;
2296 }
2297
2298 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2299 return rc;
2300 }
2301
2302 #define RTS_HCCA_RETRY_LIMIT 3
2303 #define RTS_DFAULT_RETRY_LIMIT 60
2304
2305 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2306 struct iwl_cmd *cmd,
2307 struct ieee80211_tx_control *ctrl,
2308 struct ieee80211_hdr *hdr, int sta_id,
2309 int is_hcca)
2310 {
2311 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2312 u8 rts_retry_limit = 0;
2313 u8 data_retry_limit = 0;
2314 u16 fc = le16_to_cpu(hdr->frame_control);
2315 u8 rate_plcp;
2316 u16 rate_flags = 0;
2317 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2318
2319 rate_plcp = iwl4965_rates[rate_idx].plcp;
2320
2321 rts_retry_limit = (is_hcca) ?
2322 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2323
2324 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2325 rate_flags |= RATE_MCS_CCK_MSK;
2326
2327
2328 if (ieee80211_is_probe_response(fc)) {
2329 data_retry_limit = 3;
2330 if (data_retry_limit < rts_retry_limit)
2331 rts_retry_limit = data_retry_limit;
2332 } else
2333 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2334
2335 if (priv->data_retry_limit != -1)
2336 data_retry_limit = priv->data_retry_limit;
2337
2338
2339 if (ieee80211_is_data(fc)) {
2340 tx->initial_rate_index = 0;
2341 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2342 } else {
2343 switch (fc & IEEE80211_FCTL_STYPE) {
2344 case IEEE80211_STYPE_AUTH:
2345 case IEEE80211_STYPE_DEAUTH:
2346 case IEEE80211_STYPE_ASSOC_REQ:
2347 case IEEE80211_STYPE_REASSOC_REQ:
2348 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2349 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2350 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2351 }
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 /* Alternate between antenna A and B for successive frames */
2358 if (priv->use_ant_b_for_management_frame) {
2359 priv->use_ant_b_for_management_frame = 0;
2360 rate_flags |= RATE_MCS_ANT_B_MSK;
2361 } else {
2362 priv->use_ant_b_for_management_frame = 1;
2363 rate_flags |= RATE_MCS_ANT_A_MSK;
2364 }
2365 }
2366
2367 tx->rts_retry_limit = rts_retry_limit;
2368 tx->data_retry_limit = data_retry_limit;
2369 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2370 }
2371
2372 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2373 {
2374 struct iwl4965_shared *s = priv->shared_virt;
2375 return le32_to_cpu(s->rb_closed) & 0xFFF;
2376 }
2377
2378 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2379 {
2380 return priv->temperature;
2381 }
2382
2383 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2384 struct iwl4965_frame *frame, u8 rate)
2385 {
2386 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2387 unsigned int frame_size;
2388
2389 tx_beacon_cmd = &frame->u.beacon;
2390 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2391
2392 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2393 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2394
2395 frame_size = iwl4965_fill_beacon_frame(priv,
2396 tx_beacon_cmd->frame,
2397 iwl4965_broadcast_addr,
2398 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2399
2400 BUG_ON(frame_size > MAX_MPDU_SIZE);
2401 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2402
2403 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2404 tx_beacon_cmd->tx.rate_n_flags =
2405 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2406 else
2407 tx_beacon_cmd->tx.rate_n_flags =
2408 iwl4965_hw_set_rate_n_flags(rate, 0);
2409
2410 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2411 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2412 return (sizeof(*tx_beacon_cmd) + frame_size);
2413 }
2414
2415 /*
2416 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2417 * given Tx queue, and enable the DMA channel used for that queue.
2418 *
2419 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2420 * channels supported in hardware.
2421 */
2422 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2423 {
2424 int rc;
2425 unsigned long flags;
2426 int txq_id = txq->q.id;
2427
2428 spin_lock_irqsave(&priv->lock, flags);
2429 rc = iwl_grab_nic_access(priv);
2430 if (rc) {
2431 spin_unlock_irqrestore(&priv->lock, flags);
2432 return rc;
2433 }
2434
2435 /* Circular buffer (TFD queue in DRAM) physical base address */
2436 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2437 txq->q.dma_addr >> 8);
2438
2439 /* Enable DMA channel, using same id as for TFD queue */
2440 iwl_write_direct32(
2441 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2442 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2443 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2444 iwl_release_nic_access(priv);
2445 spin_unlock_irqrestore(&priv->lock, flags);
2446
2447 return 0;
2448 }
2449
2450 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2451 dma_addr_t addr, u16 len)
2452 {
2453 int index, is_odd;
2454 struct iwl4965_tfd_frame *tfd = ptr;
2455 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2456
2457 /* Each TFD can point to a maximum 20 Tx buffers */
2458 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2459 IWL_ERROR("Error can not send more than %d chunks\n",
2460 MAX_NUM_OF_TBS);
2461 return -EINVAL;
2462 }
2463
2464 index = num_tbs / 2;
2465 is_odd = num_tbs & 0x1;
2466
2467 if (!is_odd) {
2468 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2469 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2470 iwl_get_dma_hi_address(addr));
2471 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2472 } else {
2473 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2474 (u32) (addr & 0xffff));
2475 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2476 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2477 }
2478
2479 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2480
2481 return 0;
2482 }
2483
2484 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2485 {
2486 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
2487
2488 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2489 ((hw_version >> 8) & 0x0F),
2490 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2491
2492 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2493 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
2494 }
2495
2496 #define IWL_TX_CRC_SIZE 4
2497 #define IWL_TX_DELIMITER_SIZE 4
2498
2499 /**
2500 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2501 */
2502 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2503 struct iwl4965_tx_queue *txq,
2504 u16 byte_cnt)
2505 {
2506 int len;
2507 int txq_id = txq->q.id;
2508 struct iwl4965_shared *shared_data = priv->shared_virt;
2509
2510 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2511
2512 /* Set up byte count within first 256 entries */
2513 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2514 tfd_offset[txq->q.write_ptr], byte_cnt, len);
2515
2516 /* If within first 64 entries, duplicate at end */
2517 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
2518 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2519 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
2520 byte_cnt, len);
2521 }
2522
2523 /**
2524 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2525 *
2526 * Selects how many and which Rx receivers/antennas/chains to use.
2527 * This should not be used for scan command ... it puts data in wrong place.
2528 */
2529 void iwl4965_set_rxon_chain(struct iwl_priv *priv)
2530 {
2531 u8 is_single = is_single_stream(priv);
2532 u8 idle_state, rx_state;
2533
2534 priv->staging_rxon.rx_chain = 0;
2535 rx_state = idle_state = 3;
2536
2537 /* Tell uCode which antennas are actually connected.
2538 * Before first association, we assume all antennas are connected.
2539 * Just after first association, iwl_chain_noise_calibration()
2540 * checks which antennas actually *are* connected. */
2541 priv->staging_rxon.rx_chain |=
2542 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2543
2544 /* How many receivers should we use? */
2545 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2546 priv->staging_rxon.rx_chain |=
2547 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2548 priv->staging_rxon.rx_chain |=
2549 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2550
2551 if (!is_single && (rx_state >= 2) &&
2552 !test_bit(STATUS_POWER_PMI, &priv->status))
2553 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2554 else
2555 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2556
2557 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2558 }
2559
2560 /**
2561 * sign_extend - Sign extend a value using specified bit as sign-bit
2562 *
2563 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2564 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2565 *
2566 * @param oper value to sign extend
2567 * @param index 0 based bit index (0<=index<32) to sign bit
2568 */
2569 static s32 sign_extend(u32 oper, int index)
2570 {
2571 u8 shift = 31 - index;
2572
2573 return (s32)(oper << shift) >> shift;
2574 }
2575
2576 /**
2577 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2578 * @statistics: Provides the temperature reading from the uCode
2579 *
2580 * A return of <0 indicates bogus data in the statistics
2581 */
2582 int iwl4965_get_temperature(const struct iwl_priv *priv)
2583 {
2584 s32 temperature;
2585 s32 vt;
2586 s32 R1, R2, R3;
2587 u32 R4;
2588
2589 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2590 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2591 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2592 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2593 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2594 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2595 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2596 } else {
2597 IWL_DEBUG_TEMP("Running temperature calibration\n");
2598 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2599 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2600 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2601 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2602 }
2603
2604 /*
2605 * Temperature is only 23 bits, so sign extend out to 32.
2606 *
2607 * NOTE If we haven't received a statistics notification yet
2608 * with an updated temperature, use R4 provided to us in the
2609 * "initialize" ALIVE response.
2610 */
2611 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2612 vt = sign_extend(R4, 23);
2613 else
2614 vt = sign_extend(
2615 le32_to_cpu(priv->statistics.general.temperature), 23);
2616
2617 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2618 R1, R2, R3, vt);
2619
2620 if (R3 == R1) {
2621 IWL_ERROR("Calibration conflict R1 == R3\n");
2622 return -1;
2623 }
2624
2625 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2626 * Add offset to center the adjustment around 0 degrees Centigrade. */
2627 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2628 temperature /= (R3 - R1);
2629 temperature = (temperature * 97) / 100 +
2630 TEMPERATURE_CALIB_KELVIN_OFFSET;
2631
2632 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2633 KELVIN_TO_CELSIUS(temperature));
2634
2635 return temperature;
2636 }
2637
2638 /* Adjust Txpower only if temperature variance is greater than threshold. */
2639 #define IWL_TEMPERATURE_THRESHOLD 3
2640
2641 /**
2642 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2643 *
2644 * If the temperature changed has changed sufficiently, then a recalibration
2645 * is needed.
2646 *
2647 * Assumes caller will replace priv->last_temperature once calibration
2648 * executed.
2649 */
2650 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2651 {
2652 int temp_diff;
2653
2654 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2655 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2656 return 0;
2657 }
2658
2659 temp_diff = priv->temperature - priv->last_temperature;
2660
2661 /* get absolute value */
2662 if (temp_diff < 0) {
2663 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2664 temp_diff = -temp_diff;
2665 } else if (temp_diff == 0)
2666 IWL_DEBUG_POWER("Same temp, \n");
2667 else
2668 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2669
2670 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2671 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2672 return 0;
2673 }
2674
2675 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2676
2677 return 1;
2678 }
2679
2680 /* Calculate noise level, based on measurements during network silence just
2681 * before arriving beacon. This measurement can be done only if we know
2682 * exactly when to expect beacons, therefore only when we're associated. */
2683 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2684 {
2685 struct statistics_rx_non_phy *rx_info
2686 = &(priv->statistics.rx.general);
2687 int num_active_rx = 0;
2688 int total_silence = 0;
2689 int bcn_silence_a =
2690 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2691 int bcn_silence_b =
2692 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2693 int bcn_silence_c =
2694 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2695
2696 if (bcn_silence_a) {
2697 total_silence += bcn_silence_a;
2698 num_active_rx++;
2699 }
2700 if (bcn_silence_b) {
2701 total_silence += bcn_silence_b;
2702 num_active_rx++;
2703 }
2704 if (bcn_silence_c) {
2705 total_silence += bcn_silence_c;
2706 num_active_rx++;
2707 }
2708
2709 /* Average among active antennas */
2710 if (num_active_rx)
2711 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2712 else
2713 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2714
2715 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2716 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2717 priv->last_rx_noise);
2718 }
2719
2720 void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
2721 {
2722 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2723 int change;
2724 s32 temp;
2725
2726 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2727 (int)sizeof(priv->statistics), pkt->len);
2728
2729 change = ((priv->statistics.general.temperature !=
2730 pkt->u.stats.general.temperature) ||
2731 ((priv->statistics.flag &
2732 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2733 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2734
2735 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2736
2737 set_bit(STATUS_STATISTICS, &priv->status);
2738
2739 /* Reschedule the statistics timer to occur in
2740 * REG_RECALIB_PERIOD seconds to ensure we get a
2741 * thermal update even if the uCode doesn't give
2742 * us one */
2743 mod_timer(&priv->statistics_periodic, jiffies +
2744 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2745
2746 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2747 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2748 iwl4965_rx_calc_noise(priv);
2749 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2750 queue_work(priv->workqueue, &priv->sensitivity_work);
2751 #endif
2752 }
2753
2754 iwl_leds_background(priv);
2755
2756 /* If the hardware hasn't reported a change in
2757 * temperature then don't bother computing a
2758 * calibrated temperature value */
2759 if (!change)
2760 return;
2761
2762 temp = iwl4965_get_temperature(priv);
2763 if (temp < 0)
2764 return;
2765
2766 if (priv->temperature != temp) {
2767 if (priv->temperature)
2768 IWL_DEBUG_TEMP("Temperature changed "
2769 "from %dC to %dC\n",
2770 KELVIN_TO_CELSIUS(priv->temperature),
2771 KELVIN_TO_CELSIUS(temp));
2772 else
2773 IWL_DEBUG_TEMP("Temperature "
2774 "initialized to %dC\n",
2775 KELVIN_TO_CELSIUS(temp));
2776 }
2777
2778 priv->temperature = temp;
2779 set_bit(STATUS_TEMPERATURE, &priv->status);
2780
2781 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2782 iwl4965_is_temp_calib_needed(priv))
2783 queue_work(priv->workqueue, &priv->txpower_work);
2784 }
2785
2786 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2787 struct sk_buff *skb,
2788 struct iwl4965_rx_phy_res *rx_start,
2789 struct ieee80211_rx_status *stats,
2790 u32 ampdu_status)
2791 {
2792 s8 signal = stats->ssi;
2793 s8 noise = 0;
2794 int rate = stats->rate_idx;
2795 u64 tsf = stats->mactime;
2796 __le16 antenna;
2797 __le16 phy_flags_hw = rx_start->phy_flags;
2798 struct iwl4965_rt_rx_hdr {
2799 struct ieee80211_radiotap_header rt_hdr;
2800 __le64 rt_tsf; /* TSF */
2801 u8 rt_flags; /* radiotap packet flags */
2802 u8 rt_rate; /* rate in 500kb/s */
2803 __le16 rt_channelMHz; /* channel in MHz */
2804 __le16 rt_chbitmask; /* channel bitfield */
2805 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2806 s8 rt_dbmnoise;
2807 u8 rt_antenna; /* antenna number */
2808 } __attribute__ ((packed)) *iwl4965_rt;
2809
2810 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2811 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2812 if (net_ratelimit())
2813 printk(KERN_ERR "not enough headroom [%d] for "
2814 "radiotap head [%zd]\n",
2815 skb_headroom(skb), sizeof(*iwl4965_rt));
2816 return;
2817 }
2818
2819 /* put radiotap header in front of 802.11 header and data */
2820 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2821
2822 /* initialise radiotap header */
2823 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2824 iwl4965_rt->rt_hdr.it_pad = 0;
2825
2826 /* total header + data */
2827 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2828 &iwl4965_rt->rt_hdr.it_len);
2829
2830 /* Indicate all the fields we add to the radiotap header */
2831 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2832 (1 << IEEE80211_RADIOTAP_FLAGS) |
2833 (1 << IEEE80211_RADIOTAP_RATE) |
2834 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2835 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2836 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2837 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2838 &iwl4965_rt->rt_hdr.it_present);
2839
2840 /* Zero the flags, we'll add to them as we go */
2841 iwl4965_rt->rt_flags = 0;
2842
2843 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2844
2845 iwl4965_rt->rt_dbmsignal = signal;
2846 iwl4965_rt->rt_dbmnoise = noise;
2847
2848 /* Convert the channel frequency and set the flags */
2849 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2850 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2851 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2852 IEEE80211_CHAN_5GHZ),
2853 &iwl4965_rt->rt_chbitmask);
2854 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2855 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2856 IEEE80211_CHAN_2GHZ),
2857 &iwl4965_rt->rt_chbitmask);
2858 else /* 802.11g */
2859 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2860 IEEE80211_CHAN_2GHZ),
2861 &iwl4965_rt->rt_chbitmask);
2862
2863 if (rate == -1)
2864 iwl4965_rt->rt_rate = 0;
2865 else
2866 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2867
2868 /*
2869 * "antenna number"
2870 *
2871 * It seems that the antenna field in the phy flags value
2872 * is actually a bitfield. This is undefined by radiotap,
2873 * it wants an actual antenna number but I always get "7"
2874 * for most legacy frames I receive indicating that the
2875 * same frame was received on all three RX chains.
2876 *
2877 * I think this field should be removed in favour of a
2878 * new 802.11n radiotap field "RX chains" that is defined
2879 * as a bitmask.
2880 */
2881 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2882 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2883
2884 /* set the preamble flag if appropriate */
2885 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2886 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2887
2888 stats->flag |= RX_FLAG_RADIOTAP;
2889 }
2890
2891 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2892 {
2893 /* 0 - mgmt, 1 - cnt, 2 - data */
2894 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2895 priv->rx_stats[idx].cnt++;
2896 priv->rx_stats[idx].bytes += len;
2897 }
2898
2899 /*
2900 * returns non-zero if packet should be dropped
2901 */
2902 static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2903 struct ieee80211_hdr *hdr,
2904 u32 decrypt_res,
2905 struct ieee80211_rx_status *stats)
2906 {
2907 u16 fc = le16_to_cpu(hdr->frame_control);
2908
2909 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2910 return 0;
2911
2912 if (!(fc & IEEE80211_FCTL_PROTECTED))
2913 return 0;
2914
2915 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2916 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2917 case RX_RES_STATUS_SEC_TYPE_TKIP:
2918 /* The uCode has got a bad phase 1 Key, pushes the packet.
2919 * Decryption will be done in SW. */
2920 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2921 RX_RES_STATUS_BAD_KEY_TTAK)
2922 break;
2923
2924 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2925 RX_RES_STATUS_BAD_ICV_MIC) {
2926 /* bad ICV, the packet is destroyed since the
2927 * decryption is inplace, drop it */
2928 IWL_DEBUG_RX("Packet destroyed\n");
2929 return -1;
2930 }
2931 case RX_RES_STATUS_SEC_TYPE_WEP:
2932 case RX_RES_STATUS_SEC_TYPE_CCMP:
2933 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2934 RX_RES_STATUS_DECRYPT_OK) {
2935 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2936 stats->flag |= RX_FLAG_DECRYPTED;
2937 }
2938 break;
2939
2940 default:
2941 break;
2942 }
2943 return 0;
2944 }
2945
2946 static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2947 {
2948 u32 decrypt_out = 0;
2949
2950 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2951 RX_RES_STATUS_STATION_FOUND)
2952 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2953 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2954
2955 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2956
2957 /* packet was not encrypted */
2958 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2959 RX_RES_STATUS_SEC_TYPE_NONE)
2960 return decrypt_out;
2961
2962 /* packet was encrypted with unknown alg */
2963 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2964 RX_RES_STATUS_SEC_TYPE_ERR)
2965 return decrypt_out;
2966
2967 /* decryption was not done in HW */
2968 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2969 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2970 return decrypt_out;
2971
2972 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2973
2974 case RX_RES_STATUS_SEC_TYPE_CCMP:
2975 /* alg is CCM: check MIC only */
2976 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2977 /* Bad MIC */
2978 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2979 else
2980 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2981
2982 break;
2983
2984 case RX_RES_STATUS_SEC_TYPE_TKIP:
2985 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2986 /* Bad TTAK */
2987 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2988 break;
2989 }
2990 /* fall through if TTAK OK */
2991 default:
2992 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2993 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2994 else
2995 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2996 break;
2997 };
2998
2999 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3000 decrypt_in, decrypt_out);
3001
3002 return decrypt_out;
3003 }
3004
3005 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
3006 int include_phy,
3007 struct iwl4965_rx_mem_buffer *rxb,
3008 struct ieee80211_rx_status *stats)
3009 {
3010 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
3011 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3012 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3013 struct ieee80211_hdr *hdr;
3014 u16 len;
3015 __le32 *rx_end;
3016 unsigned int skblen;
3017 u32 ampdu_status;
3018 u32 ampdu_status_legacy;
3019
3020 if (!include_phy && priv->last_phy_res[0])
3021 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3022
3023 if (!rx_start) {
3024 IWL_ERROR("MPDU frame without a PHY data\n");
3025 return;
3026 }
3027 if (include_phy) {
3028 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3029 rx_start->cfg_phy_cnt);
3030
3031 len = le16_to_cpu(rx_start->byte_count);
3032
3033 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3034 sizeof(struct iwl4965_rx_phy_res) +
3035 rx_start->cfg_phy_cnt + len);
3036
3037 } else {
3038 struct iwl4965_rx_mpdu_res_start *amsdu =
3039 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3040
3041 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3042 sizeof(struct iwl4965_rx_mpdu_res_start));
3043 len = le16_to_cpu(amsdu->byte_count);
3044 rx_start->byte_count = amsdu->byte_count;
3045 rx_end = (__le32 *) (((u8 *) hdr) + len);
3046 }
3047 if (len > priv->hw_params.max_pkt_size || len < 16) {
3048 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
3049 return;
3050 }
3051
3052 ampdu_status = le32_to_cpu(*rx_end);
3053 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3054
3055 if (!include_phy) {
3056 /* New status scheme, need to translate */
3057 ampdu_status_legacy = ampdu_status;
3058 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3059 }
3060
3061 /* start from MAC */
3062 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3063 skb_put(rxb->skb, len); /* end where data ends */
3064
3065 /* We only process data packets if the interface is open */
3066 if (unlikely(!priv->is_open)) {
3067 IWL_DEBUG_DROP_LIMIT
3068 ("Dropping packet while interface is not open.\n");
3069 return;
3070 }
3071
3072 stats->flag = 0;
3073 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3074
3075 /* in case of HW accelerated crypto and bad decryption, drop */
3076 if (!priv->hw_params.sw_crypto &&
3077 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3078 return;
3079
3080 if (priv->add_radiotap)
3081 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3082
3083 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
3084 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3085 priv->alloc_rxb_skb--;
3086 rxb->skb = NULL;
3087 }
3088
3089 /* Calc max signal level (dBm) among 3 possible receivers */
3090 static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3091 {
3092 /* data from PHY/DSP regarding signal strength, etc.,
3093 * contents are always there, not configurable by host. */
3094 struct iwl4965_rx_non_cfg_phy *ncphy =
3095 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3096 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3097 >> IWL_AGC_DB_POS;
3098
3099 u32 valid_antennae =
3100 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3101 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3102 u8 max_rssi = 0;
3103 u32 i;
3104
3105 /* Find max rssi among 3 possible receivers.
3106 * These values are measured by the digital signal processor (DSP).
3107 * They should stay fairly constant even as the signal strength varies,
3108 * if the radio's automatic gain control (AGC) is working right.
3109 * AGC value (see below) will provide the "interesting" info. */
3110 for (i = 0; i < 3; i++)
3111 if (valid_antennae & (1 << i))
3112 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3113
3114 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3115 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3116 max_rssi, agc);
3117
3118 /* dBm = max_rssi dB - agc dB - constant.
3119 * Higher AGC (higher radio gain) means lower signal. */
3120 return (max_rssi - agc - IWL_RSSI_OFFSET);
3121 }
3122
3123 #ifdef CONFIG_IWL4965_HT
3124
3125 void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3126 struct ieee80211_ht_info *ht_info,
3127 enum ieee80211_band band)
3128 {
3129 ht_info->cap = 0;
3130 memset(ht_info->supp_mcs_set, 0, 16);
3131
3132 ht_info->ht_supported = 1;
3133
3134 if (priv->hw_params.fat_channel & BIT(band)) {
3135 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3136 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3137 ht_info->supp_mcs_set[4] = 0x01;
3138 }
3139 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3140 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3141 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3142 (IWL_MIMO_PS_NONE << 2));
3143
3144 if (priv->cfg->mod_params->amsdu_size_8K)
3145 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3146
3147 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3148 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3149
3150 ht_info->supp_mcs_set[0] = 0xFF;
3151 ht_info->supp_mcs_set[1] = 0xFF;
3152 }
3153 #endif /* CONFIG_IWL4965_HT */
3154
3155 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
3156 {
3157 unsigned long flags;
3158
3159 spin_lock_irqsave(&priv->sta_lock, flags);
3160 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3161 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3162 priv->stations[sta_id].sta.sta.modify_mask = 0;
3163 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3164 spin_unlock_irqrestore(&priv->sta_lock, flags);
3165
3166 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3167 }
3168
3169 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
3170 {
3171 /* FIXME: need locking over ps_status ??? */
3172 u8 sta_id = iwl_find_station(priv, addr);
3173
3174 if (sta_id != IWL_INVALID_STATION) {
3175 u8 sta_awake = priv->stations[sta_id].
3176 ps_status == STA_PS_STATUS_WAKE;
3177
3178 if (sta_awake && ps_bit)
3179 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3180 else if (!sta_awake && !ps_bit) {
3181 iwl4965_sta_modify_ps_wake(priv, sta_id);
3182 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3183 }
3184 }
3185 }
3186 #ifdef CONFIG_IWLWIFI_DEBUG
3187
3188 /**
3189 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3190 *
3191 * You may hack this function to show different aspects of received frames,
3192 * including selective frame dumps.
3193 * group100 parameter selects whether to show 1 out of 100 good frames.
3194 *
3195 * TODO: This was originally written for 3945, need to audit for
3196 * proper operation with 4965.
3197 */
3198 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3199 struct iwl4965_rx_packet *pkt,
3200 struct ieee80211_hdr *header, int group100)
3201 {
3202 u32 to_us;
3203 u32 print_summary = 0;
3204 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3205 u32 hundred = 0;
3206 u32 dataframe = 0;
3207 u16 fc;
3208 u16 seq_ctl;
3209 u16 channel;
3210 u16 phy_flags;
3211 int rate_sym;
3212 u16 length;
3213 u16 status;
3214 u16 bcn_tmr;
3215 u32 tsf_low;
3216 u64 tsf;
3217 u8 rssi;
3218 u8 agc;
3219 u16 sig_avg;
3220 u16 noise_diff;
3221 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3222 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3223 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3224 u8 *data = IWL_RX_DATA(pkt);
3225
3226 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3227 return;
3228
3229 /* MAC header */
3230 fc = le16_to_cpu(header->frame_control);
3231 seq_ctl = le16_to_cpu(header->seq_ctrl);
3232
3233 /* metadata */
3234 channel = le16_to_cpu(rx_hdr->channel);
3235 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3236 rate_sym = rx_hdr->rate;
3237 length = le16_to_cpu(rx_hdr->len);
3238
3239 /* end-of-frame status and timestamp */
3240 status = le32_to_cpu(rx_end->status);
3241 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3242 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3243 tsf = le64_to_cpu(rx_end->timestamp);
3244
3245 /* signal statistics */
3246 rssi = rx_stats->rssi;
3247 agc = rx_stats->agc;
3248 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3249 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3250
3251 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3252
3253 /* if data frame is to us and all is good,
3254 * (optionally) print summary for only 1 out of every 100 */
3255 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3256 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3257 dataframe = 1;
3258 if (!group100)
3259 print_summary = 1; /* print each frame */
3260 else if (priv->framecnt_to_us < 100) {
3261 priv->framecnt_to_us++;
3262 print_summary = 0;
3263 } else {
3264 priv->framecnt_to_us = 0;
3265 print_summary = 1;
3266 hundred = 1;
3267 }
3268 } else {
3269 /* print summary for all other frames */
3270 print_summary = 1;
3271 }
3272
3273 if (print_summary) {
3274 char *title;
3275 int rate_idx;
3276 u32 bitrate;
3277
3278 if (hundred)
3279 title = "100Frames";
3280 else if (fc & IEEE80211_FCTL_RETRY)
3281 title = "Retry";
3282 else if (ieee80211_is_assoc_response(fc))
3283 title = "AscRsp";
3284 else if (ieee80211_is_reassoc_response(fc))
3285 title = "RasRsp";
3286 else if (ieee80211_is_probe_response(fc)) {
3287 title = "PrbRsp";
3288 print_dump = 1; /* dump frame contents */
3289 } else if (ieee80211_is_beacon(fc)) {
3290 title = "Beacon";
3291 print_dump = 1; /* dump frame contents */
3292 } else if (ieee80211_is_atim(fc))
3293 title = "ATIM";
3294 else if (ieee80211_is_auth(fc))
3295 title = "Auth";
3296 else if (ieee80211_is_deauth(fc))
3297 title = "DeAuth";
3298 else if (ieee80211_is_disassoc(fc))
3299 title = "DisAssoc";
3300 else
3301 title = "Frame";
3302
3303 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3304 if (unlikely(rate_idx == -1))
3305 bitrate = 0;
3306 else
3307 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3308
3309 /* print frame summary.
3310 * MAC addresses show just the last byte (for brevity),
3311 * but you can hack it to show more, if you'd like to. */
3312 if (dataframe)
3313 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3314 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3315 title, fc, header->addr1[5],
3316 length, rssi, channel, bitrate);
3317 else {
3318 /* src/dst addresses assume managed mode */
3319 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3320 "src=0x%02x, rssi=%u, tim=%lu usec, "
3321 "phy=0x%02x, chnl=%d\n",
3322 title, fc, header->addr1[5],
3323 header->addr3[5], rssi,
3324 tsf_low - priv->scan_start_tsf,
3325 phy_flags, channel);
3326 }
3327 }
3328 if (print_dump)
3329 iwl_print_hex_dump(IWL_DL_RX, data, length);
3330 }
3331 #else
3332 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3333 struct iwl4965_rx_packet *pkt,
3334 struct ieee80211_hdr *header,
3335 int group100)
3336 {
3337 }
3338 #endif
3339
3340
3341
3342 /* Called for REPLY_RX (legacy ABG frames), or
3343 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3344 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3345 struct iwl4965_rx_mem_buffer *rxb)
3346 {
3347 struct ieee80211_hdr *header;
3348 struct ieee80211_rx_status rx_status;
3349 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3350 /* Use phy data (Rx signal strength, etc.) contained within
3351 * this rx packet for legacy frames,
3352 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3353 int include_phy = (pkt->hdr.cmd == REPLY_RX);
3354 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3355 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3356 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3357 __le32 *rx_end;
3358 unsigned int len = 0;
3359 u16 fc;
3360 u8 network_packet;
3361
3362 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3363 rx_status.freq =
3364 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3365 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3366 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3367 rx_status.rate_idx =
3368 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3369 if (rx_status.band == IEEE80211_BAND_5GHZ)
3370 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3371
3372 rx_status.antenna = 0;
3373 rx_status.flag = 0;
3374
3375 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3376 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3377 rx_start->cfg_phy_cnt);
3378 return;
3379 }
3380
3381 if (!include_phy) {
3382 if (priv->last_phy_res[0])
3383 rx_start = (struct iwl4965_rx_phy_res *)
3384 &priv->last_phy_res[1];
3385 else
3386 rx_start = NULL;
3387 }
3388
3389 if (!rx_start) {
3390 IWL_ERROR("MPDU frame without a PHY data\n");
3391 return;
3392 }
3393
3394 if (include_phy) {
3395 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3396 + rx_start->cfg_phy_cnt);
3397
3398 len = le16_to_cpu(rx_start->byte_count);
3399 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3400 sizeof(struct iwl4965_rx_phy_res) + len);
3401 } else {
3402 struct iwl4965_rx_mpdu_res_start *amsdu =
3403 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3404
3405 header = (void *)(pkt->u.raw +
3406 sizeof(struct iwl4965_rx_mpdu_res_start));
3407 len = le16_to_cpu(amsdu->byte_count);
3408 rx_end = (__le32 *) (pkt->u.raw +
3409 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3410 }
3411
3412 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3413 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3414 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3415 le32_to_cpu(*rx_end));
3416 return;
3417 }
3418
3419 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3420
3421 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3422 rx_status.ssi = iwl4965_calc_rssi(rx_start);
3423
3424 /* Meaningful noise values are available only from beacon statistics,
3425 * which are gathered only when associated, and indicate noise
3426 * only for the associated network channel ...
3427 * Ignore these noise values while scanning (other channels) */
3428 if (iwl_is_associated(priv) &&
3429 !test_bit(STATUS_SCANNING, &priv->status)) {
3430 rx_status.noise = priv->last_rx_noise;
3431 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3432 rx_status.noise);
3433 } else {
3434 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3435 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3436 }
3437
3438 /* Reset beacon noise level if not associated. */
3439 if (!iwl_is_associated(priv))
3440 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3441
3442 /* Set "1" to report good data frames in groups of 100 */
3443 /* FIXME: need to optimze the call: */
3444 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3445
3446 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3447 rx_status.ssi, rx_status.noise, rx_status.signal,
3448 (unsigned long long)rx_status.mactime);
3449
3450 network_packet = iwl4965_is_network_packet(priv, header);
3451 if (network_packet) {
3452 priv->last_rx_rssi = rx_status.ssi;
3453 priv->last_beacon_time = priv->ucode_beacon_time;
3454 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3455 }
3456
3457 fc = le16_to_cpu(header->frame_control);
3458 switch (fc & IEEE80211_FCTL_FTYPE) {
3459 case IEEE80211_FTYPE_MGMT:
3460 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3461 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3462 header->addr2);
3463 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3464 break;
3465
3466 case IEEE80211_FTYPE_CTL:
3467 #ifdef CONFIG_IWL4965_HT
3468 switch (fc & IEEE80211_FCTL_STYPE) {
3469 case IEEE80211_STYPE_BACK_REQ:
3470 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3471 iwl4965_handle_data_packet(priv, 0, include_phy,
3472 rxb, &rx_status);
3473 break;
3474 default:
3475 break;
3476 }
3477 #endif
3478 break;
3479
3480 case IEEE80211_FTYPE_DATA: {
3481 DECLARE_MAC_BUF(mac1);
3482 DECLARE_MAC_BUF(mac2);
3483 DECLARE_MAC_BUF(mac3);
3484
3485 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3486 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3487 header->addr2);
3488
3489 if (unlikely(!network_packet))
3490 IWL_DEBUG_DROP("Dropping (non network): "
3491 "%s, %s, %s\n",
3492 print_mac(mac1, header->addr1),
3493 print_mac(mac2, header->addr2),
3494 print_mac(mac3, header->addr3));
3495 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3496 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3497 print_mac(mac1, header->addr1),
3498 print_mac(mac2, header->addr2),
3499 print_mac(mac3, header->addr3));
3500 else
3501 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3502 &rx_status);
3503 break;
3504 }
3505 default:
3506 break;
3507
3508 }
3509 }
3510
3511 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3512 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3513 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3514 struct iwl4965_rx_mem_buffer *rxb)
3515 {
3516 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3517 priv->last_phy_res[0] = 1;
3518 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3519 sizeof(struct iwl4965_rx_phy_res));
3520 }
3521 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3522 struct iwl4965_rx_mem_buffer *rxb)
3523
3524 {
3525 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3526 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3527 struct iwl4965_missed_beacon_notif *missed_beacon;
3528
3529 missed_beacon = &pkt->u.missed_beacon;
3530 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3531 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3532 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3533 le32_to_cpu(missed_beacon->total_missed_becons),
3534 le32_to_cpu(missed_beacon->num_recvd_beacons),
3535 le32_to_cpu(missed_beacon->num_expected_beacons));
3536 if (!test_bit(STATUS_SCANNING, &priv->status))
3537 iwl_init_sensitivity(priv);
3538 }
3539 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3540 }
3541 #ifdef CONFIG_IWL4965_HT
3542
3543 /**
3544 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3545 */
3546 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3547 int sta_id, int tid)
3548 {
3549 unsigned long flags;
3550
3551 /* Remove "disable" flag, to enable Tx for this TID */
3552 spin_lock_irqsave(&priv->sta_lock, flags);
3553 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3554 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3555 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3556 spin_unlock_irqrestore(&priv->sta_lock, flags);
3557
3558 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3559 }
3560
3561 /**
3562 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3563 *
3564 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3565 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3566 */
3567 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3568 struct iwl4965_ht_agg *agg,
3569 struct iwl4965_compressed_ba_resp*
3570 ba_resp)
3571
3572 {
3573 int i, sh, ack;
3574 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3575 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3576 u64 bitmap;
3577 int successes = 0;
3578 struct ieee80211_tx_status *tx_status;
3579
3580 if (unlikely(!agg->wait_for_ba)) {
3581 IWL_ERROR("Received BA when not expected\n");
3582 return -EINVAL;
3583 }
3584
3585 /* Mark that the expected block-ack response arrived */
3586 agg->wait_for_ba = 0;
3587 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3588
3589 /* Calculate shift to align block-ack bits with our Tx window bits */
3590 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3591 if (sh < 0) /* tbw something is wrong with indices */
3592 sh += 0x100;
3593
3594 /* don't use 64-bit values for now */
3595 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3596
3597 if (agg->frame_count > (64 - sh)) {
3598 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3599 return -1;
3600 }
3601
3602 /* check for success or failure according to the
3603 * transmitted bitmap and block-ack bitmap */
3604 bitmap &= agg->bitmap;
3605
3606 /* For each frame attempted in aggregation,
3607 * update driver's record of tx frame's status. */
3608 for (i = 0; i < agg->frame_count ; i++) {
3609 ack = bitmap & (1 << i);
3610 successes += !!ack;
3611 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3612 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3613 agg->start_idx + i);
3614 }
3615
3616 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3617 tx_status->flags = IEEE80211_TX_STATUS_ACK;
3618 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3619 tx_status->ampdu_ack_map = successes;
3620 tx_status->ampdu_ack_len = agg->frame_count;
3621 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3622 &tx_status->control);
3623
3624 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3625
3626 return 0;
3627 }
3628
3629 /**
3630 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3631 */
3632 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3633 u16 txq_id)
3634 {
3635 /* Simply stop the queue, but don't change any configuration;
3636 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3637 iwl_write_prph(priv,
3638 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3639 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3640 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3641 }
3642
3643 /**
3644 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3645 * priv->lock must be held by the caller
3646 */
3647 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3648 u16 ssn_idx, u8 tx_fifo)
3649 {
3650 int ret = 0;
3651
3652 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3653 IWL_WARNING("queue number too small: %d, must be > %d\n",
3654 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3655 return -EINVAL;
3656 }
3657
3658 ret = iwl_grab_nic_access(priv);
3659 if (ret)
3660 return ret;
3661
3662 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3663
3664 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3665
3666 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3667 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3668 /* supposes that ssn_idx is valid (!= 0xFFF) */
3669 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3670
3671 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3672 iwl4965_txq_ctx_deactivate(priv, txq_id);
3673 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3674
3675 iwl_release_nic_access(priv);
3676
3677 return 0;
3678 }
3679
3680 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3681 u8 tid, int txq_id)
3682 {
3683 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3684 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3685 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3686
3687 switch (priv->stations[sta_id].tid[tid].agg.state) {
3688 case IWL_EMPTYING_HW_QUEUE_DELBA:
3689 /* We are reclaiming the last packet of the */
3690 /* aggregated HW queue */
3691 if (txq_id == tid_data->agg.txq_id &&
3692 q->read_ptr == q->write_ptr) {
3693 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3694 int tx_fifo = default_tid_to_tx_fifo[tid];
3695 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3696 iwl4965_tx_queue_agg_disable(priv, txq_id,
3697 ssn, tx_fifo);
3698 tid_data->agg.state = IWL_AGG_OFF;
3699 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3700 }
3701 break;
3702 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3703 /* We are reclaiming the last packet of the queue */
3704 if (tid_data->tfds_in_queue == 0) {
3705 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3706 tid_data->agg.state = IWL_AGG_ON;
3707 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3708 }
3709 break;
3710 }
3711 return 0;
3712 }
3713
3714 /**
3715 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3716 * @index -- current index
3717 * @n_bd -- total number of entries in queue (s/b power of 2)
3718 */
3719 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3720 {
3721 return (index == 0) ? n_bd - 1 : index - 1;
3722 }
3723
3724 /**
3725 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3726 *
3727 * Handles block-acknowledge notification from device, which reports success
3728 * of frames sent via aggregation.
3729 */
3730 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3731 struct iwl4965_rx_mem_buffer *rxb)
3732 {
3733 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3734 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3735 int index;
3736 struct iwl4965_tx_queue *txq = NULL;
3737 struct iwl4965_ht_agg *agg;
3738 DECLARE_MAC_BUF(mac);
3739
3740 /* "flow" corresponds to Tx queue */
3741 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3742
3743 /* "ssn" is start of block-ack Tx window, corresponds to index
3744 * (in Tx queue's circular buffer) of first TFD/frame in window */
3745 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3746
3747 if (scd_flow >= priv->hw_params.max_txq_num) {
3748 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3749 return;
3750 }
3751
3752 txq = &priv->txq[scd_flow];
3753 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3754
3755 /* Find index just before block-ack window */
3756 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3757
3758 /* TODO: Need to get this copy more safely - now good for debug */
3759
3760 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3761 "sta_id = %d\n",
3762 agg->wait_for_ba,
3763 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3764 ba_resp->sta_id);
3765 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3766 "%d, scd_ssn = %d\n",
3767 ba_resp->tid,
3768 ba_resp->seq_ctl,
3769 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3770 ba_resp->scd_flow,
3771 ba_resp->scd_ssn);
3772 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3773 agg->start_idx,
3774 (unsigned long long)agg->bitmap);
3775
3776 /* Update driver's record of ACK vs. not for each frame in window */
3777 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3778
3779 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3780 * block-ack window (we assume that they've been successfully
3781 * transmitted ... if not, it's too late anyway). */
3782 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3783 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3784 priv->stations[ba_resp->sta_id].
3785 tid[ba_resp->tid].tfds_in_queue -= freed;
3786 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3787 priv->mac80211_registered &&
3788 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3789 ieee80211_wake_queue(priv->hw, scd_flow);
3790 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3791 ba_resp->tid, scd_flow);
3792 }
3793 }
3794
3795 /**
3796 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3797 */
3798 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3799 u16 txq_id)
3800 {
3801 u32 tbl_dw_addr;
3802 u32 tbl_dw;
3803 u16 scd_q2ratid;
3804
3805 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3806
3807 tbl_dw_addr = priv->scd_base_addr +
3808 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3809
3810 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3811
3812 if (txq_id & 0x1)
3813 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3814 else
3815 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3816
3817 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3818
3819 return 0;
3820 }
3821
3822
3823 /**
3824 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3825 *
3826 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3827 * i.e. it must be one of the higher queues used for aggregation
3828 */
3829 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3830 int tx_fifo, int sta_id, int tid,
3831 u16 ssn_idx)
3832 {
3833 unsigned long flags;
3834 int rc;
3835 u16 ra_tid;
3836
3837 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3838 IWL_WARNING("queue number too small: %d, must be > %d\n",
3839 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3840
3841 ra_tid = BUILD_RAxTID(sta_id, tid);
3842
3843 /* Modify device's station table to Tx this TID */
3844 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3845
3846 spin_lock_irqsave(&priv->lock, flags);
3847 rc = iwl_grab_nic_access(priv);
3848 if (rc) {
3849 spin_unlock_irqrestore(&priv->lock, flags);
3850 return rc;
3851 }
3852
3853 /* Stop this Tx queue before configuring it */
3854 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3855
3856 /* Map receiver-address / traffic-ID to this queue */
3857 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3858
3859 /* Set this queue as a chain-building queue */
3860 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3861
3862 /* Place first TFD at index corresponding to start sequence number.
3863 * Assumes that ssn_idx is valid (!= 0xFFF) */
3864 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3865 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3866 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3867
3868 /* Set up Tx window size and frame limit for this queue */
3869 iwl_write_targ_mem(priv,
3870 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3871 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3872 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3873
3874 iwl_write_targ_mem(priv, priv->scd_base_addr +
3875 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3876 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3877 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3878
3879 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3880
3881 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3882 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3883
3884 iwl_release_nic_access(priv);
3885 spin_unlock_irqrestore(&priv->lock, flags);
3886
3887 return 0;
3888 }
3889
3890 #endif /* CONFIG_IWL4965_HT */
3891
3892 /**
3893 * iwl4965_add_station - Initialize a station's hardware rate table
3894 *
3895 * The uCode's station table contains a table of fallback rates
3896 * for automatic fallback during transmission.
3897 *
3898 * NOTE: This sets up a default set of values. These will be replaced later
3899 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3900 * rc80211_simple.
3901 *
3902 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3903 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3904 * which requires station table entry to exist).
3905 */
3906 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3907 {
3908 int i, r;
3909 struct iwl_link_quality_cmd link_cmd = {
3910 .reserved1 = 0,
3911 };
3912 u16 rate_flags;
3913
3914 /* Set up the rate scaling to start at selected rate, fall back
3915 * all the way down to 1M in IEEE order, and then spin on 1M */
3916 if (is_ap)
3917 r = IWL_RATE_54M_INDEX;
3918 else if (priv->band == IEEE80211_BAND_5GHZ)
3919 r = IWL_RATE_6M_INDEX;
3920 else
3921 r = IWL_RATE_1M_INDEX;
3922
3923 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3924 rate_flags = 0;
3925 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3926 rate_flags |= RATE_MCS_CCK_MSK;
3927
3928 /* Use Tx antenna B only */
3929 rate_flags |= RATE_MCS_ANT_B_MSK;
3930 rate_flags &= ~RATE_MCS_ANT_A_MSK;
3931
3932 link_cmd.rs_table[i].rate_n_flags =
3933 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3934 r = iwl4965_get_prev_ieee_rate(r);
3935 }
3936
3937 link_cmd.general_params.single_stream_ant_msk = 2;
3938 link_cmd.general_params.dual_stream_ant_msk = 3;
3939 link_cmd.agg_params.agg_dis_start_th = 3;
3940 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3941
3942 /* Update the rate scaling for control frame Tx to AP */
3943 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3944
3945 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3946 sizeof(link_cmd), &link_cmd, NULL);
3947 }
3948
3949 #ifdef CONFIG_IWL4965_HT
3950
3951 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3952 enum ieee80211_band band,
3953 u16 channel, u8 extension_chan_offset)
3954 {
3955 const struct iwl_channel_info *ch_info;
3956
3957 ch_info = iwl_get_channel_info(priv, band, channel);
3958 if (!is_channel_valid(ch_info))
3959 return 0;
3960
3961 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3962 return 0;
3963
3964 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3965 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3966 return 1;
3967
3968 return 0;
3969 }
3970
3971 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3972 struct ieee80211_ht_info *sta_ht_inf)
3973 {
3974 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3975
3976 if ((!iwl_ht_conf->is_ht) ||
3977 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3978 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3979 return 0;
3980
3981 if (sta_ht_inf) {
3982 if ((!sta_ht_inf->ht_supported) ||
3983 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3984 return 0;
3985 }
3986
3987 return (iwl4965_is_channel_extension(priv, priv->band,
3988 iwl_ht_conf->control_channel,
3989 iwl_ht_conf->extension_chan_offset));
3990 }
3991
3992 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
3993 {
3994 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
3995 u32 val;
3996
3997 if (!ht_info->is_ht)
3998 return;
3999
4000 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
4001 if (iwl4965_is_fat_tx_allowed(priv, NULL))
4002 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4003 else
4004 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4005 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4006
4007 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4008 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4009 le16_to_cpu(rxon->channel),
4010 ht_info->control_channel);
4011 rxon->channel = cpu_to_le16(ht_info->control_channel);
4012 return;
4013 }
4014
4015 /* Note: control channel is opposite of extension channel */
4016 switch (ht_info->extension_chan_offset) {
4017 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4018 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4019 break;
4020 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4021 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4022 break;
4023 case IWL_EXT_CHANNEL_OFFSET_NONE:
4024 default:
4025 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4026 break;
4027 }
4028
4029 val = ht_info->ht_protection;
4030
4031 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4032
4033 iwl4965_set_rxon_chain(priv);
4034
4035 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4036 "rxon flags 0x%X operation mode :0x%X "
4037 "extension channel offset 0x%x "
4038 "control chan %d\n",
4039 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4040 le32_to_cpu(rxon->flags), ht_info->ht_protection,
4041 ht_info->extension_chan_offset,
4042 ht_info->control_channel);
4043 return;
4044 }
4045
4046 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
4047 struct ieee80211_ht_info *sta_ht_inf)
4048 {
4049 __le32 sta_flags;
4050 u8 mimo_ps_mode;
4051
4052 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
4053 goto done;
4054
4055 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4056
4057 sta_flags = priv->stations[index].sta.station_flags;
4058
4059 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4060
4061 switch (mimo_ps_mode) {
4062 case WLAN_HT_CAP_MIMO_PS_STATIC:
4063 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4064 break;
4065 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
4066 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
4067 break;
4068 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4069 break;
4070 default:
4071 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4072 break;
4073 }
4074
4075 sta_flags |= cpu_to_le32(
4076 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
4077
4078 sta_flags |= cpu_to_le32(
4079 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
4080
4081 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
4082 sta_flags |= STA_FLG_FAT_EN_MSK;
4083 else
4084 sta_flags &= ~STA_FLG_FAT_EN_MSK;
4085
4086 priv->stations[index].sta.station_flags = sta_flags;
4087 done:
4088 return;
4089 }
4090
4091 static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4092 const u8 *addr, int tid, u16 ssn)
4093 {
4094 unsigned long flags;
4095 int sta_id;
4096
4097 sta_id = iwl_find_station(priv, addr);
4098 if (sta_id == IWL_INVALID_STATION)
4099 return -ENXIO;
4100
4101 spin_lock_irqsave(&priv->sta_lock, flags);
4102 priv->stations[sta_id].sta.station_flags_msk = 0;
4103 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4104 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4105 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4106 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4107 spin_unlock_irqrestore(&priv->sta_lock, flags);
4108
4109 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4110 CMD_ASYNC);
4111 }
4112
4113 static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4114 const u8 *addr, int tid)
4115 {
4116 unsigned long flags;
4117 int sta_id;
4118
4119 sta_id = iwl_find_station(priv, addr);
4120 if (sta_id == IWL_INVALID_STATION)
4121 return -ENXIO;
4122
4123 spin_lock_irqsave(&priv->sta_lock, flags);
4124 priv->stations[sta_id].sta.station_flags_msk = 0;
4125 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4126 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4127 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4128 spin_unlock_irqrestore(&priv->sta_lock, flags);
4129
4130 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4131 CMD_ASYNC);
4132 }
4133
4134 /*
4135 * Find first available (lowest unused) Tx Queue, mark it "active".
4136 * Called only when finding queue for aggregation.
4137 * Should never return anything < 7, because they should already
4138 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4139 */
4140 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
4141 {
4142 int txq_id;
4143
4144 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
4145 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4146 return txq_id;
4147 return -1;
4148 }
4149
4150 static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4151 u16 tid, u16 *start_seq_num)
4152 {
4153 struct iwl_priv *priv = hw->priv;
4154 int sta_id;
4155 int tx_fifo;
4156 int txq_id;
4157 int ssn = -1;
4158 int ret = 0;
4159 unsigned long flags;
4160 struct iwl4965_tid_data *tid_data;
4161 DECLARE_MAC_BUF(mac);
4162
4163 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4164 tx_fifo = default_tid_to_tx_fifo[tid];
4165 else
4166 return -EINVAL;
4167
4168 IWL_WARNING("%s on ra = %s tid = %d\n",
4169 __func__, print_mac(mac, ra), tid);
4170
4171 sta_id = iwl_find_station(priv, ra);
4172 if (sta_id == IWL_INVALID_STATION)
4173 return -ENXIO;
4174
4175 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4176 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4177 return -ENXIO;
4178 }
4179
4180 txq_id = iwl4965_txq_ctx_activate_free(priv);
4181 if (txq_id == -1)
4182 return -ENXIO;
4183
4184 spin_lock_irqsave(&priv->sta_lock, flags);
4185 tid_data = &priv->stations[sta_id].tid[tid];
4186 ssn = SEQ_TO_SN(tid_data->seq_number);
4187 tid_data->agg.txq_id = txq_id;
4188 spin_unlock_irqrestore(&priv->sta_lock, flags);
4189
4190 *start_seq_num = ssn;
4191 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4192 sta_id, tid, ssn);
4193 if (ret)
4194 return ret;
4195
4196 ret = 0;
4197 if (tid_data->tfds_in_queue == 0) {
4198 printk(KERN_ERR "HW queue is empty\n");
4199 tid_data->agg.state = IWL_AGG_ON;
4200 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
4201 } else {
4202 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4203 tid_data->tfds_in_queue);
4204 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4205 }
4206 return ret;
4207 }
4208
4209 static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
4210 {
4211 struct iwl_priv *priv = hw->priv;
4212 int tx_fifo_id, txq_id, sta_id, ssn = -1;
4213 struct iwl4965_tid_data *tid_data;
4214 int ret, write_ptr, read_ptr;
4215 unsigned long flags;
4216 DECLARE_MAC_BUF(mac);
4217
4218 if (!ra) {
4219 IWL_ERROR("ra = NULL\n");
4220 return -EINVAL;
4221 }
4222
4223 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4224 tx_fifo_id = default_tid_to_tx_fifo[tid];
4225 else
4226 return -EINVAL;
4227
4228 sta_id = iwl_find_station(priv, ra);
4229
4230 if (sta_id == IWL_INVALID_STATION)
4231 return -ENXIO;
4232
4233 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4234 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4235
4236 tid_data = &priv->stations[sta_id].tid[tid];
4237 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4238 txq_id = tid_data->agg.txq_id;
4239 write_ptr = priv->txq[txq_id].q.write_ptr;
4240 read_ptr = priv->txq[txq_id].q.read_ptr;
4241
4242 /* The queue is not empty */
4243 if (write_ptr != read_ptr) {
4244 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4245 priv->stations[sta_id].tid[tid].agg.state =
4246 IWL_EMPTYING_HW_QUEUE_DELBA;
4247 return 0;
4248 }
4249
4250 IWL_DEBUG_HT("HW queue is empty\n");
4251 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4252
4253 spin_lock_irqsave(&priv->lock, flags);
4254 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4255 spin_unlock_irqrestore(&priv->lock, flags);
4256
4257 if (ret)
4258 return ret;
4259
4260 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
4261
4262 return 0;
4263 }
4264
4265 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4266 enum ieee80211_ampdu_mlme_action action,
4267 const u8 *addr, u16 tid, u16 *ssn)
4268 {
4269 struct iwl_priv *priv = hw->priv;
4270 DECLARE_MAC_BUF(mac);
4271
4272 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4273 print_mac(mac, addr), tid);
4274
4275 switch (action) {
4276 case IEEE80211_AMPDU_RX_START:
4277 IWL_DEBUG_HT("start Rx\n");
4278 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
4279 case IEEE80211_AMPDU_RX_STOP:
4280 IWL_DEBUG_HT("stop Rx\n");
4281 return iwl4965_rx_agg_stop(priv, addr, tid);
4282 case IEEE80211_AMPDU_TX_START:
4283 IWL_DEBUG_HT("start Tx\n");
4284 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
4285 case IEEE80211_AMPDU_TX_STOP:
4286 IWL_DEBUG_HT("stop Tx\n");
4287 return iwl4965_tx_agg_stop(hw, addr, tid);
4288 default:
4289 IWL_DEBUG_HT("unknown\n");
4290 return -EINVAL;
4291 break;
4292 }
4293 return 0;
4294 }
4295
4296 #endif /* CONFIG_IWL4965_HT */
4297
4298 /* Set up 4965-specific Rx frame reply handlers */
4299 void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
4300 {
4301 /* Legacy Rx frames */
4302 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4303
4304 /* High-throughput (HT) Rx frames */
4305 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4306 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4307
4308 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4309 iwl4965_rx_missed_beacon_notif;
4310
4311 #ifdef CONFIG_IWL4965_HT
4312 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4313 #endif /* CONFIG_IWL4965_HT */
4314 }
4315
4316 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4317 {
4318 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4319 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4320 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4321 #endif
4322 init_timer(&priv->statistics_periodic);
4323 priv->statistics_periodic.data = (unsigned long)priv;
4324 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4325 }
4326
4327 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4328 {
4329 del_timer_sync(&priv->statistics_periodic);
4330
4331 cancel_delayed_work(&priv->init_alive_start);
4332 }
4333
4334
4335 static struct iwl_hcmd_ops iwl4965_hcmd = {
4336 .rxon_assoc = iwl4965_send_rxon_assoc,
4337 };
4338
4339 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4340 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4341 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4342 .chain_noise_reset = iwl4965_chain_noise_reset,
4343 .gain_computation = iwl4965_gain_computation,
4344 #endif
4345 };
4346
4347 static struct iwl_lib_ops iwl4965_lib = {
4348 .init_drv = iwl4965_init_drv,
4349 .set_hw_params = iwl4965_hw_set_hw_params,
4350 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4351 .hw_nic_init = iwl4965_hw_nic_init,
4352 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4353 .alive_notify = iwl4965_alive_notify,
4354 .load_ucode = iwl4965_load_bsm,
4355 .apm_ops = {
4356 .set_pwr_src = iwl4965_set_pwr_src,
4357 },
4358 .eeprom_ops = {
4359 .regulatory_bands = {
4360 EEPROM_REGULATORY_BAND_1_CHANNELS,
4361 EEPROM_REGULATORY_BAND_2_CHANNELS,
4362 EEPROM_REGULATORY_BAND_3_CHANNELS,
4363 EEPROM_REGULATORY_BAND_4_CHANNELS,
4364 EEPROM_REGULATORY_BAND_5_CHANNELS,
4365 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4366 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4367 },
4368 .verify_signature = iwlcore_eeprom_verify_signature,
4369 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4370 .release_semaphore = iwlcore_eeprom_release_semaphore,
4371 .query_addr = iwlcore_eeprom_query_addr,
4372 },
4373 .radio_kill_sw = iwl4965_radio_kill_sw,
4374 .set_power = iwl4965_set_power,
4375 .update_chain_flags = iwl4965_update_chain_flags,
4376 };
4377
4378 static struct iwl_ops iwl4965_ops = {
4379 .lib = &iwl4965_lib,
4380 .hcmd = &iwl4965_hcmd,
4381 .utils = &iwl4965_hcmd_utils,
4382 };
4383
4384 struct iwl_cfg iwl4965_agn_cfg = {
4385 .name = "4965AGN",
4386 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4387 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4388 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
4389 .ops = &iwl4965_ops,
4390 .mod_params = &iwl4965_mod_params,
4391 };
4392
4393 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4394 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4395 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4396 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4397 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4398 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4399 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4400 MODULE_PARM_DESC(debug, "debug output mask");
4401 module_param_named(
4402 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4403 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4404
4405 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4406 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4407
4408 /* QoS */
4409 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4410 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4411 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4412 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4413
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