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[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-4965.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47
48 /* module parameters */
49 static struct iwl_mod_params iwl4965_mod_params = {
50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54 };
55
56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
57
58 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
61 IWL_RATE_MIMO2_##s##M_PLCP,\
62 IWL_RATE_MIMO3_##s##M_PLCP,\
63 IWL_RATE_##r##M_IEEE, \
64 IWL_RATE_##ip##M_INDEX, \
65 IWL_RATE_##in##M_INDEX, \
66 IWL_RATE_##rp##M_INDEX, \
67 IWL_RATE_##rn##M_INDEX, \
68 IWL_RATE_##pp##M_INDEX, \
69 IWL_RATE_##np##M_INDEX }
70
71 /*
72 * Parameter order:
73 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
74 *
75 * If there isn't a valid next or previous rate then INV is used which
76 * maps to IWL_RATE_INVALID
77 *
78 */
79 const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
80 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
81 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
82 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
83 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
84 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
85 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
86 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
87 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
88 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
89 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
90 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
91 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
92 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
93 /* FIXME:RS: ^^ should be INV (legacy) */
94 };
95
96 #ifdef CONFIG_IWL4965_HT
97
98 static const u16 default_tid_to_tx_fifo[] = {
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC0,
101 IWL_TX_FIFO_AC0,
102 IWL_TX_FIFO_AC1,
103 IWL_TX_FIFO_AC2,
104 IWL_TX_FIFO_AC2,
105 IWL_TX_FIFO_AC3,
106 IWL_TX_FIFO_AC3,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_NONE,
114 IWL_TX_FIFO_NONE,
115 IWL_TX_FIFO_AC3
116 };
117
118 #endif /*CONFIG_IWL4965_HT */
119
120 /* check contents of special bootstrap uCode SRAM */
121 static int iwl4965_verify_bsm(struct iwl_priv *priv)
122 {
123 __le32 *image = priv->ucode_boot.v_addr;
124 u32 len = priv->ucode_boot.len;
125 u32 reg;
126 u32 val;
127
128 IWL_DEBUG_INFO("Begin verify bsm\n");
129
130 /* verify BSM SRAM contents */
131 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
132 for (reg = BSM_SRAM_LOWER_BOUND;
133 reg < BSM_SRAM_LOWER_BOUND + len;
134 reg += sizeof(u32), image++) {
135 val = iwl_read_prph(priv, reg);
136 if (val != le32_to_cpu(*image)) {
137 IWL_ERROR("BSM uCode verification failed at "
138 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
139 BSM_SRAM_LOWER_BOUND,
140 reg - BSM_SRAM_LOWER_BOUND, len,
141 val, le32_to_cpu(*image));
142 return -EIO;
143 }
144 }
145
146 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
147
148 return 0;
149 }
150
151 /**
152 * iwl4965_load_bsm - Load bootstrap instructions
153 *
154 * BSM operation:
155 *
156 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
157 * in special SRAM that does not power down during RFKILL. When powering back
158 * up after power-saving sleeps (or during initial uCode load), the BSM loads
159 * the bootstrap program into the on-board processor, and starts it.
160 *
161 * The bootstrap program loads (via DMA) instructions and data for a new
162 * program from host DRAM locations indicated by the host driver in the
163 * BSM_DRAM_* registers. Once the new program is loaded, it starts
164 * automatically.
165 *
166 * When initializing the NIC, the host driver points the BSM to the
167 * "initialize" uCode image. This uCode sets up some internal data, then
168 * notifies host via "initialize alive" that it is complete.
169 *
170 * The host then replaces the BSM_DRAM_* pointer values to point to the
171 * normal runtime uCode instructions and a backup uCode data cache buffer
172 * (filled initially with starting data values for the on-board processor),
173 * then triggers the "initialize" uCode to load and launch the runtime uCode,
174 * which begins normal operation.
175 *
176 * When doing a power-save shutdown, runtime uCode saves data SRAM into
177 * the backup data cache in DRAM before SRAM is powered down.
178 *
179 * When powering back up, the BSM loads the bootstrap program. This reloads
180 * the runtime uCode instructions and the backup data cache into SRAM,
181 * and re-launches the runtime uCode from where it left off.
182 */
183 static int iwl4965_load_bsm(struct iwl_priv *priv)
184 {
185 __le32 *image = priv->ucode_boot.v_addr;
186 u32 len = priv->ucode_boot.len;
187 dma_addr_t pinst;
188 dma_addr_t pdata;
189 u32 inst_len;
190 u32 data_len;
191 int i;
192 u32 done;
193 u32 reg_offset;
194 int ret;
195
196 IWL_DEBUG_INFO("Begin load bsm\n");
197
198 /* make sure bootstrap program is no larger than BSM's SRAM size */
199 if (len > IWL_MAX_BSM_SIZE)
200 return -EINVAL;
201
202 /* Tell bootstrap uCode where to find the "Initialize" uCode
203 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
204 * NOTE: iwl4965_initialize_alive_start() will replace these values,
205 * after the "initialize" uCode has run, to point to
206 * runtime/protocol instructions and backup data cache. */
207 pinst = priv->ucode_init.p_addr >> 4;
208 pdata = priv->ucode_init_data.p_addr >> 4;
209 inst_len = priv->ucode_init.len;
210 data_len = priv->ucode_init_data.len;
211
212 ret = iwl_grab_nic_access(priv);
213 if (ret)
214 return ret;
215
216 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
217 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
218 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
219 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
220
221 /* Fill BSM memory with bootstrap instructions */
222 for (reg_offset = BSM_SRAM_LOWER_BOUND;
223 reg_offset < BSM_SRAM_LOWER_BOUND + len;
224 reg_offset += sizeof(u32), image++)
225 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
226
227 ret = iwl4965_verify_bsm(priv);
228 if (ret) {
229 iwl_release_nic_access(priv);
230 return ret;
231 }
232
233 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
234 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
235 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
236 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
237
238 /* Load bootstrap code into instruction SRAM now,
239 * to prepare to load "initialize" uCode */
240 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
241
242 /* Wait for load of bootstrap uCode to finish */
243 for (i = 0; i < 100; i++) {
244 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
245 if (!(done & BSM_WR_CTRL_REG_BIT_START))
246 break;
247 udelay(10);
248 }
249 if (i < 100)
250 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
251 else {
252 IWL_ERROR("BSM write did not complete!\n");
253 return -EIO;
254 }
255
256 /* Enable future boot loads whenever power management unit triggers it
257 * (e.g. when powering back up after power-save shutdown) */
258 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
259
260 iwl_release_nic_access(priv);
261
262 return 0;
263 }
264
265 static int iwl4965_init_drv(struct iwl_priv *priv)
266 {
267 int ret;
268 int i;
269
270 priv->retry_rate = 1;
271 priv->ibss_beacon = NULL;
272
273 spin_lock_init(&priv->lock);
274 spin_lock_init(&priv->power_data.lock);
275 spin_lock_init(&priv->sta_lock);
276 spin_lock_init(&priv->hcmd_lock);
277 spin_lock_init(&priv->lq_mngr.lock);
278
279 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
280 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
281
282 INIT_LIST_HEAD(&priv->free_frames);
283
284 mutex_init(&priv->mutex);
285
286 /* Clear the driver's (not device's) station table */
287 iwlcore_clear_stations_table(priv);
288
289 priv->data_retry_limit = -1;
290 priv->ieee_channels = NULL;
291 priv->ieee_rates = NULL;
292 priv->band = IEEE80211_BAND_2GHZ;
293
294 priv->iw_mode = IEEE80211_IF_TYPE_STA;
295
296 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
297 priv->ps_mode = IWL_MIMO_PS_NONE;
298
299 /* Choose which receivers/antennas to use */
300 iwl4965_set_rxon_chain(priv);
301
302 iwlcore_reset_qos(priv);
303
304 priv->qos_data.qos_active = 0;
305 priv->qos_data.qos_cap.val = 0;
306
307 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
308
309 priv->rates_mask = IWL_RATES_MASK;
310 /* If power management is turned on, default to AC mode */
311 priv->power_mode = IWL_POWER_AC;
312 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
313
314 ret = iwl_init_channel_map(priv);
315 if (ret) {
316 IWL_ERROR("initializing regulatory failed: %d\n", ret);
317 goto err;
318 }
319
320 ret = iwl4965_init_geos(priv);
321 if (ret) {
322 IWL_ERROR("initializing geos failed: %d\n", ret);
323 goto err_free_channel_map;
324 }
325
326 ret = ieee80211_register_hw(priv->hw);
327 if (ret) {
328 IWL_ERROR("Failed to register network device (error %d)\n",
329 ret);
330 goto err_free_geos;
331 }
332
333 priv->hw->conf.beacon_int = 100;
334 priv->mac80211_registered = 1;
335
336 return 0;
337
338 err_free_geos:
339 iwl4965_free_geos(priv);
340 err_free_channel_map:
341 iwl_free_channel_map(priv);
342 err:
343 return ret;
344 }
345
346 static int is_fat_channel(__le32 rxon_flags)
347 {
348 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
349 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
350 }
351
352 #ifdef CONFIG_IWL4965_HT
353 static u8 is_single_rx_stream(struct iwl_priv *priv)
354 {
355 return !priv->current_ht_config.is_ht ||
356 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
357 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
358 priv->ps_mode == IWL_MIMO_PS_STATIC;
359 }
360 #else
361 static inline u8 is_single_rx_stream(struct iwl_priv *priv)
362 {
363 return 1;
364 }
365 #endif /*CONFIG_IWL4965_HT */
366
367 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
368 {
369 int idx = 0;
370
371 /* 4965 HT rate format */
372 if (rate_n_flags & RATE_MCS_HT_MSK) {
373 idx = (rate_n_flags & 0xff);
374
375 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
376 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
377
378 idx += IWL_FIRST_OFDM_RATE;
379 /* skip 9M not supported in ht*/
380 if (idx >= IWL_RATE_9M_INDEX)
381 idx += 1;
382 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
383 return idx;
384
385 /* 4965 legacy rate format, search for match in table */
386 } else {
387 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
388 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
389 return idx;
390 }
391
392 return -1;
393 }
394
395 /**
396 * translate ucode response to mac80211 tx status control values
397 */
398 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
399 struct ieee80211_tx_control *control)
400 {
401 int rate_index;
402
403 control->antenna_sel_tx =
404 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
405 if (rate_n_flags & RATE_MCS_HT_MSK)
406 control->flags |= IEEE80211_TXCTL_OFDM_HT;
407 if (rate_n_flags & RATE_MCS_GF_MSK)
408 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
409 if (rate_n_flags & RATE_MCS_FAT_MSK)
410 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
411 if (rate_n_flags & RATE_MCS_DUP_MSK)
412 control->flags |= IEEE80211_TXCTL_DUP_DATA;
413 if (rate_n_flags & RATE_MCS_SGI_MSK)
414 control->flags |= IEEE80211_TXCTL_SHORT_GI;
415 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
416 * IEEE80211_BAND_2GHZ band as it contains all the rates */
417 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
418 if (rate_index == -1)
419 control->tx_rate = NULL;
420 else
421 control->tx_rate =
422 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
423 }
424
425 /*
426 * Determine how many receiver/antenna chains to use.
427 * More provides better reception via diversity. Fewer saves power.
428 * MIMO (dual stream) requires at least 2, but works better with 3.
429 * This does not determine *which* chains to use, just how many.
430 */
431 static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
432 u8 *idle_state, u8 *rx_state)
433 {
434 u8 is_single = is_single_rx_stream(priv);
435 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
436
437 /* # of Rx chains to use when expecting MIMO. */
438 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
439 *rx_state = 2;
440 else
441 *rx_state = 3;
442
443 /* # Rx chains when idling and maybe trying to save power */
444 switch (priv->ps_mode) {
445 case IWL_MIMO_PS_STATIC:
446 case IWL_MIMO_PS_DYNAMIC:
447 *idle_state = (is_cam) ? 2 : 1;
448 break;
449 case IWL_MIMO_PS_NONE:
450 *idle_state = (is_cam) ? *rx_state : 1;
451 break;
452 default:
453 *idle_state = 1;
454 break;
455 }
456
457 return 0;
458 }
459
460 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
461 {
462 int rc;
463 unsigned long flags;
464
465 spin_lock_irqsave(&priv->lock, flags);
466 rc = iwl_grab_nic_access(priv);
467 if (rc) {
468 spin_unlock_irqrestore(&priv->lock, flags);
469 return rc;
470 }
471
472 /* stop Rx DMA */
473 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
474 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
475 (1 << 24), 1000);
476 if (rc < 0)
477 IWL_ERROR("Can't stop Rx DMA.\n");
478
479 iwl_release_nic_access(priv);
480 spin_unlock_irqrestore(&priv->lock, flags);
481
482 return 0;
483 }
484
485 /*
486 * EEPROM handlers
487 */
488
489 static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
490 {
491 u16 eeprom_ver;
492 u16 calib_ver;
493
494 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
495
496 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
497
498 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
499 calib_ver < EEPROM_4965_TX_POWER_VERSION)
500 goto err;
501
502 return 0;
503 err:
504 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
505 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
506 calib_ver, EEPROM_4965_TX_POWER_VERSION);
507 return -EINVAL;
508
509 }
510 int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
511 {
512 int ret;
513 unsigned long flags;
514
515 spin_lock_irqsave(&priv->lock, flags);
516 ret = iwl_grab_nic_access(priv);
517 if (ret) {
518 spin_unlock_irqrestore(&priv->lock, flags);
519 return ret;
520 }
521
522 if (src == IWL_PWR_SRC_VAUX) {
523 u32 val;
524 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
525 &val);
526
527 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
528 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
529 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
530 ~APMG_PS_CTRL_MSK_PWR_SRC);
531 }
532 } else {
533 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
534 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
535 ~APMG_PS_CTRL_MSK_PWR_SRC);
536 }
537
538 iwl_release_nic_access(priv);
539 spin_unlock_irqrestore(&priv->lock, flags);
540
541 return ret;
542 }
543
544 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
545 {
546 int ret;
547 unsigned long flags;
548 unsigned int rb_size;
549
550 spin_lock_irqsave(&priv->lock, flags);
551 ret = iwl_grab_nic_access(priv);
552 if (ret) {
553 spin_unlock_irqrestore(&priv->lock, flags);
554 return ret;
555 }
556
557 if (priv->cfg->mod_params->amsdu_size_8K)
558 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
559 else
560 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
561
562 /* Stop Rx DMA */
563 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
564
565 /* Reset driver's Rx queue write index */
566 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
567
568 /* Tell device where to find RBD circular buffer in DRAM */
569 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
570 rxq->dma_addr >> 8);
571
572 /* Tell device where in DRAM to update its Rx status */
573 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
574 (priv->shared_phys +
575 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
576
577 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
578 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
579 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
580 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
581 rb_size |
582 /* 0x10 << 4 | */
583 (RX_QUEUE_SIZE_LOG <<
584 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
585
586 /*
587 * iwl_write32(priv,CSR_INT_COAL_REG,0);
588 */
589
590 iwl_release_nic_access(priv);
591 spin_unlock_irqrestore(&priv->lock, flags);
592
593 return 0;
594 }
595
596 /* Tell 4965 where to find the "keep warm" buffer */
597 static int iwl4965_kw_init(struct iwl_priv *priv)
598 {
599 unsigned long flags;
600 int rc;
601
602 spin_lock_irqsave(&priv->lock, flags);
603 rc = iwl_grab_nic_access(priv);
604 if (rc)
605 goto out;
606
607 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
608 priv->kw.dma_addr >> 4);
609 iwl_release_nic_access(priv);
610 out:
611 spin_unlock_irqrestore(&priv->lock, flags);
612 return rc;
613 }
614
615 static int iwl4965_kw_alloc(struct iwl_priv *priv)
616 {
617 struct pci_dev *dev = priv->pci_dev;
618 struct iwl4965_kw *kw = &priv->kw;
619
620 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
621 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
622 if (!kw->v_addr)
623 return -ENOMEM;
624
625 return 0;
626 }
627
628 /**
629 * iwl4965_kw_free - Free the "keep warm" buffer
630 */
631 static void iwl4965_kw_free(struct iwl_priv *priv)
632 {
633 struct pci_dev *dev = priv->pci_dev;
634 struct iwl4965_kw *kw = &priv->kw;
635
636 if (kw->v_addr) {
637 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
638 memset(kw, 0, sizeof(*kw));
639 }
640 }
641
642 /**
643 * iwl4965_txq_ctx_reset - Reset TX queue context
644 * Destroys all DMA structures and initialise them again
645 *
646 * @param priv
647 * @return error code
648 */
649 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
650 {
651 int rc = 0;
652 int txq_id, slots_num;
653 unsigned long flags;
654
655 iwl4965_kw_free(priv);
656
657 /* Free all tx/cmd queues and keep-warm buffer */
658 iwl4965_hw_txq_ctx_free(priv);
659
660 /* Alloc keep-warm buffer */
661 rc = iwl4965_kw_alloc(priv);
662 if (rc) {
663 IWL_ERROR("Keep Warm allocation failed");
664 goto error_kw;
665 }
666
667 spin_lock_irqsave(&priv->lock, flags);
668
669 rc = iwl_grab_nic_access(priv);
670 if (unlikely(rc)) {
671 IWL_ERROR("TX reset failed");
672 spin_unlock_irqrestore(&priv->lock, flags);
673 goto error_reset;
674 }
675
676 /* Turn off all Tx DMA channels */
677 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
678 iwl_release_nic_access(priv);
679 spin_unlock_irqrestore(&priv->lock, flags);
680
681 /* Tell 4965 where to find the keep-warm buffer */
682 rc = iwl4965_kw_init(priv);
683 if (rc) {
684 IWL_ERROR("kw_init failed\n");
685 goto error_reset;
686 }
687
688 /* Alloc and init all (default 16) Tx queues,
689 * including the command queue (#4) */
690 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
691 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
692 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
693 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
694 txq_id);
695 if (rc) {
696 IWL_ERROR("Tx %d queue init failed\n", txq_id);
697 goto error;
698 }
699 }
700
701 return rc;
702
703 error:
704 iwl4965_hw_txq_ctx_free(priv);
705 error_reset:
706 iwl4965_kw_free(priv);
707 error_kw:
708 return rc;
709 }
710 static int iwl4965_apm_init(struct iwl_priv *priv)
711 {
712 unsigned long flags;
713 int ret = 0;
714
715 spin_lock_irqsave(&priv->lock, flags);
716 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
717 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
718
719 /* set "initialization complete" bit to move adapter
720 * D0U* --> D0A* state */
721 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
722
723 /* wait for clock stabilization */
724 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
725 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
726 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
727 if (ret < 0) {
728 IWL_DEBUG_INFO("Failed to init the card\n");
729 goto out;
730 }
731
732 ret = iwl_grab_nic_access(priv);
733 if (ret)
734 goto out;
735
736 /* enable DMA */
737 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
738 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
739
740 udelay(20);
741
742 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
743 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
744
745 iwl_release_nic_access(priv);
746 out:
747 spin_unlock_irqrestore(&priv->lock, flags);
748 return ret;
749 }
750
751 int iwl4965_hw_nic_init(struct iwl_priv *priv)
752 {
753 unsigned long flags;
754 struct iwl4965_rx_queue *rxq = &priv->rxq;
755 u8 val_link;
756 u32 val;
757 int ret;
758
759 /* nic_init */
760 priv->cfg->ops->lib->apm_ops.init(priv);
761
762 spin_lock_irqsave(&priv->lock, flags);
763 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
764 spin_unlock_irqrestore(&priv->lock, flags);
765
766 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
767
768 spin_lock_irqsave(&priv->lock, flags);
769
770 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
771 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
772 /* Enable No Snoop field */
773 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
774 val & ~(1 << 11));
775 }
776
777 spin_unlock_irqrestore(&priv->lock, flags);
778
779 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
780
781 /* disable L1 entry -- workaround for pre-B1 */
782 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
783
784 spin_lock_irqsave(&priv->lock, flags);
785
786 /* set CSR_HW_CONFIG_REG for uCode use */
787
788 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
789 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
790 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
791 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
792
793 ret = iwl_grab_nic_access(priv);
794 if (ret < 0) {
795 spin_unlock_irqrestore(&priv->lock, flags);
796 IWL_DEBUG_INFO("Failed to init the card\n");
797 return ret;
798 }
799
800 iwl_read_prph(priv, APMG_PS_CTRL_REG);
801 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
802 udelay(5);
803 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
804
805 iwl_release_nic_access(priv);
806 spin_unlock_irqrestore(&priv->lock, flags);
807
808 iwl4965_hw_card_show_info(priv);
809
810 /* end nic_init */
811
812 /* Allocate the RX queue, or reset if it is already allocated */
813 if (!rxq->bd) {
814 ret = iwl4965_rx_queue_alloc(priv);
815 if (ret) {
816 IWL_ERROR("Unable to initialize Rx queue\n");
817 return -ENOMEM;
818 }
819 } else
820 iwl4965_rx_queue_reset(priv, rxq);
821
822 iwl4965_rx_replenish(priv);
823
824 iwl4965_rx_init(priv, rxq);
825
826 spin_lock_irqsave(&priv->lock, flags);
827
828 rxq->need_update = 1;
829 iwl4965_rx_queue_update_write_ptr(priv, rxq);
830
831 /* init the txpower calibration pointer */
832 priv->calib_info = (struct iwl_eeprom_calib_info *)
833 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
834
835 spin_unlock_irqrestore(&priv->lock, flags);
836
837 /* Allocate and init all Tx and Command queues */
838 ret = iwl4965_txq_ctx_reset(priv);
839 if (ret)
840 return ret;
841
842 set_bit(STATUS_INIT, &priv->status);
843
844 return 0;
845 }
846
847 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
848 {
849 int rc = 0;
850 u32 reg_val;
851 unsigned long flags;
852
853 spin_lock_irqsave(&priv->lock, flags);
854
855 /* set stop master bit */
856 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
857
858 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
859
860 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
861 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
862 IWL_DEBUG_INFO("Card in power save, master is already "
863 "stopped\n");
864 else {
865 rc = iwl_poll_bit(priv, CSR_RESET,
866 CSR_RESET_REG_FLAG_MASTER_DISABLED,
867 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
868 if (rc < 0) {
869 spin_unlock_irqrestore(&priv->lock, flags);
870 return rc;
871 }
872 }
873
874 spin_unlock_irqrestore(&priv->lock, flags);
875 IWL_DEBUG_INFO("stop master\n");
876
877 return rc;
878 }
879
880 /**
881 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
882 */
883 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
884 {
885
886 int txq_id;
887 unsigned long flags;
888
889 /* Stop each Tx DMA channel, and wait for it to be idle */
890 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
891 spin_lock_irqsave(&priv->lock, flags);
892 if (iwl_grab_nic_access(priv)) {
893 spin_unlock_irqrestore(&priv->lock, flags);
894 continue;
895 }
896
897 iwl_write_direct32(priv,
898 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
899 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
900 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
901 (txq_id), 200);
902 iwl_release_nic_access(priv);
903 spin_unlock_irqrestore(&priv->lock, flags);
904 }
905
906 /* Deallocate memory for all Tx queues */
907 iwl4965_hw_txq_ctx_free(priv);
908 }
909
910 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
911 {
912 int rc = 0;
913 unsigned long flags;
914
915 iwl4965_hw_nic_stop_master(priv);
916
917 spin_lock_irqsave(&priv->lock, flags);
918
919 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
920
921 udelay(10);
922
923 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
924 rc = iwl_poll_bit(priv, CSR_RESET,
925 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
926 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
927
928 udelay(10);
929
930 rc = iwl_grab_nic_access(priv);
931 if (!rc) {
932 iwl_write_prph(priv, APMG_CLK_EN_REG,
933 APMG_CLK_VAL_DMA_CLK_RQT |
934 APMG_CLK_VAL_BSM_CLK_RQT);
935
936 udelay(10);
937
938 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
939 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
940
941 iwl_release_nic_access(priv);
942 }
943
944 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
945 wake_up_interruptible(&priv->wait_command_queue);
946
947 spin_unlock_irqrestore(&priv->lock, flags);
948
949 return rc;
950
951 }
952
953 #define REG_RECALIB_PERIOD (60)
954
955 /**
956 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
957 *
958 * This callback is provided in order to send a statistics request.
959 *
960 * This timer function is continually reset to execute within
961 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
962 * was received. We need to ensure we receive the statistics in order
963 * to update the temperature used for calibrating the TXPOWER.
964 */
965 static void iwl4965_bg_statistics_periodic(unsigned long data)
966 {
967 struct iwl_priv *priv = (struct iwl_priv *)data;
968
969 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
970 return;
971
972 iwl_send_statistics_request(priv, CMD_ASYNC);
973 }
974
975 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
976 {
977 struct iwl4965_ct_kill_config cmd;
978 unsigned long flags;
979 int ret = 0;
980
981 spin_lock_irqsave(&priv->lock, flags);
982 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
983 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
984 spin_unlock_irqrestore(&priv->lock, flags);
985
986 cmd.critical_temperature_R =
987 cpu_to_le32(priv->hw_params.ct_kill_threshold);
988
989 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
990 sizeof(cmd), &cmd);
991 if (ret)
992 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
993 else
994 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
995 "critical temperature is %d\n",
996 cmd.critical_temperature_R);
997 }
998
999 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1000
1001 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1002 * Called after every association, but this runs only once!
1003 * ... once chain noise is calibrated the first time, it's good forever. */
1004 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1005 {
1006 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
1007
1008 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
1009 struct iwl4965_calibration_cmd cmd;
1010
1011 memset(&cmd, 0, sizeof(cmd));
1012 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1013 cmd.diff_gain_a = 0;
1014 cmd.diff_gain_b = 0;
1015 cmd.diff_gain_c = 0;
1016 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1017 sizeof(cmd), &cmd))
1018 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
1019 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1020 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1021 }
1022 }
1023
1024 static void iwl4965_gain_computation(struct iwl_priv *priv,
1025 u32 *average_noise,
1026 u16 min_average_noise_antenna_i,
1027 u32 min_average_noise)
1028 {
1029 int i, ret;
1030 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
1031
1032 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1033
1034 for (i = 0; i < NUM_RX_CHAINS; i++) {
1035 s32 delta_g = 0;
1036
1037 if (!(data->disconn_array[i]) &&
1038 (data->delta_gain_code[i] ==
1039 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1040 delta_g = average_noise[i] - min_average_noise;
1041 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1042 data->delta_gain_code[i] =
1043 min(data->delta_gain_code[i],
1044 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1045
1046 data->delta_gain_code[i] =
1047 (data->delta_gain_code[i] | (1 << 2));
1048 } else {
1049 data->delta_gain_code[i] = 0;
1050 }
1051 }
1052 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1053 data->delta_gain_code[0],
1054 data->delta_gain_code[1],
1055 data->delta_gain_code[2]);
1056
1057 /* Differential gain gets sent to uCode only once */
1058 if (!data->radio_write) {
1059 struct iwl4965_calibration_cmd cmd;
1060 data->radio_write = 1;
1061
1062 memset(&cmd, 0, sizeof(cmd));
1063 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1064 cmd.diff_gain_a = data->delta_gain_code[0];
1065 cmd.diff_gain_b = data->delta_gain_code[1];
1066 cmd.diff_gain_c = data->delta_gain_code[2];
1067 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1068 sizeof(cmd), &cmd);
1069 if (ret)
1070 IWL_DEBUG_CALIB("fail sending cmd "
1071 "REPLY_PHY_CALIBRATION_CMD \n");
1072
1073 /* TODO we might want recalculate
1074 * rx_chain in rxon cmd */
1075
1076 /* Mark so we run this algo only once! */
1077 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1078 }
1079 data->chain_noise_a = 0;
1080 data->chain_noise_b = 0;
1081 data->chain_noise_c = 0;
1082 data->chain_signal_a = 0;
1083 data->chain_signal_b = 0;
1084 data->chain_signal_c = 0;
1085 data->beacon_count = 0;
1086 }
1087
1088 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1089 {
1090 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1091 sensitivity_work);
1092
1093 mutex_lock(&priv->mutex);
1094
1095 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1096 test_bit(STATUS_SCANNING, &priv->status)) {
1097 mutex_unlock(&priv->mutex);
1098 return;
1099 }
1100
1101 if (priv->start_calib) {
1102 iwl_chain_noise_calibration(priv, &priv->statistics);
1103
1104 iwl_sensitivity_calibration(priv, &priv->statistics);
1105 }
1106
1107 mutex_unlock(&priv->mutex);
1108 return;
1109 }
1110 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
1111
1112 static void iwl4965_bg_txpower_work(struct work_struct *work)
1113 {
1114 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1115 txpower_work);
1116
1117 /* If a scan happened to start before we got here
1118 * then just return; the statistics notification will
1119 * kick off another scheduled work to compensate for
1120 * any temperature delta we missed here. */
1121 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1122 test_bit(STATUS_SCANNING, &priv->status))
1123 return;
1124
1125 mutex_lock(&priv->mutex);
1126
1127 /* Regardless of if we are assocaited, we must reconfigure the
1128 * TX power since frames can be sent on non-radar channels while
1129 * not associated */
1130 iwl4965_hw_reg_send_txpower(priv);
1131
1132 /* Update last_temperature to keep is_calib_needed from running
1133 * when it isn't needed... */
1134 priv->last_temperature = priv->temperature;
1135
1136 mutex_unlock(&priv->mutex);
1137 }
1138
1139 /*
1140 * Acquire priv->lock before calling this function !
1141 */
1142 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1143 {
1144 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1145 (index & 0xff) | (txq_id << 8));
1146 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
1147 }
1148
1149 /**
1150 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1151 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1152 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1153 *
1154 * NOTE: Acquire priv->lock before calling this function !
1155 */
1156 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1157 struct iwl4965_tx_queue *txq,
1158 int tx_fifo_id, int scd_retry)
1159 {
1160 int txq_id = txq->q.id;
1161
1162 /* Find out whether to activate Tx queue */
1163 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1164
1165 /* Set up and activate */
1166 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1167 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1168 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1169 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1170 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1171 SCD_QUEUE_STTS_REG_MSK);
1172
1173 txq->sched_retry = scd_retry;
1174
1175 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1176 active ? "Activate" : "Deactivate",
1177 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1178 }
1179
1180 static const u16 default_queue_to_tx_fifo[] = {
1181 IWL_TX_FIFO_AC3,
1182 IWL_TX_FIFO_AC2,
1183 IWL_TX_FIFO_AC1,
1184 IWL_TX_FIFO_AC0,
1185 IWL_CMD_FIFO_NUM,
1186 IWL_TX_FIFO_HCCA_1,
1187 IWL_TX_FIFO_HCCA_2
1188 };
1189
1190 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1191 {
1192 set_bit(txq_id, &priv->txq_ctx_active_msk);
1193 }
1194
1195 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1196 {
1197 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1198 }
1199
1200 int iwl4965_alive_notify(struct iwl_priv *priv)
1201 {
1202 u32 a;
1203 int i = 0;
1204 unsigned long flags;
1205 int ret;
1206
1207 spin_lock_irqsave(&priv->lock, flags);
1208
1209 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1210 memset(&(priv->sensitivity_data), 0,
1211 sizeof(struct iwl_sensitivity_data));
1212 memset(&(priv->chain_noise_data), 0,
1213 sizeof(struct iwl_chain_noise_data));
1214 for (i = 0; i < NUM_RX_CHAINS; i++)
1215 priv->chain_noise_data.delta_gain_code[i] =
1216 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1217 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1218 ret = iwl_grab_nic_access(priv);
1219 if (ret) {
1220 spin_unlock_irqrestore(&priv->lock, flags);
1221 return ret;
1222 }
1223
1224 /* Clear 4965's internal Tx Scheduler data base */
1225 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1226 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1227 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1228 iwl_write_targ_mem(priv, a, 0);
1229 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1230 iwl_write_targ_mem(priv, a, 0);
1231 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1232 iwl_write_targ_mem(priv, a, 0);
1233
1234 /* Tel 4965 where to find Tx byte count tables */
1235 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1236 (priv->shared_phys +
1237 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1238
1239 /* Disable chain mode for all queues */
1240 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1241
1242 /* Initialize each Tx queue (including the command queue) */
1243 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1244
1245 /* TFD circular buffer read/write indexes */
1246 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1247 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1248
1249 /* Max Tx Window size for Scheduler-ACK mode */
1250 iwl_write_targ_mem(priv, priv->scd_base_addr +
1251 SCD_CONTEXT_QUEUE_OFFSET(i),
1252 (SCD_WIN_SIZE <<
1253 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1254 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1255
1256 /* Frame limit */
1257 iwl_write_targ_mem(priv, priv->scd_base_addr +
1258 SCD_CONTEXT_QUEUE_OFFSET(i) +
1259 sizeof(u32),
1260 (SCD_FRAME_LIMIT <<
1261 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1262 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1263
1264 }
1265 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1266 (1 << priv->hw_params.max_txq_num) - 1);
1267
1268 /* Activate all Tx DMA/FIFO channels */
1269 iwl_write_prph(priv, IWL49_SCD_TXFACT,
1270 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1271
1272 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1273
1274 /* Map each Tx/cmd queue to its corresponding fifo */
1275 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1276 int ac = default_queue_to_tx_fifo[i];
1277 iwl4965_txq_ctx_activate(priv, i);
1278 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1279 }
1280
1281 iwl_release_nic_access(priv);
1282 spin_unlock_irqrestore(&priv->lock, flags);
1283
1284 /* Ask for statistics now, the uCode will send statistics notification
1285 * periodically after association */
1286 iwl_send_statistics_request(priv, CMD_ASYNC);
1287 return ret;
1288 }
1289
1290 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1291 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1292 .min_nrg_cck = 97,
1293 .max_nrg_cck = 0,
1294
1295 .auto_corr_min_ofdm = 85,
1296 .auto_corr_min_ofdm_mrc = 170,
1297 .auto_corr_min_ofdm_x1 = 105,
1298 .auto_corr_min_ofdm_mrc_x1 = 220,
1299
1300 .auto_corr_max_ofdm = 120,
1301 .auto_corr_max_ofdm_mrc = 210,
1302 .auto_corr_max_ofdm_x1 = 140,
1303 .auto_corr_max_ofdm_mrc_x1 = 270,
1304
1305 .auto_corr_min_cck = 125,
1306 .auto_corr_max_cck = 200,
1307 .auto_corr_min_cck_mrc = 200,
1308 .auto_corr_max_cck_mrc = 400,
1309
1310 .nrg_th_cck = 100,
1311 .nrg_th_ofdm = 100,
1312 };
1313 #endif
1314
1315 /**
1316 * iwl4965_hw_set_hw_params
1317 *
1318 * Called when initializing driver
1319 */
1320 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1321 {
1322
1323 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1324 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1325 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1326 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
1327 return -EINVAL;
1328 }
1329
1330 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1331 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1332 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1333 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1334 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1335 if (priv->cfg->mod_params->amsdu_size_8K)
1336 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1337 else
1338 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1339 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1340 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1341 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1342
1343 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1344 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1345 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1346 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1347
1348 priv->hw_params.tx_chains_num = 2;
1349 priv->hw_params.rx_chains_num = 2;
1350 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1351 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
1352 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1353
1354 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1355 priv->hw_params.sens = &iwl4965_sensitivity;
1356 #endif
1357
1358 return 0;
1359 }
1360
1361 /**
1362 * iwl4965_hw_txq_ctx_free - Free TXQ Context
1363 *
1364 * Destroy all TX DMA queues and structures
1365 */
1366 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1367 {
1368 int txq_id;
1369
1370 /* Tx queues */
1371 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1372 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1373
1374 /* Keep-warm buffer */
1375 iwl4965_kw_free(priv);
1376 }
1377
1378 /**
1379 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1380 *
1381 * Does NOT advance any TFD circular buffer read/write indexes
1382 * Does NOT free the TFD itself (which is within circular buffer)
1383 */
1384 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1385 {
1386 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1387 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1388 struct pci_dev *dev = priv->pci_dev;
1389 int i;
1390 int counter = 0;
1391 int index, is_odd;
1392
1393 /* Host command buffers stay mapped in memory, nothing to clean */
1394 if (txq->q.id == IWL_CMD_QUEUE_NUM)
1395 return 0;
1396
1397 /* Sanity check on number of chunks */
1398 counter = IWL_GET_BITS(*bd, num_tbs);
1399 if (counter > MAX_NUM_OF_TBS) {
1400 IWL_ERROR("Too many chunks: %i\n", counter);
1401 /* @todo issue fatal error, it is quite serious situation */
1402 return 0;
1403 }
1404
1405 /* Unmap chunks, if any.
1406 * TFD info for odd chunks is different format than for even chunks. */
1407 for (i = 0; i < counter; i++) {
1408 index = i / 2;
1409 is_odd = i & 0x1;
1410
1411 if (is_odd)
1412 pci_unmap_single(
1413 dev,
1414 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1415 (IWL_GET_BITS(bd->pa[index],
1416 tb2_addr_hi20) << 16),
1417 IWL_GET_BITS(bd->pa[index], tb2_len),
1418 PCI_DMA_TODEVICE);
1419
1420 else if (i > 0)
1421 pci_unmap_single(dev,
1422 le32_to_cpu(bd->pa[index].tb1_addr),
1423 IWL_GET_BITS(bd->pa[index], tb1_len),
1424 PCI_DMA_TODEVICE);
1425
1426 /* Free SKB, if any, for this chunk */
1427 if (txq->txb[txq->q.read_ptr].skb[i]) {
1428 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1429
1430 dev_kfree_skb(skb);
1431 txq->txb[txq->q.read_ptr].skb[i] = NULL;
1432 }
1433 }
1434 return 0;
1435 }
1436
1437 /* set card power command */
1438 static int iwl4965_set_power(struct iwl_priv *priv,
1439 void *cmd)
1440 {
1441 int ret = 0;
1442
1443 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1444 sizeof(struct iwl4965_powertable_cmd),
1445 cmd, NULL);
1446 return ret;
1447 }
1448 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1449 {
1450 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1451 return -EINVAL;
1452 }
1453
1454 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1455 {
1456 s32 sign = 1;
1457
1458 if (num < 0) {
1459 sign = -sign;
1460 num = -num;
1461 }
1462 if (denom < 0) {
1463 sign = -sign;
1464 denom = -denom;
1465 }
1466 *res = 1;
1467 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1468
1469 return 1;
1470 }
1471
1472 /**
1473 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1474 *
1475 * Determines power supply voltage compensation for txpower calculations.
1476 * Returns number of 1/2-dB steps to subtract from gain table index,
1477 * to compensate for difference between power supply voltage during
1478 * factory measurements, vs. current power supply voltage.
1479 *
1480 * Voltage indication is higher for lower voltage.
1481 * Lower voltage requires more gain (lower gain table index).
1482 */
1483 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1484 s32 current_voltage)
1485 {
1486 s32 comp = 0;
1487
1488 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1489 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1490 return 0;
1491
1492 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1493 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1494
1495 if (current_voltage > eeprom_voltage)
1496 comp *= 2;
1497 if ((comp < -2) || (comp > 2))
1498 comp = 0;
1499
1500 return comp;
1501 }
1502
1503 static const struct iwl_channel_info *
1504 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1505 enum ieee80211_band band, u16 channel)
1506 {
1507 const struct iwl_channel_info *ch_info;
1508
1509 ch_info = iwl_get_channel_info(priv, band, channel);
1510
1511 if (!is_channel_valid(ch_info))
1512 return NULL;
1513
1514 return ch_info;
1515 }
1516
1517 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1518 {
1519 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1520 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1521 return CALIB_CH_GROUP_5;
1522
1523 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1524 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1525 return CALIB_CH_GROUP_1;
1526
1527 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1528 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1529 return CALIB_CH_GROUP_2;
1530
1531 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1532 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1533 return CALIB_CH_GROUP_3;
1534
1535 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1536 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1537 return CALIB_CH_GROUP_4;
1538
1539 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1540 return -1;
1541 }
1542
1543 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1544 {
1545 s32 b = -1;
1546
1547 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1548 if (priv->calib_info->band_info[b].ch_from == 0)
1549 continue;
1550
1551 if ((channel >= priv->calib_info->band_info[b].ch_from)
1552 && (channel <= priv->calib_info->band_info[b].ch_to))
1553 break;
1554 }
1555
1556 return b;
1557 }
1558
1559 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1560 {
1561 s32 val;
1562
1563 if (x2 == x1)
1564 return y1;
1565 else {
1566 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1567 return val + y2;
1568 }
1569 }
1570
1571 /**
1572 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1573 *
1574 * Interpolates factory measurements from the two sample channels within a
1575 * sub-band, to apply to channel of interest. Interpolation is proportional to
1576 * differences in channel frequencies, which is proportional to differences
1577 * in channel number.
1578 */
1579 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1580 struct iwl_eeprom_calib_ch_info *chan_info)
1581 {
1582 s32 s = -1;
1583 u32 c;
1584 u32 m;
1585 const struct iwl_eeprom_calib_measure *m1;
1586 const struct iwl_eeprom_calib_measure *m2;
1587 struct iwl_eeprom_calib_measure *omeas;
1588 u32 ch_i1;
1589 u32 ch_i2;
1590
1591 s = iwl4965_get_sub_band(priv, channel);
1592 if (s >= EEPROM_TX_POWER_BANDS) {
1593 IWL_ERROR("Tx Power can not find channel %d ", channel);
1594 return -1;
1595 }
1596
1597 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1598 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
1599 chan_info->ch_num = (u8) channel;
1600
1601 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1602 channel, s, ch_i1, ch_i2);
1603
1604 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1605 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1606 m1 = &(priv->calib_info->band_info[s].ch1.
1607 measurements[c][m]);
1608 m2 = &(priv->calib_info->band_info[s].ch2.
1609 measurements[c][m]);
1610 omeas = &(chan_info->measurements[c][m]);
1611
1612 omeas->actual_pow =
1613 (u8) iwl4965_interpolate_value(channel, ch_i1,
1614 m1->actual_pow,
1615 ch_i2,
1616 m2->actual_pow);
1617 omeas->gain_idx =
1618 (u8) iwl4965_interpolate_value(channel, ch_i1,
1619 m1->gain_idx, ch_i2,
1620 m2->gain_idx);
1621 omeas->temperature =
1622 (u8) iwl4965_interpolate_value(channel, ch_i1,
1623 m1->temperature,
1624 ch_i2,
1625 m2->temperature);
1626 omeas->pa_det =
1627 (s8) iwl4965_interpolate_value(channel, ch_i1,
1628 m1->pa_det, ch_i2,
1629 m2->pa_det);
1630
1631 IWL_DEBUG_TXPOWER
1632 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1633 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1634 IWL_DEBUG_TXPOWER
1635 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1636 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1637 IWL_DEBUG_TXPOWER
1638 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1639 m1->pa_det, m2->pa_det, omeas->pa_det);
1640 IWL_DEBUG_TXPOWER
1641 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1642 m1->temperature, m2->temperature,
1643 omeas->temperature);
1644 }
1645 }
1646
1647 return 0;
1648 }
1649
1650 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1651 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1652 static s32 back_off_table[] = {
1653 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1654 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1655 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1656 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1657 10 /* CCK */
1658 };
1659
1660 /* Thermal compensation values for txpower for various frequency ranges ...
1661 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1662 static struct iwl4965_txpower_comp_entry {
1663 s32 degrees_per_05db_a;
1664 s32 degrees_per_05db_a_denom;
1665 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1666 {9, 2}, /* group 0 5.2, ch 34-43 */
1667 {4, 1}, /* group 1 5.2, ch 44-70 */
1668 {4, 1}, /* group 2 5.2, ch 71-124 */
1669 {4, 1}, /* group 3 5.2, ch 125-200 */
1670 {3, 1} /* group 4 2.4, ch all */
1671 };
1672
1673 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1674 {
1675 if (!band) {
1676 if ((rate_power_index & 7) <= 4)
1677 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1678 }
1679 return MIN_TX_GAIN_INDEX;
1680 }
1681
1682 struct gain_entry {
1683 u8 dsp;
1684 u8 radio;
1685 };
1686
1687 static const struct gain_entry gain_table[2][108] = {
1688 /* 5.2GHz power gain index table */
1689 {
1690 {123, 0x3F}, /* highest txpower */
1691 {117, 0x3F},
1692 {110, 0x3F},
1693 {104, 0x3F},
1694 {98, 0x3F},
1695 {110, 0x3E},
1696 {104, 0x3E},
1697 {98, 0x3E},
1698 {110, 0x3D},
1699 {104, 0x3D},
1700 {98, 0x3D},
1701 {110, 0x3C},
1702 {104, 0x3C},
1703 {98, 0x3C},
1704 {110, 0x3B},
1705 {104, 0x3B},
1706 {98, 0x3B},
1707 {110, 0x3A},
1708 {104, 0x3A},
1709 {98, 0x3A},
1710 {110, 0x39},
1711 {104, 0x39},
1712 {98, 0x39},
1713 {110, 0x38},
1714 {104, 0x38},
1715 {98, 0x38},
1716 {110, 0x37},
1717 {104, 0x37},
1718 {98, 0x37},
1719 {110, 0x36},
1720 {104, 0x36},
1721 {98, 0x36},
1722 {110, 0x35},
1723 {104, 0x35},
1724 {98, 0x35},
1725 {110, 0x34},
1726 {104, 0x34},
1727 {98, 0x34},
1728 {110, 0x33},
1729 {104, 0x33},
1730 {98, 0x33},
1731 {110, 0x32},
1732 {104, 0x32},
1733 {98, 0x32},
1734 {110, 0x31},
1735 {104, 0x31},
1736 {98, 0x31},
1737 {110, 0x30},
1738 {104, 0x30},
1739 {98, 0x30},
1740 {110, 0x25},
1741 {104, 0x25},
1742 {98, 0x25},
1743 {110, 0x24},
1744 {104, 0x24},
1745 {98, 0x24},
1746 {110, 0x23},
1747 {104, 0x23},
1748 {98, 0x23},
1749 {110, 0x22},
1750 {104, 0x18},
1751 {98, 0x18},
1752 {110, 0x17},
1753 {104, 0x17},
1754 {98, 0x17},
1755 {110, 0x16},
1756 {104, 0x16},
1757 {98, 0x16},
1758 {110, 0x15},
1759 {104, 0x15},
1760 {98, 0x15},
1761 {110, 0x14},
1762 {104, 0x14},
1763 {98, 0x14},
1764 {110, 0x13},
1765 {104, 0x13},
1766 {98, 0x13},
1767 {110, 0x12},
1768 {104, 0x08},
1769 {98, 0x08},
1770 {110, 0x07},
1771 {104, 0x07},
1772 {98, 0x07},
1773 {110, 0x06},
1774 {104, 0x06},
1775 {98, 0x06},
1776 {110, 0x05},
1777 {104, 0x05},
1778 {98, 0x05},
1779 {110, 0x04},
1780 {104, 0x04},
1781 {98, 0x04},
1782 {110, 0x03},
1783 {104, 0x03},
1784 {98, 0x03},
1785 {110, 0x02},
1786 {104, 0x02},
1787 {98, 0x02},
1788 {110, 0x01},
1789 {104, 0x01},
1790 {98, 0x01},
1791 {110, 0x00},
1792 {104, 0x00},
1793 {98, 0x00},
1794 {93, 0x00},
1795 {88, 0x00},
1796 {83, 0x00},
1797 {78, 0x00},
1798 },
1799 /* 2.4GHz power gain index table */
1800 {
1801 {110, 0x3f}, /* highest txpower */
1802 {104, 0x3f},
1803 {98, 0x3f},
1804 {110, 0x3e},
1805 {104, 0x3e},
1806 {98, 0x3e},
1807 {110, 0x3d},
1808 {104, 0x3d},
1809 {98, 0x3d},
1810 {110, 0x3c},
1811 {104, 0x3c},
1812 {98, 0x3c},
1813 {110, 0x3b},
1814 {104, 0x3b},
1815 {98, 0x3b},
1816 {110, 0x3a},
1817 {104, 0x3a},
1818 {98, 0x3a},
1819 {110, 0x39},
1820 {104, 0x39},
1821 {98, 0x39},
1822 {110, 0x38},
1823 {104, 0x38},
1824 {98, 0x38},
1825 {110, 0x37},
1826 {104, 0x37},
1827 {98, 0x37},
1828 {110, 0x36},
1829 {104, 0x36},
1830 {98, 0x36},
1831 {110, 0x35},
1832 {104, 0x35},
1833 {98, 0x35},
1834 {110, 0x34},
1835 {104, 0x34},
1836 {98, 0x34},
1837 {110, 0x33},
1838 {104, 0x33},
1839 {98, 0x33},
1840 {110, 0x32},
1841 {104, 0x32},
1842 {98, 0x32},
1843 {110, 0x31},
1844 {104, 0x31},
1845 {98, 0x31},
1846 {110, 0x30},
1847 {104, 0x30},
1848 {98, 0x30},
1849 {110, 0x6},
1850 {104, 0x6},
1851 {98, 0x6},
1852 {110, 0x5},
1853 {104, 0x5},
1854 {98, 0x5},
1855 {110, 0x4},
1856 {104, 0x4},
1857 {98, 0x4},
1858 {110, 0x3},
1859 {104, 0x3},
1860 {98, 0x3},
1861 {110, 0x2},
1862 {104, 0x2},
1863 {98, 0x2},
1864 {110, 0x1},
1865 {104, 0x1},
1866 {98, 0x1},
1867 {110, 0x0},
1868 {104, 0x0},
1869 {98, 0x0},
1870 {97, 0},
1871 {96, 0},
1872 {95, 0},
1873 {94, 0},
1874 {93, 0},
1875 {92, 0},
1876 {91, 0},
1877 {90, 0},
1878 {89, 0},
1879 {88, 0},
1880 {87, 0},
1881 {86, 0},
1882 {85, 0},
1883 {84, 0},
1884 {83, 0},
1885 {82, 0},
1886 {81, 0},
1887 {80, 0},
1888 {79, 0},
1889 {78, 0},
1890 {77, 0},
1891 {76, 0},
1892 {75, 0},
1893 {74, 0},
1894 {73, 0},
1895 {72, 0},
1896 {71, 0},
1897 {70, 0},
1898 {69, 0},
1899 {68, 0},
1900 {67, 0},
1901 {66, 0},
1902 {65, 0},
1903 {64, 0},
1904 {63, 0},
1905 {62, 0},
1906 {61, 0},
1907 {60, 0},
1908 {59, 0},
1909 }
1910 };
1911
1912 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1913 u8 is_fat, u8 ctrl_chan_high,
1914 struct iwl4965_tx_power_db *tx_power_tbl)
1915 {
1916 u8 saturation_power;
1917 s32 target_power;
1918 s32 user_target_power;
1919 s32 power_limit;
1920 s32 current_temp;
1921 s32 reg_limit;
1922 s32 current_regulatory;
1923 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1924 int i;
1925 int c;
1926 const struct iwl_channel_info *ch_info = NULL;
1927 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1928 const struct iwl_eeprom_calib_measure *measurement;
1929 s16 voltage;
1930 s32 init_voltage;
1931 s32 voltage_compensation;
1932 s32 degrees_per_05db_num;
1933 s32 degrees_per_05db_denom;
1934 s32 factory_temp;
1935 s32 temperature_comp[2];
1936 s32 factory_gain_index[2];
1937 s32 factory_actual_pwr[2];
1938 s32 power_index;
1939
1940 /* Sanity check requested level (dBm) */
1941 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1942 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1943 priv->user_txpower_limit);
1944 return -EINVAL;
1945 }
1946 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1947 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1948 priv->user_txpower_limit);
1949 return -EINVAL;
1950 }
1951
1952 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1953 * are used for indexing into txpower table) */
1954 user_target_power = 2 * priv->user_txpower_limit;
1955
1956 /* Get current (RXON) channel, band, width */
1957 ch_info =
1958 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1959
1960 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1961 is_fat);
1962
1963 if (!ch_info)
1964 return -EINVAL;
1965
1966 /* get txatten group, used to select 1) thermal txpower adjustment
1967 * and 2) mimo txpower balance between Tx chains. */
1968 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1969 if (txatten_grp < 0)
1970 return -EINVAL;
1971
1972 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1973 channel, txatten_grp);
1974
1975 if (is_fat) {
1976 if (ctrl_chan_high)
1977 channel -= 2;
1978 else
1979 channel += 2;
1980 }
1981
1982 /* hardware txpower limits ...
1983 * saturation (clipping distortion) txpowers are in half-dBm */
1984 if (band)
1985 saturation_power = priv->calib_info->saturation_power24;
1986 else
1987 saturation_power = priv->calib_info->saturation_power52;
1988
1989 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1990 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1991 if (band)
1992 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1993 else
1994 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1995 }
1996
1997 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1998 * max_power_avg values are in dBm, convert * 2 */
1999 if (is_fat)
2000 reg_limit = ch_info->fat_max_power_avg * 2;
2001 else
2002 reg_limit = ch_info->max_power_avg * 2;
2003
2004 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2005 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2006 if (band)
2007 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2008 else
2009 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2010 }
2011
2012 /* Interpolate txpower calibration values for this channel,
2013 * based on factory calibration tests on spaced channels. */
2014 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2015
2016 /* calculate tx gain adjustment based on power supply voltage */
2017 voltage = priv->calib_info->voltage;
2018 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2019 voltage_compensation =
2020 iwl4965_get_voltage_compensation(voltage, init_voltage);
2021
2022 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2023 init_voltage,
2024 voltage, voltage_compensation);
2025
2026 /* get current temperature (Celsius) */
2027 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2028 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2029 current_temp = KELVIN_TO_CELSIUS(current_temp);
2030
2031 /* select thermal txpower adjustment params, based on channel group
2032 * (same frequency group used for mimo txatten adjustment) */
2033 degrees_per_05db_num =
2034 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2035 degrees_per_05db_denom =
2036 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2037
2038 /* get per-chain txpower values from factory measurements */
2039 for (c = 0; c < 2; c++) {
2040 measurement = &ch_eeprom_info.measurements[c][1];
2041
2042 /* txgain adjustment (in half-dB steps) based on difference
2043 * between factory and current temperature */
2044 factory_temp = measurement->temperature;
2045 iwl4965_math_div_round((current_temp - factory_temp) *
2046 degrees_per_05db_denom,
2047 degrees_per_05db_num,
2048 &temperature_comp[c]);
2049
2050 factory_gain_index[c] = measurement->gain_idx;
2051 factory_actual_pwr[c] = measurement->actual_pow;
2052
2053 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2054 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2055 "curr tmp %d, comp %d steps\n",
2056 factory_temp, current_temp,
2057 temperature_comp[c]);
2058
2059 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2060 factory_gain_index[c],
2061 factory_actual_pwr[c]);
2062 }
2063
2064 /* for each of 33 bit-rates (including 1 for CCK) */
2065 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2066 u8 is_mimo_rate;
2067 union iwl4965_tx_power_dual_stream tx_power;
2068
2069 /* for mimo, reduce each chain's txpower by half
2070 * (3dB, 6 steps), so total output power is regulatory
2071 * compliant. */
2072 if (i & 0x8) {
2073 current_regulatory = reg_limit -
2074 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2075 is_mimo_rate = 1;
2076 } else {
2077 current_regulatory = reg_limit;
2078 is_mimo_rate = 0;
2079 }
2080
2081 /* find txpower limit, either hardware or regulatory */
2082 power_limit = saturation_power - back_off_table[i];
2083 if (power_limit > current_regulatory)
2084 power_limit = current_regulatory;
2085
2086 /* reduce user's txpower request if necessary
2087 * for this rate on this channel */
2088 target_power = user_target_power;
2089 if (target_power > power_limit)
2090 target_power = power_limit;
2091
2092 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2093 i, saturation_power - back_off_table[i],
2094 current_regulatory, user_target_power,
2095 target_power);
2096
2097 /* for each of 2 Tx chains (radio transmitters) */
2098 for (c = 0; c < 2; c++) {
2099 s32 atten_value;
2100
2101 if (is_mimo_rate)
2102 atten_value =
2103 (s32)le32_to_cpu(priv->card_alive_init.
2104 tx_atten[txatten_grp][c]);
2105 else
2106 atten_value = 0;
2107
2108 /* calculate index; higher index means lower txpower */
2109 power_index = (u8) (factory_gain_index[c] -
2110 (target_power -
2111 factory_actual_pwr[c]) -
2112 temperature_comp[c] -
2113 voltage_compensation +
2114 atten_value);
2115
2116 /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2117 power_index); */
2118
2119 if (power_index < get_min_power_index(i, band))
2120 power_index = get_min_power_index(i, band);
2121
2122 /* adjust 5 GHz index to support negative indexes */
2123 if (!band)
2124 power_index += 9;
2125
2126 /* CCK, rate 32, reduce txpower for CCK */
2127 if (i == POWER_TABLE_CCK_ENTRY)
2128 power_index +=
2129 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2130
2131 /* stay within the table! */
2132 if (power_index > 107) {
2133 IWL_WARNING("txpower index %d > 107\n",
2134 power_index);
2135 power_index = 107;
2136 }
2137 if (power_index < 0) {
2138 IWL_WARNING("txpower index %d < 0\n",
2139 power_index);
2140 power_index = 0;
2141 }
2142
2143 /* fill txpower command for this rate/chain */
2144 tx_power.s.radio_tx_gain[c] =
2145 gain_table[band][power_index].radio;
2146 tx_power.s.dsp_predis_atten[c] =
2147 gain_table[band][power_index].dsp;
2148
2149 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2150 "gain 0x%02x dsp %d\n",
2151 c, atten_value, power_index,
2152 tx_power.s.radio_tx_gain[c],
2153 tx_power.s.dsp_predis_atten[c]);
2154 }/* for each chain */
2155
2156 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2157
2158 }/* for each rate */
2159
2160 return 0;
2161 }
2162
2163 /**
2164 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
2165 *
2166 * Uses the active RXON for channel, band, and characteristics (fat, high)
2167 * The power limit is taken from priv->user_txpower_limit.
2168 */
2169 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2170 {
2171 struct iwl4965_txpowertable_cmd cmd = { 0 };
2172 int ret;
2173 u8 band = 0;
2174 u8 is_fat = 0;
2175 u8 ctrl_chan_high = 0;
2176
2177 if (test_bit(STATUS_SCANNING, &priv->status)) {
2178 /* If this gets hit a lot, switch it to a BUG() and catch
2179 * the stack trace to find out who is calling this during
2180 * a scan. */
2181 IWL_WARNING("TX Power requested while scanning!\n");
2182 return -EAGAIN;
2183 }
2184
2185 band = priv->band == IEEE80211_BAND_2GHZ;
2186
2187 is_fat = is_fat_channel(priv->active_rxon.flags);
2188
2189 if (is_fat &&
2190 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2191 ctrl_chan_high = 1;
2192
2193 cmd.band = band;
2194 cmd.channel = priv->active_rxon.channel;
2195
2196 ret = iwl4965_fill_txpower_tbl(priv, band,
2197 le16_to_cpu(priv->active_rxon.channel),
2198 is_fat, ctrl_chan_high, &cmd.tx_power);
2199 if (ret)
2200 goto out;
2201
2202 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2203
2204 out:
2205 return ret;
2206 }
2207
2208 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2209 {
2210 int ret = 0;
2211 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2212 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2213 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2214
2215 if ((rxon1->flags == rxon2->flags) &&
2216 (rxon1->filter_flags == rxon2->filter_flags) &&
2217 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2218 (rxon1->ofdm_ht_single_stream_basic_rates ==
2219 rxon2->ofdm_ht_single_stream_basic_rates) &&
2220 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2221 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2222 (rxon1->rx_chain == rxon2->rx_chain) &&
2223 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2224 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2225 return 0;
2226 }
2227
2228 rxon_assoc.flags = priv->staging_rxon.flags;
2229 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2230 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2231 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2232 rxon_assoc.reserved = 0;
2233 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2234 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2235 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2236 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2237 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2238
2239 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2240 sizeof(rxon_assoc), &rxon_assoc, NULL);
2241 if (ret)
2242 return ret;
2243
2244 return ret;
2245 }
2246
2247
2248 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2249 {
2250 int rc;
2251 u8 band = 0;
2252 u8 is_fat = 0;
2253 u8 ctrl_chan_high = 0;
2254 struct iwl4965_channel_switch_cmd cmd = { 0 };
2255 const struct iwl_channel_info *ch_info;
2256
2257 band = priv->band == IEEE80211_BAND_2GHZ;
2258
2259 ch_info = iwl_get_channel_info(priv, priv->band, channel);
2260
2261 is_fat = is_fat_channel(priv->staging_rxon.flags);
2262
2263 if (is_fat &&
2264 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2265 ctrl_chan_high = 1;
2266
2267 cmd.band = band;
2268 cmd.expect_beacon = 0;
2269 cmd.channel = cpu_to_le16(channel);
2270 cmd.rxon_flags = priv->active_rxon.flags;
2271 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2272 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2273 if (ch_info)
2274 cmd.expect_beacon = is_channel_radar(ch_info);
2275 else
2276 cmd.expect_beacon = 1;
2277
2278 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2279 ctrl_chan_high, &cmd.tx_power);
2280 if (rc) {
2281 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2282 return rc;
2283 }
2284
2285 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2286 return rc;
2287 }
2288
2289 #define RTS_HCCA_RETRY_LIMIT 3
2290 #define RTS_DFAULT_RETRY_LIMIT 60
2291
2292 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2293 struct iwl_cmd *cmd,
2294 struct ieee80211_tx_control *ctrl,
2295 struct ieee80211_hdr *hdr, int sta_id,
2296 int is_hcca)
2297 {
2298 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2299 u8 rts_retry_limit = 0;
2300 u8 data_retry_limit = 0;
2301 u16 fc = le16_to_cpu(hdr->frame_control);
2302 u8 rate_plcp;
2303 u16 rate_flags = 0;
2304 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2305
2306 rate_plcp = iwl4965_rates[rate_idx].plcp;
2307
2308 rts_retry_limit = (is_hcca) ?
2309 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2310
2311 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2312 rate_flags |= RATE_MCS_CCK_MSK;
2313
2314
2315 if (ieee80211_is_probe_response(fc)) {
2316 data_retry_limit = 3;
2317 if (data_retry_limit < rts_retry_limit)
2318 rts_retry_limit = data_retry_limit;
2319 } else
2320 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2321
2322 if (priv->data_retry_limit != -1)
2323 data_retry_limit = priv->data_retry_limit;
2324
2325
2326 if (ieee80211_is_data(fc)) {
2327 tx->initial_rate_index = 0;
2328 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2329 } else {
2330 switch (fc & IEEE80211_FCTL_STYPE) {
2331 case IEEE80211_STYPE_AUTH:
2332 case IEEE80211_STYPE_DEAUTH:
2333 case IEEE80211_STYPE_ASSOC_REQ:
2334 case IEEE80211_STYPE_REASSOC_REQ:
2335 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2336 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2337 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2338 }
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 /* Alternate between antenna A and B for successive frames */
2345 if (priv->use_ant_b_for_management_frame) {
2346 priv->use_ant_b_for_management_frame = 0;
2347 rate_flags |= RATE_MCS_ANT_B_MSK;
2348 } else {
2349 priv->use_ant_b_for_management_frame = 1;
2350 rate_flags |= RATE_MCS_ANT_A_MSK;
2351 }
2352 }
2353
2354 tx->rts_retry_limit = rts_retry_limit;
2355 tx->data_retry_limit = data_retry_limit;
2356 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2357 }
2358
2359 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2360 {
2361 struct iwl4965_shared *s = priv->shared_virt;
2362 return le32_to_cpu(s->rb_closed) & 0xFFF;
2363 }
2364
2365 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2366 {
2367 return priv->temperature;
2368 }
2369
2370 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2371 struct iwl4965_frame *frame, u8 rate)
2372 {
2373 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2374 unsigned int frame_size;
2375
2376 tx_beacon_cmd = &frame->u.beacon;
2377 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2378
2379 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2380 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2381
2382 frame_size = iwl4965_fill_beacon_frame(priv,
2383 tx_beacon_cmd->frame,
2384 iwl4965_broadcast_addr,
2385 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2386
2387 BUG_ON(frame_size > MAX_MPDU_SIZE);
2388 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2389
2390 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2391 tx_beacon_cmd->tx.rate_n_flags =
2392 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2393 else
2394 tx_beacon_cmd->tx.rate_n_flags =
2395 iwl4965_hw_set_rate_n_flags(rate, 0);
2396
2397 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2398 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2399 return (sizeof(*tx_beacon_cmd) + frame_size);
2400 }
2401
2402 /*
2403 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2404 * given Tx queue, and enable the DMA channel used for that queue.
2405 *
2406 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2407 * channels supported in hardware.
2408 */
2409 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2410 {
2411 int rc;
2412 unsigned long flags;
2413 int txq_id = txq->q.id;
2414
2415 spin_lock_irqsave(&priv->lock, flags);
2416 rc = iwl_grab_nic_access(priv);
2417 if (rc) {
2418 spin_unlock_irqrestore(&priv->lock, flags);
2419 return rc;
2420 }
2421
2422 /* Circular buffer (TFD queue in DRAM) physical base address */
2423 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2424 txq->q.dma_addr >> 8);
2425
2426 /* Enable DMA channel, using same id as for TFD queue */
2427 iwl_write_direct32(
2428 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2429 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2430 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2431 iwl_release_nic_access(priv);
2432 spin_unlock_irqrestore(&priv->lock, flags);
2433
2434 return 0;
2435 }
2436
2437 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2438 dma_addr_t addr, u16 len)
2439 {
2440 int index, is_odd;
2441 struct iwl4965_tfd_frame *tfd = ptr;
2442 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2443
2444 /* Each TFD can point to a maximum 20 Tx buffers */
2445 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2446 IWL_ERROR("Error can not send more than %d chunks\n",
2447 MAX_NUM_OF_TBS);
2448 return -EINVAL;
2449 }
2450
2451 index = num_tbs / 2;
2452 is_odd = num_tbs & 0x1;
2453
2454 if (!is_odd) {
2455 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2456 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2457 iwl_get_dma_hi_address(addr));
2458 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2459 } else {
2460 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2461 (u32) (addr & 0xffff));
2462 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2463 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2464 }
2465
2466 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2467
2468 return 0;
2469 }
2470
2471 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2472 {
2473 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
2474
2475 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2476 ((hw_version >> 8) & 0x0F),
2477 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2478
2479 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2480 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
2481 }
2482
2483 static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
2484 {
2485 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
2486 sizeof(struct iwl4965_shared),
2487 &priv->shared_phys);
2488 if (!priv->shared_virt)
2489 return -ENOMEM;
2490
2491 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
2492
2493 return 0;
2494 }
2495
2496 static void iwl4965_free_shared_mem(struct iwl_priv *priv)
2497 {
2498 if (priv->shared_virt)
2499 pci_free_consistent(priv->pci_dev,
2500 sizeof(struct iwl4965_shared),
2501 priv->shared_virt,
2502 priv->shared_phys);
2503 }
2504
2505 /**
2506 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2507 */
2508 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2509 struct iwl4965_tx_queue *txq,
2510 u16 byte_cnt)
2511 {
2512 int len;
2513 int txq_id = txq->q.id;
2514 struct iwl4965_shared *shared_data = priv->shared_virt;
2515
2516 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2517
2518 /* Set up byte count within first 256 entries */
2519 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2520 tfd_offset[txq->q.write_ptr], byte_cnt, len);
2521
2522 /* If within first 64 entries, duplicate at end */
2523 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
2524 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2525 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
2526 byte_cnt, len);
2527 }
2528
2529 /**
2530 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2531 *
2532 * Selects how many and which Rx receivers/antennas/chains to use.
2533 * This should not be used for scan command ... it puts data in wrong place.
2534 */
2535 void iwl4965_set_rxon_chain(struct iwl_priv *priv)
2536 {
2537 u8 is_single = is_single_rx_stream(priv);
2538 u8 idle_state, rx_state;
2539
2540 priv->staging_rxon.rx_chain = 0;
2541 rx_state = idle_state = 3;
2542
2543 /* Tell uCode which antennas are actually connected.
2544 * Before first association, we assume all antennas are connected.
2545 * Just after first association, iwl_chain_noise_calibration()
2546 * checks which antennas actually *are* connected. */
2547 priv->staging_rxon.rx_chain |=
2548 cpu_to_le16(priv->hw_params.valid_rx_ant <<
2549 RXON_RX_CHAIN_VALID_POS);
2550
2551 /* How many receivers should we use? */
2552 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2553 priv->staging_rxon.rx_chain |=
2554 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2555 priv->staging_rxon.rx_chain |=
2556 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2557
2558 if (!is_single && (rx_state >= 2) &&
2559 !test_bit(STATUS_POWER_PMI, &priv->status))
2560 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2561 else
2562 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2563
2564 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2565 }
2566
2567 /**
2568 * sign_extend - Sign extend a value using specified bit as sign-bit
2569 *
2570 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2571 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2572 *
2573 * @param oper value to sign extend
2574 * @param index 0 based bit index (0<=index<32) to sign bit
2575 */
2576 static s32 sign_extend(u32 oper, int index)
2577 {
2578 u8 shift = 31 - index;
2579
2580 return (s32)(oper << shift) >> shift;
2581 }
2582
2583 /**
2584 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2585 * @statistics: Provides the temperature reading from the uCode
2586 *
2587 * A return of <0 indicates bogus data in the statistics
2588 */
2589 int iwl4965_get_temperature(const struct iwl_priv *priv)
2590 {
2591 s32 temperature;
2592 s32 vt;
2593 s32 R1, R2, R3;
2594 u32 R4;
2595
2596 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2597 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2598 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2599 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2600 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2601 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2602 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2603 } else {
2604 IWL_DEBUG_TEMP("Running temperature calibration\n");
2605 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2606 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2607 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2608 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2609 }
2610
2611 /*
2612 * Temperature is only 23 bits, so sign extend out to 32.
2613 *
2614 * NOTE If we haven't received a statistics notification yet
2615 * with an updated temperature, use R4 provided to us in the
2616 * "initialize" ALIVE response.
2617 */
2618 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2619 vt = sign_extend(R4, 23);
2620 else
2621 vt = sign_extend(
2622 le32_to_cpu(priv->statistics.general.temperature), 23);
2623
2624 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2625 R1, R2, R3, vt);
2626
2627 if (R3 == R1) {
2628 IWL_ERROR("Calibration conflict R1 == R3\n");
2629 return -1;
2630 }
2631
2632 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2633 * Add offset to center the adjustment around 0 degrees Centigrade. */
2634 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2635 temperature /= (R3 - R1);
2636 temperature = (temperature * 97) / 100 +
2637 TEMPERATURE_CALIB_KELVIN_OFFSET;
2638
2639 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2640 KELVIN_TO_CELSIUS(temperature));
2641
2642 return temperature;
2643 }
2644
2645 /* Adjust Txpower only if temperature variance is greater than threshold. */
2646 #define IWL_TEMPERATURE_THRESHOLD 3
2647
2648 /**
2649 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2650 *
2651 * If the temperature changed has changed sufficiently, then a recalibration
2652 * is needed.
2653 *
2654 * Assumes caller will replace priv->last_temperature once calibration
2655 * executed.
2656 */
2657 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2658 {
2659 int temp_diff;
2660
2661 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2662 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2663 return 0;
2664 }
2665
2666 temp_diff = priv->temperature - priv->last_temperature;
2667
2668 /* get absolute value */
2669 if (temp_diff < 0) {
2670 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2671 temp_diff = -temp_diff;
2672 } else if (temp_diff == 0)
2673 IWL_DEBUG_POWER("Same temp, \n");
2674 else
2675 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2676
2677 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2678 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2679 return 0;
2680 }
2681
2682 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2683
2684 return 1;
2685 }
2686
2687 /* Calculate noise level, based on measurements during network silence just
2688 * before arriving beacon. This measurement can be done only if we know
2689 * exactly when to expect beacons, therefore only when we're associated. */
2690 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2691 {
2692 struct statistics_rx_non_phy *rx_info
2693 = &(priv->statistics.rx.general);
2694 int num_active_rx = 0;
2695 int total_silence = 0;
2696 int bcn_silence_a =
2697 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2698 int bcn_silence_b =
2699 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2700 int bcn_silence_c =
2701 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2702
2703 if (bcn_silence_a) {
2704 total_silence += bcn_silence_a;
2705 num_active_rx++;
2706 }
2707 if (bcn_silence_b) {
2708 total_silence += bcn_silence_b;
2709 num_active_rx++;
2710 }
2711 if (bcn_silence_c) {
2712 total_silence += bcn_silence_c;
2713 num_active_rx++;
2714 }
2715
2716 /* Average among active antennas */
2717 if (num_active_rx)
2718 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2719 else
2720 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2721
2722 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2723 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2724 priv->last_rx_noise);
2725 }
2726
2727 void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
2728 {
2729 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2730 int change;
2731 s32 temp;
2732
2733 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2734 (int)sizeof(priv->statistics), pkt->len);
2735
2736 change = ((priv->statistics.general.temperature !=
2737 pkt->u.stats.general.temperature) ||
2738 ((priv->statistics.flag &
2739 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2740 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2741
2742 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2743
2744 set_bit(STATUS_STATISTICS, &priv->status);
2745
2746 /* Reschedule the statistics timer to occur in
2747 * REG_RECALIB_PERIOD seconds to ensure we get a
2748 * thermal update even if the uCode doesn't give
2749 * us one */
2750 mod_timer(&priv->statistics_periodic, jiffies +
2751 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2752
2753 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2754 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2755 iwl4965_rx_calc_noise(priv);
2756 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2757 queue_work(priv->workqueue, &priv->sensitivity_work);
2758 #endif
2759 }
2760
2761 iwl_leds_background(priv);
2762
2763 /* If the hardware hasn't reported a change in
2764 * temperature then don't bother computing a
2765 * calibrated temperature value */
2766 if (!change)
2767 return;
2768
2769 temp = iwl4965_get_temperature(priv);
2770 if (temp < 0)
2771 return;
2772
2773 if (priv->temperature != temp) {
2774 if (priv->temperature)
2775 IWL_DEBUG_TEMP("Temperature changed "
2776 "from %dC to %dC\n",
2777 KELVIN_TO_CELSIUS(priv->temperature),
2778 KELVIN_TO_CELSIUS(temp));
2779 else
2780 IWL_DEBUG_TEMP("Temperature "
2781 "initialized to %dC\n",
2782 KELVIN_TO_CELSIUS(temp));
2783 }
2784
2785 priv->temperature = temp;
2786 set_bit(STATUS_TEMPERATURE, &priv->status);
2787
2788 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2789 iwl4965_is_temp_calib_needed(priv))
2790 queue_work(priv->workqueue, &priv->txpower_work);
2791 }
2792
2793 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2794 struct sk_buff *skb,
2795 struct iwl4965_rx_phy_res *rx_start,
2796 struct ieee80211_rx_status *stats,
2797 u32 ampdu_status)
2798 {
2799 s8 signal = stats->ssi;
2800 s8 noise = 0;
2801 int rate = stats->rate_idx;
2802 u64 tsf = stats->mactime;
2803 __le16 antenna;
2804 __le16 phy_flags_hw = rx_start->phy_flags;
2805 struct iwl4965_rt_rx_hdr {
2806 struct ieee80211_radiotap_header rt_hdr;
2807 __le64 rt_tsf; /* TSF */
2808 u8 rt_flags; /* radiotap packet flags */
2809 u8 rt_rate; /* rate in 500kb/s */
2810 __le16 rt_channelMHz; /* channel in MHz */
2811 __le16 rt_chbitmask; /* channel bitfield */
2812 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2813 s8 rt_dbmnoise;
2814 u8 rt_antenna; /* antenna number */
2815 } __attribute__ ((packed)) *iwl4965_rt;
2816
2817 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2818 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2819 if (net_ratelimit())
2820 printk(KERN_ERR "not enough headroom [%d] for "
2821 "radiotap head [%zd]\n",
2822 skb_headroom(skb), sizeof(*iwl4965_rt));
2823 return;
2824 }
2825
2826 /* put radiotap header in front of 802.11 header and data */
2827 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2828
2829 /* initialise radiotap header */
2830 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2831 iwl4965_rt->rt_hdr.it_pad = 0;
2832
2833 /* total header + data */
2834 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2835 &iwl4965_rt->rt_hdr.it_len);
2836
2837 /* Indicate all the fields we add to the radiotap header */
2838 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2839 (1 << IEEE80211_RADIOTAP_FLAGS) |
2840 (1 << IEEE80211_RADIOTAP_RATE) |
2841 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2842 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2843 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2844 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2845 &iwl4965_rt->rt_hdr.it_present);
2846
2847 /* Zero the flags, we'll add to them as we go */
2848 iwl4965_rt->rt_flags = 0;
2849
2850 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2851
2852 iwl4965_rt->rt_dbmsignal = signal;
2853 iwl4965_rt->rt_dbmnoise = noise;
2854
2855 /* Convert the channel frequency and set the flags */
2856 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2857 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2858 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2859 IEEE80211_CHAN_5GHZ),
2860 &iwl4965_rt->rt_chbitmask);
2861 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2862 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2863 IEEE80211_CHAN_2GHZ),
2864 &iwl4965_rt->rt_chbitmask);
2865 else /* 802.11g */
2866 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2867 IEEE80211_CHAN_2GHZ),
2868 &iwl4965_rt->rt_chbitmask);
2869
2870 if (rate == -1)
2871 iwl4965_rt->rt_rate = 0;
2872 else
2873 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2874
2875 /*
2876 * "antenna number"
2877 *
2878 * It seems that the antenna field in the phy flags value
2879 * is actually a bitfield. This is undefined by radiotap,
2880 * it wants an actual antenna number but I always get "7"
2881 * for most legacy frames I receive indicating that the
2882 * same frame was received on all three RX chains.
2883 *
2884 * I think this field should be removed in favour of a
2885 * new 802.11n radiotap field "RX chains" that is defined
2886 * as a bitmask.
2887 */
2888 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2889 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2890
2891 /* set the preamble flag if appropriate */
2892 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2893 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2894
2895 stats->flag |= RX_FLAG_RADIOTAP;
2896 }
2897
2898 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2899 {
2900 /* 0 - mgmt, 1 - cnt, 2 - data */
2901 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2902 priv->rx_stats[idx].cnt++;
2903 priv->rx_stats[idx].bytes += len;
2904 }
2905
2906 /*
2907 * returns non-zero if packet should be dropped
2908 */
2909 static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2910 struct ieee80211_hdr *hdr,
2911 u32 decrypt_res,
2912 struct ieee80211_rx_status *stats)
2913 {
2914 u16 fc = le16_to_cpu(hdr->frame_control);
2915
2916 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2917 return 0;
2918
2919 if (!(fc & IEEE80211_FCTL_PROTECTED))
2920 return 0;
2921
2922 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2923 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2924 case RX_RES_STATUS_SEC_TYPE_TKIP:
2925 /* The uCode has got a bad phase 1 Key, pushes the packet.
2926 * Decryption will be done in SW. */
2927 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2928 RX_RES_STATUS_BAD_KEY_TTAK)
2929 break;
2930
2931 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2932 RX_RES_STATUS_BAD_ICV_MIC) {
2933 /* bad ICV, the packet is destroyed since the
2934 * decryption is inplace, drop it */
2935 IWL_DEBUG_RX("Packet destroyed\n");
2936 return -1;
2937 }
2938 case RX_RES_STATUS_SEC_TYPE_WEP:
2939 case RX_RES_STATUS_SEC_TYPE_CCMP:
2940 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2941 RX_RES_STATUS_DECRYPT_OK) {
2942 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2943 stats->flag |= RX_FLAG_DECRYPTED;
2944 }
2945 break;
2946
2947 default:
2948 break;
2949 }
2950 return 0;
2951 }
2952
2953 static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2954 {
2955 u32 decrypt_out = 0;
2956
2957 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2958 RX_RES_STATUS_STATION_FOUND)
2959 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2960 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2961
2962 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2963
2964 /* packet was not encrypted */
2965 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2966 RX_RES_STATUS_SEC_TYPE_NONE)
2967 return decrypt_out;
2968
2969 /* packet was encrypted with unknown alg */
2970 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2971 RX_RES_STATUS_SEC_TYPE_ERR)
2972 return decrypt_out;
2973
2974 /* decryption was not done in HW */
2975 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2976 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2977 return decrypt_out;
2978
2979 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2980
2981 case RX_RES_STATUS_SEC_TYPE_CCMP:
2982 /* alg is CCM: check MIC only */
2983 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2984 /* Bad MIC */
2985 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2986 else
2987 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2988
2989 break;
2990
2991 case RX_RES_STATUS_SEC_TYPE_TKIP:
2992 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2993 /* Bad TTAK */
2994 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2995 break;
2996 }
2997 /* fall through if TTAK OK */
2998 default:
2999 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3000 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3001 else
3002 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3003 break;
3004 };
3005
3006 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3007 decrypt_in, decrypt_out);
3008
3009 return decrypt_out;
3010 }
3011
3012 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
3013 int include_phy,
3014 struct iwl4965_rx_mem_buffer *rxb,
3015 struct ieee80211_rx_status *stats)
3016 {
3017 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
3018 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3019 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3020 struct ieee80211_hdr *hdr;
3021 u16 len;
3022 __le32 *rx_end;
3023 unsigned int skblen;
3024 u32 ampdu_status;
3025 u32 ampdu_status_legacy;
3026
3027 if (!include_phy && priv->last_phy_res[0])
3028 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3029
3030 if (!rx_start) {
3031 IWL_ERROR("MPDU frame without a PHY data\n");
3032 return;
3033 }
3034 if (include_phy) {
3035 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3036 rx_start->cfg_phy_cnt);
3037
3038 len = le16_to_cpu(rx_start->byte_count);
3039
3040 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3041 sizeof(struct iwl4965_rx_phy_res) +
3042 rx_start->cfg_phy_cnt + len);
3043
3044 } else {
3045 struct iwl4965_rx_mpdu_res_start *amsdu =
3046 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3047
3048 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3049 sizeof(struct iwl4965_rx_mpdu_res_start));
3050 len = le16_to_cpu(amsdu->byte_count);
3051 rx_start->byte_count = amsdu->byte_count;
3052 rx_end = (__le32 *) (((u8 *) hdr) + len);
3053 }
3054 if (len > priv->hw_params.max_pkt_size || len < 16) {
3055 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
3056 return;
3057 }
3058
3059 ampdu_status = le32_to_cpu(*rx_end);
3060 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3061
3062 if (!include_phy) {
3063 /* New status scheme, need to translate */
3064 ampdu_status_legacy = ampdu_status;
3065 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3066 }
3067
3068 /* start from MAC */
3069 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3070 skb_put(rxb->skb, len); /* end where data ends */
3071
3072 /* We only process data packets if the interface is open */
3073 if (unlikely(!priv->is_open)) {
3074 IWL_DEBUG_DROP_LIMIT
3075 ("Dropping packet while interface is not open.\n");
3076 return;
3077 }
3078
3079 stats->flag = 0;
3080 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3081
3082 /* in case of HW accelerated crypto and bad decryption, drop */
3083 if (!priv->hw_params.sw_crypto &&
3084 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3085 return;
3086
3087 if (priv->add_radiotap)
3088 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3089
3090 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
3091 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3092 priv->alloc_rxb_skb--;
3093 rxb->skb = NULL;
3094 }
3095
3096 /* Calc max signal level (dBm) among 3 possible receivers */
3097 static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3098 {
3099 /* data from PHY/DSP regarding signal strength, etc.,
3100 * contents are always there, not configurable by host. */
3101 struct iwl4965_rx_non_cfg_phy *ncphy =
3102 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3103 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3104 >> IWL_AGC_DB_POS;
3105
3106 u32 valid_antennae =
3107 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3108 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3109 u8 max_rssi = 0;
3110 u32 i;
3111
3112 /* Find max rssi among 3 possible receivers.
3113 * These values are measured by the digital signal processor (DSP).
3114 * They should stay fairly constant even as the signal strength varies,
3115 * if the radio's automatic gain control (AGC) is working right.
3116 * AGC value (see below) will provide the "interesting" info. */
3117 for (i = 0; i < 3; i++)
3118 if (valid_antennae & (1 << i))
3119 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3120
3121 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3122 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3123 max_rssi, agc);
3124
3125 /* dBm = max_rssi dB - agc dB - constant.
3126 * Higher AGC (higher radio gain) means lower signal. */
3127 return (max_rssi - agc - IWL_RSSI_OFFSET);
3128 }
3129
3130 #ifdef CONFIG_IWL4965_HT
3131
3132 void iwl4965_init_ht_hw_capab(const struct iwl_priv *priv,
3133 struct ieee80211_ht_info *ht_info,
3134 enum ieee80211_band band)
3135 {
3136 ht_info->cap = 0;
3137 memset(ht_info->supp_mcs_set, 0, 16);
3138
3139 ht_info->ht_supported = 1;
3140
3141 if (priv->hw_params.fat_channel & BIT(band)) {
3142 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3143 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3144 ht_info->supp_mcs_set[4] = 0x01;
3145 }
3146 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3147 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3148 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3149 (IWL_MIMO_PS_NONE << 2));
3150
3151 if (priv->cfg->mod_params->amsdu_size_8K)
3152 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3153
3154 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3155 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3156
3157 ht_info->supp_mcs_set[0] = 0xFF;
3158 if (priv->hw_params.tx_chains_num >= 2)
3159 ht_info->supp_mcs_set[1] = 0xFF;
3160 if (priv->hw_params.tx_chains_num >= 3)
3161 ht_info->supp_mcs_set[2] = 0xFF;
3162 }
3163 #endif /* CONFIG_IWL4965_HT */
3164
3165 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
3166 {
3167 unsigned long flags;
3168
3169 spin_lock_irqsave(&priv->sta_lock, flags);
3170 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3171 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3172 priv->stations[sta_id].sta.sta.modify_mask = 0;
3173 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3174 spin_unlock_irqrestore(&priv->sta_lock, flags);
3175
3176 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3177 }
3178
3179 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
3180 {
3181 /* FIXME: need locking over ps_status ??? */
3182 u8 sta_id = iwl_find_station(priv, addr);
3183
3184 if (sta_id != IWL_INVALID_STATION) {
3185 u8 sta_awake = priv->stations[sta_id].
3186 ps_status == STA_PS_STATUS_WAKE;
3187
3188 if (sta_awake && ps_bit)
3189 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3190 else if (!sta_awake && !ps_bit) {
3191 iwl4965_sta_modify_ps_wake(priv, sta_id);
3192 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3193 }
3194 }
3195 }
3196 #ifdef CONFIG_IWLWIFI_DEBUG
3197
3198 /**
3199 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3200 *
3201 * You may hack this function to show different aspects of received frames,
3202 * including selective frame dumps.
3203 * group100 parameter selects whether to show 1 out of 100 good frames.
3204 *
3205 * TODO: This was originally written for 3945, need to audit for
3206 * proper operation with 4965.
3207 */
3208 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3209 struct iwl4965_rx_packet *pkt,
3210 struct ieee80211_hdr *header, int group100)
3211 {
3212 u32 to_us;
3213 u32 print_summary = 0;
3214 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3215 u32 hundred = 0;
3216 u32 dataframe = 0;
3217 u16 fc;
3218 u16 seq_ctl;
3219 u16 channel;
3220 u16 phy_flags;
3221 int rate_sym;
3222 u16 length;
3223 u16 status;
3224 u16 bcn_tmr;
3225 u32 tsf_low;
3226 u64 tsf;
3227 u8 rssi;
3228 u8 agc;
3229 u16 sig_avg;
3230 u16 noise_diff;
3231 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3232 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3233 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3234 u8 *data = IWL_RX_DATA(pkt);
3235
3236 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3237 return;
3238
3239 /* MAC header */
3240 fc = le16_to_cpu(header->frame_control);
3241 seq_ctl = le16_to_cpu(header->seq_ctrl);
3242
3243 /* metadata */
3244 channel = le16_to_cpu(rx_hdr->channel);
3245 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3246 rate_sym = rx_hdr->rate;
3247 length = le16_to_cpu(rx_hdr->len);
3248
3249 /* end-of-frame status and timestamp */
3250 status = le32_to_cpu(rx_end->status);
3251 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3252 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3253 tsf = le64_to_cpu(rx_end->timestamp);
3254
3255 /* signal statistics */
3256 rssi = rx_stats->rssi;
3257 agc = rx_stats->agc;
3258 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3259 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3260
3261 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3262
3263 /* if data frame is to us and all is good,
3264 * (optionally) print summary for only 1 out of every 100 */
3265 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3266 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3267 dataframe = 1;
3268 if (!group100)
3269 print_summary = 1; /* print each frame */
3270 else if (priv->framecnt_to_us < 100) {
3271 priv->framecnt_to_us++;
3272 print_summary = 0;
3273 } else {
3274 priv->framecnt_to_us = 0;
3275 print_summary = 1;
3276 hundred = 1;
3277 }
3278 } else {
3279 /* print summary for all other frames */
3280 print_summary = 1;
3281 }
3282
3283 if (print_summary) {
3284 char *title;
3285 int rate_idx;
3286 u32 bitrate;
3287
3288 if (hundred)
3289 title = "100Frames";
3290 else if (fc & IEEE80211_FCTL_RETRY)
3291 title = "Retry";
3292 else if (ieee80211_is_assoc_response(fc))
3293 title = "AscRsp";
3294 else if (ieee80211_is_reassoc_response(fc))
3295 title = "RasRsp";
3296 else if (ieee80211_is_probe_response(fc)) {
3297 title = "PrbRsp";
3298 print_dump = 1; /* dump frame contents */
3299 } else if (ieee80211_is_beacon(fc)) {
3300 title = "Beacon";
3301 print_dump = 1; /* dump frame contents */
3302 } else if (ieee80211_is_atim(fc))
3303 title = "ATIM";
3304 else if (ieee80211_is_auth(fc))
3305 title = "Auth";
3306 else if (ieee80211_is_deauth(fc))
3307 title = "DeAuth";
3308 else if (ieee80211_is_disassoc(fc))
3309 title = "DisAssoc";
3310 else
3311 title = "Frame";
3312
3313 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3314 if (unlikely(rate_idx == -1))
3315 bitrate = 0;
3316 else
3317 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3318
3319 /* print frame summary.
3320 * MAC addresses show just the last byte (for brevity),
3321 * but you can hack it to show more, if you'd like to. */
3322 if (dataframe)
3323 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3324 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3325 title, fc, header->addr1[5],
3326 length, rssi, channel, bitrate);
3327 else {
3328 /* src/dst addresses assume managed mode */
3329 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3330 "src=0x%02x, rssi=%u, tim=%lu usec, "
3331 "phy=0x%02x, chnl=%d\n",
3332 title, fc, header->addr1[5],
3333 header->addr3[5], rssi,
3334 tsf_low - priv->scan_start_tsf,
3335 phy_flags, channel);
3336 }
3337 }
3338 if (print_dump)
3339 iwl_print_hex_dump(IWL_DL_RX, data, length);
3340 }
3341 #else
3342 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3343 struct iwl4965_rx_packet *pkt,
3344 struct ieee80211_hdr *header,
3345 int group100)
3346 {
3347 }
3348 #endif
3349
3350
3351
3352 /* Called for REPLY_RX (legacy ABG frames), or
3353 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3354 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3355 struct iwl4965_rx_mem_buffer *rxb)
3356 {
3357 struct ieee80211_hdr *header;
3358 struct ieee80211_rx_status rx_status;
3359 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3360 /* Use phy data (Rx signal strength, etc.) contained within
3361 * this rx packet for legacy frames,
3362 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3363 int include_phy = (pkt->hdr.cmd == REPLY_RX);
3364 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3365 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3366 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3367 __le32 *rx_end;
3368 unsigned int len = 0;
3369 u16 fc;
3370 u8 network_packet;
3371
3372 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3373 rx_status.freq =
3374 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3375 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3376 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3377 rx_status.rate_idx =
3378 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3379 if (rx_status.band == IEEE80211_BAND_5GHZ)
3380 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3381
3382 rx_status.antenna = 0;
3383 rx_status.flag = 0;
3384
3385 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3386 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3387 rx_start->cfg_phy_cnt);
3388 return;
3389 }
3390
3391 if (!include_phy) {
3392 if (priv->last_phy_res[0])
3393 rx_start = (struct iwl4965_rx_phy_res *)
3394 &priv->last_phy_res[1];
3395 else
3396 rx_start = NULL;
3397 }
3398
3399 if (!rx_start) {
3400 IWL_ERROR("MPDU frame without a PHY data\n");
3401 return;
3402 }
3403
3404 if (include_phy) {
3405 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3406 + rx_start->cfg_phy_cnt);
3407
3408 len = le16_to_cpu(rx_start->byte_count);
3409 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3410 sizeof(struct iwl4965_rx_phy_res) + len);
3411 } else {
3412 struct iwl4965_rx_mpdu_res_start *amsdu =
3413 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3414
3415 header = (void *)(pkt->u.raw +
3416 sizeof(struct iwl4965_rx_mpdu_res_start));
3417 len = le16_to_cpu(amsdu->byte_count);
3418 rx_end = (__le32 *) (pkt->u.raw +
3419 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3420 }
3421
3422 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3423 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3424 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3425 le32_to_cpu(*rx_end));
3426 return;
3427 }
3428
3429 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3430
3431 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3432 rx_status.ssi = iwl4965_calc_rssi(rx_start);
3433
3434 /* Meaningful noise values are available only from beacon statistics,
3435 * which are gathered only when associated, and indicate noise
3436 * only for the associated network channel ...
3437 * Ignore these noise values while scanning (other channels) */
3438 if (iwl_is_associated(priv) &&
3439 !test_bit(STATUS_SCANNING, &priv->status)) {
3440 rx_status.noise = priv->last_rx_noise;
3441 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3442 rx_status.noise);
3443 } else {
3444 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3445 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3446 }
3447
3448 /* Reset beacon noise level if not associated. */
3449 if (!iwl_is_associated(priv))
3450 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3451
3452 /* Set "1" to report good data frames in groups of 100 */
3453 /* FIXME: need to optimze the call: */
3454 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3455
3456 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3457 rx_status.ssi, rx_status.noise, rx_status.signal,
3458 (unsigned long long)rx_status.mactime);
3459
3460 network_packet = iwl4965_is_network_packet(priv, header);
3461 if (network_packet) {
3462 priv->last_rx_rssi = rx_status.ssi;
3463 priv->last_beacon_time = priv->ucode_beacon_time;
3464 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3465 }
3466
3467 fc = le16_to_cpu(header->frame_control);
3468 switch (fc & IEEE80211_FCTL_FTYPE) {
3469 case IEEE80211_FTYPE_MGMT:
3470 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3471 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3472 header->addr2);
3473 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3474 break;
3475
3476 case IEEE80211_FTYPE_CTL:
3477 #ifdef CONFIG_IWL4965_HT
3478 switch (fc & IEEE80211_FCTL_STYPE) {
3479 case IEEE80211_STYPE_BACK_REQ:
3480 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3481 iwl4965_handle_data_packet(priv, 0, include_phy,
3482 rxb, &rx_status);
3483 break;
3484 default:
3485 break;
3486 }
3487 #endif
3488 break;
3489
3490 case IEEE80211_FTYPE_DATA: {
3491 DECLARE_MAC_BUF(mac1);
3492 DECLARE_MAC_BUF(mac2);
3493 DECLARE_MAC_BUF(mac3);
3494
3495 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3496 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3497 header->addr2);
3498
3499 if (unlikely(!network_packet))
3500 IWL_DEBUG_DROP("Dropping (non network): "
3501 "%s, %s, %s\n",
3502 print_mac(mac1, header->addr1),
3503 print_mac(mac2, header->addr2),
3504 print_mac(mac3, header->addr3));
3505 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3506 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3507 print_mac(mac1, header->addr1),
3508 print_mac(mac2, header->addr2),
3509 print_mac(mac3, header->addr3));
3510 else
3511 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3512 &rx_status);
3513 break;
3514 }
3515 default:
3516 break;
3517
3518 }
3519 }
3520
3521 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3522 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3523 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3524 struct iwl4965_rx_mem_buffer *rxb)
3525 {
3526 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3527 priv->last_phy_res[0] = 1;
3528 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3529 sizeof(struct iwl4965_rx_phy_res));
3530 }
3531 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3532 struct iwl4965_rx_mem_buffer *rxb)
3533
3534 {
3535 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3536 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3537 struct iwl4965_missed_beacon_notif *missed_beacon;
3538
3539 missed_beacon = &pkt->u.missed_beacon;
3540 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3541 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3542 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3543 le32_to_cpu(missed_beacon->total_missed_becons),
3544 le32_to_cpu(missed_beacon->num_recvd_beacons),
3545 le32_to_cpu(missed_beacon->num_expected_beacons));
3546 if (!test_bit(STATUS_SCANNING, &priv->status))
3547 iwl_init_sensitivity(priv);
3548 }
3549 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3550 }
3551 #ifdef CONFIG_IWL4965_HT
3552
3553 /**
3554 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3555 */
3556 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3557 int sta_id, int tid)
3558 {
3559 unsigned long flags;
3560
3561 /* Remove "disable" flag, to enable Tx for this TID */
3562 spin_lock_irqsave(&priv->sta_lock, flags);
3563 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3564 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3565 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3566 spin_unlock_irqrestore(&priv->sta_lock, flags);
3567
3568 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3569 }
3570
3571 /**
3572 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3573 *
3574 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3575 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3576 */
3577 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3578 struct iwl4965_ht_agg *agg,
3579 struct iwl4965_compressed_ba_resp*
3580 ba_resp)
3581
3582 {
3583 int i, sh, ack;
3584 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3585 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3586 u64 bitmap;
3587 int successes = 0;
3588 struct ieee80211_tx_status *tx_status;
3589
3590 if (unlikely(!agg->wait_for_ba)) {
3591 IWL_ERROR("Received BA when not expected\n");
3592 return -EINVAL;
3593 }
3594
3595 /* Mark that the expected block-ack response arrived */
3596 agg->wait_for_ba = 0;
3597 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3598
3599 /* Calculate shift to align block-ack bits with our Tx window bits */
3600 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3601 if (sh < 0) /* tbw something is wrong with indices */
3602 sh += 0x100;
3603
3604 /* don't use 64-bit values for now */
3605 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3606
3607 if (agg->frame_count > (64 - sh)) {
3608 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3609 return -1;
3610 }
3611
3612 /* check for success or failure according to the
3613 * transmitted bitmap and block-ack bitmap */
3614 bitmap &= agg->bitmap;
3615
3616 /* For each frame attempted in aggregation,
3617 * update driver's record of tx frame's status. */
3618 for (i = 0; i < agg->frame_count ; i++) {
3619 ack = bitmap & (1 << i);
3620 successes += !!ack;
3621 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3622 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3623 agg->start_idx + i);
3624 }
3625
3626 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3627 tx_status->flags = IEEE80211_TX_STATUS_ACK;
3628 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3629 tx_status->ampdu_ack_map = successes;
3630 tx_status->ampdu_ack_len = agg->frame_count;
3631 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3632 &tx_status->control);
3633
3634 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3635
3636 return 0;
3637 }
3638
3639 /**
3640 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3641 */
3642 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3643 u16 txq_id)
3644 {
3645 /* Simply stop the queue, but don't change any configuration;
3646 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3647 iwl_write_prph(priv,
3648 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3649 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3650 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3651 }
3652
3653 /**
3654 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3655 * priv->lock must be held by the caller
3656 */
3657 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3658 u16 ssn_idx, u8 tx_fifo)
3659 {
3660 int ret = 0;
3661
3662 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3663 IWL_WARNING("queue number too small: %d, must be > %d\n",
3664 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3665 return -EINVAL;
3666 }
3667
3668 ret = iwl_grab_nic_access(priv);
3669 if (ret)
3670 return ret;
3671
3672 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3673
3674 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3675
3676 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3677 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3678 /* supposes that ssn_idx is valid (!= 0xFFF) */
3679 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3680
3681 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3682 iwl4965_txq_ctx_deactivate(priv, txq_id);
3683 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3684
3685 iwl_release_nic_access(priv);
3686
3687 return 0;
3688 }
3689
3690 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3691 u8 tid, int txq_id)
3692 {
3693 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3694 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3695 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3696
3697 switch (priv->stations[sta_id].tid[tid].agg.state) {
3698 case IWL_EMPTYING_HW_QUEUE_DELBA:
3699 /* We are reclaiming the last packet of the */
3700 /* aggregated HW queue */
3701 if (txq_id == tid_data->agg.txq_id &&
3702 q->read_ptr == q->write_ptr) {
3703 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3704 int tx_fifo = default_tid_to_tx_fifo[tid];
3705 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3706 iwl4965_tx_queue_agg_disable(priv, txq_id,
3707 ssn, tx_fifo);
3708 tid_data->agg.state = IWL_AGG_OFF;
3709 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3710 }
3711 break;
3712 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3713 /* We are reclaiming the last packet of the queue */
3714 if (tid_data->tfds_in_queue == 0) {
3715 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3716 tid_data->agg.state = IWL_AGG_ON;
3717 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3718 }
3719 break;
3720 }
3721 return 0;
3722 }
3723
3724 /**
3725 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3726 * @index -- current index
3727 * @n_bd -- total number of entries in queue (s/b power of 2)
3728 */
3729 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3730 {
3731 return (index == 0) ? n_bd - 1 : index - 1;
3732 }
3733
3734 /**
3735 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3736 *
3737 * Handles block-acknowledge notification from device, which reports success
3738 * of frames sent via aggregation.
3739 */
3740 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3741 struct iwl4965_rx_mem_buffer *rxb)
3742 {
3743 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3744 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3745 int index;
3746 struct iwl4965_tx_queue *txq = NULL;
3747 struct iwl4965_ht_agg *agg;
3748 DECLARE_MAC_BUF(mac);
3749
3750 /* "flow" corresponds to Tx queue */
3751 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3752
3753 /* "ssn" is start of block-ack Tx window, corresponds to index
3754 * (in Tx queue's circular buffer) of first TFD/frame in window */
3755 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3756
3757 if (scd_flow >= priv->hw_params.max_txq_num) {
3758 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3759 return;
3760 }
3761
3762 txq = &priv->txq[scd_flow];
3763 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3764
3765 /* Find index just before block-ack window */
3766 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3767
3768 /* TODO: Need to get this copy more safely - now good for debug */
3769
3770 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3771 "sta_id = %d\n",
3772 agg->wait_for_ba,
3773 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3774 ba_resp->sta_id);
3775 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3776 "%d, scd_ssn = %d\n",
3777 ba_resp->tid,
3778 ba_resp->seq_ctl,
3779 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3780 ba_resp->scd_flow,
3781 ba_resp->scd_ssn);
3782 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3783 agg->start_idx,
3784 (unsigned long long)agg->bitmap);
3785
3786 /* Update driver's record of ACK vs. not for each frame in window */
3787 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3788
3789 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3790 * block-ack window (we assume that they've been successfully
3791 * transmitted ... if not, it's too late anyway). */
3792 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3793 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3794 priv->stations[ba_resp->sta_id].
3795 tid[ba_resp->tid].tfds_in_queue -= freed;
3796 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3797 priv->mac80211_registered &&
3798 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3799 ieee80211_wake_queue(priv->hw, scd_flow);
3800 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3801 ba_resp->tid, scd_flow);
3802 }
3803 }
3804
3805 /**
3806 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3807 */
3808 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3809 u16 txq_id)
3810 {
3811 u32 tbl_dw_addr;
3812 u32 tbl_dw;
3813 u16 scd_q2ratid;
3814
3815 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3816
3817 tbl_dw_addr = priv->scd_base_addr +
3818 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3819
3820 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3821
3822 if (txq_id & 0x1)
3823 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3824 else
3825 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3826
3827 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3828
3829 return 0;
3830 }
3831
3832
3833 /**
3834 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3835 *
3836 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3837 * i.e. it must be one of the higher queues used for aggregation
3838 */
3839 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3840 int tx_fifo, int sta_id, int tid,
3841 u16 ssn_idx)
3842 {
3843 unsigned long flags;
3844 int rc;
3845 u16 ra_tid;
3846
3847 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3848 IWL_WARNING("queue number too small: %d, must be > %d\n",
3849 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3850
3851 ra_tid = BUILD_RAxTID(sta_id, tid);
3852
3853 /* Modify device's station table to Tx this TID */
3854 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3855
3856 spin_lock_irqsave(&priv->lock, flags);
3857 rc = iwl_grab_nic_access(priv);
3858 if (rc) {
3859 spin_unlock_irqrestore(&priv->lock, flags);
3860 return rc;
3861 }
3862
3863 /* Stop this Tx queue before configuring it */
3864 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3865
3866 /* Map receiver-address / traffic-ID to this queue */
3867 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3868
3869 /* Set this queue as a chain-building queue */
3870 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3871
3872 /* Place first TFD at index corresponding to start sequence number.
3873 * Assumes that ssn_idx is valid (!= 0xFFF) */
3874 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3875 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3876 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3877
3878 /* Set up Tx window size and frame limit for this queue */
3879 iwl_write_targ_mem(priv,
3880 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3881 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3882 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3883
3884 iwl_write_targ_mem(priv, priv->scd_base_addr +
3885 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3886 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3887 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3888
3889 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3890
3891 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3892 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3893
3894 iwl_release_nic_access(priv);
3895 spin_unlock_irqrestore(&priv->lock, flags);
3896
3897 return 0;
3898 }
3899
3900 #endif /* CONFIG_IWL4965_HT */
3901
3902 /**
3903 * iwl4965_add_station - Initialize a station's hardware rate table
3904 *
3905 * The uCode's station table contains a table of fallback rates
3906 * for automatic fallback during transmission.
3907 *
3908 * NOTE: This sets up a default set of values. These will be replaced later
3909 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3910 * rc80211_simple.
3911 *
3912 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3913 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3914 * which requires station table entry to exist).
3915 */
3916 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3917 {
3918 int i, r;
3919 struct iwl_link_quality_cmd link_cmd = {
3920 .reserved1 = 0,
3921 };
3922 u16 rate_flags;
3923
3924 /* Set up the rate scaling to start at selected rate, fall back
3925 * all the way down to 1M in IEEE order, and then spin on 1M */
3926 if (is_ap)
3927 r = IWL_RATE_54M_INDEX;
3928 else if (priv->band == IEEE80211_BAND_5GHZ)
3929 r = IWL_RATE_6M_INDEX;
3930 else
3931 r = IWL_RATE_1M_INDEX;
3932
3933 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3934 rate_flags = 0;
3935 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3936 rate_flags |= RATE_MCS_CCK_MSK;
3937
3938 /* Use Tx antenna B only */
3939 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
3940
3941 link_cmd.rs_table[i].rate_n_flags =
3942 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3943 r = iwl4965_get_prev_ieee_rate(r);
3944 }
3945
3946 link_cmd.general_params.single_stream_ant_msk = 2;
3947 link_cmd.general_params.dual_stream_ant_msk = 3;
3948 link_cmd.agg_params.agg_dis_start_th = 3;
3949 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3950
3951 /* Update the rate scaling for control frame Tx to AP */
3952 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3953
3954 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3955 sizeof(link_cmd), &link_cmd, NULL);
3956 }
3957
3958 #ifdef CONFIG_IWL4965_HT
3959
3960 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3961 enum ieee80211_band band,
3962 u16 channel, u8 extension_chan_offset)
3963 {
3964 const struct iwl_channel_info *ch_info;
3965
3966 ch_info = iwl_get_channel_info(priv, band, channel);
3967 if (!is_channel_valid(ch_info))
3968 return 0;
3969
3970 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3971 return 0;
3972
3973 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3974 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3975 return 1;
3976
3977 return 0;
3978 }
3979
3980 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3981 struct ieee80211_ht_info *sta_ht_inf)
3982 {
3983 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3984
3985 if ((!iwl_ht_conf->is_ht) ||
3986 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3987 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3988 return 0;
3989
3990 if (sta_ht_inf) {
3991 if ((!sta_ht_inf->ht_supported) ||
3992 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3993 return 0;
3994 }
3995
3996 return (iwl4965_is_channel_extension(priv, priv->band,
3997 iwl_ht_conf->control_channel,
3998 iwl_ht_conf->extension_chan_offset));
3999 }
4000
4001 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
4002 {
4003 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
4004 u32 val;
4005
4006 if (!ht_info->is_ht)
4007 return;
4008
4009 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
4010 if (iwl4965_is_fat_tx_allowed(priv, NULL))
4011 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4012 else
4013 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4014 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4015
4016 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4017 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4018 le16_to_cpu(rxon->channel),
4019 ht_info->control_channel);
4020 rxon->channel = cpu_to_le16(ht_info->control_channel);
4021 return;
4022 }
4023
4024 /* Note: control channel is opposite of extension channel */
4025 switch (ht_info->extension_chan_offset) {
4026 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4027 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4028 break;
4029 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4030 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4031 break;
4032 case IWL_EXT_CHANNEL_OFFSET_NONE:
4033 default:
4034 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4035 break;
4036 }
4037
4038 val = ht_info->ht_protection;
4039
4040 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4041
4042 iwl4965_set_rxon_chain(priv);
4043
4044 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
4045 "rxon flags 0x%X operation mode :0x%X "
4046 "extension channel offset 0x%x "
4047 "control chan %d\n",
4048 ht_info->supp_mcs_set[0],
4049 ht_info->supp_mcs_set[1],
4050 ht_info->supp_mcs_set[2],
4051 le32_to_cpu(rxon->flags), ht_info->ht_protection,
4052 ht_info->extension_chan_offset,
4053 ht_info->control_channel);
4054 return;
4055 }
4056
4057 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
4058 struct ieee80211_ht_info *sta_ht_inf)
4059 {
4060 __le32 sta_flags;
4061 u8 mimo_ps_mode;
4062
4063 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
4064 goto done;
4065
4066 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4067
4068 sta_flags = priv->stations[index].sta.station_flags;
4069
4070 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4071
4072 switch (mimo_ps_mode) {
4073 case WLAN_HT_CAP_MIMO_PS_STATIC:
4074 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4075 break;
4076 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
4077 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
4078 break;
4079 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4080 break;
4081 default:
4082 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4083 break;
4084 }
4085
4086 sta_flags |= cpu_to_le32(
4087 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
4088
4089 sta_flags |= cpu_to_le32(
4090 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
4091
4092 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
4093 sta_flags |= STA_FLG_FAT_EN_MSK;
4094 else
4095 sta_flags &= ~STA_FLG_FAT_EN_MSK;
4096
4097 priv->stations[index].sta.station_flags = sta_flags;
4098 done:
4099 return;
4100 }
4101
4102 static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4103 const u8 *addr, int tid, u16 ssn)
4104 {
4105 unsigned long flags;
4106 int sta_id;
4107
4108 sta_id = iwl_find_station(priv, addr);
4109 if (sta_id == IWL_INVALID_STATION)
4110 return -ENXIO;
4111
4112 spin_lock_irqsave(&priv->sta_lock, flags);
4113 priv->stations[sta_id].sta.station_flags_msk = 0;
4114 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4115 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4116 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4117 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4118 spin_unlock_irqrestore(&priv->sta_lock, flags);
4119
4120 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4121 CMD_ASYNC);
4122 }
4123
4124 static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4125 const u8 *addr, int tid)
4126 {
4127 unsigned long flags;
4128 int sta_id;
4129
4130 sta_id = iwl_find_station(priv, addr);
4131 if (sta_id == IWL_INVALID_STATION)
4132 return -ENXIO;
4133
4134 spin_lock_irqsave(&priv->sta_lock, flags);
4135 priv->stations[sta_id].sta.station_flags_msk = 0;
4136 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4137 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4138 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4139 spin_unlock_irqrestore(&priv->sta_lock, flags);
4140
4141 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4142 CMD_ASYNC);
4143 }
4144
4145 /*
4146 * Find first available (lowest unused) Tx Queue, mark it "active".
4147 * Called only when finding queue for aggregation.
4148 * Should never return anything < 7, because they should already
4149 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4150 */
4151 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
4152 {
4153 int txq_id;
4154
4155 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
4156 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4157 return txq_id;
4158 return -1;
4159 }
4160
4161 static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4162 u16 tid, u16 *start_seq_num)
4163 {
4164 struct iwl_priv *priv = hw->priv;
4165 int sta_id;
4166 int tx_fifo;
4167 int txq_id;
4168 int ssn = -1;
4169 int ret = 0;
4170 unsigned long flags;
4171 struct iwl4965_tid_data *tid_data;
4172 DECLARE_MAC_BUF(mac);
4173
4174 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4175 tx_fifo = default_tid_to_tx_fifo[tid];
4176 else
4177 return -EINVAL;
4178
4179 IWL_WARNING("%s on ra = %s tid = %d\n",
4180 __func__, print_mac(mac, ra), tid);
4181
4182 sta_id = iwl_find_station(priv, ra);
4183 if (sta_id == IWL_INVALID_STATION)
4184 return -ENXIO;
4185
4186 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4187 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4188 return -ENXIO;
4189 }
4190
4191 txq_id = iwl4965_txq_ctx_activate_free(priv);
4192 if (txq_id == -1)
4193 return -ENXIO;
4194
4195 spin_lock_irqsave(&priv->sta_lock, flags);
4196 tid_data = &priv->stations[sta_id].tid[tid];
4197 ssn = SEQ_TO_SN(tid_data->seq_number);
4198 tid_data->agg.txq_id = txq_id;
4199 spin_unlock_irqrestore(&priv->sta_lock, flags);
4200
4201 *start_seq_num = ssn;
4202 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4203 sta_id, tid, ssn);
4204 if (ret)
4205 return ret;
4206
4207 ret = 0;
4208 if (tid_data->tfds_in_queue == 0) {
4209 printk(KERN_ERR "HW queue is empty\n");
4210 tid_data->agg.state = IWL_AGG_ON;
4211 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
4212 } else {
4213 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4214 tid_data->tfds_in_queue);
4215 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4216 }
4217 return ret;
4218 }
4219
4220 static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
4221 {
4222 struct iwl_priv *priv = hw->priv;
4223 int tx_fifo_id, txq_id, sta_id, ssn = -1;
4224 struct iwl4965_tid_data *tid_data;
4225 int ret, write_ptr, read_ptr;
4226 unsigned long flags;
4227 DECLARE_MAC_BUF(mac);
4228
4229 if (!ra) {
4230 IWL_ERROR("ra = NULL\n");
4231 return -EINVAL;
4232 }
4233
4234 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4235 tx_fifo_id = default_tid_to_tx_fifo[tid];
4236 else
4237 return -EINVAL;
4238
4239 sta_id = iwl_find_station(priv, ra);
4240
4241 if (sta_id == IWL_INVALID_STATION)
4242 return -ENXIO;
4243
4244 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4245 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4246
4247 tid_data = &priv->stations[sta_id].tid[tid];
4248 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4249 txq_id = tid_data->agg.txq_id;
4250 write_ptr = priv->txq[txq_id].q.write_ptr;
4251 read_ptr = priv->txq[txq_id].q.read_ptr;
4252
4253 /* The queue is not empty */
4254 if (write_ptr != read_ptr) {
4255 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4256 priv->stations[sta_id].tid[tid].agg.state =
4257 IWL_EMPTYING_HW_QUEUE_DELBA;
4258 return 0;
4259 }
4260
4261 IWL_DEBUG_HT("HW queue is empty\n");
4262 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4263
4264 spin_lock_irqsave(&priv->lock, flags);
4265 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4266 spin_unlock_irqrestore(&priv->lock, flags);
4267
4268 if (ret)
4269 return ret;
4270
4271 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
4272
4273 return 0;
4274 }
4275
4276 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4277 enum ieee80211_ampdu_mlme_action action,
4278 const u8 *addr, u16 tid, u16 *ssn)
4279 {
4280 struct iwl_priv *priv = hw->priv;
4281 DECLARE_MAC_BUF(mac);
4282
4283 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4284 print_mac(mac, addr), tid);
4285
4286 switch (action) {
4287 case IEEE80211_AMPDU_RX_START:
4288 IWL_DEBUG_HT("start Rx\n");
4289 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
4290 case IEEE80211_AMPDU_RX_STOP:
4291 IWL_DEBUG_HT("stop Rx\n");
4292 return iwl4965_rx_agg_stop(priv, addr, tid);
4293 case IEEE80211_AMPDU_TX_START:
4294 IWL_DEBUG_HT("start Tx\n");
4295 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
4296 case IEEE80211_AMPDU_TX_STOP:
4297 IWL_DEBUG_HT("stop Tx\n");
4298 return iwl4965_tx_agg_stop(hw, addr, tid);
4299 default:
4300 IWL_DEBUG_HT("unknown\n");
4301 return -EINVAL;
4302 break;
4303 }
4304 return 0;
4305 }
4306
4307 #endif /* CONFIG_IWL4965_HT */
4308
4309 /* Set up 4965-specific Rx frame reply handlers */
4310 void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
4311 {
4312 /* Legacy Rx frames */
4313 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4314
4315 /* High-throughput (HT) Rx frames */
4316 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4317 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4318
4319 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4320 iwl4965_rx_missed_beacon_notif;
4321
4322 #ifdef CONFIG_IWL4965_HT
4323 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4324 #endif /* CONFIG_IWL4965_HT */
4325 }
4326
4327 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4328 {
4329 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4330 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4331 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4332 #endif
4333 init_timer(&priv->statistics_periodic);
4334 priv->statistics_periodic.data = (unsigned long)priv;
4335 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4336 }
4337
4338 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4339 {
4340 del_timer_sync(&priv->statistics_periodic);
4341
4342 cancel_delayed_work(&priv->init_alive_start);
4343 }
4344
4345
4346 static struct iwl_hcmd_ops iwl4965_hcmd = {
4347 .rxon_assoc = iwl4965_send_rxon_assoc,
4348 };
4349
4350 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4351 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4352 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4353 .chain_noise_reset = iwl4965_chain_noise_reset,
4354 .gain_computation = iwl4965_gain_computation,
4355 #endif
4356 };
4357
4358 static struct iwl_lib_ops iwl4965_lib = {
4359 .init_drv = iwl4965_init_drv,
4360 .set_hw_params = iwl4965_hw_set_hw_params,
4361 .alloc_shared_mem = iwl4965_alloc_shared_mem,
4362 .free_shared_mem = iwl4965_free_shared_mem,
4363 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4364 .hw_nic_init = iwl4965_hw_nic_init,
4365 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4366 .alive_notify = iwl4965_alive_notify,
4367 .load_ucode = iwl4965_load_bsm,
4368 .apm_ops = {
4369 .init = iwl4965_apm_init,
4370 .set_pwr_src = iwl4965_set_pwr_src,
4371 },
4372 .eeprom_ops = {
4373 .regulatory_bands = {
4374 EEPROM_REGULATORY_BAND_1_CHANNELS,
4375 EEPROM_REGULATORY_BAND_2_CHANNELS,
4376 EEPROM_REGULATORY_BAND_3_CHANNELS,
4377 EEPROM_REGULATORY_BAND_4_CHANNELS,
4378 EEPROM_REGULATORY_BAND_5_CHANNELS,
4379 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4380 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4381 },
4382 .verify_signature = iwlcore_eeprom_verify_signature,
4383 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4384 .release_semaphore = iwlcore_eeprom_release_semaphore,
4385 .check_version = iwl4965_eeprom_check_version,
4386 .query_addr = iwlcore_eeprom_query_addr,
4387 },
4388 .radio_kill_sw = iwl4965_radio_kill_sw,
4389 .set_power = iwl4965_set_power,
4390 .update_chain_flags = iwl4965_update_chain_flags,
4391 };
4392
4393 static struct iwl_ops iwl4965_ops = {
4394 .lib = &iwl4965_lib,
4395 .hcmd = &iwl4965_hcmd,
4396 .utils = &iwl4965_hcmd_utils,
4397 };
4398
4399 struct iwl_cfg iwl4965_agn_cfg = {
4400 .name = "4965AGN",
4401 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4402 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4403 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
4404 .ops = &iwl4965_ops,
4405 .mod_params = &iwl4965_mod_params,
4406 };
4407
4408 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4409 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4410 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4411 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4412 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4413 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4414 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4415 MODULE_PARM_DESC(debug, "debug output mask");
4416 module_param_named(
4417 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4418 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4419
4420 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4421 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4422
4423 /* QoS */
4424 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4425 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4426 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4427 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4428
Linux kernel - Deliverables
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