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iwlwifi: more clean up to move agn only rx functions from iwlcore to iwlagn
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47 #include "iwl-sta.h"
48 #include "iwl-agn-led.h"
49 #include "iwl-agn.h"
50
51 static int iwl4965_send_tx_power(struct iwl_priv *priv);
52 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
53
54 /* Highest firmware API version supported */
55 #define IWL4965_UCODE_API_MAX 2
56
57 /* Lowest firmware API version supported */
58 #define IWL4965_UCODE_API_MIN 2
59
60 #define IWL4965_FW_PRE "iwlwifi-4965-"
61 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
62 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
63
64
65 /* module parameters */
66 static struct iwl_mod_params iwl4965_mod_params = {
67 .amsdu_size_8K = 1,
68 .restart_fw = 1,
69 /* the rest are 0 by default */
70 };
71
72 /* check contents of special bootstrap uCode SRAM */
73 static int iwl4965_verify_bsm(struct iwl_priv *priv)
74 {
75 __le32 *image = priv->ucode_boot.v_addr;
76 u32 len = priv->ucode_boot.len;
77 u32 reg;
78 u32 val;
79
80 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
81
82 /* verify BSM SRAM contents */
83 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
84 for (reg = BSM_SRAM_LOWER_BOUND;
85 reg < BSM_SRAM_LOWER_BOUND + len;
86 reg += sizeof(u32), image++) {
87 val = iwl_read_prph(priv, reg);
88 if (val != le32_to_cpu(*image)) {
89 IWL_ERR(priv, "BSM uCode verification failed at "
90 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
91 BSM_SRAM_LOWER_BOUND,
92 reg - BSM_SRAM_LOWER_BOUND, len,
93 val, le32_to_cpu(*image));
94 return -EIO;
95 }
96 }
97
98 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
99
100 return 0;
101 }
102
103 /**
104 * iwl4965_load_bsm - Load bootstrap instructions
105 *
106 * BSM operation:
107 *
108 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
109 * in special SRAM that does not power down during RFKILL. When powering back
110 * up after power-saving sleeps (or during initial uCode load), the BSM loads
111 * the bootstrap program into the on-board processor, and starts it.
112 *
113 * The bootstrap program loads (via DMA) instructions and data for a new
114 * program from host DRAM locations indicated by the host driver in the
115 * BSM_DRAM_* registers. Once the new program is loaded, it starts
116 * automatically.
117 *
118 * When initializing the NIC, the host driver points the BSM to the
119 * "initialize" uCode image. This uCode sets up some internal data, then
120 * notifies host via "initialize alive" that it is complete.
121 *
122 * The host then replaces the BSM_DRAM_* pointer values to point to the
123 * normal runtime uCode instructions and a backup uCode data cache buffer
124 * (filled initially with starting data values for the on-board processor),
125 * then triggers the "initialize" uCode to load and launch the runtime uCode,
126 * which begins normal operation.
127 *
128 * When doing a power-save shutdown, runtime uCode saves data SRAM into
129 * the backup data cache in DRAM before SRAM is powered down.
130 *
131 * When powering back up, the BSM loads the bootstrap program. This reloads
132 * the runtime uCode instructions and the backup data cache into SRAM,
133 * and re-launches the runtime uCode from where it left off.
134 */
135 static int iwl4965_load_bsm(struct iwl_priv *priv)
136 {
137 __le32 *image = priv->ucode_boot.v_addr;
138 u32 len = priv->ucode_boot.len;
139 dma_addr_t pinst;
140 dma_addr_t pdata;
141 u32 inst_len;
142 u32 data_len;
143 int i;
144 u32 done;
145 u32 reg_offset;
146 int ret;
147
148 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
149
150 priv->ucode_type = UCODE_RT;
151
152 /* make sure bootstrap program is no larger than BSM's SRAM size */
153 if (len > IWL49_MAX_BSM_SIZE)
154 return -EINVAL;
155
156 /* Tell bootstrap uCode where to find the "Initialize" uCode
157 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
158 * NOTE: iwl_init_alive_start() will replace these values,
159 * after the "initialize" uCode has run, to point to
160 * runtime/protocol instructions and backup data cache.
161 */
162 pinst = priv->ucode_init.p_addr >> 4;
163 pdata = priv->ucode_init_data.p_addr >> 4;
164 inst_len = priv->ucode_init.len;
165 data_len = priv->ucode_init_data.len;
166
167 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
168 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
169 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
170 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
171
172 /* Fill BSM memory with bootstrap instructions */
173 for (reg_offset = BSM_SRAM_LOWER_BOUND;
174 reg_offset < BSM_SRAM_LOWER_BOUND + len;
175 reg_offset += sizeof(u32), image++)
176 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
177
178 ret = iwl4965_verify_bsm(priv);
179 if (ret)
180 return ret;
181
182 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
183 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
184 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
185 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
186
187 /* Load bootstrap code into instruction SRAM now,
188 * to prepare to load "initialize" uCode */
189 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
190
191 /* Wait for load of bootstrap uCode to finish */
192 for (i = 0; i < 100; i++) {
193 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
194 if (!(done & BSM_WR_CTRL_REG_BIT_START))
195 break;
196 udelay(10);
197 }
198 if (i < 100)
199 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
200 else {
201 IWL_ERR(priv, "BSM write did not complete!\n");
202 return -EIO;
203 }
204
205 /* Enable future boot loads whenever power management unit triggers it
206 * (e.g. when powering back up after power-save shutdown) */
207 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
208
209
210 return 0;
211 }
212
213 /**
214 * iwl4965_set_ucode_ptrs - Set uCode address location
215 *
216 * Tell initialization uCode where to find runtime uCode.
217 *
218 * BSM registers initially contain pointers to initialization uCode.
219 * We need to replace them to load runtime uCode inst and data,
220 * and to save runtime data when powering down.
221 */
222 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
223 {
224 dma_addr_t pinst;
225 dma_addr_t pdata;
226 int ret = 0;
227
228 /* bits 35:4 for 4965 */
229 pinst = priv->ucode_code.p_addr >> 4;
230 pdata = priv->ucode_data_backup.p_addr >> 4;
231
232 /* Tell bootstrap uCode where to find image to load */
233 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
234 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
235 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
236 priv->ucode_data.len);
237
238 /* Inst byte count must be last to set up, bit 31 signals uCode
239 * that all new ptr/size info is in place */
240 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
241 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
242 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
243
244 return ret;
245 }
246
247 /**
248 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
249 *
250 * Called after REPLY_ALIVE notification received from "initialize" uCode.
251 *
252 * The 4965 "initialize" ALIVE reply contains calibration data for:
253 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
254 * (3945 does not contain this data).
255 *
256 * Tell "initialize" uCode to go ahead and load the runtime uCode.
257 */
258 static void iwl4965_init_alive_start(struct iwl_priv *priv)
259 {
260 /* Check alive response for "valid" sign from uCode */
261 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
262 /* We had an error bringing up the hardware, so take it
263 * all the way back down so we can try again */
264 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
265 goto restart;
266 }
267
268 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
269 * This is a paranoid check, because we would not have gotten the
270 * "initialize" alive if code weren't properly loaded. */
271 if (iwl_verify_ucode(priv)) {
272 /* Runtime instruction load was bad;
273 * take it all the way back down so we can try again */
274 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
275 goto restart;
276 }
277
278 /* Calculate temperature */
279 priv->temperature = iwl4965_hw_get_temperature(priv);
280
281 /* Send pointers to protocol/runtime uCode image ... init code will
282 * load and launch runtime uCode, which will send us another "Alive"
283 * notification. */
284 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
285 if (iwl4965_set_ucode_ptrs(priv)) {
286 /* Runtime instruction load won't happen;
287 * take it all the way back down so we can try again */
288 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
289 goto restart;
290 }
291 return;
292
293 restart:
294 queue_work(priv->workqueue, &priv->restart);
295 }
296
297 static bool is_ht40_channel(__le32 rxon_flags)
298 {
299 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
300 >> RXON_FLG_CHANNEL_MODE_POS;
301 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
302 (chan_mod == CHANNEL_MODE_MIXED));
303 }
304
305 /*
306 * EEPROM handlers
307 */
308 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
309 {
310 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
311 }
312
313 /*
314 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
315 * must be called under priv->lock and mac access
316 */
317 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
318 {
319 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
320 }
321
322 static void iwl4965_nic_config(struct iwl_priv *priv)
323 {
324 unsigned long flags;
325 u16 radio_cfg;
326
327 spin_lock_irqsave(&priv->lock, flags);
328
329 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
330
331 /* write radio config values to register */
332 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
333 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
334 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
335 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
336 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
337
338 /* set CSR_HW_CONFIG_REG for uCode use */
339 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
340 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
341 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
342
343 priv->calib_info = (struct iwl_eeprom_calib_info *)
344 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
345
346 spin_unlock_irqrestore(&priv->lock, flags);
347 }
348
349 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
350 * Called after every association, but this runs only once!
351 * ... once chain noise is calibrated the first time, it's good forever. */
352 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
353 {
354 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
355
356 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
357 struct iwl_calib_diff_gain_cmd cmd;
358
359 memset(&cmd, 0, sizeof(cmd));
360 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
361 cmd.diff_gain_a = 0;
362 cmd.diff_gain_b = 0;
363 cmd.diff_gain_c = 0;
364 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
365 sizeof(cmd), &cmd))
366 IWL_ERR(priv,
367 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
368 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
369 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
370 }
371 }
372
373 static void iwl4965_gain_computation(struct iwl_priv *priv,
374 u32 *average_noise,
375 u16 min_average_noise_antenna_i,
376 u32 min_average_noise,
377 u8 default_chain)
378 {
379 int i, ret;
380 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
381
382 data->delta_gain_code[min_average_noise_antenna_i] = 0;
383
384 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
385 s32 delta_g = 0;
386
387 if (!(data->disconn_array[i]) &&
388 (data->delta_gain_code[i] ==
389 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
390 delta_g = average_noise[i] - min_average_noise;
391 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
392 data->delta_gain_code[i] =
393 min(data->delta_gain_code[i],
394 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
395
396 data->delta_gain_code[i] =
397 (data->delta_gain_code[i] | (1 << 2));
398 } else {
399 data->delta_gain_code[i] = 0;
400 }
401 }
402 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
403 data->delta_gain_code[0],
404 data->delta_gain_code[1],
405 data->delta_gain_code[2]);
406
407 /* Differential gain gets sent to uCode only once */
408 if (!data->radio_write) {
409 struct iwl_calib_diff_gain_cmd cmd;
410 data->radio_write = 1;
411
412 memset(&cmd, 0, sizeof(cmd));
413 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
414 cmd.diff_gain_a = data->delta_gain_code[0];
415 cmd.diff_gain_b = data->delta_gain_code[1];
416 cmd.diff_gain_c = data->delta_gain_code[2];
417 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
418 sizeof(cmd), &cmd);
419 if (ret)
420 IWL_DEBUG_CALIB(priv, "fail sending cmd "
421 "REPLY_PHY_CALIBRATION_CMD \n");
422
423 /* TODO we might want recalculate
424 * rx_chain in rxon cmd */
425
426 /* Mark so we run this algo only once! */
427 data->state = IWL_CHAIN_NOISE_CALIBRATED;
428 }
429 data->chain_noise_a = 0;
430 data->chain_noise_b = 0;
431 data->chain_noise_c = 0;
432 data->chain_signal_a = 0;
433 data->chain_signal_b = 0;
434 data->chain_signal_c = 0;
435 data->beacon_count = 0;
436 }
437
438 static void iwl4965_bg_txpower_work(struct work_struct *work)
439 {
440 struct iwl_priv *priv = container_of(work, struct iwl_priv,
441 txpower_work);
442
443 /* If a scan happened to start before we got here
444 * then just return; the statistics notification will
445 * kick off another scheduled work to compensate for
446 * any temperature delta we missed here. */
447 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
448 test_bit(STATUS_SCANNING, &priv->status))
449 return;
450
451 mutex_lock(&priv->mutex);
452
453 /* Regardless of if we are associated, we must reconfigure the
454 * TX power since frames can be sent on non-radar channels while
455 * not associated */
456 iwl4965_send_tx_power(priv);
457
458 /* Update last_temperature to keep is_calib_needed from running
459 * when it isn't needed... */
460 priv->last_temperature = priv->temperature;
461
462 mutex_unlock(&priv->mutex);
463 }
464
465 /*
466 * Acquire priv->lock before calling this function !
467 */
468 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
469 {
470 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
471 (index & 0xff) | (txq_id << 8));
472 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
473 }
474
475 /**
476 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
477 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
478 * @scd_retry: (1) Indicates queue will be used in aggregation mode
479 *
480 * NOTE: Acquire priv->lock before calling this function !
481 */
482 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
483 struct iwl_tx_queue *txq,
484 int tx_fifo_id, int scd_retry)
485 {
486 int txq_id = txq->q.id;
487
488 /* Find out whether to activate Tx queue */
489 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
490
491 /* Set up and activate */
492 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
493 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
494 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
495 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
496 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
497 IWL49_SCD_QUEUE_STTS_REG_MSK);
498
499 txq->sched_retry = scd_retry;
500
501 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
502 active ? "Activate" : "Deactivate",
503 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
504 }
505
506 static const s8 default_queue_to_tx_fifo[] = {
507 IWL_TX_FIFO_VO,
508 IWL_TX_FIFO_VI,
509 IWL_TX_FIFO_BE,
510 IWL_TX_FIFO_BK,
511 IWL49_CMD_FIFO_NUM,
512 IWL_TX_FIFO_UNUSED,
513 IWL_TX_FIFO_UNUSED,
514 };
515
516 static int iwl4965_alive_notify(struct iwl_priv *priv)
517 {
518 u32 a;
519 unsigned long flags;
520 int i, chan;
521 u32 reg_val;
522
523 spin_lock_irqsave(&priv->lock, flags);
524
525 /* Clear 4965's internal Tx Scheduler data base */
526 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
527 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
528 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
529 iwl_write_targ_mem(priv, a, 0);
530 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
531 iwl_write_targ_mem(priv, a, 0);
532 for (; a < priv->scd_base_addr +
533 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
534 iwl_write_targ_mem(priv, a, 0);
535
536 /* Tel 4965 where to find Tx byte count tables */
537 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
538 priv->scd_bc_tbls.dma >> 10);
539
540 /* Enable DMA channel */
541 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
542 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
543 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
544 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
545
546 /* Update FH chicken bits */
547 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
548 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
549 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
550
551 /* Disable chain mode for all queues */
552 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
553
554 /* Initialize each Tx queue (including the command queue) */
555 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
556
557 /* TFD circular buffer read/write indexes */
558 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
559 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
560
561 /* Max Tx Window size for Scheduler-ACK mode */
562 iwl_write_targ_mem(priv, priv->scd_base_addr +
563 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
564 (SCD_WIN_SIZE <<
565 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
566 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
567
568 /* Frame limit */
569 iwl_write_targ_mem(priv, priv->scd_base_addr +
570 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
571 sizeof(u32),
572 (SCD_FRAME_LIMIT <<
573 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
574 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
575
576 }
577 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
578 (1 << priv->hw_params.max_txq_num) - 1);
579
580 /* Activate all Tx DMA/FIFO channels */
581 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
582
583 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
584
585 /* make sure all queue are not stopped */
586 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
587 for (i = 0; i < 4; i++)
588 atomic_set(&priv->queue_stop_count[i], 0);
589
590 /* reset to 0 to enable all the queue first */
591 priv->txq_ctx_active_msk = 0;
592 /* Map each Tx/cmd queue to its corresponding fifo */
593 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
594 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
595 int ac = default_queue_to_tx_fifo[i];
596
597 iwl_txq_ctx_activate(priv, i);
598
599 if (ac == IWL_TX_FIFO_UNUSED)
600 continue;
601
602 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
603 }
604
605 spin_unlock_irqrestore(&priv->lock, flags);
606
607 return 0;
608 }
609
610 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
611 .min_nrg_cck = 97,
612 .max_nrg_cck = 0, /* not used, set to 0 */
613
614 .auto_corr_min_ofdm = 85,
615 .auto_corr_min_ofdm_mrc = 170,
616 .auto_corr_min_ofdm_x1 = 105,
617 .auto_corr_min_ofdm_mrc_x1 = 220,
618
619 .auto_corr_max_ofdm = 120,
620 .auto_corr_max_ofdm_mrc = 210,
621 .auto_corr_max_ofdm_x1 = 140,
622 .auto_corr_max_ofdm_mrc_x1 = 270,
623
624 .auto_corr_min_cck = 125,
625 .auto_corr_max_cck = 200,
626 .auto_corr_min_cck_mrc = 200,
627 .auto_corr_max_cck_mrc = 400,
628
629 .nrg_th_cck = 100,
630 .nrg_th_ofdm = 100,
631
632 .barker_corr_th_min = 190,
633 .barker_corr_th_min_mrc = 390,
634 .nrg_th_cca = 62,
635 };
636
637 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
638 {
639 /* want Kelvin */
640 priv->hw_params.ct_kill_threshold =
641 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
642 }
643
644 /**
645 * iwl4965_hw_set_hw_params
646 *
647 * Called when initializing driver
648 */
649 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
650 {
651 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
652 priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
653 priv->cfg->num_of_queues =
654 priv->cfg->mod_params->num_of_queues;
655
656 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
657 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
658 priv->hw_params.scd_bc_tbls_size =
659 priv->cfg->num_of_queues *
660 sizeof(struct iwl4965_scd_bc_tbl);
661 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
662 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
663 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
664 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
665 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
666 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
667 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
668
669 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
670
671 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
672 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
673 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
674 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
675 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
676 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
677
678 priv->hw_params.sens = &iwl4965_sensitivity;
679
680 return 0;
681 }
682
683 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
684 {
685 s32 sign = 1;
686
687 if (num < 0) {
688 sign = -sign;
689 num = -num;
690 }
691 if (denom < 0) {
692 sign = -sign;
693 denom = -denom;
694 }
695 *res = 1;
696 *res = ((num * 2 + denom) / (denom * 2)) * sign;
697
698 return 1;
699 }
700
701 /**
702 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
703 *
704 * Determines power supply voltage compensation for txpower calculations.
705 * Returns number of 1/2-dB steps to subtract from gain table index,
706 * to compensate for difference between power supply voltage during
707 * factory measurements, vs. current power supply voltage.
708 *
709 * Voltage indication is higher for lower voltage.
710 * Lower voltage requires more gain (lower gain table index).
711 */
712 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
713 s32 current_voltage)
714 {
715 s32 comp = 0;
716
717 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
718 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
719 return 0;
720
721 iwl4965_math_div_round(current_voltage - eeprom_voltage,
722 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
723
724 if (current_voltage > eeprom_voltage)
725 comp *= 2;
726 if ((comp < -2) || (comp > 2))
727 comp = 0;
728
729 return comp;
730 }
731
732 static s32 iwl4965_get_tx_atten_grp(u16 channel)
733 {
734 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
735 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
736 return CALIB_CH_GROUP_5;
737
738 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
739 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
740 return CALIB_CH_GROUP_1;
741
742 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
743 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
744 return CALIB_CH_GROUP_2;
745
746 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
747 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
748 return CALIB_CH_GROUP_3;
749
750 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
751 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
752 return CALIB_CH_GROUP_4;
753
754 return -1;
755 }
756
757 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
758 {
759 s32 b = -1;
760
761 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
762 if (priv->calib_info->band_info[b].ch_from == 0)
763 continue;
764
765 if ((channel >= priv->calib_info->band_info[b].ch_from)
766 && (channel <= priv->calib_info->band_info[b].ch_to))
767 break;
768 }
769
770 return b;
771 }
772
773 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
774 {
775 s32 val;
776
777 if (x2 == x1)
778 return y1;
779 else {
780 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
781 return val + y2;
782 }
783 }
784
785 /**
786 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
787 *
788 * Interpolates factory measurements from the two sample channels within a
789 * sub-band, to apply to channel of interest. Interpolation is proportional to
790 * differences in channel frequencies, which is proportional to differences
791 * in channel number.
792 */
793 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
794 struct iwl_eeprom_calib_ch_info *chan_info)
795 {
796 s32 s = -1;
797 u32 c;
798 u32 m;
799 const struct iwl_eeprom_calib_measure *m1;
800 const struct iwl_eeprom_calib_measure *m2;
801 struct iwl_eeprom_calib_measure *omeas;
802 u32 ch_i1;
803 u32 ch_i2;
804
805 s = iwl4965_get_sub_band(priv, channel);
806 if (s >= EEPROM_TX_POWER_BANDS) {
807 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
808 return -1;
809 }
810
811 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
812 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
813 chan_info->ch_num = (u8) channel;
814
815 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
816 channel, s, ch_i1, ch_i2);
817
818 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
819 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
820 m1 = &(priv->calib_info->band_info[s].ch1.
821 measurements[c][m]);
822 m2 = &(priv->calib_info->band_info[s].ch2.
823 measurements[c][m]);
824 omeas = &(chan_info->measurements[c][m]);
825
826 omeas->actual_pow =
827 (u8) iwl4965_interpolate_value(channel, ch_i1,
828 m1->actual_pow,
829 ch_i2,
830 m2->actual_pow);
831 omeas->gain_idx =
832 (u8) iwl4965_interpolate_value(channel, ch_i1,
833 m1->gain_idx, ch_i2,
834 m2->gain_idx);
835 omeas->temperature =
836 (u8) iwl4965_interpolate_value(channel, ch_i1,
837 m1->temperature,
838 ch_i2,
839 m2->temperature);
840 omeas->pa_det =
841 (s8) iwl4965_interpolate_value(channel, ch_i1,
842 m1->pa_det, ch_i2,
843 m2->pa_det);
844
845 IWL_DEBUG_TXPOWER(priv,
846 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
847 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
848 IWL_DEBUG_TXPOWER(priv,
849 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
850 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
851 IWL_DEBUG_TXPOWER(priv,
852 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
853 m1->pa_det, m2->pa_det, omeas->pa_det);
854 IWL_DEBUG_TXPOWER(priv,
855 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
856 m1->temperature, m2->temperature,
857 omeas->temperature);
858 }
859 }
860
861 return 0;
862 }
863
864 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
865 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
866 static s32 back_off_table[] = {
867 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
868 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
869 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
870 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
871 10 /* CCK */
872 };
873
874 /* Thermal compensation values for txpower for various frequency ranges ...
875 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
876 static struct iwl4965_txpower_comp_entry {
877 s32 degrees_per_05db_a;
878 s32 degrees_per_05db_a_denom;
879 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
880 {9, 2}, /* group 0 5.2, ch 34-43 */
881 {4, 1}, /* group 1 5.2, ch 44-70 */
882 {4, 1}, /* group 2 5.2, ch 71-124 */
883 {4, 1}, /* group 3 5.2, ch 125-200 */
884 {3, 1} /* group 4 2.4, ch all */
885 };
886
887 static s32 get_min_power_index(s32 rate_power_index, u32 band)
888 {
889 if (!band) {
890 if ((rate_power_index & 7) <= 4)
891 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
892 }
893 return MIN_TX_GAIN_INDEX;
894 }
895
896 struct gain_entry {
897 u8 dsp;
898 u8 radio;
899 };
900
901 static const struct gain_entry gain_table[2][108] = {
902 /* 5.2GHz power gain index table */
903 {
904 {123, 0x3F}, /* highest txpower */
905 {117, 0x3F},
906 {110, 0x3F},
907 {104, 0x3F},
908 {98, 0x3F},
909 {110, 0x3E},
910 {104, 0x3E},
911 {98, 0x3E},
912 {110, 0x3D},
913 {104, 0x3D},
914 {98, 0x3D},
915 {110, 0x3C},
916 {104, 0x3C},
917 {98, 0x3C},
918 {110, 0x3B},
919 {104, 0x3B},
920 {98, 0x3B},
921 {110, 0x3A},
922 {104, 0x3A},
923 {98, 0x3A},
924 {110, 0x39},
925 {104, 0x39},
926 {98, 0x39},
927 {110, 0x38},
928 {104, 0x38},
929 {98, 0x38},
930 {110, 0x37},
931 {104, 0x37},
932 {98, 0x37},
933 {110, 0x36},
934 {104, 0x36},
935 {98, 0x36},
936 {110, 0x35},
937 {104, 0x35},
938 {98, 0x35},
939 {110, 0x34},
940 {104, 0x34},
941 {98, 0x34},
942 {110, 0x33},
943 {104, 0x33},
944 {98, 0x33},
945 {110, 0x32},
946 {104, 0x32},
947 {98, 0x32},
948 {110, 0x31},
949 {104, 0x31},
950 {98, 0x31},
951 {110, 0x30},
952 {104, 0x30},
953 {98, 0x30},
954 {110, 0x25},
955 {104, 0x25},
956 {98, 0x25},
957 {110, 0x24},
958 {104, 0x24},
959 {98, 0x24},
960 {110, 0x23},
961 {104, 0x23},
962 {98, 0x23},
963 {110, 0x22},
964 {104, 0x18},
965 {98, 0x18},
966 {110, 0x17},
967 {104, 0x17},
968 {98, 0x17},
969 {110, 0x16},
970 {104, 0x16},
971 {98, 0x16},
972 {110, 0x15},
973 {104, 0x15},
974 {98, 0x15},
975 {110, 0x14},
976 {104, 0x14},
977 {98, 0x14},
978 {110, 0x13},
979 {104, 0x13},
980 {98, 0x13},
981 {110, 0x12},
982 {104, 0x08},
983 {98, 0x08},
984 {110, 0x07},
985 {104, 0x07},
986 {98, 0x07},
987 {110, 0x06},
988 {104, 0x06},
989 {98, 0x06},
990 {110, 0x05},
991 {104, 0x05},
992 {98, 0x05},
993 {110, 0x04},
994 {104, 0x04},
995 {98, 0x04},
996 {110, 0x03},
997 {104, 0x03},
998 {98, 0x03},
999 {110, 0x02},
1000 {104, 0x02},
1001 {98, 0x02},
1002 {110, 0x01},
1003 {104, 0x01},
1004 {98, 0x01},
1005 {110, 0x00},
1006 {104, 0x00},
1007 {98, 0x00},
1008 {93, 0x00},
1009 {88, 0x00},
1010 {83, 0x00},
1011 {78, 0x00},
1012 },
1013 /* 2.4GHz power gain index table */
1014 {
1015 {110, 0x3f}, /* highest txpower */
1016 {104, 0x3f},
1017 {98, 0x3f},
1018 {110, 0x3e},
1019 {104, 0x3e},
1020 {98, 0x3e},
1021 {110, 0x3d},
1022 {104, 0x3d},
1023 {98, 0x3d},
1024 {110, 0x3c},
1025 {104, 0x3c},
1026 {98, 0x3c},
1027 {110, 0x3b},
1028 {104, 0x3b},
1029 {98, 0x3b},
1030 {110, 0x3a},
1031 {104, 0x3a},
1032 {98, 0x3a},
1033 {110, 0x39},
1034 {104, 0x39},
1035 {98, 0x39},
1036 {110, 0x38},
1037 {104, 0x38},
1038 {98, 0x38},
1039 {110, 0x37},
1040 {104, 0x37},
1041 {98, 0x37},
1042 {110, 0x36},
1043 {104, 0x36},
1044 {98, 0x36},
1045 {110, 0x35},
1046 {104, 0x35},
1047 {98, 0x35},
1048 {110, 0x34},
1049 {104, 0x34},
1050 {98, 0x34},
1051 {110, 0x33},
1052 {104, 0x33},
1053 {98, 0x33},
1054 {110, 0x32},
1055 {104, 0x32},
1056 {98, 0x32},
1057 {110, 0x31},
1058 {104, 0x31},
1059 {98, 0x31},
1060 {110, 0x30},
1061 {104, 0x30},
1062 {98, 0x30},
1063 {110, 0x6},
1064 {104, 0x6},
1065 {98, 0x6},
1066 {110, 0x5},
1067 {104, 0x5},
1068 {98, 0x5},
1069 {110, 0x4},
1070 {104, 0x4},
1071 {98, 0x4},
1072 {110, 0x3},
1073 {104, 0x3},
1074 {98, 0x3},
1075 {110, 0x2},
1076 {104, 0x2},
1077 {98, 0x2},
1078 {110, 0x1},
1079 {104, 0x1},
1080 {98, 0x1},
1081 {110, 0x0},
1082 {104, 0x0},
1083 {98, 0x0},
1084 {97, 0},
1085 {96, 0},
1086 {95, 0},
1087 {94, 0},
1088 {93, 0},
1089 {92, 0},
1090 {91, 0},
1091 {90, 0},
1092 {89, 0},
1093 {88, 0},
1094 {87, 0},
1095 {86, 0},
1096 {85, 0},
1097 {84, 0},
1098 {83, 0},
1099 {82, 0},
1100 {81, 0},
1101 {80, 0},
1102 {79, 0},
1103 {78, 0},
1104 {77, 0},
1105 {76, 0},
1106 {75, 0},
1107 {74, 0},
1108 {73, 0},
1109 {72, 0},
1110 {71, 0},
1111 {70, 0},
1112 {69, 0},
1113 {68, 0},
1114 {67, 0},
1115 {66, 0},
1116 {65, 0},
1117 {64, 0},
1118 {63, 0},
1119 {62, 0},
1120 {61, 0},
1121 {60, 0},
1122 {59, 0},
1123 }
1124 };
1125
1126 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1127 u8 is_ht40, u8 ctrl_chan_high,
1128 struct iwl4965_tx_power_db *tx_power_tbl)
1129 {
1130 u8 saturation_power;
1131 s32 target_power;
1132 s32 user_target_power;
1133 s32 power_limit;
1134 s32 current_temp;
1135 s32 reg_limit;
1136 s32 current_regulatory;
1137 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1138 int i;
1139 int c;
1140 const struct iwl_channel_info *ch_info = NULL;
1141 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1142 const struct iwl_eeprom_calib_measure *measurement;
1143 s16 voltage;
1144 s32 init_voltage;
1145 s32 voltage_compensation;
1146 s32 degrees_per_05db_num;
1147 s32 degrees_per_05db_denom;
1148 s32 factory_temp;
1149 s32 temperature_comp[2];
1150 s32 factory_gain_index[2];
1151 s32 factory_actual_pwr[2];
1152 s32 power_index;
1153
1154 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1155 * are used for indexing into txpower table) */
1156 user_target_power = 2 * priv->tx_power_user_lmt;
1157
1158 /* Get current (RXON) channel, band, width */
1159 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1160 is_ht40);
1161
1162 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1163
1164 if (!is_channel_valid(ch_info))
1165 return -EINVAL;
1166
1167 /* get txatten group, used to select 1) thermal txpower adjustment
1168 * and 2) mimo txpower balance between Tx chains. */
1169 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1170 if (txatten_grp < 0) {
1171 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1172 channel);
1173 return -EINVAL;
1174 }
1175
1176 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1177 channel, txatten_grp);
1178
1179 if (is_ht40) {
1180 if (ctrl_chan_high)
1181 channel -= 2;
1182 else
1183 channel += 2;
1184 }
1185
1186 /* hardware txpower limits ...
1187 * saturation (clipping distortion) txpowers are in half-dBm */
1188 if (band)
1189 saturation_power = priv->calib_info->saturation_power24;
1190 else
1191 saturation_power = priv->calib_info->saturation_power52;
1192
1193 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1194 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1195 if (band)
1196 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1197 else
1198 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1199 }
1200
1201 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1202 * max_power_avg values are in dBm, convert * 2 */
1203 if (is_ht40)
1204 reg_limit = ch_info->ht40_max_power_avg * 2;
1205 else
1206 reg_limit = ch_info->max_power_avg * 2;
1207
1208 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1209 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1210 if (band)
1211 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1212 else
1213 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1214 }
1215
1216 /* Interpolate txpower calibration values for this channel,
1217 * based on factory calibration tests on spaced channels. */
1218 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1219
1220 /* calculate tx gain adjustment based on power supply voltage */
1221 voltage = le16_to_cpu(priv->calib_info->voltage);
1222 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1223 voltage_compensation =
1224 iwl4965_get_voltage_compensation(voltage, init_voltage);
1225
1226 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1227 init_voltage,
1228 voltage, voltage_compensation);
1229
1230 /* get current temperature (Celsius) */
1231 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1232 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1233 current_temp = KELVIN_TO_CELSIUS(current_temp);
1234
1235 /* select thermal txpower adjustment params, based on channel group
1236 * (same frequency group used for mimo txatten adjustment) */
1237 degrees_per_05db_num =
1238 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1239 degrees_per_05db_denom =
1240 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1241
1242 /* get per-chain txpower values from factory measurements */
1243 for (c = 0; c < 2; c++) {
1244 measurement = &ch_eeprom_info.measurements[c][1];
1245
1246 /* txgain adjustment (in half-dB steps) based on difference
1247 * between factory and current temperature */
1248 factory_temp = measurement->temperature;
1249 iwl4965_math_div_round((current_temp - factory_temp) *
1250 degrees_per_05db_denom,
1251 degrees_per_05db_num,
1252 &temperature_comp[c]);
1253
1254 factory_gain_index[c] = measurement->gain_idx;
1255 factory_actual_pwr[c] = measurement->actual_pow;
1256
1257 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1258 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1259 "curr tmp %d, comp %d steps\n",
1260 factory_temp, current_temp,
1261 temperature_comp[c]);
1262
1263 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1264 factory_gain_index[c],
1265 factory_actual_pwr[c]);
1266 }
1267
1268 /* for each of 33 bit-rates (including 1 for CCK) */
1269 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1270 u8 is_mimo_rate;
1271 union iwl4965_tx_power_dual_stream tx_power;
1272
1273 /* for mimo, reduce each chain's txpower by half
1274 * (3dB, 6 steps), so total output power is regulatory
1275 * compliant. */
1276 if (i & 0x8) {
1277 current_regulatory = reg_limit -
1278 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1279 is_mimo_rate = 1;
1280 } else {
1281 current_regulatory = reg_limit;
1282 is_mimo_rate = 0;
1283 }
1284
1285 /* find txpower limit, either hardware or regulatory */
1286 power_limit = saturation_power - back_off_table[i];
1287 if (power_limit > current_regulatory)
1288 power_limit = current_regulatory;
1289
1290 /* reduce user's txpower request if necessary
1291 * for this rate on this channel */
1292 target_power = user_target_power;
1293 if (target_power > power_limit)
1294 target_power = power_limit;
1295
1296 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1297 i, saturation_power - back_off_table[i],
1298 current_regulatory, user_target_power,
1299 target_power);
1300
1301 /* for each of 2 Tx chains (radio transmitters) */
1302 for (c = 0; c < 2; c++) {
1303 s32 atten_value;
1304
1305 if (is_mimo_rate)
1306 atten_value =
1307 (s32)le32_to_cpu(priv->card_alive_init.
1308 tx_atten[txatten_grp][c]);
1309 else
1310 atten_value = 0;
1311
1312 /* calculate index; higher index means lower txpower */
1313 power_index = (u8) (factory_gain_index[c] -
1314 (target_power -
1315 factory_actual_pwr[c]) -
1316 temperature_comp[c] -
1317 voltage_compensation +
1318 atten_value);
1319
1320 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1321 power_index); */
1322
1323 if (power_index < get_min_power_index(i, band))
1324 power_index = get_min_power_index(i, band);
1325
1326 /* adjust 5 GHz index to support negative indexes */
1327 if (!band)
1328 power_index += 9;
1329
1330 /* CCK, rate 32, reduce txpower for CCK */
1331 if (i == POWER_TABLE_CCK_ENTRY)
1332 power_index +=
1333 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1334
1335 /* stay within the table! */
1336 if (power_index > 107) {
1337 IWL_WARN(priv, "txpower index %d > 107\n",
1338 power_index);
1339 power_index = 107;
1340 }
1341 if (power_index < 0) {
1342 IWL_WARN(priv, "txpower index %d < 0\n",
1343 power_index);
1344 power_index = 0;
1345 }
1346
1347 /* fill txpower command for this rate/chain */
1348 tx_power.s.radio_tx_gain[c] =
1349 gain_table[band][power_index].radio;
1350 tx_power.s.dsp_predis_atten[c] =
1351 gain_table[band][power_index].dsp;
1352
1353 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1354 "gain 0x%02x dsp %d\n",
1355 c, atten_value, power_index,
1356 tx_power.s.radio_tx_gain[c],
1357 tx_power.s.dsp_predis_atten[c]);
1358 } /* for each chain */
1359
1360 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1361
1362 } /* for each rate */
1363
1364 return 0;
1365 }
1366
1367 /**
1368 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1369 *
1370 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1371 * The power limit is taken from priv->tx_power_user_lmt.
1372 */
1373 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1374 {
1375 struct iwl4965_txpowertable_cmd cmd = { 0 };
1376 int ret;
1377 u8 band = 0;
1378 bool is_ht40 = false;
1379 u8 ctrl_chan_high = 0;
1380
1381 if (test_bit(STATUS_SCANNING, &priv->status)) {
1382 /* If this gets hit a lot, switch it to a BUG() and catch
1383 * the stack trace to find out who is calling this during
1384 * a scan. */
1385 IWL_WARN(priv, "TX Power requested while scanning!\n");
1386 return -EAGAIN;
1387 }
1388
1389 band = priv->band == IEEE80211_BAND_2GHZ;
1390
1391 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1392
1393 if (is_ht40 &&
1394 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1395 ctrl_chan_high = 1;
1396
1397 cmd.band = band;
1398 cmd.channel = priv->active_rxon.channel;
1399
1400 ret = iwl4965_fill_txpower_tbl(priv, band,
1401 le16_to_cpu(priv->active_rxon.channel),
1402 is_ht40, ctrl_chan_high, &cmd.tx_power);
1403 if (ret)
1404 goto out;
1405
1406 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1407
1408 out:
1409 return ret;
1410 }
1411
1412 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1413 {
1414 int ret = 0;
1415 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1416 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1417 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1418
1419 if ((rxon1->flags == rxon2->flags) &&
1420 (rxon1->filter_flags == rxon2->filter_flags) &&
1421 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1422 (rxon1->ofdm_ht_single_stream_basic_rates ==
1423 rxon2->ofdm_ht_single_stream_basic_rates) &&
1424 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1425 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1426 (rxon1->rx_chain == rxon2->rx_chain) &&
1427 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1428 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1429 return 0;
1430 }
1431
1432 rxon_assoc.flags = priv->staging_rxon.flags;
1433 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1434 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1435 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1436 rxon_assoc.reserved = 0;
1437 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1438 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1439 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1440 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1441 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1442
1443 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1444 sizeof(rxon_assoc), &rxon_assoc, NULL);
1445 if (ret)
1446 return ret;
1447
1448 return ret;
1449 }
1450
1451 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1452 {
1453 int rc;
1454 u8 band = 0;
1455 bool is_ht40 = false;
1456 u8 ctrl_chan_high = 0;
1457 struct iwl4965_channel_switch_cmd cmd;
1458 const struct iwl_channel_info *ch_info;
1459
1460 band = priv->band == IEEE80211_BAND_2GHZ;
1461
1462 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1463
1464 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1465
1466 if (is_ht40 &&
1467 (priv->staging_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1468 ctrl_chan_high = 1;
1469
1470 cmd.band = band;
1471 cmd.expect_beacon = 0;
1472 cmd.channel = cpu_to_le16(channel);
1473 cmd.rxon_flags = priv->staging_rxon.flags;
1474 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1475 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1476 if (ch_info)
1477 cmd.expect_beacon = is_channel_radar(ch_info);
1478 else {
1479 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1480 priv->active_rxon.channel, channel);
1481 return -EFAULT;
1482 }
1483
1484 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1485 ctrl_chan_high, &cmd.tx_power);
1486 if (rc) {
1487 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1488 return rc;
1489 }
1490
1491 priv->switch_rxon.channel = cpu_to_le16(channel);
1492 priv->switch_rxon.switch_in_progress = true;
1493
1494 return iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1495 }
1496
1497 /**
1498 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1499 */
1500 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1501 struct iwl_tx_queue *txq,
1502 u16 byte_cnt)
1503 {
1504 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1505 int txq_id = txq->q.id;
1506 int write_ptr = txq->q.write_ptr;
1507 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1508 __le16 bc_ent;
1509
1510 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1511
1512 bc_ent = cpu_to_le16(len & 0xFFF);
1513 /* Set up byte count within first 256 entries */
1514 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1515
1516 /* If within first 64 entries, duplicate at end */
1517 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1518 scd_bc_tbl[txq_id].
1519 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1520 }
1521
1522 /**
1523 * sign_extend - Sign extend a value using specified bit as sign-bit
1524 *
1525 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1526 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1527 *
1528 * @param oper value to sign extend
1529 * @param index 0 based bit index (0<=index<32) to sign bit
1530 */
1531 static s32 sign_extend(u32 oper, int index)
1532 {
1533 u8 shift = 31 - index;
1534
1535 return (s32)(oper << shift) >> shift;
1536 }
1537
1538 /**
1539 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1540 * @statistics: Provides the temperature reading from the uCode
1541 *
1542 * A return of <0 indicates bogus data in the statistics
1543 */
1544 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1545 {
1546 s32 temperature;
1547 s32 vt;
1548 s32 R1, R2, R3;
1549 u32 R4;
1550
1551 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1552 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1553 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1554 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1555 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1556 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1557 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1558 } else {
1559 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1560 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1561 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1562 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1563 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1564 }
1565
1566 /*
1567 * Temperature is only 23 bits, so sign extend out to 32.
1568 *
1569 * NOTE If we haven't received a statistics notification yet
1570 * with an updated temperature, use R4 provided to us in the
1571 * "initialize" ALIVE response.
1572 */
1573 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1574 vt = sign_extend(R4, 23);
1575 else
1576 vt = sign_extend(
1577 le32_to_cpu(priv->statistics.general.temperature), 23);
1578
1579 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1580
1581 if (R3 == R1) {
1582 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1583 return -1;
1584 }
1585
1586 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1587 * Add offset to center the adjustment around 0 degrees Centigrade. */
1588 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1589 temperature /= (R3 - R1);
1590 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1591
1592 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1593 temperature, KELVIN_TO_CELSIUS(temperature));
1594
1595 return temperature;
1596 }
1597
1598 /* Adjust Txpower only if temperature variance is greater than threshold. */
1599 #define IWL_TEMPERATURE_THRESHOLD 3
1600
1601 /**
1602 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1603 *
1604 * If the temperature changed has changed sufficiently, then a recalibration
1605 * is needed.
1606 *
1607 * Assumes caller will replace priv->last_temperature once calibration
1608 * executed.
1609 */
1610 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1611 {
1612 int temp_diff;
1613
1614 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1615 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1616 return 0;
1617 }
1618
1619 temp_diff = priv->temperature - priv->last_temperature;
1620
1621 /* get absolute value */
1622 if (temp_diff < 0) {
1623 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1624 temp_diff = -temp_diff;
1625 } else if (temp_diff == 0)
1626 IWL_DEBUG_POWER(priv, "Same temp, \n");
1627 else
1628 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1629
1630 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1631 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1632 return 0;
1633 }
1634
1635 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1636
1637 return 1;
1638 }
1639
1640 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1641 {
1642 s32 temp;
1643
1644 temp = iwl4965_hw_get_temperature(priv);
1645 if (temp < 0)
1646 return;
1647
1648 if (priv->temperature != temp) {
1649 if (priv->temperature)
1650 IWL_DEBUG_TEMP(priv, "Temperature changed "
1651 "from %dC to %dC\n",
1652 KELVIN_TO_CELSIUS(priv->temperature),
1653 KELVIN_TO_CELSIUS(temp));
1654 else
1655 IWL_DEBUG_TEMP(priv, "Temperature "
1656 "initialized to %dC\n",
1657 KELVIN_TO_CELSIUS(temp));
1658 }
1659
1660 priv->temperature = temp;
1661 iwl_tt_handler(priv);
1662 set_bit(STATUS_TEMPERATURE, &priv->status);
1663
1664 if (!priv->disable_tx_power_cal &&
1665 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1666 iwl4965_is_temp_calib_needed(priv))
1667 queue_work(priv->workqueue, &priv->txpower_work);
1668 }
1669
1670 /**
1671 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1672 */
1673 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1674 u16 txq_id)
1675 {
1676 /* Simply stop the queue, but don't change any configuration;
1677 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1678 iwl_write_prph(priv,
1679 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1680 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1681 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1682 }
1683
1684 /**
1685 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1686 * priv->lock must be held by the caller
1687 */
1688 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1689 u16 ssn_idx, u8 tx_fifo)
1690 {
1691 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1692 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1693 <= txq_id)) {
1694 IWL_WARN(priv,
1695 "queue number out of range: %d, must be %d to %d\n",
1696 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1697 IWL49_FIRST_AMPDU_QUEUE +
1698 priv->cfg->num_of_ampdu_queues - 1);
1699 return -EINVAL;
1700 }
1701
1702 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1703
1704 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1705
1706 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1707 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1708 /* supposes that ssn_idx is valid (!= 0xFFF) */
1709 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1710
1711 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1712 iwl_txq_ctx_deactivate(priv, txq_id);
1713 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1714
1715 return 0;
1716 }
1717
1718 /**
1719 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1720 */
1721 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1722 u16 txq_id)
1723 {
1724 u32 tbl_dw_addr;
1725 u32 tbl_dw;
1726 u16 scd_q2ratid;
1727
1728 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1729
1730 tbl_dw_addr = priv->scd_base_addr +
1731 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1732
1733 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1734
1735 if (txq_id & 0x1)
1736 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1737 else
1738 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1739
1740 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1741
1742 return 0;
1743 }
1744
1745
1746 /**
1747 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1748 *
1749 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1750 * i.e. it must be one of the higher queues used for aggregation
1751 */
1752 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1753 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1754 {
1755 unsigned long flags;
1756 u16 ra_tid;
1757
1758 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1759 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1760 <= txq_id)) {
1761 IWL_WARN(priv,
1762 "queue number out of range: %d, must be %d to %d\n",
1763 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1764 IWL49_FIRST_AMPDU_QUEUE +
1765 priv->cfg->num_of_ampdu_queues - 1);
1766 return -EINVAL;
1767 }
1768
1769 ra_tid = BUILD_RAxTID(sta_id, tid);
1770
1771 /* Modify device's station table to Tx this TID */
1772 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1773
1774 spin_lock_irqsave(&priv->lock, flags);
1775
1776 /* Stop this Tx queue before configuring it */
1777 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1778
1779 /* Map receiver-address / traffic-ID to this queue */
1780 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1781
1782 /* Set this queue as a chain-building queue */
1783 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1784
1785 /* Place first TFD at index corresponding to start sequence number.
1786 * Assumes that ssn_idx is valid (!= 0xFFF) */
1787 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1788 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1789 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1790
1791 /* Set up Tx window size and frame limit for this queue */
1792 iwl_write_targ_mem(priv,
1793 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1794 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1795 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1796
1797 iwl_write_targ_mem(priv, priv->scd_base_addr +
1798 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1799 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1800 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1801
1802 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1803
1804 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1805 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1806
1807 spin_unlock_irqrestore(&priv->lock, flags);
1808
1809 return 0;
1810 }
1811
1812
1813 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1814 {
1815 switch (cmd_id) {
1816 case REPLY_RXON:
1817 return (u16) sizeof(struct iwl4965_rxon_cmd);
1818 default:
1819 return len;
1820 }
1821 }
1822
1823 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1824 {
1825 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1826 addsta->mode = cmd->mode;
1827 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1828 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1829 addsta->station_flags = cmd->station_flags;
1830 addsta->station_flags_msk = cmd->station_flags_msk;
1831 addsta->tid_disable_tx = cmd->tid_disable_tx;
1832 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1833 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1834 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1835 addsta->sleep_tx_count = cmd->sleep_tx_count;
1836 addsta->reserved1 = cpu_to_le16(0);
1837 addsta->reserved2 = cpu_to_le16(0);
1838
1839 return (u16)sizeof(struct iwl4965_addsta_cmd);
1840 }
1841
1842 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1843 {
1844 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1845 }
1846
1847 /**
1848 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1849 */
1850 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1851 struct iwl_ht_agg *agg,
1852 struct iwl4965_tx_resp *tx_resp,
1853 int txq_id, u16 start_idx)
1854 {
1855 u16 status;
1856 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1857 struct ieee80211_tx_info *info = NULL;
1858 struct ieee80211_hdr *hdr = NULL;
1859 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1860 int i, sh, idx;
1861 u16 seq;
1862 if (agg->wait_for_ba)
1863 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1864
1865 agg->frame_count = tx_resp->frame_count;
1866 agg->start_idx = start_idx;
1867 agg->rate_n_flags = rate_n_flags;
1868 agg->bitmap = 0;
1869
1870 /* num frames attempted by Tx command */
1871 if (agg->frame_count == 1) {
1872 /* Only one frame was attempted; no block-ack will arrive */
1873 status = le16_to_cpu(frame_status[0].status);
1874 idx = start_idx;
1875
1876 /* FIXME: code repetition */
1877 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1878 agg->frame_count, agg->start_idx, idx);
1879
1880 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1881 info->status.rates[0].count = tx_resp->failure_frame + 1;
1882 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1883 info->flags |= iwl_tx_status_to_mac80211(status);
1884 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
1885 /* FIXME: code repetition end */
1886
1887 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1888 status & 0xff, tx_resp->failure_frame);
1889 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1890
1891 agg->wait_for_ba = 0;
1892 } else {
1893 /* Two or more frames were attempted; expect block-ack */
1894 u64 bitmap = 0;
1895 int start = agg->start_idx;
1896
1897 /* Construct bit-map of pending frames within Tx window */
1898 for (i = 0; i < agg->frame_count; i++) {
1899 u16 sc;
1900 status = le16_to_cpu(frame_status[i].status);
1901 seq = le16_to_cpu(frame_status[i].sequence);
1902 idx = SEQ_TO_INDEX(seq);
1903 txq_id = SEQ_TO_QUEUE(seq);
1904
1905 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1906 AGG_TX_STATE_ABORT_MSK))
1907 continue;
1908
1909 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1910 agg->frame_count, txq_id, idx);
1911
1912 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1913 if (!hdr) {
1914 IWL_ERR(priv,
1915 "BUG_ON idx doesn't point to valid skb"
1916 " idx=%d, txq_id=%d\n", idx, txq_id);
1917 return -1;
1918 }
1919
1920 sc = le16_to_cpu(hdr->seq_ctrl);
1921 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1922 IWL_ERR(priv,
1923 "BUG_ON idx doesn't match seq control"
1924 " idx=%d, seq_idx=%d, seq=%d\n",
1925 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1926 return -1;
1927 }
1928
1929 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1930 i, idx, SEQ_TO_SN(sc));
1931
1932 sh = idx - start;
1933 if (sh > 64) {
1934 sh = (start - idx) + 0xff;
1935 bitmap = bitmap << sh;
1936 sh = 0;
1937 start = idx;
1938 } else if (sh < -64)
1939 sh = 0xff - (start - idx);
1940 else if (sh < 0) {
1941 sh = start - idx;
1942 start = idx;
1943 bitmap = bitmap << sh;
1944 sh = 0;
1945 }
1946 bitmap |= 1ULL << sh;
1947 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1948 start, (unsigned long long)bitmap);
1949 }
1950
1951 agg->bitmap = bitmap;
1952 agg->start_idx = start;
1953 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1954 agg->frame_count, agg->start_idx,
1955 (unsigned long long)agg->bitmap);
1956
1957 if (bitmap)
1958 agg->wait_for_ba = 1;
1959 }
1960 return 0;
1961 }
1962
1963 /**
1964 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
1965 */
1966 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
1967 struct iwl_rx_mem_buffer *rxb)
1968 {
1969 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1970 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1971 int txq_id = SEQ_TO_QUEUE(sequence);
1972 int index = SEQ_TO_INDEX(sequence);
1973 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1974 struct ieee80211_hdr *hdr;
1975 struct ieee80211_tx_info *info;
1976 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1977 u32 status = le32_to_cpu(tx_resp->u.status);
1978 int uninitialized_var(tid);
1979 int sta_id;
1980 int freed;
1981 u8 *qc = NULL;
1982
1983 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1984 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1985 "is out of range [0-%d] %d %d\n", txq_id,
1986 index, txq->q.n_bd, txq->q.write_ptr,
1987 txq->q.read_ptr);
1988 return;
1989 }
1990
1991 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1992 memset(&info->status, 0, sizeof(info->status));
1993
1994 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1995 if (ieee80211_is_data_qos(hdr->frame_control)) {
1996 qc = ieee80211_get_qos_ctl(hdr);
1997 tid = qc[0] & 0xf;
1998 }
1999
2000 sta_id = iwl_get_ra_sta_id(priv, hdr);
2001 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2002 IWL_ERR(priv, "Station not known\n");
2003 return;
2004 }
2005
2006 if (txq->sched_retry) {
2007 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2008 struct iwl_ht_agg *agg = NULL;
2009
2010 WARN_ON(!qc);
2011
2012 agg = &priv->stations[sta_id].tid[tid].agg;
2013
2014 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2015
2016 /* check if BAR is needed */
2017 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2018 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2019
2020 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2021 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2022 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2023 "%d index %d\n", scd_ssn , index);
2024 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2025 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
2026
2027 if (priv->mac80211_registered &&
2028 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2029 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2030 if (agg->state == IWL_AGG_OFF)
2031 iwl_wake_queue(priv, txq_id);
2032 else
2033 iwl_wake_queue(priv, txq->swq_id);
2034 }
2035 }
2036 } else {
2037 info->status.rates[0].count = tx_resp->failure_frame + 1;
2038 info->flags |= iwl_tx_status_to_mac80211(status);
2039 iwlagn_hwrate_to_tx_control(priv,
2040 le32_to_cpu(tx_resp->rate_n_flags),
2041 info);
2042
2043 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2044 "rate_n_flags 0x%x retries %d\n",
2045 txq_id,
2046 iwl_get_tx_fail_reason(status), status,
2047 le32_to_cpu(tx_resp->rate_n_flags),
2048 tx_resp->failure_frame);
2049
2050 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2051 if (qc && likely(sta_id != IWL_INVALID_STATION))
2052 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2053
2054 if (priv->mac80211_registered &&
2055 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2056 iwl_wake_queue(priv, txq_id);
2057 }
2058
2059 if (qc && likely(sta_id != IWL_INVALID_STATION))
2060 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
2061
2062 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2063 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
2064 }
2065
2066 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2067 struct iwl_rx_phy_res *rx_resp)
2068 {
2069 /* data from PHY/DSP regarding signal strength, etc.,
2070 * contents are always there, not configurable by host. */
2071 struct iwl4965_rx_non_cfg_phy *ncphy =
2072 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2073 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2074 >> IWL49_AGC_DB_POS;
2075
2076 u32 valid_antennae =
2077 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2078 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2079 u8 max_rssi = 0;
2080 u32 i;
2081
2082 /* Find max rssi among 3 possible receivers.
2083 * These values are measured by the digital signal processor (DSP).
2084 * They should stay fairly constant even as the signal strength varies,
2085 * if the radio's automatic gain control (AGC) is working right.
2086 * AGC value (see below) will provide the "interesting" info. */
2087 for (i = 0; i < 3; i++)
2088 if (valid_antennae & (1 << i))
2089 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2090
2091 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2092 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2093 max_rssi, agc);
2094
2095 /* dBm = max_rssi dB - agc dB - constant.
2096 * Higher AGC (higher radio gain) means lower signal. */
2097 return max_rssi - agc - IWL49_RSSI_OFFSET;
2098 }
2099
2100
2101 /* Set up 4965-specific Rx frame reply handlers */
2102 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2103 {
2104 /* Legacy Rx frames */
2105 priv->rx_handlers[REPLY_RX] = iwlagn_rx_reply_rx;
2106 /* Tx response */
2107 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2108 }
2109
2110 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2111 {
2112 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2113 }
2114
2115 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2116 {
2117 cancel_work_sync(&priv->txpower_work);
2118 }
2119
2120 #define IWL4965_UCODE_GET(item) \
2121 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2122 u32 api_ver) \
2123 { \
2124 return le32_to_cpu(ucode->u.v1.item); \
2125 }
2126
2127 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2128 {
2129 return UCODE_HEADER_SIZE(1);
2130 }
2131 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2132 u32 api_ver)
2133 {
2134 return 0;
2135 }
2136 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2137 u32 api_ver)
2138 {
2139 return (u8 *) ucode->u.v1.data;
2140 }
2141
2142 IWL4965_UCODE_GET(inst_size);
2143 IWL4965_UCODE_GET(data_size);
2144 IWL4965_UCODE_GET(init_size);
2145 IWL4965_UCODE_GET(init_data_size);
2146 IWL4965_UCODE_GET(boot_size);
2147
2148 static struct iwl_hcmd_ops iwl4965_hcmd = {
2149 .rxon_assoc = iwl4965_send_rxon_assoc,
2150 .commit_rxon = iwl_commit_rxon,
2151 .set_rxon_chain = iwl_set_rxon_chain,
2152 };
2153
2154 static struct iwl_ucode_ops iwl4965_ucode = {
2155 .get_header_size = iwl4965_ucode_get_header_size,
2156 .get_build = iwl4965_ucode_get_build,
2157 .get_inst_size = iwl4965_ucode_get_inst_size,
2158 .get_data_size = iwl4965_ucode_get_data_size,
2159 .get_init_size = iwl4965_ucode_get_init_size,
2160 .get_init_data_size = iwl4965_ucode_get_init_data_size,
2161 .get_boot_size = iwl4965_ucode_get_boot_size,
2162 .get_data = iwl4965_ucode_get_data,
2163 };
2164 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2165 .get_hcmd_size = iwl4965_get_hcmd_size,
2166 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2167 .chain_noise_reset = iwl4965_chain_noise_reset,
2168 .gain_computation = iwl4965_gain_computation,
2169 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2170 .calc_rssi = iwl4965_calc_rssi,
2171 };
2172
2173 static struct iwl_lib_ops iwl4965_lib = {
2174 .set_hw_params = iwl4965_hw_set_hw_params,
2175 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2176 .txq_set_sched = iwl4965_txq_set_sched,
2177 .txq_agg_enable = iwl4965_txq_agg_enable,
2178 .txq_agg_disable = iwl4965_txq_agg_disable,
2179 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2180 .txq_free_tfd = iwl_hw_txq_free_tfd,
2181 .txq_init = iwl_hw_tx_queue_init,
2182 .rx_handler_setup = iwl4965_rx_handler_setup,
2183 .setup_deferred_work = iwl4965_setup_deferred_work,
2184 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2185 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2186 .alive_notify = iwl4965_alive_notify,
2187 .init_alive_start = iwl4965_init_alive_start,
2188 .load_ucode = iwl4965_load_bsm,
2189 .dump_nic_event_log = iwl_dump_nic_event_log,
2190 .dump_nic_error_log = iwl_dump_nic_error_log,
2191 .dump_fh = iwl_dump_fh,
2192 .set_channel_switch = iwl4965_hw_channel_switch,
2193 .apm_ops = {
2194 .init = iwl_apm_init,
2195 .stop = iwl_apm_stop,
2196 .config = iwl4965_nic_config,
2197 .set_pwr_src = iwl_set_pwr_src,
2198 },
2199 .eeprom_ops = {
2200 .regulatory_bands = {
2201 EEPROM_REGULATORY_BAND_1_CHANNELS,
2202 EEPROM_REGULATORY_BAND_2_CHANNELS,
2203 EEPROM_REGULATORY_BAND_3_CHANNELS,
2204 EEPROM_REGULATORY_BAND_4_CHANNELS,
2205 EEPROM_REGULATORY_BAND_5_CHANNELS,
2206 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2207 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2208 },
2209 .verify_signature = iwlcore_eeprom_verify_signature,
2210 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2211 .release_semaphore = iwlcore_eeprom_release_semaphore,
2212 .calib_version = iwl4965_eeprom_calib_version,
2213 .query_addr = iwlcore_eeprom_query_addr,
2214 },
2215 .send_tx_power = iwl4965_send_tx_power,
2216 .update_chain_flags = iwl_update_chain_flags,
2217 .post_associate = iwl_post_associate,
2218 .config_ap = iwl_config_ap,
2219 .isr = iwl_isr_legacy,
2220 .temp_ops = {
2221 .temperature = iwl4965_temperature_calib,
2222 .set_ct_kill = iwl4965_set_ct_threshold,
2223 },
2224 .add_bcast_station = iwl_add_bcast_station,
2225 .check_plcp_health = iwl_good_plcp_health,
2226 };
2227
2228 static const struct iwl_ops iwl4965_ops = {
2229 .ucode = &iwl4965_ucode,
2230 .lib = &iwl4965_lib,
2231 .hcmd = &iwl4965_hcmd,
2232 .utils = &iwl4965_hcmd_utils,
2233 .led = &iwlagn_led_ops,
2234 };
2235
2236 struct iwl_cfg iwl4965_agn_cfg = {
2237 .name = "Intel(R) Wireless WiFi Link 4965AGN",
2238 .fw_name_pre = IWL4965_FW_PRE,
2239 .ucode_api_max = IWL4965_UCODE_API_MAX,
2240 .ucode_api_min = IWL4965_UCODE_API_MIN,
2241 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2242 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2243 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2244 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2245 .ops = &iwl4965_ops,
2246 .num_of_queues = IWL49_NUM_QUEUES,
2247 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2248 .mod_params = &iwl4965_mod_params,
2249 .valid_tx_ant = ANT_AB,
2250 .valid_rx_ant = ANT_ABC,
2251 .pll_cfg_val = 0,
2252 .set_l0s = true,
2253 .use_bsm = true,
2254 .use_isr_legacy = true,
2255 .ht_greenfield_support = false,
2256 .broken_powersave = true,
2257 .led_compensation = 61,
2258 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2259 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2260 .monitor_recover_period = IWL_MONITORING_PERIOD,
2261 };
2262
2263 /* Module firmware */
2264 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2265
2266 module_param_named(antenna, iwl4965_mod_params.antenna, int, S_IRUGO);
2267 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2268 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
2269 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2270 module_param_named(
2271 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, S_IRUGO);
2272 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2273
2274 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
2275 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2276 /* 11n */
2277 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
2278 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2279 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
2280 int, S_IRUGO);
2281 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2282
2283 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, S_IRUGO);
2284 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux kernel - Deliverables
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