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iwlwifi: update supported PCI_ID list for 5xx0 series
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-agn-led.h"
46 #include "iwl-5000-hw.h"
47 #include "iwl-6000-hw.h"
48
49 /* Highest firmware API version supported */
50 #define IWL5000_UCODE_API_MAX 2
51 #define IWL5150_UCODE_API_MAX 2
52
53 /* Lowest firmware API version supported */
54 #define IWL5000_UCODE_API_MIN 1
55 #define IWL5150_UCODE_API_MIN 1
56
57 #define IWL5000_FW_PRE "iwlwifi-5000-"
58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60
61 #define IWL5150_FW_PRE "iwlwifi-5150-"
62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64
65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
66 IWL_TX_FIFO_AC3,
67 IWL_TX_FIFO_AC2,
68 IWL_TX_FIFO_AC1,
69 IWL_TX_FIFO_AC0,
70 IWL50_CMD_FIFO_NUM,
71 IWL_TX_FIFO_HCCA_1,
72 IWL_TX_FIFO_HCCA_2
73 };
74
75 /* NIC configuration for 5000 series */
76 void iwl5000_nic_config(struct iwl_priv *priv)
77 {
78 unsigned long flags;
79 u16 radio_cfg;
80
81 spin_lock_irqsave(&priv->lock, flags);
82
83 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
84
85 /* write radio config values to register */
86 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
87 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
88 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
89 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
90 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
91
92 /* set CSR_HW_CONFIG_REG for uCode use */
93 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
94 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
95 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
96
97 /* W/A : NIC is stuck in a reset state after Early PCIe power off
98 * (PCIe power is lost before PERST# is asserted),
99 * causing ME FW to lose ownership and not being able to obtain it back.
100 */
101 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
102 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
103 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
104
105
106 spin_unlock_irqrestore(&priv->lock, flags);
107 }
108
109
110 /*
111 * EEPROM
112 */
113 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
114 {
115 u16 offset = 0;
116
117 if ((address & INDIRECT_ADDRESS) == 0)
118 return address;
119
120 switch (address & INDIRECT_TYPE_MSK) {
121 case INDIRECT_HOST:
122 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
123 break;
124 case INDIRECT_GENERAL:
125 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
126 break;
127 case INDIRECT_REGULATORY:
128 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
129 break;
130 case INDIRECT_CALIBRATION:
131 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
132 break;
133 case INDIRECT_PROCESS_ADJST:
134 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
135 break;
136 case INDIRECT_OTHERS:
137 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
138 break;
139 default:
140 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
141 address & INDIRECT_TYPE_MSK);
142 break;
143 }
144
145 /* translate the offset from words to byte */
146 return (address & ADDRESS_MSK) + (offset << 1);
147 }
148
149 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
150 {
151 struct iwl_eeprom_calib_hdr {
152 u8 version;
153 u8 pa_type;
154 u16 voltage;
155 } *hdr;
156
157 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
158 EEPROM_5000_CALIB_ALL);
159 return hdr->version;
160
161 }
162
163 static void iwl5000_gain_computation(struct iwl_priv *priv,
164 u32 average_noise[NUM_RX_CHAINS],
165 u16 min_average_noise_antenna_i,
166 u32 min_average_noise,
167 u8 default_chain)
168 {
169 int i;
170 s32 delta_g;
171 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
172
173 /*
174 * Find Gain Code for the chains based on "default chain"
175 */
176 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
177 if ((data->disconn_array[i])) {
178 data->delta_gain_code[i] = 0;
179 continue;
180 }
181 delta_g = (1000 * ((s32)average_noise[default_chain] -
182 (s32)average_noise[i])) / 1500;
183 /* bound gain by 2 bits value max, 3rd bit is sign */
184 data->delta_gain_code[i] =
185 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
186
187 if (delta_g < 0)
188 /* set negative sign */
189 data->delta_gain_code[i] |= (1 << 2);
190 }
191
192 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
193 data->delta_gain_code[1], data->delta_gain_code[2]);
194
195 if (!data->radio_write) {
196 struct iwl_calib_chain_noise_gain_cmd cmd;
197
198 memset(&cmd, 0, sizeof(cmd));
199
200 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
201 cmd.hdr.first_group = 0;
202 cmd.hdr.groups_num = 1;
203 cmd.hdr.data_valid = 1;
204 cmd.delta_gain_1 = data->delta_gain_code[1];
205 cmd.delta_gain_2 = data->delta_gain_code[2];
206 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
207 sizeof(cmd), &cmd, NULL);
208
209 data->radio_write = 1;
210 data->state = IWL_CHAIN_NOISE_CALIBRATED;
211 }
212
213 data->chain_noise_a = 0;
214 data->chain_noise_b = 0;
215 data->chain_noise_c = 0;
216 data->chain_signal_a = 0;
217 data->chain_signal_b = 0;
218 data->chain_signal_c = 0;
219 data->beacon_count = 0;
220 }
221
222 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
223 {
224 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
225 int ret;
226
227 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
228 struct iwl_calib_chain_noise_reset_cmd cmd;
229 memset(&cmd, 0, sizeof(cmd));
230
231 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
232 cmd.hdr.first_group = 0;
233 cmd.hdr.groups_num = 1;
234 cmd.hdr.data_valid = 1;
235 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
236 sizeof(cmd), &cmd);
237 if (ret)
238 IWL_ERR(priv,
239 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
240 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
241 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
242 }
243 }
244
245 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
246 __le32 *tx_flags)
247 {
248 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
249 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
250 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
251 else
252 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
253 }
254
255 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
256 .min_nrg_cck = 95,
257 .max_nrg_cck = 0, /* not used, set to 0 */
258 .auto_corr_min_ofdm = 90,
259 .auto_corr_min_ofdm_mrc = 170,
260 .auto_corr_min_ofdm_x1 = 120,
261 .auto_corr_min_ofdm_mrc_x1 = 240,
262
263 .auto_corr_max_ofdm = 120,
264 .auto_corr_max_ofdm_mrc = 210,
265 .auto_corr_max_ofdm_x1 = 155,
266 .auto_corr_max_ofdm_mrc_x1 = 290,
267
268 .auto_corr_min_cck = 125,
269 .auto_corr_max_cck = 200,
270 .auto_corr_min_cck_mrc = 170,
271 .auto_corr_max_cck_mrc = 400,
272 .nrg_th_cck = 95,
273 .nrg_th_ofdm = 95,
274
275 .barker_corr_th_min = 190,
276 .barker_corr_th_min_mrc = 390,
277 .nrg_th_cca = 62,
278 };
279
280 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
281 .min_nrg_cck = 95,
282 .max_nrg_cck = 0, /* not used, set to 0 */
283 .auto_corr_min_ofdm = 90,
284 .auto_corr_min_ofdm_mrc = 170,
285 .auto_corr_min_ofdm_x1 = 105,
286 .auto_corr_min_ofdm_mrc_x1 = 220,
287
288 .auto_corr_max_ofdm = 120,
289 .auto_corr_max_ofdm_mrc = 210,
290 /* max = min for performance bug in 5150 DSP */
291 .auto_corr_max_ofdm_x1 = 105,
292 .auto_corr_max_ofdm_mrc_x1 = 220,
293
294 .auto_corr_min_cck = 125,
295 .auto_corr_max_cck = 200,
296 .auto_corr_min_cck_mrc = 170,
297 .auto_corr_max_cck_mrc = 400,
298 .nrg_th_cck = 95,
299 .nrg_th_ofdm = 95,
300
301 .barker_corr_th_min = 190,
302 .barker_corr_th_min_mrc = 390,
303 .nrg_th_cca = 62,
304 };
305
306 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
307 size_t offset)
308 {
309 u32 address = eeprom_indirect_address(priv, offset);
310 BUG_ON(address >= priv->cfg->eeprom_size);
311 return &priv->eeprom[address];
312 }
313
314 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
315 {
316 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
317 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
318 iwl_temp_calib_to_offset(priv);
319
320 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
321 }
322
323 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
324 {
325 /* want Celsius */
326 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
327 }
328
329 /*
330 * Calibration
331 */
332 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
333 {
334 struct iwl_calib_xtal_freq_cmd cmd;
335 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
336
337 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
338 cmd.hdr.first_group = 0;
339 cmd.hdr.groups_num = 1;
340 cmd.hdr.data_valid = 1;
341 cmd.cap_pin1 = (u8)xtal_calib[0];
342 cmd.cap_pin2 = (u8)xtal_calib[1];
343 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
344 (u8 *)&cmd, sizeof(cmd));
345 }
346
347 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
348 {
349 struct iwl_calib_cfg_cmd calib_cfg_cmd;
350 struct iwl_host_cmd cmd = {
351 .id = CALIBRATION_CFG_CMD,
352 .len = sizeof(struct iwl_calib_cfg_cmd),
353 .data = &calib_cfg_cmd,
354 };
355
356 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
357 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
358 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
359 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
360 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
361
362 return iwl_send_cmd(priv, &cmd);
363 }
364
365 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
366 struct iwl_rx_mem_buffer *rxb)
367 {
368 struct iwl_rx_packet *pkt = rxb_addr(rxb);
369 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
370 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
371 int index;
372
373 /* reduce the size of the length field itself */
374 len -= 4;
375
376 /* Define the order in which the results will be sent to the runtime
377 * uCode. iwl_send_calib_results sends them in a row according to their
378 * index. We sort them here */
379 switch (hdr->op_code) {
380 case IWL_PHY_CALIBRATE_DC_CMD:
381 index = IWL_CALIB_DC;
382 break;
383 case IWL_PHY_CALIBRATE_LO_CMD:
384 index = IWL_CALIB_LO;
385 break;
386 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
387 index = IWL_CALIB_TX_IQ;
388 break;
389 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
390 index = IWL_CALIB_TX_IQ_PERD;
391 break;
392 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
393 index = IWL_CALIB_BASE_BAND;
394 break;
395 default:
396 IWL_ERR(priv, "Unknown calibration notification %d\n",
397 hdr->op_code);
398 return;
399 }
400 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
401 }
402
403 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
404 struct iwl_rx_mem_buffer *rxb)
405 {
406 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
407 queue_work(priv->workqueue, &priv->restart);
408 }
409
410 /*
411 * ucode
412 */
413 static int iwl5000_load_section(struct iwl_priv *priv,
414 struct fw_desc *image,
415 u32 dst_addr)
416 {
417 dma_addr_t phy_addr = image->p_addr;
418 u32 byte_cnt = image->len;
419
420 iwl_write_direct32(priv,
421 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
422 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
423
424 iwl_write_direct32(priv,
425 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
426
427 iwl_write_direct32(priv,
428 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
429 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
430
431 iwl_write_direct32(priv,
432 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
433 (iwl_get_dma_hi_addr(phy_addr)
434 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
435
436 iwl_write_direct32(priv,
437 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
438 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
439 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
440 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
441
442 iwl_write_direct32(priv,
443 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
444 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
445 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
446 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
447
448 return 0;
449 }
450
451 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
452 struct fw_desc *inst_image,
453 struct fw_desc *data_image)
454 {
455 int ret = 0;
456
457 ret = iwl5000_load_section(priv, inst_image,
458 IWL50_RTC_INST_LOWER_BOUND);
459 if (ret)
460 return ret;
461
462 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
463 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
464 priv->ucode_write_complete, 5 * HZ);
465 if (ret == -ERESTARTSYS) {
466 IWL_ERR(priv, "Could not load the INST uCode section due "
467 "to interrupt\n");
468 return ret;
469 }
470 if (!ret) {
471 IWL_ERR(priv, "Could not load the INST uCode section\n");
472 return -ETIMEDOUT;
473 }
474
475 priv->ucode_write_complete = 0;
476
477 ret = iwl5000_load_section(
478 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
479 if (ret)
480 return ret;
481
482 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
483
484 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
485 priv->ucode_write_complete, 5 * HZ);
486 if (ret == -ERESTARTSYS) {
487 IWL_ERR(priv, "Could not load the INST uCode section due "
488 "to interrupt\n");
489 return ret;
490 } else if (!ret) {
491 IWL_ERR(priv, "Could not load the DATA uCode section\n");
492 return -ETIMEDOUT;
493 } else
494 ret = 0;
495
496 priv->ucode_write_complete = 0;
497
498 return ret;
499 }
500
501 int iwl5000_load_ucode(struct iwl_priv *priv)
502 {
503 int ret = 0;
504
505 /* check whether init ucode should be loaded, or rather runtime ucode */
506 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
507 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
508 ret = iwl5000_load_given_ucode(priv,
509 &priv->ucode_init, &priv->ucode_init_data);
510 if (!ret) {
511 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
512 priv->ucode_type = UCODE_INIT;
513 }
514 } else {
515 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
516 "Loading runtime ucode...\n");
517 ret = iwl5000_load_given_ucode(priv,
518 &priv->ucode_code, &priv->ucode_data);
519 if (!ret) {
520 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
521 priv->ucode_type = UCODE_RT;
522 }
523 }
524
525 return ret;
526 }
527
528 void iwl5000_init_alive_start(struct iwl_priv *priv)
529 {
530 int ret = 0;
531
532 /* Check alive response for "valid" sign from uCode */
533 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
534 /* We had an error bringing up the hardware, so take it
535 * all the way back down so we can try again */
536 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
537 goto restart;
538 }
539
540 /* initialize uCode was loaded... verify inst image.
541 * This is a paranoid check, because we would not have gotten the
542 * "initialize" alive if code weren't properly loaded. */
543 if (iwl_verify_ucode(priv)) {
544 /* Runtime instruction load was bad;
545 * take it all the way back down so we can try again */
546 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
547 goto restart;
548 }
549
550 iwl_clear_stations_table(priv);
551 ret = priv->cfg->ops->lib->alive_notify(priv);
552 if (ret) {
553 IWL_WARN(priv,
554 "Could not complete ALIVE transition: %d\n", ret);
555 goto restart;
556 }
557
558 iwl5000_send_calib_cfg(priv);
559 return;
560
561 restart:
562 /* real restart (first load init_ucode) */
563 queue_work(priv->workqueue, &priv->restart);
564 }
565
566 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
567 int txq_id, u32 index)
568 {
569 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
570 (index & 0xff) | (txq_id << 8));
571 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
572 }
573
574 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
575 struct iwl_tx_queue *txq,
576 int tx_fifo_id, int scd_retry)
577 {
578 int txq_id = txq->q.id;
579 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
580
581 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
582 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
583 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
584 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
585 IWL50_SCD_QUEUE_STTS_REG_MSK);
586
587 txq->sched_retry = scd_retry;
588
589 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
590 active ? "Activate" : "Deactivate",
591 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
592 }
593
594 int iwl5000_alive_notify(struct iwl_priv *priv)
595 {
596 u32 a;
597 unsigned long flags;
598 int i, chan;
599 u32 reg_val;
600
601 spin_lock_irqsave(&priv->lock, flags);
602
603 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
604 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
605 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
606 a += 4)
607 iwl_write_targ_mem(priv, a, 0);
608 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
609 a += 4)
610 iwl_write_targ_mem(priv, a, 0);
611 for (; a < priv->scd_base_addr +
612 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
613 iwl_write_targ_mem(priv, a, 0);
614
615 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
616 priv->scd_bc_tbls.dma >> 10);
617
618 /* Enable DMA channel */
619 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
620 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
621 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
622 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
623
624 /* Update FH chicken bits */
625 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
626 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
627 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
628
629 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
630 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
631 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
632
633 /* initiate the queues */
634 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
635 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
636 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
637 iwl_write_targ_mem(priv, priv->scd_base_addr +
638 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
639 iwl_write_targ_mem(priv, priv->scd_base_addr +
640 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
641 sizeof(u32),
642 ((SCD_WIN_SIZE <<
643 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
644 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
645 ((SCD_FRAME_LIMIT <<
646 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
647 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
648 }
649
650 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
651 IWL_MASK(0, priv->hw_params.max_txq_num));
652
653 /* Activate all Tx DMA/FIFO channels */
654 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
655
656 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
657
658 /* map qos queues to fifos one-to-one */
659 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
660 int ac = iwl5000_default_queue_to_tx_fifo[i];
661 iwl_txq_ctx_activate(priv, i);
662 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
663 }
664
665 /*
666 * TODO - need to initialize these queues and map them to FIFOs
667 * in the loop above, not only mark them as active. We do this
668 * because we want the first aggregation queue to be queue #10,
669 * but do not use 8 or 9 otherwise yet.
670 */
671 iwl_txq_ctx_activate(priv, 7);
672 iwl_txq_ctx_activate(priv, 8);
673 iwl_txq_ctx_activate(priv, 9);
674
675 spin_unlock_irqrestore(&priv->lock, flags);
676
677
678 iwl_send_wimax_coex(priv);
679
680 iwl5000_set_Xtal_calib(priv);
681 iwl_send_calib_results(priv);
682
683 return 0;
684 }
685
686 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
687 {
688 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
689 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
690 priv->cfg->num_of_queues =
691 priv->cfg->mod_params->num_of_queues;
692
693 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
694 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
695 priv->hw_params.scd_bc_tbls_size =
696 priv->cfg->num_of_queues *
697 sizeof(struct iwl5000_scd_bc_tbl);
698 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
699 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
700 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
701
702 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
703 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
704
705 priv->hw_params.max_bsm_size = 0;
706 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
707 BIT(IEEE80211_BAND_5GHZ);
708 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
709
710 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
711 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
712 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
713 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
714
715 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
716 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
717
718 /* Set initial sensitivity parameters */
719 /* Set initial calibration set */
720 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
721 case CSR_HW_REV_TYPE_5150:
722 priv->hw_params.sens = &iwl5150_sensitivity;
723 priv->hw_params.calib_init_cfg =
724 BIT(IWL_CALIB_DC) |
725 BIT(IWL_CALIB_LO) |
726 BIT(IWL_CALIB_TX_IQ) |
727 BIT(IWL_CALIB_BASE_BAND);
728
729 break;
730 default:
731 priv->hw_params.sens = &iwl5000_sensitivity;
732 priv->hw_params.calib_init_cfg =
733 BIT(IWL_CALIB_XTAL) |
734 BIT(IWL_CALIB_LO) |
735 BIT(IWL_CALIB_TX_IQ) |
736 BIT(IWL_CALIB_TX_IQ_PERD) |
737 BIT(IWL_CALIB_BASE_BAND);
738 break;
739 }
740
741 return 0;
742 }
743
744 /**
745 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
746 */
747 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
748 struct iwl_tx_queue *txq,
749 u16 byte_cnt)
750 {
751 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
752 int write_ptr = txq->q.write_ptr;
753 int txq_id = txq->q.id;
754 u8 sec_ctl = 0;
755 u8 sta_id = 0;
756 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
757 __le16 bc_ent;
758
759 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
760
761 if (txq_id != IWL_CMD_QUEUE_NUM) {
762 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
763 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
764
765 switch (sec_ctl & TX_CMD_SEC_MSK) {
766 case TX_CMD_SEC_CCM:
767 len += CCMP_MIC_LEN;
768 break;
769 case TX_CMD_SEC_TKIP:
770 len += TKIP_ICV_LEN;
771 break;
772 case TX_CMD_SEC_WEP:
773 len += WEP_IV_LEN + WEP_ICV_LEN;
774 break;
775 }
776 }
777
778 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
779
780 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
781
782 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
783 scd_bc_tbl[txq_id].
784 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
785 }
786
787 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
788 struct iwl_tx_queue *txq)
789 {
790 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
791 int txq_id = txq->q.id;
792 int read_ptr = txq->q.read_ptr;
793 u8 sta_id = 0;
794 __le16 bc_ent;
795
796 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
797
798 if (txq_id != IWL_CMD_QUEUE_NUM)
799 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
800
801 bc_ent = cpu_to_le16(1 | (sta_id << 12));
802 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
803
804 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
805 scd_bc_tbl[txq_id].
806 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
807 }
808
809 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
810 u16 txq_id)
811 {
812 u32 tbl_dw_addr;
813 u32 tbl_dw;
814 u16 scd_q2ratid;
815
816 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
817
818 tbl_dw_addr = priv->scd_base_addr +
819 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
820
821 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
822
823 if (txq_id & 0x1)
824 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
825 else
826 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
827
828 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
829
830 return 0;
831 }
832 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
833 {
834 /* Simply stop the queue, but don't change any configuration;
835 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
836 iwl_write_prph(priv,
837 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
838 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
839 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
840 }
841
842 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
843 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
844 {
845 unsigned long flags;
846 u16 ra_tid;
847
848 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
849 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
850 <= txq_id)) {
851 IWL_WARN(priv,
852 "queue number out of range: %d, must be %d to %d\n",
853 txq_id, IWL50_FIRST_AMPDU_QUEUE,
854 IWL50_FIRST_AMPDU_QUEUE +
855 priv->cfg->num_of_ampdu_queues - 1);
856 return -EINVAL;
857 }
858
859 ra_tid = BUILD_RAxTID(sta_id, tid);
860
861 /* Modify device's station table to Tx this TID */
862 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
863
864 spin_lock_irqsave(&priv->lock, flags);
865
866 /* Stop this Tx queue before configuring it */
867 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
868
869 /* Map receiver-address / traffic-ID to this queue */
870 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
871
872 /* Set this queue as a chain-building queue */
873 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
874
875 /* enable aggregations for the queue */
876 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
877
878 /* Place first TFD at index corresponding to start sequence number.
879 * Assumes that ssn_idx is valid (!= 0xFFF) */
880 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
881 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
882 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
883
884 /* Set up Tx window size and frame limit for this queue */
885 iwl_write_targ_mem(priv, priv->scd_base_addr +
886 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
887 sizeof(u32),
888 ((SCD_WIN_SIZE <<
889 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
890 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
891 ((SCD_FRAME_LIMIT <<
892 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
893 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
894
895 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
896
897 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
898 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
899
900 spin_unlock_irqrestore(&priv->lock, flags);
901
902 return 0;
903 }
904
905 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
906 u16 ssn_idx, u8 tx_fifo)
907 {
908 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
909 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
910 <= txq_id)) {
911 IWL_ERR(priv,
912 "queue number out of range: %d, must be %d to %d\n",
913 txq_id, IWL50_FIRST_AMPDU_QUEUE,
914 IWL50_FIRST_AMPDU_QUEUE +
915 priv->cfg->num_of_ampdu_queues - 1);
916 return -EINVAL;
917 }
918
919 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
920
921 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
922
923 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
924 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
925 /* supposes that ssn_idx is valid (!= 0xFFF) */
926 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
927
928 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
929 iwl_txq_ctx_deactivate(priv, txq_id);
930 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
931
932 return 0;
933 }
934
935 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
936 {
937 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
938 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
939 memcpy(addsta, cmd, size);
940 /* resrved in 5000 */
941 addsta->rate_n_flags = cpu_to_le16(0);
942 return size;
943 }
944
945
946 /*
947 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
948 * must be called under priv->lock and mac access
949 */
950 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
951 {
952 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
953 }
954
955
956 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
957 {
958 return le32_to_cpup((__le32 *)&tx_resp->status +
959 tx_resp->frame_count) & MAX_SN;
960 }
961
962 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
963 struct iwl_ht_agg *agg,
964 struct iwl5000_tx_resp *tx_resp,
965 int txq_id, u16 start_idx)
966 {
967 u16 status;
968 struct agg_tx_status *frame_status = &tx_resp->status;
969 struct ieee80211_tx_info *info = NULL;
970 struct ieee80211_hdr *hdr = NULL;
971 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
972 int i, sh, idx;
973 u16 seq;
974
975 if (agg->wait_for_ba)
976 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
977
978 agg->frame_count = tx_resp->frame_count;
979 agg->start_idx = start_idx;
980 agg->rate_n_flags = rate_n_flags;
981 agg->bitmap = 0;
982
983 /* # frames attempted by Tx command */
984 if (agg->frame_count == 1) {
985 /* Only one frame was attempted; no block-ack will arrive */
986 status = le16_to_cpu(frame_status[0].status);
987 idx = start_idx;
988
989 /* FIXME: code repetition */
990 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
991 agg->frame_count, agg->start_idx, idx);
992
993 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
994 info->status.rates[0].count = tx_resp->failure_frame + 1;
995 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
996 info->flags |= iwl_tx_status_to_mac80211(status);
997 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
998
999 /* FIXME: code repetition end */
1000
1001 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1002 status & 0xff, tx_resp->failure_frame);
1003 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1004
1005 agg->wait_for_ba = 0;
1006 } else {
1007 /* Two or more frames were attempted; expect block-ack */
1008 u64 bitmap = 0;
1009 int start = agg->start_idx;
1010
1011 /* Construct bit-map of pending frames within Tx window */
1012 for (i = 0; i < agg->frame_count; i++) {
1013 u16 sc;
1014 status = le16_to_cpu(frame_status[i].status);
1015 seq = le16_to_cpu(frame_status[i].sequence);
1016 idx = SEQ_TO_INDEX(seq);
1017 txq_id = SEQ_TO_QUEUE(seq);
1018
1019 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1020 AGG_TX_STATE_ABORT_MSK))
1021 continue;
1022
1023 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1024 agg->frame_count, txq_id, idx);
1025
1026 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1027 if (!hdr) {
1028 IWL_ERR(priv,
1029 "BUG_ON idx doesn't point to valid skb"
1030 " idx=%d, txq_id=%d\n", idx, txq_id);
1031 return -1;
1032 }
1033
1034 sc = le16_to_cpu(hdr->seq_ctrl);
1035 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1036 IWL_ERR(priv,
1037 "BUG_ON idx doesn't match seq control"
1038 " idx=%d, seq_idx=%d, seq=%d\n",
1039 idx, SEQ_TO_SN(sc),
1040 hdr->seq_ctrl);
1041 return -1;
1042 }
1043
1044 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1045 i, idx, SEQ_TO_SN(sc));
1046
1047 sh = idx - start;
1048 if (sh > 64) {
1049 sh = (start - idx) + 0xff;
1050 bitmap = bitmap << sh;
1051 sh = 0;
1052 start = idx;
1053 } else if (sh < -64)
1054 sh = 0xff - (start - idx);
1055 else if (sh < 0) {
1056 sh = start - idx;
1057 start = idx;
1058 bitmap = bitmap << sh;
1059 sh = 0;
1060 }
1061 bitmap |= 1ULL << sh;
1062 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1063 start, (unsigned long long)bitmap);
1064 }
1065
1066 agg->bitmap = bitmap;
1067 agg->start_idx = start;
1068 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1069 agg->frame_count, agg->start_idx,
1070 (unsigned long long)agg->bitmap);
1071
1072 if (bitmap)
1073 agg->wait_for_ba = 1;
1074 }
1075 return 0;
1076 }
1077
1078 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1079 struct iwl_rx_mem_buffer *rxb)
1080 {
1081 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1082 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1083 int txq_id = SEQ_TO_QUEUE(sequence);
1084 int index = SEQ_TO_INDEX(sequence);
1085 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1086 struct ieee80211_tx_info *info;
1087 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1088 u32 status = le16_to_cpu(tx_resp->status.status);
1089 int tid;
1090 int sta_id;
1091 int freed;
1092
1093 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1094 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1095 "is out of range [0-%d] %d %d\n", txq_id,
1096 index, txq->q.n_bd, txq->q.write_ptr,
1097 txq->q.read_ptr);
1098 return;
1099 }
1100
1101 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1102 memset(&info->status, 0, sizeof(info->status));
1103
1104 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1105 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1106
1107 if (txq->sched_retry) {
1108 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1109 struct iwl_ht_agg *agg = NULL;
1110
1111 agg = &priv->stations[sta_id].tid[tid].agg;
1112
1113 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1114
1115 /* check if BAR is needed */
1116 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1117 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1118
1119 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1120 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1121 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1122 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1123 scd_ssn , index, txq_id, txq->swq_id);
1124
1125 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1126 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1127
1128 if (priv->mac80211_registered &&
1129 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1130 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1131 if (agg->state == IWL_AGG_OFF)
1132 iwl_wake_queue(priv, txq_id);
1133 else
1134 iwl_wake_queue(priv, txq->swq_id);
1135 }
1136 }
1137 } else {
1138 BUG_ON(txq_id != txq->swq_id);
1139
1140 info->status.rates[0].count = tx_resp->failure_frame + 1;
1141 info->flags |= iwl_tx_status_to_mac80211(status);
1142 iwl_hwrate_to_tx_control(priv,
1143 le32_to_cpu(tx_resp->rate_n_flags),
1144 info);
1145
1146 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1147 "0x%x retries %d\n",
1148 txq_id,
1149 iwl_get_tx_fail_reason(status), status,
1150 le32_to_cpu(tx_resp->rate_n_flags),
1151 tx_resp->failure_frame);
1152
1153 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1154 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1155 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1156
1157 if (priv->mac80211_registered &&
1158 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1159 iwl_wake_queue(priv, txq_id);
1160 }
1161
1162 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1163 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1164
1165 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1166 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1167 }
1168
1169 /* Currently 5000 is the superset of everything */
1170 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1171 {
1172 return len;
1173 }
1174
1175 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1176 {
1177 /* in 5000 the tx power calibration is done in uCode */
1178 priv->disable_tx_power_cal = 1;
1179 }
1180
1181 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1182 {
1183 /* init calibration handlers */
1184 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1185 iwl5000_rx_calib_result;
1186 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1187 iwl5000_rx_calib_complete;
1188 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1189 }
1190
1191
1192 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1193 {
1194 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1195 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1196 }
1197
1198 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1199 {
1200 int ret = 0;
1201 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1202 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1203 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1204
1205 if ((rxon1->flags == rxon2->flags) &&
1206 (rxon1->filter_flags == rxon2->filter_flags) &&
1207 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1208 (rxon1->ofdm_ht_single_stream_basic_rates ==
1209 rxon2->ofdm_ht_single_stream_basic_rates) &&
1210 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1211 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1212 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1213 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1214 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1215 (rxon1->rx_chain == rxon2->rx_chain) &&
1216 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1217 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1218 return 0;
1219 }
1220
1221 rxon_assoc.flags = priv->staging_rxon.flags;
1222 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1223 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1224 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1225 rxon_assoc.reserved1 = 0;
1226 rxon_assoc.reserved2 = 0;
1227 rxon_assoc.reserved3 = 0;
1228 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1229 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1230 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1231 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1232 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1233 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1234 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1235 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1236
1237 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1238 sizeof(rxon_assoc), &rxon_assoc, NULL);
1239 if (ret)
1240 return ret;
1241
1242 return ret;
1243 }
1244 int iwl5000_send_tx_power(struct iwl_priv *priv)
1245 {
1246 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1247 u8 tx_ant_cfg_cmd;
1248
1249 /* half dBm need to multiply */
1250 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1251
1252 if (priv->tx_power_lmt_in_half_dbm &&
1253 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1254 /*
1255 * For the newer devices which using enhanced/extend tx power
1256 * table in EEPROM, the format is in half dBm. driver need to
1257 * convert to dBm format before report to mac80211.
1258 * By doing so, there is a possibility of 1/2 dBm resolution
1259 * lost. driver will perform "round-up" operation before
1260 * reporting, but it will cause 1/2 dBm tx power over the
1261 * regulatory limit. Perform the checking here, if the
1262 * "tx_power_user_lmt" is higher than EEPROM value (in
1263 * half-dBm format), lower the tx power based on EEPROM
1264 */
1265 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1266 }
1267 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1268 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1269
1270 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1271 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1272 else
1273 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1274
1275 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1276 sizeof(tx_power_cmd), &tx_power_cmd,
1277 NULL);
1278 }
1279
1280 void iwl5000_temperature(struct iwl_priv *priv)
1281 {
1282 /* store temperature from statistics (in Celsius) */
1283 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1284 iwl_tt_handler(priv);
1285 }
1286
1287 static void iwl5150_temperature(struct iwl_priv *priv)
1288 {
1289 u32 vt = 0;
1290 s32 offset = iwl_temp_calib_to_offset(priv);
1291
1292 vt = le32_to_cpu(priv->statistics.general.temperature);
1293 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1294 /* now vt hold the temperature in Kelvin */
1295 priv->temperature = KELVIN_TO_CELSIUS(vt);
1296 iwl_tt_handler(priv);
1297 }
1298
1299 /* Calc max signal level (dBm) among 3 possible receivers */
1300 int iwl5000_calc_rssi(struct iwl_priv *priv,
1301 struct iwl_rx_phy_res *rx_resp)
1302 {
1303 /* data from PHY/DSP regarding signal strength, etc.,
1304 * contents are always there, not configurable by host
1305 */
1306 struct iwl5000_non_cfg_phy *ncphy =
1307 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1308 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1309 u8 agc;
1310
1311 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1312 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1313
1314 /* Find max rssi among 3 possible receivers.
1315 * These values are measured by the digital signal processor (DSP).
1316 * They should stay fairly constant even as the signal strength varies,
1317 * if the radio's automatic gain control (AGC) is working right.
1318 * AGC value (see below) will provide the "interesting" info.
1319 */
1320 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1321 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1322 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1323 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1324 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1325
1326 max_rssi = max_t(u32, rssi_a, rssi_b);
1327 max_rssi = max_t(u32, max_rssi, rssi_c);
1328
1329 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1330 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1331
1332 /* dBm = max_rssi dB - agc dB - constant.
1333 * Higher AGC (higher radio gain) means lower signal. */
1334 return max_rssi - agc - IWL49_RSSI_OFFSET;
1335 }
1336
1337 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1338 {
1339 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1340 .valid = cpu_to_le32(valid_tx_ant),
1341 };
1342
1343 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1344 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1345 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1346 sizeof(struct iwl_tx_ant_config_cmd),
1347 &tx_ant_cmd);
1348 } else {
1349 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1350 return -EOPNOTSUPP;
1351 }
1352 }
1353
1354
1355 #define IWL5000_UCODE_GET(item) \
1356 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1357 u32 api_ver) \
1358 { \
1359 if (api_ver <= 2) \
1360 return le32_to_cpu(ucode->u.v1.item); \
1361 return le32_to_cpu(ucode->u.v2.item); \
1362 }
1363
1364 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1365 {
1366 if (api_ver <= 2)
1367 return UCODE_HEADER_SIZE(1);
1368 return UCODE_HEADER_SIZE(2);
1369 }
1370
1371 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1372 u32 api_ver)
1373 {
1374 if (api_ver <= 2)
1375 return 0;
1376 return le32_to_cpu(ucode->u.v2.build);
1377 }
1378
1379 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1380 u32 api_ver)
1381 {
1382 if (api_ver <= 2)
1383 return (u8 *) ucode->u.v1.data;
1384 return (u8 *) ucode->u.v2.data;
1385 }
1386
1387 IWL5000_UCODE_GET(inst_size);
1388 IWL5000_UCODE_GET(data_size);
1389 IWL5000_UCODE_GET(init_size);
1390 IWL5000_UCODE_GET(init_data_size);
1391 IWL5000_UCODE_GET(boot_size);
1392
1393 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1394 {
1395 struct iwl5000_channel_switch_cmd cmd;
1396 const struct iwl_channel_info *ch_info;
1397 struct iwl_host_cmd hcmd = {
1398 .id = REPLY_CHANNEL_SWITCH,
1399 .len = sizeof(cmd),
1400 .flags = CMD_SIZE_HUGE,
1401 .data = &cmd,
1402 };
1403
1404 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1405 priv->active_rxon.channel, channel);
1406 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1407 cmd.channel = cpu_to_le16(channel);
1408 cmd.rxon_flags = priv->staging_rxon.flags;
1409 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1410 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1411 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1412 if (ch_info)
1413 cmd.expect_beacon = is_channel_radar(ch_info);
1414 else {
1415 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1416 priv->active_rxon.channel, channel);
1417 return -EFAULT;
1418 }
1419 priv->switch_rxon.channel = cpu_to_le16(channel);
1420 priv->switch_rxon.switch_in_progress = true;
1421
1422 return iwl_send_cmd_sync(priv, &hcmd);
1423 }
1424
1425 struct iwl_hcmd_ops iwl5000_hcmd = {
1426 .rxon_assoc = iwl5000_send_rxon_assoc,
1427 .commit_rxon = iwl_commit_rxon,
1428 .set_rxon_chain = iwl_set_rxon_chain,
1429 .set_tx_ant = iwl5000_send_tx_ant_config,
1430 };
1431
1432 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1433 .get_hcmd_size = iwl5000_get_hcmd_size,
1434 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1435 .gain_computation = iwl5000_gain_computation,
1436 .chain_noise_reset = iwl5000_chain_noise_reset,
1437 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1438 .calc_rssi = iwl5000_calc_rssi,
1439 };
1440
1441 struct iwl_ucode_ops iwl5000_ucode = {
1442 .get_header_size = iwl5000_ucode_get_header_size,
1443 .get_build = iwl5000_ucode_get_build,
1444 .get_inst_size = iwl5000_ucode_get_inst_size,
1445 .get_data_size = iwl5000_ucode_get_data_size,
1446 .get_init_size = iwl5000_ucode_get_init_size,
1447 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1448 .get_boot_size = iwl5000_ucode_get_boot_size,
1449 .get_data = iwl5000_ucode_get_data,
1450 };
1451
1452 struct iwl_lib_ops iwl5000_lib = {
1453 .set_hw_params = iwl5000_hw_set_hw_params,
1454 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1455 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1456 .txq_set_sched = iwl5000_txq_set_sched,
1457 .txq_agg_enable = iwl5000_txq_agg_enable,
1458 .txq_agg_disable = iwl5000_txq_agg_disable,
1459 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1460 .txq_free_tfd = iwl_hw_txq_free_tfd,
1461 .txq_init = iwl_hw_tx_queue_init,
1462 .rx_handler_setup = iwl5000_rx_handler_setup,
1463 .setup_deferred_work = iwl5000_setup_deferred_work,
1464 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1465 .dump_nic_event_log = iwl_dump_nic_event_log,
1466 .dump_nic_error_log = iwl_dump_nic_error_log,
1467 .load_ucode = iwl5000_load_ucode,
1468 .init_alive_start = iwl5000_init_alive_start,
1469 .alive_notify = iwl5000_alive_notify,
1470 .send_tx_power = iwl5000_send_tx_power,
1471 .update_chain_flags = iwl_update_chain_flags,
1472 .set_channel_switch = iwl5000_hw_channel_switch,
1473 .apm_ops = {
1474 .init = iwl_apm_init,
1475 .stop = iwl_apm_stop,
1476 .config = iwl5000_nic_config,
1477 .set_pwr_src = iwl_set_pwr_src,
1478 },
1479 .eeprom_ops = {
1480 .regulatory_bands = {
1481 EEPROM_5000_REG_BAND_1_CHANNELS,
1482 EEPROM_5000_REG_BAND_2_CHANNELS,
1483 EEPROM_5000_REG_BAND_3_CHANNELS,
1484 EEPROM_5000_REG_BAND_4_CHANNELS,
1485 EEPROM_5000_REG_BAND_5_CHANNELS,
1486 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1487 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1488 },
1489 .verify_signature = iwlcore_eeprom_verify_signature,
1490 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1491 .release_semaphore = iwlcore_eeprom_release_semaphore,
1492 .calib_version = iwl5000_eeprom_calib_version,
1493 .query_addr = iwl5000_eeprom_query_addr,
1494 },
1495 .post_associate = iwl_post_associate,
1496 .isr = iwl_isr_ict,
1497 .config_ap = iwl_config_ap,
1498 .temp_ops = {
1499 .temperature = iwl5000_temperature,
1500 .set_ct_kill = iwl5000_set_ct_threshold,
1501 },
1502 };
1503
1504 static struct iwl_lib_ops iwl5150_lib = {
1505 .set_hw_params = iwl5000_hw_set_hw_params,
1506 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1507 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1508 .txq_set_sched = iwl5000_txq_set_sched,
1509 .txq_agg_enable = iwl5000_txq_agg_enable,
1510 .txq_agg_disable = iwl5000_txq_agg_disable,
1511 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1512 .txq_free_tfd = iwl_hw_txq_free_tfd,
1513 .txq_init = iwl_hw_tx_queue_init,
1514 .rx_handler_setup = iwl5000_rx_handler_setup,
1515 .setup_deferred_work = iwl5000_setup_deferred_work,
1516 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1517 .dump_nic_event_log = iwl_dump_nic_event_log,
1518 .dump_nic_error_log = iwl_dump_nic_error_log,
1519 .load_ucode = iwl5000_load_ucode,
1520 .init_alive_start = iwl5000_init_alive_start,
1521 .alive_notify = iwl5000_alive_notify,
1522 .send_tx_power = iwl5000_send_tx_power,
1523 .update_chain_flags = iwl_update_chain_flags,
1524 .set_channel_switch = iwl5000_hw_channel_switch,
1525 .apm_ops = {
1526 .init = iwl_apm_init,
1527 .stop = iwl_apm_stop,
1528 .config = iwl5000_nic_config,
1529 .set_pwr_src = iwl_set_pwr_src,
1530 },
1531 .eeprom_ops = {
1532 .regulatory_bands = {
1533 EEPROM_5000_REG_BAND_1_CHANNELS,
1534 EEPROM_5000_REG_BAND_2_CHANNELS,
1535 EEPROM_5000_REG_BAND_3_CHANNELS,
1536 EEPROM_5000_REG_BAND_4_CHANNELS,
1537 EEPROM_5000_REG_BAND_5_CHANNELS,
1538 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1539 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1540 },
1541 .verify_signature = iwlcore_eeprom_verify_signature,
1542 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1543 .release_semaphore = iwlcore_eeprom_release_semaphore,
1544 .calib_version = iwl5000_eeprom_calib_version,
1545 .query_addr = iwl5000_eeprom_query_addr,
1546 },
1547 .post_associate = iwl_post_associate,
1548 .isr = iwl_isr_ict,
1549 .config_ap = iwl_config_ap,
1550 .temp_ops = {
1551 .temperature = iwl5150_temperature,
1552 .set_ct_kill = iwl5150_set_ct_threshold,
1553 },
1554 };
1555
1556 static struct iwl_ops iwl5000_ops = {
1557 .ucode = &iwl5000_ucode,
1558 .lib = &iwl5000_lib,
1559 .hcmd = &iwl5000_hcmd,
1560 .utils = &iwl5000_hcmd_utils,
1561 .led = &iwlagn_led_ops,
1562 };
1563
1564 static struct iwl_ops iwl5150_ops = {
1565 .ucode = &iwl5000_ucode,
1566 .lib = &iwl5150_lib,
1567 .hcmd = &iwl5000_hcmd,
1568 .utils = &iwl5000_hcmd_utils,
1569 .led = &iwlagn_led_ops,
1570 };
1571
1572 struct iwl_mod_params iwl50_mod_params = {
1573 .amsdu_size_8K = 1,
1574 .restart_fw = 1,
1575 /* the rest are 0 by default */
1576 };
1577
1578
1579 struct iwl_cfg iwl5300_agn_cfg = {
1580 .name = "5300AGN",
1581 .fw_name_pre = IWL5000_FW_PRE,
1582 .ucode_api_max = IWL5000_UCODE_API_MAX,
1583 .ucode_api_min = IWL5000_UCODE_API_MIN,
1584 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1585 .ops = &iwl5000_ops,
1586 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1587 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1588 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1589 .num_of_queues = IWL50_NUM_QUEUES,
1590 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1591 .mod_params = &iwl50_mod_params,
1592 .valid_tx_ant = ANT_ABC,
1593 .valid_rx_ant = ANT_ABC,
1594 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1595 .set_l0s = true,
1596 .use_bsm = false,
1597 .ht_greenfield_support = true,
1598 .led_compensation = 51,
1599 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1600 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1601 };
1602
1603 struct iwl_cfg iwl5100_bgn_cfg = {
1604 .name = "5100BGN",
1605 .fw_name_pre = IWL5000_FW_PRE,
1606 .ucode_api_max = IWL5000_UCODE_API_MAX,
1607 .ucode_api_min = IWL5000_UCODE_API_MIN,
1608 .sku = IWL_SKU_G|IWL_SKU_N,
1609 .ops = &iwl5000_ops,
1610 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1611 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1612 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1613 .num_of_queues = IWL50_NUM_QUEUES,
1614 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1615 .mod_params = &iwl50_mod_params,
1616 .valid_tx_ant = ANT_B,
1617 .valid_rx_ant = ANT_AB,
1618 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1619 .set_l0s = true,
1620 .use_bsm = false,
1621 .ht_greenfield_support = true,
1622 .led_compensation = 51,
1623 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1624 };
1625
1626 struct iwl_cfg iwl5100_abg_cfg = {
1627 .name = "5100ABG",
1628 .fw_name_pre = IWL5000_FW_PRE,
1629 .ucode_api_max = IWL5000_UCODE_API_MAX,
1630 .ucode_api_min = IWL5000_UCODE_API_MIN,
1631 .sku = IWL_SKU_A|IWL_SKU_G,
1632 .ops = &iwl5000_ops,
1633 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1634 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1635 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1636 .num_of_queues = IWL50_NUM_QUEUES,
1637 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1638 .mod_params = &iwl50_mod_params,
1639 .valid_tx_ant = ANT_B,
1640 .valid_rx_ant = ANT_AB,
1641 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1642 .set_l0s = true,
1643 .use_bsm = false,
1644 .led_compensation = 51,
1645 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1646 };
1647
1648 struct iwl_cfg iwl5100_agn_cfg = {
1649 .name = "5100AGN",
1650 .fw_name_pre = IWL5000_FW_PRE,
1651 .ucode_api_max = IWL5000_UCODE_API_MAX,
1652 .ucode_api_min = IWL5000_UCODE_API_MIN,
1653 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1654 .ops = &iwl5000_ops,
1655 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1656 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1657 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1658 .num_of_queues = IWL50_NUM_QUEUES,
1659 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1660 .mod_params = &iwl50_mod_params,
1661 .valid_tx_ant = ANT_B,
1662 .valid_rx_ant = ANT_AB,
1663 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1664 .set_l0s = true,
1665 .use_bsm = false,
1666 .ht_greenfield_support = true,
1667 .led_compensation = 51,
1668 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1669 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1670 };
1671
1672 struct iwl_cfg iwl5350_agn_cfg = {
1673 .name = "5350AGN",
1674 .fw_name_pre = IWL5000_FW_PRE,
1675 .ucode_api_max = IWL5000_UCODE_API_MAX,
1676 .ucode_api_min = IWL5000_UCODE_API_MIN,
1677 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1678 .ops = &iwl5000_ops,
1679 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1680 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1681 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1682 .num_of_queues = IWL50_NUM_QUEUES,
1683 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1684 .mod_params = &iwl50_mod_params,
1685 .valid_tx_ant = ANT_ABC,
1686 .valid_rx_ant = ANT_ABC,
1687 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1688 .set_l0s = true,
1689 .use_bsm = false,
1690 .ht_greenfield_support = true,
1691 .led_compensation = 51,
1692 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1693 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1694 };
1695
1696 struct iwl_cfg iwl5150_agn_cfg = {
1697 .name = "5150AGN",
1698 .fw_name_pre = IWL5150_FW_PRE,
1699 .ucode_api_max = IWL5150_UCODE_API_MAX,
1700 .ucode_api_min = IWL5150_UCODE_API_MIN,
1701 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1702 .ops = &iwl5150_ops,
1703 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1704 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1705 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1706 .num_of_queues = IWL50_NUM_QUEUES,
1707 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1708 .mod_params = &iwl50_mod_params,
1709 .valid_tx_ant = ANT_A,
1710 .valid_rx_ant = ANT_AB,
1711 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1712 .set_l0s = true,
1713 .use_bsm = false,
1714 .ht_greenfield_support = true,
1715 .led_compensation = 51,
1716 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1717 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1718 };
1719
1720 struct iwl_cfg iwl5150_abg_cfg = {
1721 .name = "5150ABG",
1722 .fw_name_pre = IWL5150_FW_PRE,
1723 .ucode_api_max = IWL5150_UCODE_API_MAX,
1724 .ucode_api_min = IWL5150_UCODE_API_MIN,
1725 .sku = IWL_SKU_A|IWL_SKU_G,
1726 .ops = &iwl5150_ops,
1727 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1728 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1729 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1730 .num_of_queues = IWL50_NUM_QUEUES,
1731 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1732 .mod_params = &iwl50_mod_params,
1733 .valid_tx_ant = ANT_A,
1734 .valid_rx_ant = ANT_AB,
1735 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1736 .set_l0s = true,
1737 .use_bsm = false,
1738 .led_compensation = 51,
1739 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1740 };
1741
1742 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1743 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1744
1745 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1746 MODULE_PARM_DESC(swcrypto50,
1747 "using software crypto engine (default 0 [hardware])\n");
1748 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1749 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1750 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1751 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1752 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1753 int, S_IRUGO);
1754 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1755 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1756 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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