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iwlwifi: Temperature sensor voltage reading for 5150
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
47
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 1
50 #define IWL5150_UCODE_API_MAX 2
51
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
55
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
59
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
63
64 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
65 IWL_TX_FIFO_AC3,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC1,
68 IWL_TX_FIFO_AC0,
69 IWL50_CMD_FIFO_NUM,
70 IWL_TX_FIFO_HCCA_1,
71 IWL_TX_FIFO_HCCA_2
72 };
73
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
76 {
77 unsigned long flags;
78
79 spin_lock_irqsave(&priv->lock, flags);
80
81 /* set stop master bit */
82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
83
84 iwl_poll_direct_bit(priv, CSR_RESET,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
86
87 spin_unlock_irqrestore(&priv->lock, flags);
88 IWL_DEBUG_INFO(priv, "stop master\n");
89
90 return 0;
91 }
92
93
94 static int iwl5000_apm_init(struct iwl_priv *priv)
95 {
96 int ret = 0;
97
98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
100
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
104
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
107
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
111
112 if (priv->cfg->need_pll_cfg)
113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
114
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
118
119 /* wait for clock stabilization */
120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
122 if (ret < 0) {
123 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
124 return ret;
125 }
126
127 ret = iwl_grab_nic_access(priv);
128 if (ret)
129 return ret;
130
131 /* enable DMA */
132 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
133
134 udelay(20);
135
136 /* disable L1-Active */
137 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
138 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
139
140 iwl_release_nic_access(priv);
141
142 return ret;
143 }
144
145 /* FIXME: this is identical to 4965 */
146 static void iwl5000_apm_stop(struct iwl_priv *priv)
147 {
148 unsigned long flags;
149
150 iwl5000_apm_stop_master(priv);
151
152 spin_lock_irqsave(&priv->lock, flags);
153
154 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
155
156 udelay(10);
157
158 /* clear "init complete" move adapter D0A* --> D0U state */
159 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
160
161 spin_unlock_irqrestore(&priv->lock, flags);
162 }
163
164
165 static int iwl5000_apm_reset(struct iwl_priv *priv)
166 {
167 int ret = 0;
168 unsigned long flags;
169
170 iwl5000_apm_stop_master(priv);
171
172 spin_lock_irqsave(&priv->lock, flags);
173
174 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
175
176 udelay(10);
177
178
179 /* FIXME: put here L1A -L0S w/a */
180
181 if (priv->cfg->need_pll_cfg)
182 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
183
184 /* set "initialization complete" bit to move adapter
185 * D0U* --> D0A* state */
186 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
187
188 /* wait for clock stabilization */
189 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
191 if (ret < 0) {
192 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
193 goto out;
194 }
195
196 ret = iwl_grab_nic_access(priv);
197 if (ret)
198 goto out;
199
200 /* enable DMA */
201 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
202
203 udelay(20);
204
205 /* disable L1-Active */
206 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
207 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
208
209 iwl_release_nic_access(priv);
210
211 out:
212 spin_unlock_irqrestore(&priv->lock, flags);
213
214 return ret;
215 }
216
217
218 static void iwl5000_nic_config(struct iwl_priv *priv)
219 {
220 unsigned long flags;
221 u16 radio_cfg;
222 u16 lctl;
223
224 spin_lock_irqsave(&priv->lock, flags);
225
226 lctl = iwl_pcie_link_ctl(priv);
227
228 /* HW bug W/A */
229 /* L1-ASPM is enabled by BIOS */
230 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
231 /* L1-APSM enabled: disable L0S */
232 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
233 else
234 /* L1-ASPM disabled: enable L0S */
235 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
236
237 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
238
239 /* write radio config values to register */
240 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
241 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
242 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
243 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
244 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
245
246 /* set CSR_HW_CONFIG_REG for uCode use */
247 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
248 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
249 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
250
251 /* W/A : NIC is stuck in a reset state after Early PCIe power off
252 * (PCIe power is lost before PERST# is asserted),
253 * causing ME FW to lose ownership and not being able to obtain it back.
254 */
255 iwl_grab_nic_access(priv);
256 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
257 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
258 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
259 iwl_release_nic_access(priv);
260
261 spin_unlock_irqrestore(&priv->lock, flags);
262 }
263
264
265
266 /*
267 * EEPROM
268 */
269 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
270 {
271 u16 offset = 0;
272
273 if ((address & INDIRECT_ADDRESS) == 0)
274 return address;
275
276 switch (address & INDIRECT_TYPE_MSK) {
277 case INDIRECT_HOST:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
279 break;
280 case INDIRECT_GENERAL:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
282 break;
283 case INDIRECT_REGULATORY:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
285 break;
286 case INDIRECT_CALIBRATION:
287 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
288 break;
289 case INDIRECT_PROCESS_ADJST:
290 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
291 break;
292 case INDIRECT_OTHERS:
293 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
294 break;
295 default:
296 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
297 address & INDIRECT_TYPE_MSK);
298 break;
299 }
300
301 /* translate the offset from words to byte */
302 return (address & ADDRESS_MSK) + (offset << 1);
303 }
304
305 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
306 {
307 struct iwl_eeprom_calib_hdr {
308 u8 version;
309 u8 pa_type;
310 u16 voltage;
311 } *hdr;
312
313 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
314 EEPROM_5000_CALIB_ALL);
315 return hdr->version;
316
317 }
318
319 static void iwl5000_gain_computation(struct iwl_priv *priv,
320 u32 average_noise[NUM_RX_CHAINS],
321 u16 min_average_noise_antenna_i,
322 u32 min_average_noise)
323 {
324 int i;
325 s32 delta_g;
326 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
327
328 /* Find Gain Code for the antennas B and C */
329 for (i = 1; i < NUM_RX_CHAINS; i++) {
330 if ((data->disconn_array[i])) {
331 data->delta_gain_code[i] = 0;
332 continue;
333 }
334 delta_g = (1000 * ((s32)average_noise[0] -
335 (s32)average_noise[i])) / 1500;
336 /* bound gain by 2 bits value max, 3rd bit is sign */
337 data->delta_gain_code[i] =
338 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
339
340 if (delta_g < 0)
341 /* set negative sign */
342 data->delta_gain_code[i] |= (1 << 2);
343 }
344
345 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
346 data->delta_gain_code[1], data->delta_gain_code[2]);
347
348 if (!data->radio_write) {
349 struct iwl_calib_chain_noise_gain_cmd cmd;
350
351 memset(&cmd, 0, sizeof(cmd));
352
353 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
354 cmd.hdr.first_group = 0;
355 cmd.hdr.groups_num = 1;
356 cmd.hdr.data_valid = 1;
357 cmd.delta_gain_1 = data->delta_gain_code[1];
358 cmd.delta_gain_2 = data->delta_gain_code[2];
359 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
360 sizeof(cmd), &cmd, NULL);
361
362 data->radio_write = 1;
363 data->state = IWL_CHAIN_NOISE_CALIBRATED;
364 }
365
366 data->chain_noise_a = 0;
367 data->chain_noise_b = 0;
368 data->chain_noise_c = 0;
369 data->chain_signal_a = 0;
370 data->chain_signal_b = 0;
371 data->chain_signal_c = 0;
372 data->beacon_count = 0;
373 }
374
375 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
376 {
377 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
378 int ret;
379
380 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
381 struct iwl_calib_chain_noise_reset_cmd cmd;
382 memset(&cmd, 0, sizeof(cmd));
383
384 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
385 cmd.hdr.first_group = 0;
386 cmd.hdr.groups_num = 1;
387 cmd.hdr.data_valid = 1;
388 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
389 sizeof(cmd), &cmd);
390 if (ret)
391 IWL_ERR(priv,
392 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
393 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
394 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
395 }
396 }
397
398 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
399 __le32 *tx_flags)
400 {
401 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
402 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
403 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
404 else
405 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
406 }
407
408 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
409 .min_nrg_cck = 95,
410 .max_nrg_cck = 0,
411 .auto_corr_min_ofdm = 90,
412 .auto_corr_min_ofdm_mrc = 170,
413 .auto_corr_min_ofdm_x1 = 120,
414 .auto_corr_min_ofdm_mrc_x1 = 240,
415
416 .auto_corr_max_ofdm = 120,
417 .auto_corr_max_ofdm_mrc = 210,
418 .auto_corr_max_ofdm_x1 = 155,
419 .auto_corr_max_ofdm_mrc_x1 = 290,
420
421 .auto_corr_min_cck = 125,
422 .auto_corr_max_cck = 200,
423 .auto_corr_min_cck_mrc = 170,
424 .auto_corr_max_cck_mrc = 400,
425 .nrg_th_cck = 95,
426 .nrg_th_ofdm = 95,
427 };
428
429 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
430 size_t offset)
431 {
432 u32 address = eeprom_indirect_address(priv, offset);
433 BUG_ON(address >= priv->cfg->eeprom_size);
434 return &priv->eeprom[address];
435 }
436
437 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
438 {
439 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
440 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) -
441 iwl_temp_calib_to_offset(priv);
442
443 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
444 }
445
446 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
447 {
448 /* want Celsius */
449 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
450 }
451
452 /*
453 * Calibration
454 */
455 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
456 {
457 struct iwl_calib_xtal_freq_cmd cmd;
458 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
459
460 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
461 cmd.hdr.first_group = 0;
462 cmd.hdr.groups_num = 1;
463 cmd.hdr.data_valid = 1;
464 cmd.cap_pin1 = (u8)xtal_calib[0];
465 cmd.cap_pin2 = (u8)xtal_calib[1];
466 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
467 (u8 *)&cmd, sizeof(cmd));
468 }
469
470 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
471 {
472 struct iwl_calib_cfg_cmd calib_cfg_cmd;
473 struct iwl_host_cmd cmd = {
474 .id = CALIBRATION_CFG_CMD,
475 .len = sizeof(struct iwl_calib_cfg_cmd),
476 .data = &calib_cfg_cmd,
477 };
478
479 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
480 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
481 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
482 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
483 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
484
485 return iwl_send_cmd(priv, &cmd);
486 }
487
488 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
489 struct iwl_rx_mem_buffer *rxb)
490 {
491 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
492 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
493 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
494 int index;
495
496 /* reduce the size of the length field itself */
497 len -= 4;
498
499 /* Define the order in which the results will be sent to the runtime
500 * uCode. iwl_send_calib_results sends them in a row according to their
501 * index. We sort them here */
502 switch (hdr->op_code) {
503 case IWL_PHY_CALIBRATE_DC_CMD:
504 index = IWL_CALIB_DC;
505 break;
506 case IWL_PHY_CALIBRATE_LO_CMD:
507 index = IWL_CALIB_LO;
508 break;
509 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
510 index = IWL_CALIB_TX_IQ;
511 break;
512 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
513 index = IWL_CALIB_TX_IQ_PERD;
514 break;
515 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
516 index = IWL_CALIB_BASE_BAND;
517 break;
518 default:
519 IWL_ERR(priv, "Unknown calibration notification %d\n",
520 hdr->op_code);
521 return;
522 }
523 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
524 }
525
526 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
527 struct iwl_rx_mem_buffer *rxb)
528 {
529 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
530 queue_work(priv->workqueue, &priv->restart);
531 }
532
533 /*
534 * ucode
535 */
536 static int iwl5000_load_section(struct iwl_priv *priv,
537 struct fw_desc *image,
538 u32 dst_addr)
539 {
540 int ret = 0;
541 unsigned long flags;
542
543 dma_addr_t phy_addr = image->p_addr;
544 u32 byte_cnt = image->len;
545
546 spin_lock_irqsave(&priv->lock, flags);
547 ret = iwl_grab_nic_access(priv);
548 if (ret) {
549 spin_unlock_irqrestore(&priv->lock, flags);
550 return ret;
551 }
552
553 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
556
557 iwl_write_direct32(priv,
558 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
559
560 iwl_write_direct32(priv,
561 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
562 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
563
564 iwl_write_direct32(priv,
565 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
566 (iwl_get_dma_hi_addr(phy_addr)
567 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
568
569 iwl_write_direct32(priv,
570 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
571 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
572 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
573 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
574
575 iwl_write_direct32(priv,
576 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
577 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
578 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
579 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
580
581 iwl_release_nic_access(priv);
582 spin_unlock_irqrestore(&priv->lock, flags);
583 return 0;
584 }
585
586 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
587 struct fw_desc *inst_image,
588 struct fw_desc *data_image)
589 {
590 int ret = 0;
591
592 ret = iwl5000_load_section(priv, inst_image,
593 IWL50_RTC_INST_LOWER_BOUND);
594 if (ret)
595 return ret;
596
597 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
598 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
599 priv->ucode_write_complete, 5 * HZ);
600 if (ret == -ERESTARTSYS) {
601 IWL_ERR(priv, "Could not load the INST uCode section due "
602 "to interrupt\n");
603 return ret;
604 }
605 if (!ret) {
606 IWL_ERR(priv, "Could not load the INST uCode section\n");
607 return -ETIMEDOUT;
608 }
609
610 priv->ucode_write_complete = 0;
611
612 ret = iwl5000_load_section(
613 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
614 if (ret)
615 return ret;
616
617 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
618
619 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
620 priv->ucode_write_complete, 5 * HZ);
621 if (ret == -ERESTARTSYS) {
622 IWL_ERR(priv, "Could not load the INST uCode section due "
623 "to interrupt\n");
624 return ret;
625 } else if (!ret) {
626 IWL_ERR(priv, "Could not load the DATA uCode section\n");
627 return -ETIMEDOUT;
628 } else
629 ret = 0;
630
631 priv->ucode_write_complete = 0;
632
633 return ret;
634 }
635
636 static int iwl5000_load_ucode(struct iwl_priv *priv)
637 {
638 int ret = 0;
639
640 /* check whether init ucode should be loaded, or rather runtime ucode */
641 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
642 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
643 ret = iwl5000_load_given_ucode(priv,
644 &priv->ucode_init, &priv->ucode_init_data);
645 if (!ret) {
646 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
647 priv->ucode_type = UCODE_INIT;
648 }
649 } else {
650 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
651 "Loading runtime ucode...\n");
652 ret = iwl5000_load_given_ucode(priv,
653 &priv->ucode_code, &priv->ucode_data);
654 if (!ret) {
655 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
656 priv->ucode_type = UCODE_RT;
657 }
658 }
659
660 return ret;
661 }
662
663 static void iwl5000_init_alive_start(struct iwl_priv *priv)
664 {
665 int ret = 0;
666
667 /* Check alive response for "valid" sign from uCode */
668 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
669 /* We had an error bringing up the hardware, so take it
670 * all the way back down so we can try again */
671 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
672 goto restart;
673 }
674
675 /* initialize uCode was loaded... verify inst image.
676 * This is a paranoid check, because we would not have gotten the
677 * "initialize" alive if code weren't properly loaded. */
678 if (iwl_verify_ucode(priv)) {
679 /* Runtime instruction load was bad;
680 * take it all the way back down so we can try again */
681 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
682 goto restart;
683 }
684
685 priv->cfg->ops->smgmt->clear_station_table(priv);
686 ret = priv->cfg->ops->lib->alive_notify(priv);
687 if (ret) {
688 IWL_WARN(priv,
689 "Could not complete ALIVE transition: %d\n", ret);
690 goto restart;
691 }
692
693 iwl5000_send_calib_cfg(priv);
694 return;
695
696 restart:
697 /* real restart (first load init_ucode) */
698 queue_work(priv->workqueue, &priv->restart);
699 }
700
701 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
702 int txq_id, u32 index)
703 {
704 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
705 (index & 0xff) | (txq_id << 8));
706 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
707 }
708
709 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
710 struct iwl_tx_queue *txq,
711 int tx_fifo_id, int scd_retry)
712 {
713 int txq_id = txq->q.id;
714 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
715
716 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
717 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
718 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
719 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
720 IWL50_SCD_QUEUE_STTS_REG_MSK);
721
722 txq->sched_retry = scd_retry;
723
724 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
725 active ? "Activate" : "Deactivate",
726 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
727 }
728
729 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
730 {
731 struct iwl_wimax_coex_cmd coex_cmd;
732
733 memset(&coex_cmd, 0, sizeof(coex_cmd));
734
735 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
736 sizeof(coex_cmd), &coex_cmd);
737 }
738
739 static int iwl5000_alive_notify(struct iwl_priv *priv)
740 {
741 u32 a;
742 unsigned long flags;
743 int ret;
744 int i, chan;
745 u32 reg_val;
746
747 spin_lock_irqsave(&priv->lock, flags);
748
749 ret = iwl_grab_nic_access(priv);
750 if (ret) {
751 spin_unlock_irqrestore(&priv->lock, flags);
752 return ret;
753 }
754
755 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
756 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
757 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
758 a += 4)
759 iwl_write_targ_mem(priv, a, 0);
760 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
761 a += 4)
762 iwl_write_targ_mem(priv, a, 0);
763 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
764 iwl_write_targ_mem(priv, a, 0);
765
766 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
767 priv->scd_bc_tbls.dma >> 10);
768
769 /* Enable DMA channel */
770 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
771 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
772 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
773 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
774
775 /* Update FH chicken bits */
776 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
777 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
778 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
779
780 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
781 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
782 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
783
784 /* initiate the queues */
785 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
786 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
787 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
788 iwl_write_targ_mem(priv, priv->scd_base_addr +
789 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
790 iwl_write_targ_mem(priv, priv->scd_base_addr +
791 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
792 sizeof(u32),
793 ((SCD_WIN_SIZE <<
794 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
795 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
796 ((SCD_FRAME_LIMIT <<
797 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
798 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
799 }
800
801 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
802 IWL_MASK(0, priv->hw_params.max_txq_num));
803
804 /* Activate all Tx DMA/FIFO channels */
805 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
806
807 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
808
809 /* map qos queues to fifos one-to-one */
810 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
811 int ac = iwl5000_default_queue_to_tx_fifo[i];
812 iwl_txq_ctx_activate(priv, i);
813 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
814 }
815 /* TODO - need to initialize those FIFOs inside the loop above,
816 * not only mark them as active */
817 iwl_txq_ctx_activate(priv, 4);
818 iwl_txq_ctx_activate(priv, 7);
819 iwl_txq_ctx_activate(priv, 8);
820 iwl_txq_ctx_activate(priv, 9);
821
822 iwl_release_nic_access(priv);
823 spin_unlock_irqrestore(&priv->lock, flags);
824
825
826 iwl5000_send_wimax_coex(priv);
827
828 iwl5000_set_Xtal_calib(priv);
829 iwl_send_calib_results(priv);
830
831 return 0;
832 }
833
834 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
835 {
836 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
837 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
838 IWL_ERR(priv,
839 "invalid queues_num, should be between %d and %d\n",
840 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
841 return -EINVAL;
842 }
843
844 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
845 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
846 priv->hw_params.scd_bc_tbls_size =
847 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
848 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
849 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
850 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
851
852 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
853 case CSR_HW_REV_TYPE_6x00:
854 case CSR_HW_REV_TYPE_6x50:
855 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
856 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
857 break;
858 default:
859 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
860 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
861 }
862
863 priv->hw_params.max_bsm_size = 0;
864 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
865 BIT(IEEE80211_BAND_5GHZ);
866 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
867
868 priv->hw_params.sens = &iwl5000_sensitivity;
869
870 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
871 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
872 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
873 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
874
875 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
876 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
877
878 /* Set initial calibration set */
879 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
880 case CSR_HW_REV_TYPE_5150:
881 priv->hw_params.calib_init_cfg =
882 BIT(IWL_CALIB_DC) |
883 BIT(IWL_CALIB_LO) |
884 BIT(IWL_CALIB_TX_IQ) |
885 BIT(IWL_CALIB_BASE_BAND);
886
887 break;
888 default:
889 priv->hw_params.calib_init_cfg =
890 BIT(IWL_CALIB_XTAL) |
891 BIT(IWL_CALIB_LO) |
892 BIT(IWL_CALIB_TX_IQ) |
893 BIT(IWL_CALIB_TX_IQ_PERD) |
894 BIT(IWL_CALIB_BASE_BAND);
895 break;
896 }
897
898 return 0;
899 }
900
901 /**
902 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
903 */
904 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
905 struct iwl_tx_queue *txq,
906 u16 byte_cnt)
907 {
908 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
909 int write_ptr = txq->q.write_ptr;
910 int txq_id = txq->q.id;
911 u8 sec_ctl = 0;
912 u8 sta_id = 0;
913 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
914 __le16 bc_ent;
915
916 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
917
918 if (txq_id != IWL_CMD_QUEUE_NUM) {
919 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
920 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
921
922 switch (sec_ctl & TX_CMD_SEC_MSK) {
923 case TX_CMD_SEC_CCM:
924 len += CCMP_MIC_LEN;
925 break;
926 case TX_CMD_SEC_TKIP:
927 len += TKIP_ICV_LEN;
928 break;
929 case TX_CMD_SEC_WEP:
930 len += WEP_IV_LEN + WEP_ICV_LEN;
931 break;
932 }
933 }
934
935 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
936
937 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
938
939 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
940 scd_bc_tbl[txq_id].
941 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
942 }
943
944 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
945 struct iwl_tx_queue *txq)
946 {
947 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
948 int txq_id = txq->q.id;
949 int read_ptr = txq->q.read_ptr;
950 u8 sta_id = 0;
951 __le16 bc_ent;
952
953 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
954
955 if (txq_id != IWL_CMD_QUEUE_NUM)
956 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
957
958 bc_ent = cpu_to_le16(1 | (sta_id << 12));
959 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
960
961 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
962 scd_bc_tbl[txq_id].
963 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
964 }
965
966 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
967 u16 txq_id)
968 {
969 u32 tbl_dw_addr;
970 u32 tbl_dw;
971 u16 scd_q2ratid;
972
973 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
974
975 tbl_dw_addr = priv->scd_base_addr +
976 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
977
978 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
979
980 if (txq_id & 0x1)
981 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
982 else
983 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
984
985 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
986
987 return 0;
988 }
989 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
990 {
991 /* Simply stop the queue, but don't change any configuration;
992 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
993 iwl_write_prph(priv,
994 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
995 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
996 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
997 }
998
999 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1000 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1001 {
1002 unsigned long flags;
1003 int ret;
1004 u16 ra_tid;
1005
1006 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1007 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1008 IWL_WARN(priv,
1009 "queue number out of range: %d, must be %d to %d\n",
1010 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1011 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1012 return -EINVAL;
1013 }
1014
1015 ra_tid = BUILD_RAxTID(sta_id, tid);
1016
1017 /* Modify device's station table to Tx this TID */
1018 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1019
1020 spin_lock_irqsave(&priv->lock, flags);
1021 ret = iwl_grab_nic_access(priv);
1022 if (ret) {
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024 return ret;
1025 }
1026
1027 /* Stop this Tx queue before configuring it */
1028 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1029
1030 /* Map receiver-address / traffic-ID to this queue */
1031 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1032
1033 /* Set this queue as a chain-building queue */
1034 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1035
1036 /* enable aggregations for the queue */
1037 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1038
1039 /* Place first TFD at index corresponding to start sequence number.
1040 * Assumes that ssn_idx is valid (!= 0xFFF) */
1041 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1042 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1043 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1044
1045 /* Set up Tx window size and frame limit for this queue */
1046 iwl_write_targ_mem(priv, priv->scd_base_addr +
1047 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1048 sizeof(u32),
1049 ((SCD_WIN_SIZE <<
1050 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1051 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1052 ((SCD_FRAME_LIMIT <<
1053 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1054 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1055
1056 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1057
1058 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1059 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1060
1061 iwl_release_nic_access(priv);
1062 spin_unlock_irqrestore(&priv->lock, flags);
1063
1064 return 0;
1065 }
1066
1067 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1068 u16 ssn_idx, u8 tx_fifo)
1069 {
1070 int ret;
1071
1072 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1073 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1074 IWL_ERR(priv,
1075 "queue number out of range: %d, must be %d to %d\n",
1076 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1077 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1078 return -EINVAL;
1079 }
1080
1081 ret = iwl_grab_nic_access(priv);
1082 if (ret)
1083 return ret;
1084
1085 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1086
1087 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1088
1089 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1090 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1091 /* supposes that ssn_idx is valid (!= 0xFFF) */
1092 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1093
1094 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1095 iwl_txq_ctx_deactivate(priv, txq_id);
1096 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1097
1098 iwl_release_nic_access(priv);
1099
1100 return 0;
1101 }
1102
1103 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1104 {
1105 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1106 memcpy(data, cmd, size);
1107 return size;
1108 }
1109
1110
1111 /*
1112 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1113 * must be called under priv->lock and mac access
1114 */
1115 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1116 {
1117 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1118 }
1119
1120
1121 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1122 {
1123 return le32_to_cpup((__le32 *)&tx_resp->status +
1124 tx_resp->frame_count) & MAX_SN;
1125 }
1126
1127 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1128 struct iwl_ht_agg *agg,
1129 struct iwl5000_tx_resp *tx_resp,
1130 int txq_id, u16 start_idx)
1131 {
1132 u16 status;
1133 struct agg_tx_status *frame_status = &tx_resp->status;
1134 struct ieee80211_tx_info *info = NULL;
1135 struct ieee80211_hdr *hdr = NULL;
1136 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1137 int i, sh, idx;
1138 u16 seq;
1139
1140 if (agg->wait_for_ba)
1141 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1142
1143 agg->frame_count = tx_resp->frame_count;
1144 agg->start_idx = start_idx;
1145 agg->rate_n_flags = rate_n_flags;
1146 agg->bitmap = 0;
1147
1148 /* # frames attempted by Tx command */
1149 if (agg->frame_count == 1) {
1150 /* Only one frame was attempted; no block-ack will arrive */
1151 status = le16_to_cpu(frame_status[0].status);
1152 idx = start_idx;
1153
1154 /* FIXME: code repetition */
1155 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1156 agg->frame_count, agg->start_idx, idx);
1157
1158 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1159 info->status.rates[0].count = tx_resp->failure_frame + 1;
1160 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1161 info->flags |= iwl_is_tx_success(status) ?
1162 IEEE80211_TX_STAT_ACK : 0;
1163 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1164
1165 /* FIXME: code repetition end */
1166
1167 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1168 status & 0xff, tx_resp->failure_frame);
1169 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1170
1171 agg->wait_for_ba = 0;
1172 } else {
1173 /* Two or more frames were attempted; expect block-ack */
1174 u64 bitmap = 0;
1175 int start = agg->start_idx;
1176
1177 /* Construct bit-map of pending frames within Tx window */
1178 for (i = 0; i < agg->frame_count; i++) {
1179 u16 sc;
1180 status = le16_to_cpu(frame_status[i].status);
1181 seq = le16_to_cpu(frame_status[i].sequence);
1182 idx = SEQ_TO_INDEX(seq);
1183 txq_id = SEQ_TO_QUEUE(seq);
1184
1185 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1186 AGG_TX_STATE_ABORT_MSK))
1187 continue;
1188
1189 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1190 agg->frame_count, txq_id, idx);
1191
1192 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1193
1194 sc = le16_to_cpu(hdr->seq_ctrl);
1195 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1196 IWL_ERR(priv,
1197 "BUG_ON idx doesn't match seq control"
1198 " idx=%d, seq_idx=%d, seq=%d\n",
1199 idx, SEQ_TO_SN(sc),
1200 hdr->seq_ctrl);
1201 return -1;
1202 }
1203
1204 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1205 i, idx, SEQ_TO_SN(sc));
1206
1207 sh = idx - start;
1208 if (sh > 64) {
1209 sh = (start - idx) + 0xff;
1210 bitmap = bitmap << sh;
1211 sh = 0;
1212 start = idx;
1213 } else if (sh < -64)
1214 sh = 0xff - (start - idx);
1215 else if (sh < 0) {
1216 sh = start - idx;
1217 start = idx;
1218 bitmap = bitmap << sh;
1219 sh = 0;
1220 }
1221 bitmap |= 1ULL << sh;
1222 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1223 start, (unsigned long long)bitmap);
1224 }
1225
1226 agg->bitmap = bitmap;
1227 agg->start_idx = start;
1228 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1229 agg->frame_count, agg->start_idx,
1230 (unsigned long long)agg->bitmap);
1231
1232 if (bitmap)
1233 agg->wait_for_ba = 1;
1234 }
1235 return 0;
1236 }
1237
1238 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1239 struct iwl_rx_mem_buffer *rxb)
1240 {
1241 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1242 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1243 int txq_id = SEQ_TO_QUEUE(sequence);
1244 int index = SEQ_TO_INDEX(sequence);
1245 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1246 struct ieee80211_tx_info *info;
1247 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1248 u32 status = le16_to_cpu(tx_resp->status.status);
1249 int tid;
1250 int sta_id;
1251 int freed;
1252
1253 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1254 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1255 "is out of range [0-%d] %d %d\n", txq_id,
1256 index, txq->q.n_bd, txq->q.write_ptr,
1257 txq->q.read_ptr);
1258 return;
1259 }
1260
1261 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1262 memset(&info->status, 0, sizeof(info->status));
1263
1264 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1265 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1266
1267 if (txq->sched_retry) {
1268 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1269 struct iwl_ht_agg *agg = NULL;
1270
1271 agg = &priv->stations[sta_id].tid[tid].agg;
1272
1273 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1274
1275 /* check if BAR is needed */
1276 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1277 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1278
1279 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1280 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1281 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1282 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1283 scd_ssn , index, txq_id, txq->swq_id);
1284
1285 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1286 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1287
1288 if (priv->mac80211_registered &&
1289 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1290 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1291 if (agg->state == IWL_AGG_OFF)
1292 iwl_wake_queue(priv, txq_id);
1293 else
1294 iwl_wake_queue(priv, txq->swq_id);
1295 }
1296 }
1297 } else {
1298 BUG_ON(txq_id != txq->swq_id);
1299
1300 info->status.rates[0].count = tx_resp->failure_frame + 1;
1301 info->flags |= iwl_is_tx_success(status) ?
1302 IEEE80211_TX_STAT_ACK : 0;
1303 iwl_hwrate_to_tx_control(priv,
1304 le32_to_cpu(tx_resp->rate_n_flags),
1305 info);
1306
1307 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1308 "0x%x retries %d\n",
1309 txq_id,
1310 iwl_get_tx_fail_reason(status), status,
1311 le32_to_cpu(tx_resp->rate_n_flags),
1312 tx_resp->failure_frame);
1313
1314 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1315 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1316 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1317
1318 if (priv->mac80211_registered &&
1319 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1320 iwl_wake_queue(priv, txq_id);
1321 }
1322
1323 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1324 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1325
1326 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1327 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1328 }
1329
1330 /* Currently 5000 is the superset of everything */
1331 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1332 {
1333 return len;
1334 }
1335
1336 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1337 {
1338 /* in 5000 the tx power calibration is done in uCode */
1339 priv->disable_tx_power_cal = 1;
1340 }
1341
1342 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1343 {
1344 /* init calibration handlers */
1345 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1346 iwl5000_rx_calib_result;
1347 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1348 iwl5000_rx_calib_complete;
1349 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1350 }
1351
1352
1353 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1354 {
1355 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1356 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1357 }
1358
1359 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1360 {
1361 int ret = 0;
1362 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1363 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1364 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1365
1366 if ((rxon1->flags == rxon2->flags) &&
1367 (rxon1->filter_flags == rxon2->filter_flags) &&
1368 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1369 (rxon1->ofdm_ht_single_stream_basic_rates ==
1370 rxon2->ofdm_ht_single_stream_basic_rates) &&
1371 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1372 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1373 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1374 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1375 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1376 (rxon1->rx_chain == rxon2->rx_chain) &&
1377 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1378 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1379 return 0;
1380 }
1381
1382 rxon_assoc.flags = priv->staging_rxon.flags;
1383 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1384 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1385 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1386 rxon_assoc.reserved1 = 0;
1387 rxon_assoc.reserved2 = 0;
1388 rxon_assoc.reserved3 = 0;
1389 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1390 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1391 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1392 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1393 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1394 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1395 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1396 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1397
1398 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1399 sizeof(rxon_assoc), &rxon_assoc, NULL);
1400 if (ret)
1401 return ret;
1402
1403 return ret;
1404 }
1405 static int iwl5000_send_tx_power(struct iwl_priv *priv)
1406 {
1407 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1408 u8 tx_ant_cfg_cmd;
1409
1410 /* half dBm need to multiply */
1411 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1412 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1413 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1414
1415 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1416 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1417 else
1418 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1419
1420 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1421 sizeof(tx_power_cmd), &tx_power_cmd,
1422 NULL);
1423 }
1424
1425 static void iwl5000_temperature(struct iwl_priv *priv)
1426 {
1427 /* store temperature from statistics (in Celsius) */
1428 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1429 }
1430
1431 static void iwl5150_temperature(struct iwl_priv *priv)
1432 {
1433 u32 vt = 0;
1434 s32 offset = iwl_temp_calib_to_offset(priv);
1435
1436 vt = le32_to_cpu(priv->statistics.general.temperature);
1437 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1438 /* now vt hold the temperature in Kelvin */
1439 priv->temperature = KELVIN_TO_CELSIUS(vt);
1440 }
1441
1442 /* Calc max signal level (dBm) among 3 possible receivers */
1443 int iwl5000_calc_rssi(struct iwl_priv *priv,
1444 struct iwl_rx_phy_res *rx_resp)
1445 {
1446 /* data from PHY/DSP regarding signal strength, etc.,
1447 * contents are always there, not configurable by host
1448 */
1449 struct iwl5000_non_cfg_phy *ncphy =
1450 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1451 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1452 u8 agc;
1453
1454 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1455 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1456
1457 /* Find max rssi among 3 possible receivers.
1458 * These values are measured by the digital signal processor (DSP).
1459 * They should stay fairly constant even as the signal strength varies,
1460 * if the radio's automatic gain control (AGC) is working right.
1461 * AGC value (see below) will provide the "interesting" info.
1462 */
1463 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1464 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1465 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1466 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1467 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1468
1469 max_rssi = max_t(u32, rssi_a, rssi_b);
1470 max_rssi = max_t(u32, max_rssi, rssi_c);
1471
1472 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1473 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1474
1475 /* dBm = max_rssi dB - agc dB - constant.
1476 * Higher AGC (higher radio gain) means lower signal. */
1477 return max_rssi - agc - IWL49_RSSI_OFFSET;
1478 }
1479
1480 struct iwl_station_mgmt_ops iwl5000_station_mgmt = {
1481 .add_station = iwl_add_station_flags,
1482 .remove_station = iwl_remove_station,
1483 .find_station = iwl_find_station,
1484 .clear_station_table = iwl_clear_stations_table,
1485 };
1486
1487 struct iwl_hcmd_ops iwl5000_hcmd = {
1488 .rxon_assoc = iwl5000_send_rxon_assoc,
1489 .commit_rxon = iwl_commit_rxon,
1490 .set_rxon_chain = iwl_set_rxon_chain,
1491 };
1492
1493 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1494 .get_hcmd_size = iwl5000_get_hcmd_size,
1495 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1496 .gain_computation = iwl5000_gain_computation,
1497 .chain_noise_reset = iwl5000_chain_noise_reset,
1498 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1499 .calc_rssi = iwl5000_calc_rssi,
1500 };
1501
1502 struct iwl_lib_ops iwl5000_lib = {
1503 .set_hw_params = iwl5000_hw_set_hw_params,
1504 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1505 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1506 .txq_set_sched = iwl5000_txq_set_sched,
1507 .txq_agg_enable = iwl5000_txq_agg_enable,
1508 .txq_agg_disable = iwl5000_txq_agg_disable,
1509 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1510 .txq_free_tfd = iwl_hw_txq_free_tfd,
1511 .txq_init = iwl_hw_tx_queue_init,
1512 .rx_handler_setup = iwl5000_rx_handler_setup,
1513 .setup_deferred_work = iwl5000_setup_deferred_work,
1514 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1515 .load_ucode = iwl5000_load_ucode,
1516 .init_alive_start = iwl5000_init_alive_start,
1517 .alive_notify = iwl5000_alive_notify,
1518 .send_tx_power = iwl5000_send_tx_power,
1519 .update_chain_flags = iwl_update_chain_flags,
1520 .apm_ops = {
1521 .init = iwl5000_apm_init,
1522 .reset = iwl5000_apm_reset,
1523 .stop = iwl5000_apm_stop,
1524 .config = iwl5000_nic_config,
1525 .set_pwr_src = iwl_set_pwr_src,
1526 },
1527 .eeprom_ops = {
1528 .regulatory_bands = {
1529 EEPROM_5000_REG_BAND_1_CHANNELS,
1530 EEPROM_5000_REG_BAND_2_CHANNELS,
1531 EEPROM_5000_REG_BAND_3_CHANNELS,
1532 EEPROM_5000_REG_BAND_4_CHANNELS,
1533 EEPROM_5000_REG_BAND_5_CHANNELS,
1534 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1535 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1536 },
1537 .verify_signature = iwlcore_eeprom_verify_signature,
1538 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1539 .release_semaphore = iwlcore_eeprom_release_semaphore,
1540 .calib_version = iwl5000_eeprom_calib_version,
1541 .query_addr = iwl5000_eeprom_query_addr,
1542 },
1543 .post_associate = iwl_post_associate,
1544 .config_ap = iwl_config_ap,
1545 .temp_ops = {
1546 .temperature = iwl5000_temperature,
1547 .set_ct_kill = iwl5000_set_ct_threshold,
1548 },
1549 };
1550
1551 static struct iwl_lib_ops iwl5150_lib = {
1552 .set_hw_params = iwl5000_hw_set_hw_params,
1553 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1554 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1555 .txq_set_sched = iwl5000_txq_set_sched,
1556 .txq_agg_enable = iwl5000_txq_agg_enable,
1557 .txq_agg_disable = iwl5000_txq_agg_disable,
1558 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1559 .txq_free_tfd = iwl_hw_txq_free_tfd,
1560 .txq_init = iwl_hw_tx_queue_init,
1561 .rx_handler_setup = iwl5000_rx_handler_setup,
1562 .setup_deferred_work = iwl5000_setup_deferred_work,
1563 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1564 .load_ucode = iwl5000_load_ucode,
1565 .init_alive_start = iwl5000_init_alive_start,
1566 .alive_notify = iwl5000_alive_notify,
1567 .send_tx_power = iwl5000_send_tx_power,
1568 .update_chain_flags = iwl_update_chain_flags,
1569 .apm_ops = {
1570 .init = iwl5000_apm_init,
1571 .reset = iwl5000_apm_reset,
1572 .stop = iwl5000_apm_stop,
1573 .config = iwl5000_nic_config,
1574 .set_pwr_src = iwl_set_pwr_src,
1575 },
1576 .eeprom_ops = {
1577 .regulatory_bands = {
1578 EEPROM_5000_REG_BAND_1_CHANNELS,
1579 EEPROM_5000_REG_BAND_2_CHANNELS,
1580 EEPROM_5000_REG_BAND_3_CHANNELS,
1581 EEPROM_5000_REG_BAND_4_CHANNELS,
1582 EEPROM_5000_REG_BAND_5_CHANNELS,
1583 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1584 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1585 },
1586 .verify_signature = iwlcore_eeprom_verify_signature,
1587 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1588 .release_semaphore = iwlcore_eeprom_release_semaphore,
1589 .calib_version = iwl5000_eeprom_calib_version,
1590 .query_addr = iwl5000_eeprom_query_addr,
1591 },
1592 .post_associate = iwl_post_associate,
1593 .config_ap = iwl_config_ap,
1594 .temp_ops = {
1595 .temperature = iwl5150_temperature,
1596 .set_ct_kill = iwl5150_set_ct_threshold,
1597 },
1598 };
1599
1600 struct iwl_ops iwl5000_ops = {
1601 .lib = &iwl5000_lib,
1602 .hcmd = &iwl5000_hcmd,
1603 .utils = &iwl5000_hcmd_utils,
1604 .smgmt = &iwl5000_station_mgmt,
1605 };
1606
1607 static struct iwl_ops iwl5150_ops = {
1608 .lib = &iwl5150_lib,
1609 .hcmd = &iwl5000_hcmd,
1610 .utils = &iwl5000_hcmd_utils,
1611 .smgmt = &iwl5000_station_mgmt,
1612 };
1613
1614 struct iwl_mod_params iwl50_mod_params = {
1615 .num_of_queues = IWL50_NUM_QUEUES,
1616 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1617 .amsdu_size_8K = 1,
1618 .restart_fw = 1,
1619 /* the rest are 0 by default */
1620 };
1621
1622
1623 struct iwl_cfg iwl5300_agn_cfg = {
1624 .name = "5300AGN",
1625 .fw_name_pre = IWL5000_FW_PRE,
1626 .ucode_api_max = IWL5000_UCODE_API_MAX,
1627 .ucode_api_min = IWL5000_UCODE_API_MIN,
1628 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1629 .ops = &iwl5000_ops,
1630 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1631 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1632 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1633 .mod_params = &iwl50_mod_params,
1634 .valid_tx_ant = ANT_ABC,
1635 .valid_rx_ant = ANT_ABC,
1636 .need_pll_cfg = true,
1637 };
1638
1639 struct iwl_cfg iwl5100_bg_cfg = {
1640 .name = "5100BG",
1641 .fw_name_pre = IWL5000_FW_PRE,
1642 .ucode_api_max = IWL5000_UCODE_API_MAX,
1643 .ucode_api_min = IWL5000_UCODE_API_MIN,
1644 .sku = IWL_SKU_G,
1645 .ops = &iwl5000_ops,
1646 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1647 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1648 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1649 .mod_params = &iwl50_mod_params,
1650 .valid_tx_ant = ANT_B,
1651 .valid_rx_ant = ANT_AB,
1652 .need_pll_cfg = true,
1653 };
1654
1655 struct iwl_cfg iwl5100_abg_cfg = {
1656 .name = "5100ABG",
1657 .fw_name_pre = IWL5000_FW_PRE,
1658 .ucode_api_max = IWL5000_UCODE_API_MAX,
1659 .ucode_api_min = IWL5000_UCODE_API_MIN,
1660 .sku = IWL_SKU_A|IWL_SKU_G,
1661 .ops = &iwl5000_ops,
1662 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1663 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1664 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1665 .mod_params = &iwl50_mod_params,
1666 .valid_tx_ant = ANT_B,
1667 .valid_rx_ant = ANT_AB,
1668 .need_pll_cfg = true,
1669 };
1670
1671 struct iwl_cfg iwl5100_agn_cfg = {
1672 .name = "5100AGN",
1673 .fw_name_pre = IWL5000_FW_PRE,
1674 .ucode_api_max = IWL5000_UCODE_API_MAX,
1675 .ucode_api_min = IWL5000_UCODE_API_MIN,
1676 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1677 .ops = &iwl5000_ops,
1678 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1679 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1680 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1681 .mod_params = &iwl50_mod_params,
1682 .valid_tx_ant = ANT_B,
1683 .valid_rx_ant = ANT_AB,
1684 .need_pll_cfg = true,
1685 };
1686
1687 struct iwl_cfg iwl5350_agn_cfg = {
1688 .name = "5350AGN",
1689 .fw_name_pre = IWL5000_FW_PRE,
1690 .ucode_api_max = IWL5000_UCODE_API_MAX,
1691 .ucode_api_min = IWL5000_UCODE_API_MIN,
1692 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1693 .ops = &iwl5000_ops,
1694 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1695 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1696 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1697 .mod_params = &iwl50_mod_params,
1698 .valid_tx_ant = ANT_ABC,
1699 .valid_rx_ant = ANT_ABC,
1700 .need_pll_cfg = true,
1701 };
1702
1703 struct iwl_cfg iwl5150_agn_cfg = {
1704 .name = "5150AGN",
1705 .fw_name_pre = IWL5150_FW_PRE,
1706 .ucode_api_max = IWL5150_UCODE_API_MAX,
1707 .ucode_api_min = IWL5150_UCODE_API_MIN,
1708 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1709 .ops = &iwl5150_ops,
1710 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1711 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1712 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1713 .mod_params = &iwl50_mod_params,
1714 .valid_tx_ant = ANT_A,
1715 .valid_rx_ant = ANT_AB,
1716 .need_pll_cfg = true,
1717 };
1718
1719 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1720 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1721
1722 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1723 MODULE_PARM_DESC(swcrypto50,
1724 "using software crypto engine (default 0 [hardware])\n");
1725 module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1726 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1727 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1728 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1729 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1730 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1731 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1732 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1733 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1734 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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