1 /******************************************************************************
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 1
50 #define IWL5150_UCODE_API_MAX 1
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64 static const u16 iwl5000_default_queue_to_tx_fifo
[] = {
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv
*priv
)
79 spin_lock_irqsave(&priv
->lock
, flags
);
81 /* set stop master bit */
82 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
84 iwl_poll_direct_bit(priv
, CSR_RESET
,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
87 spin_unlock_irqrestore(&priv
->lock
, flags
);
88 IWL_DEBUG_INFO(priv
, "stop master\n");
94 static int iwl5000_apm_init(struct iwl_priv
*priv
)
98 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
112 if (priv
->cfg
->need_pll_cfg
)
113 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
119 /* wait for clock stabilization */
120 ret
= iwl_poll_direct_bit(priv
, CSR_GP_CNTRL
,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
123 IWL_DEBUG_INFO(priv
, "Failed to init the card\n");
127 ret
= iwl_grab_nic_access(priv
);
132 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
136 /* disable L1-Active */
137 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
138 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
140 iwl_release_nic_access(priv
);
145 /* FIXME: this is identical to 4965 */
146 static void iwl5000_apm_stop(struct iwl_priv
*priv
)
150 iwl5000_apm_stop_master(priv
);
152 spin_lock_irqsave(&priv
->lock
, flags
);
154 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
158 /* clear "init complete" move adapter D0A* --> D0U state */
159 iwl_clear_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
161 spin_unlock_irqrestore(&priv
->lock
, flags
);
165 static int iwl5000_apm_reset(struct iwl_priv
*priv
)
170 iwl5000_apm_stop_master(priv
);
172 spin_lock_irqsave(&priv
->lock
, flags
);
174 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
179 /* FIXME: put here L1A -L0S w/a */
181 if (priv
->cfg
->need_pll_cfg
)
182 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
184 /* set "initialization complete" bit to move adapter
185 * D0U* --> D0A* state */
186 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
188 /* wait for clock stabilization */
189 ret
= iwl_poll_direct_bit(priv
, CSR_GP_CNTRL
,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
192 IWL_DEBUG_INFO(priv
, "Failed to init the card\n");
196 ret
= iwl_grab_nic_access(priv
);
201 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
205 /* disable L1-Active */
206 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
207 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
209 iwl_release_nic_access(priv
);
212 spin_unlock_irqrestore(&priv
->lock
, flags
);
218 static void iwl5000_nic_config(struct iwl_priv
*priv
)
224 spin_lock_irqsave(&priv
->lock
, flags
);
226 pci_read_config_word(priv
->pci_dev
, PCI_CFG_LINK_CTRL
, &link
);
228 /* L1 is enabled by BIOS */
229 if ((link
& PCI_CFG_LINK_CTRL_VAL_L1_EN
) == PCI_CFG_LINK_CTRL_VAL_L1_EN
)
230 /* disable L0S disabled L1A enabled */
231 iwl_set_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
233 /* L0S enabled L1A disabled */
234 iwl_clear_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
236 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
238 /* write radio config values to register */
239 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) < EEPROM_5000_RF_CFG_TYPE_MAX
)
240 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
241 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
242 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
243 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
245 /* set CSR_HW_CONFIG_REG for uCode use */
246 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
247 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
248 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);
250 /* W/A : NIC is stuck in a reset state after Early PCIe power off
251 * (PCIe power is lost before PERST# is asserted),
252 * causing ME FW to lose ownership and not being able to obtain it back.
254 iwl_grab_nic_access(priv
);
255 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
256 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
,
257 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
);
258 iwl_release_nic_access(priv
);
260 spin_unlock_irqrestore(&priv
->lock
, flags
);
268 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
272 if ((address
& INDIRECT_ADDRESS
) == 0)
275 switch (address
& INDIRECT_TYPE_MSK
) {
277 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_HOST
);
279 case INDIRECT_GENERAL
:
280 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_GENERAL
);
282 case INDIRECT_REGULATORY
:
283 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_REGULATORY
);
285 case INDIRECT_CALIBRATION
:
286 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_CALIBRATION
);
288 case INDIRECT_PROCESS_ADJST
:
289 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_PROCESS_ADJST
);
291 case INDIRECT_OTHERS
:
292 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_OTHERS
);
295 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
296 address
& INDIRECT_TYPE_MSK
);
300 /* translate the offset from words to byte */
301 return (address
& ADDRESS_MSK
) + (offset
<< 1);
304 static u16
iwl5000_eeprom_calib_version(struct iwl_priv
*priv
)
306 struct iwl_eeprom_calib_hdr
{
312 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
313 EEPROM_5000_CALIB_ALL
);
318 static void iwl5000_gain_computation(struct iwl_priv
*priv
,
319 u32 average_noise
[NUM_RX_CHAINS
],
320 u16 min_average_noise_antenna_i
,
321 u32 min_average_noise
)
325 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
327 /* Find Gain Code for the antennas B and C */
328 for (i
= 1; i
< NUM_RX_CHAINS
; i
++) {
329 if ((data
->disconn_array
[i
])) {
330 data
->delta_gain_code
[i
] = 0;
333 delta_g
= (1000 * ((s32
)average_noise
[0] -
334 (s32
)average_noise
[i
])) / 1500;
335 /* bound gain by 2 bits value max, 3rd bit is sign */
336 data
->delta_gain_code
[i
] =
337 min(abs(delta_g
), CHAIN_NOISE_MAX_DELTA_GAIN_CODE
);
340 /* set negative sign */
341 data
->delta_gain_code
[i
] |= (1 << 2);
344 IWL_DEBUG_CALIB(priv
, "Delta gains: ANT_B = %d ANT_C = %d\n",
345 data
->delta_gain_code
[1], data
->delta_gain_code
[2]);
347 if (!data
->radio_write
) {
348 struct iwl_calib_chain_noise_gain_cmd cmd
;
350 memset(&cmd
, 0, sizeof(cmd
));
352 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD
;
353 cmd
.hdr
.first_group
= 0;
354 cmd
.hdr
.groups_num
= 1;
355 cmd
.hdr
.data_valid
= 1;
356 cmd
.delta_gain_1
= data
->delta_gain_code
[1];
357 cmd
.delta_gain_2
= data
->delta_gain_code
[2];
358 iwl_send_cmd_pdu_async(priv
, REPLY_PHY_CALIBRATION_CMD
,
359 sizeof(cmd
), &cmd
, NULL
);
361 data
->radio_write
= 1;
362 data
->state
= IWL_CHAIN_NOISE_CALIBRATED
;
365 data
->chain_noise_a
= 0;
366 data
->chain_noise_b
= 0;
367 data
->chain_noise_c
= 0;
368 data
->chain_signal_a
= 0;
369 data
->chain_signal_b
= 0;
370 data
->chain_signal_c
= 0;
371 data
->beacon_count
= 0;
374 static void iwl5000_chain_noise_reset(struct iwl_priv
*priv
)
376 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
379 if ((data
->state
== IWL_CHAIN_NOISE_ALIVE
) && iwl_is_associated(priv
)) {
380 struct iwl_calib_chain_noise_reset_cmd cmd
;
381 memset(&cmd
, 0, sizeof(cmd
));
383 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD
;
384 cmd
.hdr
.first_group
= 0;
385 cmd
.hdr
.groups_num
= 1;
386 cmd
.hdr
.data_valid
= 1;
387 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
391 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
392 data
->state
= IWL_CHAIN_NOISE_ACCUMULATE
;
393 IWL_DEBUG_CALIB(priv
, "Run chain_noise_calibrate\n");
397 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info
*info
,
400 if ((info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ||
401 (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
))
402 *tx_flags
|= TX_CMD_FLG_RTS_CTS_MSK
;
404 *tx_flags
&= ~TX_CMD_FLG_RTS_CTS_MSK
;
407 static struct iwl_sensitivity_ranges iwl5000_sensitivity
= {
410 .auto_corr_min_ofdm
= 90,
411 .auto_corr_min_ofdm_mrc
= 170,
412 .auto_corr_min_ofdm_x1
= 120,
413 .auto_corr_min_ofdm_mrc_x1
= 240,
415 .auto_corr_max_ofdm
= 120,
416 .auto_corr_max_ofdm_mrc
= 210,
417 .auto_corr_max_ofdm_x1
= 155,
418 .auto_corr_max_ofdm_mrc_x1
= 290,
420 .auto_corr_min_cck
= 125,
421 .auto_corr_max_cck
= 200,
422 .auto_corr_min_cck_mrc
= 170,
423 .auto_corr_max_cck_mrc
= 400,
428 static const u8
*iwl5000_eeprom_query_addr(const struct iwl_priv
*priv
,
431 u32 address
= eeprom_indirect_address(priv
, offset
);
432 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
433 return &priv
->eeprom
[address
];
436 static s32
iwl5150_get_ct_threshold(struct iwl_priv
*priv
)
438 const s32 volt2temp_coef
= -5;
439 u16
*temp_calib
= (u16
*)iwl_eeprom_query_addr(priv
,
440 EEPROM_5000_TEMPERATURE
);
441 /* offset = temperate - voltage / coef */
442 s32 offset
= temp_calib
[0] - temp_calib
[1] / volt2temp_coef
;
443 s32 threshold
= (s32
)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD
) - offset
;
444 return threshold
* volt2temp_coef
;
450 static int iwl5000_set_Xtal_calib(struct iwl_priv
*priv
)
452 struct iwl_calib_xtal_freq_cmd cmd
;
453 u16
*xtal_calib
= (u16
*)iwl_eeprom_query_addr(priv
, EEPROM_5000_XTAL
);
455 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
;
456 cmd
.hdr
.first_group
= 0;
457 cmd
.hdr
.groups_num
= 1;
458 cmd
.hdr
.data_valid
= 1;
459 cmd
.cap_pin1
= (u8
)xtal_calib
[0];
460 cmd
.cap_pin2
= (u8
)xtal_calib
[1];
461 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_XTAL
],
462 (u8
*)&cmd
, sizeof(cmd
));
465 static int iwl5000_send_calib_cfg(struct iwl_priv
*priv
)
467 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
468 struct iwl_host_cmd cmd
= {
469 .id
= CALIBRATION_CFG_CMD
,
470 .len
= sizeof(struct iwl_calib_cfg_cmd
),
471 .data
= &calib_cfg_cmd
,
474 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
475 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
476 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
477 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
478 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
480 return iwl_send_cmd(priv
, &cmd
);
483 static void iwl5000_rx_calib_result(struct iwl_priv
*priv
,
484 struct iwl_rx_mem_buffer
*rxb
)
486 struct iwl_rx_packet
*pkt
= (void *)rxb
->skb
->data
;
487 struct iwl_calib_hdr
*hdr
= (struct iwl_calib_hdr
*)pkt
->u
.raw
;
488 int len
= le32_to_cpu(pkt
->len
) & FH_RSCSR_FRAME_SIZE_MSK
;
491 /* reduce the size of the length field itself */
494 /* Define the order in which the results will be sent to the runtime
495 * uCode. iwl_send_calib_results sends them in a row according to their
496 * index. We sort them here */
497 switch (hdr
->op_code
) {
498 case IWL_PHY_CALIBRATE_DC_CMD
:
499 index
= IWL_CALIB_DC
;
501 case IWL_PHY_CALIBRATE_LO_CMD
:
502 index
= IWL_CALIB_LO
;
504 case IWL_PHY_CALIBRATE_TX_IQ_CMD
:
505 index
= IWL_CALIB_TX_IQ
;
507 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
508 index
= IWL_CALIB_TX_IQ_PERD
;
510 case IWL_PHY_CALIBRATE_BASE_BAND_CMD
:
511 index
= IWL_CALIB_BASE_BAND
;
514 IWL_ERR(priv
, "Unknown calibration notification %d\n",
518 iwl_calib_set(&priv
->calib_results
[index
], pkt
->u
.raw
, len
);
521 static void iwl5000_rx_calib_complete(struct iwl_priv
*priv
,
522 struct iwl_rx_mem_buffer
*rxb
)
524 IWL_DEBUG_INFO(priv
, "Init. calibration is completed, restarting fw.\n");
525 queue_work(priv
->workqueue
, &priv
->restart
);
531 static int iwl5000_load_section(struct iwl_priv
*priv
,
532 struct fw_desc
*image
,
538 dma_addr_t phy_addr
= image
->p_addr
;
539 u32 byte_cnt
= image
->len
;
541 spin_lock_irqsave(&priv
->lock
, flags
);
542 ret
= iwl_grab_nic_access(priv
);
544 spin_unlock_irqrestore(&priv
->lock
, flags
);
548 iwl_write_direct32(priv
,
549 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
550 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
552 iwl_write_direct32(priv
,
553 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
555 iwl_write_direct32(priv
,
556 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
557 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
559 iwl_write_direct32(priv
,
560 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
561 (iwl_get_dma_hi_addr(phy_addr
)
562 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
564 iwl_write_direct32(priv
,
565 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
566 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
567 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
568 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
570 iwl_write_direct32(priv
,
571 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
572 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
573 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
574 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
576 iwl_release_nic_access(priv
);
577 spin_unlock_irqrestore(&priv
->lock
, flags
);
581 static int iwl5000_load_given_ucode(struct iwl_priv
*priv
,
582 struct fw_desc
*inst_image
,
583 struct fw_desc
*data_image
)
587 ret
= iwl5000_load_section(priv
, inst_image
,
588 IWL50_RTC_INST_LOWER_BOUND
);
592 IWL_DEBUG_INFO(priv
, "INST uCode section being loaded...\n");
593 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
594 priv
->ucode_write_complete
, 5 * HZ
);
595 if (ret
== -ERESTARTSYS
) {
596 IWL_ERR(priv
, "Could not load the INST uCode section due "
601 IWL_ERR(priv
, "Could not load the INST uCode section\n");
605 priv
->ucode_write_complete
= 0;
607 ret
= iwl5000_load_section(
608 priv
, data_image
, IWL50_RTC_DATA_LOWER_BOUND
);
612 IWL_DEBUG_INFO(priv
, "DATA uCode section being loaded...\n");
614 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
615 priv
->ucode_write_complete
, 5 * HZ
);
616 if (ret
== -ERESTARTSYS
) {
617 IWL_ERR(priv
, "Could not load the INST uCode section due "
621 IWL_ERR(priv
, "Could not load the DATA uCode section\n");
626 priv
->ucode_write_complete
= 0;
631 static int iwl5000_load_ucode(struct iwl_priv
*priv
)
635 /* check whether init ucode should be loaded, or rather runtime ucode */
636 if (priv
->ucode_init
.len
&& (priv
->ucode_type
== UCODE_NONE
)) {
637 IWL_DEBUG_INFO(priv
, "Init ucode found. Loading init ucode...\n");
638 ret
= iwl5000_load_given_ucode(priv
,
639 &priv
->ucode_init
, &priv
->ucode_init_data
);
641 IWL_DEBUG_INFO(priv
, "Init ucode load complete.\n");
642 priv
->ucode_type
= UCODE_INIT
;
645 IWL_DEBUG_INFO(priv
, "Init ucode not found, or already loaded. "
646 "Loading runtime ucode...\n");
647 ret
= iwl5000_load_given_ucode(priv
,
648 &priv
->ucode_code
, &priv
->ucode_data
);
650 IWL_DEBUG_INFO(priv
, "Runtime ucode load complete.\n");
651 priv
->ucode_type
= UCODE_RT
;
658 static void iwl5000_init_alive_start(struct iwl_priv
*priv
)
662 /* Check alive response for "valid" sign from uCode */
663 if (priv
->card_alive_init
.is_valid
!= UCODE_VALID_OK
) {
664 /* We had an error bringing up the hardware, so take it
665 * all the way back down so we can try again */
666 IWL_DEBUG_INFO(priv
, "Initialize Alive failed.\n");
670 /* initialize uCode was loaded... verify inst image.
671 * This is a paranoid check, because we would not have gotten the
672 * "initialize" alive if code weren't properly loaded. */
673 if (iwl_verify_ucode(priv
)) {
674 /* Runtime instruction load was bad;
675 * take it all the way back down so we can try again */
676 IWL_DEBUG_INFO(priv
, "Bad \"initialize\" uCode load.\n");
680 iwl_clear_stations_table(priv
);
681 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
684 "Could not complete ALIVE transition: %d\n", ret
);
688 iwl5000_send_calib_cfg(priv
);
692 /* real restart (first load init_ucode) */
693 queue_work(priv
->workqueue
, &priv
->restart
);
696 static void iwl5000_set_wr_ptrs(struct iwl_priv
*priv
,
697 int txq_id
, u32 index
)
699 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
700 (index
& 0xff) | (txq_id
<< 8));
701 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(txq_id
), index
);
704 static void iwl5000_tx_queue_set_status(struct iwl_priv
*priv
,
705 struct iwl_tx_queue
*txq
,
706 int tx_fifo_id
, int scd_retry
)
708 int txq_id
= txq
->q
.id
;
709 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
) ? 1 : 0;
711 iwl_write_prph(priv
, IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
712 (active
<< IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
713 (tx_fifo_id
<< IWL50_SCD_QUEUE_STTS_REG_POS_TXF
) |
714 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL
) |
715 IWL50_SCD_QUEUE_STTS_REG_MSK
);
717 txq
->sched_retry
= scd_retry
;
719 IWL_DEBUG_INFO(priv
, "%s %s Queue %d on AC %d\n",
720 active
? "Activate" : "Deactivate",
721 scd_retry
? "BA" : "AC", txq_id
, tx_fifo_id
);
724 static int iwl5000_send_wimax_coex(struct iwl_priv
*priv
)
726 struct iwl_wimax_coex_cmd coex_cmd
;
728 memset(&coex_cmd
, 0, sizeof(coex_cmd
));
730 return iwl_send_cmd_pdu(priv
, COEX_PRIORITY_TABLE_CMD
,
731 sizeof(coex_cmd
), &coex_cmd
);
734 static int iwl5000_alive_notify(struct iwl_priv
*priv
)
742 spin_lock_irqsave(&priv
->lock
, flags
);
744 ret
= iwl_grab_nic_access(priv
);
746 spin_unlock_irqrestore(&priv
->lock
, flags
);
750 priv
->scd_base_addr
= iwl_read_prph(priv
, IWL50_SCD_SRAM_BASE_ADDR
);
751 a
= priv
->scd_base_addr
+ IWL50_SCD_CONTEXT_DATA_OFFSET
;
752 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TX_STTS_BITMAP_OFFSET
;
754 iwl_write_targ_mem(priv
, a
, 0);
755 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TRANSLATE_TBL_OFFSET
;
757 iwl_write_targ_mem(priv
, a
, 0);
758 for (; a
< sizeof(u16
) * priv
->hw_params
.max_txq_num
; a
+= 4)
759 iwl_write_targ_mem(priv
, a
, 0);
761 iwl_write_prph(priv
, IWL50_SCD_DRAM_BASE_ADDR
,
762 priv
->scd_bc_tbls
.dma
>> 10);
764 /* Enable DMA channel */
765 for (chan
= 0; chan
< FH50_TCSR_CHNL_NUM
; chan
++)
766 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
767 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
768 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
770 /* Update FH chicken bits */
771 reg_val
= iwl_read_direct32(priv
, FH_TX_CHICKEN_BITS_REG
);
772 iwl_write_direct32(priv
, FH_TX_CHICKEN_BITS_REG
,
773 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
775 iwl_write_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
,
776 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv
->hw_params
.max_txq_num
));
777 iwl_write_prph(priv
, IWL50_SCD_AGGR_SEL
, 0);
779 /* initiate the queues */
780 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++) {
781 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(i
), 0);
782 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
783 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
784 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
785 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
786 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
) +
789 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
790 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
792 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
793 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
796 iwl_write_prph(priv
, IWL50_SCD_INTERRUPT_MASK
,
797 IWL_MASK(0, priv
->hw_params
.max_txq_num
));
799 /* Activate all Tx DMA/FIFO channels */
800 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, IWL_MASK(0, 7));
802 iwl5000_set_wr_ptrs(priv
, IWL_CMD_QUEUE_NUM
, 0);
804 /* map qos queues to fifos one-to-one */
805 for (i
= 0; i
< ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo
); i
++) {
806 int ac
= iwl5000_default_queue_to_tx_fifo
[i
];
807 iwl_txq_ctx_activate(priv
, i
);
808 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[i
], ac
, 0);
810 /* TODO - need to initialize those FIFOs inside the loop above,
811 * not only mark them as active */
812 iwl_txq_ctx_activate(priv
, 4);
813 iwl_txq_ctx_activate(priv
, 7);
814 iwl_txq_ctx_activate(priv
, 8);
815 iwl_txq_ctx_activate(priv
, 9);
817 iwl_release_nic_access(priv
);
818 spin_unlock_irqrestore(&priv
->lock
, flags
);
821 iwl5000_send_wimax_coex(priv
);
823 iwl5000_set_Xtal_calib(priv
);
824 iwl_send_calib_results(priv
);
829 static int iwl5000_hw_set_hw_params(struct iwl_priv
*priv
)
831 if ((priv
->cfg
->mod_params
->num_of_queues
> IWL50_NUM_QUEUES
) ||
832 (priv
->cfg
->mod_params
->num_of_queues
< IWL_MIN_NUM_QUEUES
)) {
834 "invalid queues_num, should be between %d and %d\n",
835 IWL_MIN_NUM_QUEUES
, IWL50_NUM_QUEUES
);
839 priv
->hw_params
.max_txq_num
= priv
->cfg
->mod_params
->num_of_queues
;
840 priv
->hw_params
.dma_chnl_num
= FH50_TCSR_CHNL_NUM
;
841 priv
->hw_params
.scd_bc_tbls_size
=
842 IWL50_NUM_QUEUES
* sizeof(struct iwl5000_scd_bc_tbl
);
843 priv
->hw_params
.tfd_size
= sizeof(struct iwl_tfd
);
844 priv
->hw_params
.max_stations
= IWL5000_STATION_COUNT
;
845 priv
->hw_params
.bcast_sta_id
= IWL5000_BROADCAST_ID
;
847 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
848 case CSR_HW_REV_TYPE_6x00
:
849 case CSR_HW_REV_TYPE_6x50
:
850 priv
->hw_params
.max_data_size
= IWL60_RTC_DATA_SIZE
;
851 priv
->hw_params
.max_inst_size
= IWL60_RTC_INST_SIZE
;
854 priv
->hw_params
.max_data_size
= IWL50_RTC_DATA_SIZE
;
855 priv
->hw_params
.max_inst_size
= IWL50_RTC_INST_SIZE
;
858 priv
->hw_params
.max_bsm_size
= 0;
859 priv
->hw_params
.fat_channel
= BIT(IEEE80211_BAND_2GHZ
) |
860 BIT(IEEE80211_BAND_5GHZ
);
861 priv
->hw_params
.rx_wrt_ptr_reg
= FH_RSCSR_CHNL0_WPTR
;
863 priv
->hw_params
.sens
= &iwl5000_sensitivity
;
865 priv
->hw_params
.tx_chains_num
= num_of_ant(priv
->cfg
->valid_tx_ant
);
866 priv
->hw_params
.rx_chains_num
= num_of_ant(priv
->cfg
->valid_rx_ant
);
867 priv
->hw_params
.valid_tx_ant
= priv
->cfg
->valid_tx_ant
;
868 priv
->hw_params
.valid_rx_ant
= priv
->cfg
->valid_rx_ant
;
870 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
871 case CSR_HW_REV_TYPE_5150
:
872 /* 5150 wants in Kelvin */
873 priv
->hw_params
.ct_kill_threshold
=
874 iwl5150_get_ct_threshold(priv
);
877 /* all others want Celsius */
878 priv
->hw_params
.ct_kill_threshold
= CT_KILL_THRESHOLD
;
882 /* Set initial calibration set */
883 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
884 case CSR_HW_REV_TYPE_5150
:
885 priv
->hw_params
.calib_init_cfg
=
888 BIT(IWL_CALIB_TX_IQ
) |
889 BIT(IWL_CALIB_BASE_BAND
);
893 priv
->hw_params
.calib_init_cfg
=
894 BIT(IWL_CALIB_XTAL
) |
896 BIT(IWL_CALIB_TX_IQ
) |
897 BIT(IWL_CALIB_TX_IQ_PERD
) |
898 BIT(IWL_CALIB_BASE_BAND
);
907 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
909 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
910 struct iwl_tx_queue
*txq
,
913 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
914 int write_ptr
= txq
->q
.write_ptr
;
915 int txq_id
= txq
->q
.id
;
918 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
921 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
923 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
924 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
925 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
927 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
931 case TX_CMD_SEC_TKIP
:
935 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
940 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
942 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
944 if (txq
->q
.write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
946 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
949 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
950 struct iwl_tx_queue
*txq
)
952 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
953 int txq_id
= txq
->q
.id
;
954 int read_ptr
= txq
->q
.read_ptr
;
958 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
960 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
961 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
963 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
964 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
966 if (txq
->q
.write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
968 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
971 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv
*priv
, u16 ra_tid
,
978 scd_q2ratid
= ra_tid
& IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
980 tbl_dw_addr
= priv
->scd_base_addr
+
981 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id
);
983 tbl_dw
= iwl_read_targ_mem(priv
, tbl_dw_addr
);
986 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
988 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
990 iwl_write_targ_mem(priv
, tbl_dw_addr
, tbl_dw
);
994 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv
*priv
, u16 txq_id
)
996 /* Simply stop the queue, but don't change any configuration;
997 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
999 IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
1000 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1001 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1004 static int iwl5000_txq_agg_enable(struct iwl_priv
*priv
, int txq_id
,
1005 int tx_fifo
, int sta_id
, int tid
, u16 ssn_idx
)
1007 unsigned long flags
;
1011 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
1012 (IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
<= txq_id
)) {
1014 "queue number out of range: %d, must be %d to %d\n",
1015 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
1016 IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
- 1);
1020 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1022 /* Modify device's station table to Tx this TID */
1023 iwl_sta_tx_modify_enable_tid(priv
, sta_id
, tid
);
1025 spin_lock_irqsave(&priv
->lock
, flags
);
1026 ret
= iwl_grab_nic_access(priv
);
1028 spin_unlock_irqrestore(&priv
->lock
, flags
);
1032 /* Stop this Tx queue before configuring it */
1033 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
1035 /* Map receiver-address / traffic-ID to this queue */
1036 iwl5000_tx_queue_set_q2ratid(priv
, ra_tid
, txq_id
);
1038 /* Set this queue as a chain-building queue */
1039 iwl_set_bits_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
1041 /* enable aggregations for the queue */
1042 iwl_set_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1<<txq_id
));
1044 /* Place first TFD at index corresponding to start sequence number.
1045 * Assumes that ssn_idx is valid (!= 0xFFF) */
1046 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
1047 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
1048 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
1050 /* Set up Tx window size and frame limit for this queue */
1051 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
1052 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
1055 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1056 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1057 ((SCD_FRAME_LIMIT
<<
1058 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1059 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1061 iwl_set_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
1063 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1064 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 1);
1066 iwl_release_nic_access(priv
);
1067 spin_unlock_irqrestore(&priv
->lock
, flags
);
1072 static int iwl5000_txq_agg_disable(struct iwl_priv
*priv
, u16 txq_id
,
1073 u16 ssn_idx
, u8 tx_fifo
)
1077 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
1078 (IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
<= txq_id
)) {
1080 "queue number out of range: %d, must be %d to %d\n",
1081 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
1082 IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
- 1);
1086 ret
= iwl_grab_nic_access(priv
);
1090 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
1092 iwl_clear_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1 << txq_id
));
1094 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
1095 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
1096 /* supposes that ssn_idx is valid (!= 0xFFF) */
1097 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
1099 iwl_clear_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
1100 iwl_txq_ctx_deactivate(priv
, txq_id
);
1101 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 0);
1103 iwl_release_nic_access(priv
);
1108 static u16
iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
1110 u16 size
= (u16
)sizeof(struct iwl_addsta_cmd
);
1111 memcpy(data
, cmd
, size
);
1117 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1118 * must be called under priv->lock and mac access
1120 static void iwl5000_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
1122 iwl_write_prph(priv
, IWL50_SCD_TXFACT
, mask
);
1126 static inline u32
iwl5000_get_scd_ssn(struct iwl5000_tx_resp
*tx_resp
)
1128 return le32_to_cpup((__le32
*)&tx_resp
->status
+
1129 tx_resp
->frame_count
) & MAX_SN
;
1132 static int iwl5000_tx_status_reply_tx(struct iwl_priv
*priv
,
1133 struct iwl_ht_agg
*agg
,
1134 struct iwl5000_tx_resp
*tx_resp
,
1135 int txq_id
, u16 start_idx
)
1138 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
1139 struct ieee80211_tx_info
*info
= NULL
;
1140 struct ieee80211_hdr
*hdr
= NULL
;
1141 u32 rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
1145 if (agg
->wait_for_ba
)
1146 IWL_DEBUG_TX_REPLY(priv
, "got tx response w/o block-ack\n");
1148 agg
->frame_count
= tx_resp
->frame_count
;
1149 agg
->start_idx
= start_idx
;
1150 agg
->rate_n_flags
= rate_n_flags
;
1153 /* # frames attempted by Tx command */
1154 if (agg
->frame_count
== 1) {
1155 /* Only one frame was attempted; no block-ack will arrive */
1156 status
= le16_to_cpu(frame_status
[0].status
);
1159 /* FIXME: code repetition */
1160 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1161 agg
->frame_count
, agg
->start_idx
, idx
);
1163 info
= IEEE80211_SKB_CB(priv
->txq
[txq_id
].txb
[idx
].skb
[0]);
1164 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
1165 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
1166 info
->flags
|= iwl_is_tx_success(status
) ?
1167 IEEE80211_TX_STAT_ACK
: 0;
1168 iwl_hwrate_to_tx_control(priv
, rate_n_flags
, info
);
1170 /* FIXME: code repetition end */
1172 IWL_DEBUG_TX_REPLY(priv
, "1 Frame 0x%x failure :%d\n",
1173 status
& 0xff, tx_resp
->failure_frame
);
1174 IWL_DEBUG_TX_REPLY(priv
, "Rate Info rate_n_flags=%x\n", rate_n_flags
);
1176 agg
->wait_for_ba
= 0;
1178 /* Two or more frames were attempted; expect block-ack */
1180 int start
= agg
->start_idx
;
1182 /* Construct bit-map of pending frames within Tx window */
1183 for (i
= 0; i
< agg
->frame_count
; i
++) {
1185 status
= le16_to_cpu(frame_status
[i
].status
);
1186 seq
= le16_to_cpu(frame_status
[i
].sequence
);
1187 idx
= SEQ_TO_INDEX(seq
);
1188 txq_id
= SEQ_TO_QUEUE(seq
);
1190 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
1191 AGG_TX_STATE_ABORT_MSK
))
1194 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, txq_id=%d idx=%d\n",
1195 agg
->frame_count
, txq_id
, idx
);
1197 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
1199 sc
= le16_to_cpu(hdr
->seq_ctrl
);
1200 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
1202 "BUG_ON idx doesn't match seq control"
1203 " idx=%d, seq_idx=%d, seq=%d\n",
1209 IWL_DEBUG_TX_REPLY(priv
, "AGG Frame i=%d idx %d seq=%d\n",
1210 i
, idx
, SEQ_TO_SN(sc
));
1214 sh
= (start
- idx
) + 0xff;
1215 bitmap
= bitmap
<< sh
;
1218 } else if (sh
< -64)
1219 sh
= 0xff - (start
- idx
);
1223 bitmap
= bitmap
<< sh
;
1226 bitmap
|= 1ULL << sh
;
1227 IWL_DEBUG_TX_REPLY(priv
, "start=%d bitmap=0x%llx\n",
1228 start
, (unsigned long long)bitmap
);
1231 agg
->bitmap
= bitmap
;
1232 agg
->start_idx
= start
;
1233 IWL_DEBUG_TX_REPLY(priv
, "Frames %d start_idx=%d bitmap=0x%llx\n",
1234 agg
->frame_count
, agg
->start_idx
,
1235 (unsigned long long)agg
->bitmap
);
1238 agg
->wait_for_ba
= 1;
1243 static void iwl5000_rx_reply_tx(struct iwl_priv
*priv
,
1244 struct iwl_rx_mem_buffer
*rxb
)
1246 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1247 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1248 int txq_id
= SEQ_TO_QUEUE(sequence
);
1249 int index
= SEQ_TO_INDEX(sequence
);
1250 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1251 struct ieee80211_tx_info
*info
;
1252 struct iwl5000_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
1253 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
1258 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
1259 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
1260 "is out of range [0-%d] %d %d\n", txq_id
,
1261 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
1266 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
1267 memset(&info
->status
, 0, sizeof(info
->status
));
1269 tid
= (tx_resp
->ra_tid
& IWL50_TX_RES_TID_MSK
) >> IWL50_TX_RES_TID_POS
;
1270 sta_id
= (tx_resp
->ra_tid
& IWL50_TX_RES_RA_MSK
) >> IWL50_TX_RES_RA_POS
;
1272 if (txq
->sched_retry
) {
1273 const u32 scd_ssn
= iwl5000_get_scd_ssn(tx_resp
);
1274 struct iwl_ht_agg
*agg
= NULL
;
1276 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1278 iwl5000_tx_status_reply_tx(priv
, agg
, tx_resp
, txq_id
, index
);
1280 /* check if BAR is needed */
1281 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
))
1282 info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1284 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
1285 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
1286 IWL_DEBUG_TX_REPLY(priv
, "Retry scheduler reclaim "
1287 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1288 scd_ssn
, index
, txq_id
, txq
->swq_id
);
1290 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1291 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1293 if (priv
->mac80211_registered
&&
1294 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1295 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
)) {
1296 if (agg
->state
== IWL_AGG_OFF
)
1297 ieee80211_wake_queue(priv
->hw
, txq_id
);
1299 ieee80211_wake_queue(priv
->hw
,
1304 BUG_ON(txq_id
!= txq
->swq_id
);
1306 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
1307 info
->flags
|= iwl_is_tx_success(status
) ?
1308 IEEE80211_TX_STAT_ACK
: 0;
1309 iwl_hwrate_to_tx_control(priv
,
1310 le32_to_cpu(tx_resp
->rate_n_flags
),
1313 IWL_DEBUG_TX_REPLY(priv
, "TXQ %d status %s (0x%08x) rate_n_flags "
1314 "0x%x retries %d\n",
1316 iwl_get_tx_fail_reason(status
), status
,
1317 le32_to_cpu(tx_resp
->rate_n_flags
),
1318 tx_resp
->failure_frame
);
1320 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1321 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1322 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1324 if (priv
->mac80211_registered
&&
1325 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
))
1326 ieee80211_wake_queue(priv
->hw
, txq_id
);
1329 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1330 iwl_txq_check_empty(priv
, sta_id
, tid
, txq_id
);
1332 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
1333 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1336 /* Currently 5000 is the superset of everything */
1337 static u16
iwl5000_get_hcmd_size(u8 cmd_id
, u16 len
)
1342 static void iwl5000_setup_deferred_work(struct iwl_priv
*priv
)
1344 /* in 5000 the tx power calibration is done in uCode */
1345 priv
->disable_tx_power_cal
= 1;
1348 static void iwl5000_rx_handler_setup(struct iwl_priv
*priv
)
1350 /* init calibration handlers */
1351 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
1352 iwl5000_rx_calib_result
;
1353 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
1354 iwl5000_rx_calib_complete
;
1355 priv
->rx_handlers
[REPLY_TX
] = iwl5000_rx_reply_tx
;
1359 static int iwl5000_hw_valid_rtc_data_addr(u32 addr
)
1361 return (addr
>= IWL50_RTC_DATA_LOWER_BOUND
) &&
1362 (addr
< IWL50_RTC_DATA_UPPER_BOUND
);
1365 static int iwl5000_send_rxon_assoc(struct iwl_priv
*priv
)
1368 struct iwl5000_rxon_assoc_cmd rxon_assoc
;
1369 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1370 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1372 if ((rxon1
->flags
== rxon2
->flags
) &&
1373 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1374 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1375 (rxon1
->ofdm_ht_single_stream_basic_rates
==
1376 rxon2
->ofdm_ht_single_stream_basic_rates
) &&
1377 (rxon1
->ofdm_ht_dual_stream_basic_rates
==
1378 rxon2
->ofdm_ht_dual_stream_basic_rates
) &&
1379 (rxon1
->ofdm_ht_triple_stream_basic_rates
==
1380 rxon2
->ofdm_ht_triple_stream_basic_rates
) &&
1381 (rxon1
->acquisition_data
== rxon2
->acquisition_data
) &&
1382 (rxon1
->rx_chain
== rxon2
->rx_chain
) &&
1383 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1384 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1388 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1389 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1390 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1391 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1392 rxon_assoc
.reserved1
= 0;
1393 rxon_assoc
.reserved2
= 0;
1394 rxon_assoc
.reserved3
= 0;
1395 rxon_assoc
.ofdm_ht_single_stream_basic_rates
=
1396 priv
->staging_rxon
.ofdm_ht_single_stream_basic_rates
;
1397 rxon_assoc
.ofdm_ht_dual_stream_basic_rates
=
1398 priv
->staging_rxon
.ofdm_ht_dual_stream_basic_rates
;
1399 rxon_assoc
.rx_chain_select_flags
= priv
->staging_rxon
.rx_chain
;
1400 rxon_assoc
.ofdm_ht_triple_stream_basic_rates
=
1401 priv
->staging_rxon
.ofdm_ht_triple_stream_basic_rates
;
1402 rxon_assoc
.acquisition_data
= priv
->staging_rxon
.acquisition_data
;
1404 ret
= iwl_send_cmd_pdu_async(priv
, REPLY_RXON_ASSOC
,
1405 sizeof(rxon_assoc
), &rxon_assoc
, NULL
);
1411 static int iwl5000_send_tx_power(struct iwl_priv
*priv
)
1413 struct iwl5000_tx_power_dbm_cmd tx_power_cmd
;
1415 /* half dBm need to multiply */
1416 tx_power_cmd
.global_lmt
= (s8
)(2 * priv
->tx_power_user_lmt
);
1417 tx_power_cmd
.flags
= IWL50_TX_POWER_NO_CLOSED
;
1418 tx_power_cmd
.srv_chan_lmt
= IWL50_TX_POWER_AUTO
;
1419 return iwl_send_cmd_pdu_async(priv
, REPLY_TX_POWER_DBM_CMD
,
1420 sizeof(tx_power_cmd
), &tx_power_cmd
,
1424 static void iwl5000_temperature(struct iwl_priv
*priv
)
1426 /* store temperature from statistics (in Celsius) */
1427 priv
->temperature
= le32_to_cpu(priv
->statistics
.general
.temperature
);
1430 /* Calc max signal level (dBm) among 3 possible receivers */
1431 static int iwl5000_calc_rssi(struct iwl_priv
*priv
,
1432 struct iwl_rx_phy_res
*rx_resp
)
1434 /* data from PHY/DSP regarding signal strength, etc.,
1435 * contents are always there, not configurable by host
1437 struct iwl5000_non_cfg_phy
*ncphy
=
1438 (struct iwl5000_non_cfg_phy
*)rx_resp
->non_cfg_phy_buf
;
1439 u32 val
, rssi_a
, rssi_b
, rssi_c
, max_rssi
;
1442 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_AGC_IDX
]);
1443 agc
= (val
& IWL50_OFDM_AGC_MSK
) >> IWL50_OFDM_AGC_BIT_POS
;
1445 /* Find max rssi among 3 possible receivers.
1446 * These values are measured by the digital signal processor (DSP).
1447 * They should stay fairly constant even as the signal strength varies,
1448 * if the radio's automatic gain control (AGC) is working right.
1449 * AGC value (see below) will provide the "interesting" info.
1451 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_AB_IDX
]);
1452 rssi_a
= (val
& IWL50_OFDM_RSSI_A_MSK
) >> IWL50_OFDM_RSSI_A_BIT_POS
;
1453 rssi_b
= (val
& IWL50_OFDM_RSSI_B_MSK
) >> IWL50_OFDM_RSSI_B_BIT_POS
;
1454 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_C_IDX
]);
1455 rssi_c
= (val
& IWL50_OFDM_RSSI_C_MSK
) >> IWL50_OFDM_RSSI_C_BIT_POS
;
1457 max_rssi
= max_t(u32
, rssi_a
, rssi_b
);
1458 max_rssi
= max_t(u32
, max_rssi
, rssi_c
);
1460 IWL_DEBUG_STATS(priv
, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1461 rssi_a
, rssi_b
, rssi_c
, max_rssi
, agc
);
1463 /* dBm = max_rssi dB - agc dB - constant.
1464 * Higher AGC (higher radio gain) means lower signal. */
1465 return max_rssi
- agc
- IWL49_RSSI_OFFSET
;
1468 static struct iwl_hcmd_ops iwl5000_hcmd
= {
1469 .rxon_assoc
= iwl5000_send_rxon_assoc
,
1472 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils
= {
1473 .get_hcmd_size
= iwl5000_get_hcmd_size
,
1474 .build_addsta_hcmd
= iwl5000_build_addsta_hcmd
,
1475 .gain_computation
= iwl5000_gain_computation
,
1476 .chain_noise_reset
= iwl5000_chain_noise_reset
,
1477 .rts_tx_cmd_flag
= iwl5000_rts_tx_cmd_flag
,
1478 .calc_rssi
= iwl5000_calc_rssi
,
1481 static struct iwl_lib_ops iwl5000_lib
= {
1482 .set_hw_params
= iwl5000_hw_set_hw_params
,
1483 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1484 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1485 .txq_set_sched
= iwl5000_txq_set_sched
,
1486 .txq_agg_enable
= iwl5000_txq_agg_enable
,
1487 .txq_agg_disable
= iwl5000_txq_agg_disable
,
1488 .txq_attach_buf_to_tfd
= iwl_hw_txq_attach_buf_to_tfd
,
1489 .txq_free_tfd
= iwl_hw_txq_free_tfd
,
1490 .txq_init
= iwl_hw_tx_queue_init
,
1491 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1492 .setup_deferred_work
= iwl5000_setup_deferred_work
,
1493 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1494 .load_ucode
= iwl5000_load_ucode
,
1495 .init_alive_start
= iwl5000_init_alive_start
,
1496 .alive_notify
= iwl5000_alive_notify
,
1497 .send_tx_power
= iwl5000_send_tx_power
,
1498 .temperature
= iwl5000_temperature
,
1499 .update_chain_flags
= iwl_update_chain_flags
,
1501 .init
= iwl5000_apm_init
,
1502 .reset
= iwl5000_apm_reset
,
1503 .stop
= iwl5000_apm_stop
,
1504 .config
= iwl5000_nic_config
,
1505 .set_pwr_src
= iwl_set_pwr_src
,
1508 .regulatory_bands
= {
1509 EEPROM_5000_REG_BAND_1_CHANNELS
,
1510 EEPROM_5000_REG_BAND_2_CHANNELS
,
1511 EEPROM_5000_REG_BAND_3_CHANNELS
,
1512 EEPROM_5000_REG_BAND_4_CHANNELS
,
1513 EEPROM_5000_REG_BAND_5_CHANNELS
,
1514 EEPROM_5000_REG_BAND_24_FAT_CHANNELS
,
1515 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1517 .verify_signature
= iwlcore_eeprom_verify_signature
,
1518 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1519 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1520 .calib_version
= iwl5000_eeprom_calib_version
,
1521 .query_addr
= iwl5000_eeprom_query_addr
,
1525 struct iwl_ops iwl5000_ops
= {
1526 .lib
= &iwl5000_lib
,
1527 .hcmd
= &iwl5000_hcmd
,
1528 .utils
= &iwl5000_hcmd_utils
,
1531 struct iwl_mod_params iwl50_mod_params
= {
1532 .num_of_queues
= IWL50_NUM_QUEUES
,
1533 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1536 /* the rest are 0 by default */
1540 struct iwl_cfg iwl5300_agn_cfg
= {
1542 .fw_name_pre
= IWL5000_FW_PRE
,
1543 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1544 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1545 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1546 .ops
= &iwl5000_ops
,
1547 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1548 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1549 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1550 .mod_params
= &iwl50_mod_params
,
1551 .valid_tx_ant
= ANT_ABC
,
1552 .valid_rx_ant
= ANT_ABC
,
1553 .need_pll_cfg
= true,
1556 struct iwl_cfg iwl5100_bg_cfg
= {
1558 .fw_name_pre
= IWL5000_FW_PRE
,
1559 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1560 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1562 .ops
= &iwl5000_ops
,
1563 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1564 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1565 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1566 .mod_params
= &iwl50_mod_params
,
1567 .valid_tx_ant
= ANT_B
,
1568 .valid_rx_ant
= ANT_AB
,
1569 .need_pll_cfg
= true,
1572 struct iwl_cfg iwl5100_abg_cfg
= {
1574 .fw_name_pre
= IWL5000_FW_PRE
,
1575 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1576 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1577 .sku
= IWL_SKU_A
|IWL_SKU_G
,
1578 .ops
= &iwl5000_ops
,
1579 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1580 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1581 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1582 .mod_params
= &iwl50_mod_params
,
1583 .valid_tx_ant
= ANT_B
,
1584 .valid_rx_ant
= ANT_AB
,
1585 .need_pll_cfg
= true,
1588 struct iwl_cfg iwl5100_agn_cfg
= {
1590 .fw_name_pre
= IWL5000_FW_PRE
,
1591 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1592 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1593 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1594 .ops
= &iwl5000_ops
,
1595 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1596 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1597 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1598 .mod_params
= &iwl50_mod_params
,
1599 .valid_tx_ant
= ANT_B
,
1600 .valid_rx_ant
= ANT_AB
,
1601 .need_pll_cfg
= true,
1604 struct iwl_cfg iwl5350_agn_cfg
= {
1606 .fw_name_pre
= IWL5000_FW_PRE
,
1607 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1608 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1609 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1610 .ops
= &iwl5000_ops
,
1611 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1612 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1613 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1614 .mod_params
= &iwl50_mod_params
,
1615 .valid_tx_ant
= ANT_ABC
,
1616 .valid_rx_ant
= ANT_ABC
,
1617 .need_pll_cfg
= true,
1620 struct iwl_cfg iwl5150_agn_cfg
= {
1622 .fw_name_pre
= IWL5150_FW_PRE
,
1623 .ucode_api_max
= IWL5150_UCODE_API_MAX
,
1624 .ucode_api_min
= IWL5150_UCODE_API_MIN
,
1625 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1626 .ops
= &iwl5000_ops
,
1627 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1628 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1629 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1630 .mod_params
= &iwl50_mod_params
,
1631 .valid_tx_ant
= ANT_A
,
1632 .valid_rx_ant
= ANT_AB
,
1633 .need_pll_cfg
= true,
1636 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX
));
1637 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX
));
1639 module_param_named(disable50
, iwl50_mod_params
.disable
, int, 0444);
1640 MODULE_PARM_DESC(disable50
,
1641 "manually disable the 50XX radio (default 0 [radio on])");
1642 module_param_named(swcrypto50
, iwl50_mod_params
.sw_crypto
, bool, 0444);
1643 MODULE_PARM_DESC(swcrypto50
,
1644 "using software crypto engine (default 0 [hardware])\n");
1645 module_param_named(debug50
, iwl50_mod_params
.debug
, uint
, 0444);
1646 MODULE_PARM_DESC(debug50
, "50XX debug output mask");
1647 module_param_named(queues_num50
, iwl50_mod_params
.num_of_queues
, int, 0444);
1648 MODULE_PARM_DESC(queues_num50
, "number of hw queues in 50xx series");
1649 module_param_named(11n_disable50
, iwl50_mod_params
.disable_11n
, int, 0444);
1650 MODULE_PARM_DESC(11n_disable50
, "disable 50XX 11n functionality");
1651 module_param_named(amsdu_size_8K50
, iwl50_mod_params
.amsdu_size_8K
, int, 0444);
1652 MODULE_PARM_DESC(amsdu_size_8K50
, "enable 8K amsdu size in 50XX series");
1653 module_param_named(fw_restart50
, iwl50_mod_params
.restart_fw
, int, 0444);
1654 MODULE_PARM_DESC(fw_restart50
, "restart firmware in case of error");