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iwlwifi: setup correctly L1 L0S pi link values
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/version.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46
47 #define IWL5000_UCODE_API "-1"
48
49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
50 IWL_TX_FIFO_AC3,
51 IWL_TX_FIFO_AC2,
52 IWL_TX_FIFO_AC1,
53 IWL_TX_FIFO_AC0,
54 IWL50_CMD_FIFO_NUM,
55 IWL_TX_FIFO_HCCA_1,
56 IWL_TX_FIFO_HCCA_2
57 };
58
59 static int iwl5000_apm_init(struct iwl_priv *priv)
60 {
61 int ret = 0;
62
63 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
64 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
65
66 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
67 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
68 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
69
70 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
71
72 /* set "initialization complete" bit to move adapter
73 * D0U* --> D0A* state */
74 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
75
76 /* wait for clock stabilization */
77 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
78 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
79 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
80 if (ret < 0) {
81 IWL_DEBUG_INFO("Failed to init the card\n");
82 return ret;
83 }
84
85 ret = iwl_grab_nic_access(priv);
86 if (ret)
87 return ret;
88
89 /* enable DMA */
90 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
91
92 udelay(20);
93
94 /* disable L1-Active */
95 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
96 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
97
98 iwl_release_nic_access(priv);
99
100 return ret;
101 }
102
103 static void iwl5000_nic_config(struct iwl_priv *priv)
104 {
105 unsigned long flags;
106 u16 radio_cfg;
107 u8 val_link;
108
109 spin_lock_irqsave(&priv->lock, flags);
110
111 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
112
113 /* L1 is enabled by BIOS */
114 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
115 /* diable L0S disabled L1A enabled */
116 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
117 else
118 /* L0S enabled L1A disabled */
119 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
120
121 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
122
123 /* write radio config values to register */
124 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
125 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
126 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
127 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
128 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
129
130 /* set CSR_HW_CONFIG_REG for uCode use */
131 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
132 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
133 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
134
135 spin_unlock_irqrestore(&priv->lock, flags);
136 }
137
138
139
140 /*
141 * EEPROM
142 */
143 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
144 {
145 u16 offset = 0;
146
147 if ((address & INDIRECT_ADDRESS) == 0)
148 return address;
149
150 switch (address & INDIRECT_TYPE_MSK) {
151 case INDIRECT_HOST:
152 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
153 break;
154 case INDIRECT_GENERAL:
155 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
156 break;
157 case INDIRECT_REGULATORY:
158 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
159 break;
160 case INDIRECT_CALIBRATION:
161 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
162 break;
163 case INDIRECT_PROCESS_ADJST:
164 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
165 break;
166 case INDIRECT_OTHERS:
167 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
168 break;
169 default:
170 IWL_ERROR("illegal indirect type: 0x%X\n",
171 address & INDIRECT_TYPE_MSK);
172 break;
173 }
174
175 /* translate the offset from words to byte */
176 return (address & ADDRESS_MSK) + (offset << 1);
177 }
178
179 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
180 {
181 u16 eeprom_ver;
182 struct iwl_eeprom_calib_hdr {
183 u8 version;
184 u8 pa_type;
185 u16 voltage;
186 } *hdr;
187
188 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
189
190 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
191 EEPROM_5000_CALIB_ALL);
192
193 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
194 hdr->version < EEPROM_5000_TX_POWER_VERSION)
195 goto err;
196
197 return 0;
198 err:
199 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
200 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
201 hdr->version, EEPROM_5000_TX_POWER_VERSION);
202 return -EINVAL;
203
204 }
205
206 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
207
208 static void iwl5000_gain_computation(struct iwl_priv *priv,
209 u32 average_noise[NUM_RX_CHAINS],
210 u16 min_average_noise_antenna_i,
211 u32 min_average_noise)
212 {
213 int i;
214 s32 delta_g;
215 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
216
217 /* Find Gain Code for the antennas B and C */
218 for (i = 1; i < NUM_RX_CHAINS; i++) {
219 if ((data->disconn_array[i])) {
220 data->delta_gain_code[i] = 0;
221 continue;
222 }
223 delta_g = (1000 * ((s32)average_noise[0] -
224 (s32)average_noise[i])) / 1500;
225 /* bound gain by 2 bits value max, 3rd bit is sign */
226 data->delta_gain_code[i] =
227 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
228
229 if (delta_g < 0)
230 /* set negative sign */
231 data->delta_gain_code[i] |= (1 << 2);
232 }
233
234 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
235 data->delta_gain_code[1], data->delta_gain_code[2]);
236
237 if (!data->radio_write) {
238 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
239 memset(&cmd, 0, sizeof(cmd));
240
241 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
242 cmd.delta_gain_1 = data->delta_gain_code[1];
243 cmd.delta_gain_2 = data->delta_gain_code[2];
244 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
245 sizeof(cmd), &cmd, NULL);
246
247 data->radio_write = 1;
248 data->state = IWL_CHAIN_NOISE_CALIBRATED;
249 }
250
251 data->chain_noise_a = 0;
252 data->chain_noise_b = 0;
253 data->chain_noise_c = 0;
254 data->chain_signal_a = 0;
255 data->chain_signal_b = 0;
256 data->chain_signal_c = 0;
257 data->beacon_count = 0;
258 }
259
260
261 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
262 {
263 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
264
265 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
266 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
267
268 memset(&cmd, 0, sizeof(cmd));
269 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
270 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
271 sizeof(cmd), &cmd))
272 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
273 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
274 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
275 }
276 }
277
278 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
279 .min_nrg_cck = 95,
280 .max_nrg_cck = 0,
281 .auto_corr_min_ofdm = 90,
282 .auto_corr_min_ofdm_mrc = 170,
283 .auto_corr_min_ofdm_x1 = 120,
284 .auto_corr_min_ofdm_mrc_x1 = 240,
285
286 .auto_corr_max_ofdm = 120,
287 .auto_corr_max_ofdm_mrc = 210,
288 .auto_corr_max_ofdm_x1 = 155,
289 .auto_corr_max_ofdm_mrc_x1 = 290,
290
291 .auto_corr_min_cck = 125,
292 .auto_corr_max_cck = 200,
293 .auto_corr_min_cck_mrc = 170,
294 .auto_corr_max_cck_mrc = 400,
295 .nrg_th_cck = 95,
296 .nrg_th_ofdm = 95,
297 };
298
299 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
300
301 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
302 size_t offset)
303 {
304 u32 address = eeprom_indirect_address(priv, offset);
305 BUG_ON(address >= priv->cfg->eeprom_size);
306 return &priv->eeprom[address];
307 }
308
309 /*
310 * ucode
311 */
312 static int iwl5000_load_section(struct iwl_priv *priv,
313 struct fw_desc *image,
314 u32 dst_addr)
315 {
316 int ret = 0;
317 unsigned long flags;
318
319 dma_addr_t phy_addr = image->p_addr;
320 u32 byte_cnt = image->len;
321
322 spin_lock_irqsave(&priv->lock, flags);
323 ret = iwl_grab_nic_access(priv);
324 if (ret) {
325 spin_unlock_irqrestore(&priv->lock, flags);
326 return ret;
327 }
328
329 iwl_write_direct32(priv,
330 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
331 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
332
333 iwl_write_direct32(priv,
334 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
335
336 iwl_write_direct32(priv,
337 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
338 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
339
340 /* FIME: write the MSB of the phy_addr in CTRL1
341 * iwl_write_direct32(priv,
342 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
343 ((phy_addr & MSB_MSK)
344 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
345 */
346 iwl_write_direct32(priv,
347 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
348 iwl_write_direct32(priv,
349 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
350 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
351 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
352 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
353
354 iwl_write_direct32(priv,
355 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
356 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
357 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
358 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
359
360 iwl_release_nic_access(priv);
361 spin_unlock_irqrestore(&priv->lock, flags);
362 return 0;
363 }
364
365 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
366 struct fw_desc *inst_image,
367 struct fw_desc *data_image)
368 {
369 int ret = 0;
370
371 ret = iwl5000_load_section(
372 priv, inst_image, RTC_INST_LOWER_BOUND);
373 if (ret)
374 return ret;
375
376 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
377 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
378 priv->ucode_write_complete, 5 * HZ);
379 if (ret == -ERESTARTSYS) {
380 IWL_ERROR("Could not load the INST uCode section due "
381 "to interrupt\n");
382 return ret;
383 }
384 if (!ret) {
385 IWL_ERROR("Could not load the INST uCode section\n");
386 return -ETIMEDOUT;
387 }
388
389 priv->ucode_write_complete = 0;
390
391 ret = iwl5000_load_section(
392 priv, data_image, RTC_DATA_LOWER_BOUND);
393 if (ret)
394 return ret;
395
396 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
397
398 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
399 priv->ucode_write_complete, 5 * HZ);
400 if (ret == -ERESTARTSYS) {
401 IWL_ERROR("Could not load the INST uCode section due "
402 "to interrupt\n");
403 return ret;
404 } else if (!ret) {
405 IWL_ERROR("Could not load the DATA uCode section\n");
406 return -ETIMEDOUT;
407 } else
408 ret = 0;
409
410 priv->ucode_write_complete = 0;
411
412 return ret;
413 }
414
415 static int iwl5000_load_ucode(struct iwl_priv *priv)
416 {
417 int ret = 0;
418
419 /* check whether init ucode should be loaded, or rather runtime ucode */
420 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
421 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
422 ret = iwl5000_load_given_ucode(priv,
423 &priv->ucode_init, &priv->ucode_init_data);
424 if (!ret) {
425 IWL_DEBUG_INFO("Init ucode load complete.\n");
426 priv->ucode_type = UCODE_INIT;
427 }
428 } else {
429 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
430 "Loading runtime ucode...\n");
431 ret = iwl5000_load_given_ucode(priv,
432 &priv->ucode_code, &priv->ucode_data);
433 if (!ret) {
434 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
435 priv->ucode_type = UCODE_RT;
436 }
437 }
438
439 return ret;
440 }
441
442 static void iwl5000_init_alive_start(struct iwl_priv *priv)
443 {
444 int ret = 0;
445
446 /* Check alive response for "valid" sign from uCode */
447 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
448 /* We had an error bringing up the hardware, so take it
449 * all the way back down so we can try again */
450 IWL_DEBUG_INFO("Initialize Alive failed.\n");
451 goto restart;
452 }
453
454 /* initialize uCode was loaded... verify inst image.
455 * This is a paranoid check, because we would not have gotten the
456 * "initialize" alive if code weren't properly loaded. */
457 if (iwl_verify_ucode(priv)) {
458 /* Runtime instruction load was bad;
459 * take it all the way back down so we can try again */
460 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
461 goto restart;
462 }
463
464 iwlcore_clear_stations_table(priv);
465 ret = priv->cfg->ops->lib->alive_notify(priv);
466 if (ret) {
467 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
468 goto restart;
469 }
470
471 return;
472
473 restart:
474 /* real restart (first load init_ucode) */
475 queue_work(priv->workqueue, &priv->restart);
476 }
477
478 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
479 int txq_id, u32 index)
480 {
481 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
482 (index & 0xff) | (txq_id << 8));
483 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
484 }
485
486 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
487 struct iwl_tx_queue *txq,
488 int tx_fifo_id, int scd_retry)
489 {
490 int txq_id = txq->q.id;
491 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
492
493 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
494 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
495 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
496 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
497 IWL50_SCD_QUEUE_STTS_REG_MSK);
498
499 txq->sched_retry = scd_retry;
500
501 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
502 active ? "Activate" : "Deactivate",
503 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
504 }
505
506 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
507 {
508 struct iwl_wimax_coex_cmd coex_cmd;
509
510 memset(&coex_cmd, 0, sizeof(coex_cmd));
511
512 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
513 sizeof(coex_cmd), &coex_cmd);
514 }
515
516 static int iwl5000_alive_notify(struct iwl_priv *priv)
517 {
518 u32 a;
519 int i = 0;
520 unsigned long flags;
521 int ret;
522
523 spin_lock_irqsave(&priv->lock, flags);
524
525 ret = iwl_grab_nic_access(priv);
526 if (ret) {
527 spin_unlock_irqrestore(&priv->lock, flags);
528 return ret;
529 }
530
531 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
532 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
533 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
534 a += 4)
535 iwl_write_targ_mem(priv, a, 0);
536 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
537 a += 4)
538 iwl_write_targ_mem(priv, a, 0);
539 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
540 iwl_write_targ_mem(priv, a, 0);
541
542 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
543 (priv->shared_phys +
544 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
545 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
546 IWL50_SCD_QUEUECHAIN_SEL_ALL(
547 priv->hw_params.max_txq_num));
548 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
549
550 /* initiate the queues */
551 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
552 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
553 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
554 iwl_write_targ_mem(priv, priv->scd_base_addr +
555 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
556 iwl_write_targ_mem(priv, priv->scd_base_addr +
557 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
558 sizeof(u32),
559 ((SCD_WIN_SIZE <<
560 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
561 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
562 ((SCD_FRAME_LIMIT <<
563 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
564 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
565 }
566
567 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
568 (1 << priv->hw_params.max_txq_num) - 1);
569
570 iwl_write_prph(priv, IWL50_SCD_TXFACT,
571 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
572
573 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
574 /* map qos queues to fifos one-to-one */
575 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
576 int ac = iwl5000_default_queue_to_tx_fifo[i];
577 iwl_txq_ctx_activate(priv, i);
578 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
579 }
580 /* TODO - need to initialize those FIFOs inside the loop above,
581 * not only mark them as active */
582 iwl_txq_ctx_activate(priv, 4);
583 iwl_txq_ctx_activate(priv, 7);
584 iwl_txq_ctx_activate(priv, 8);
585 iwl_txq_ctx_activate(priv, 9);
586
587 iwl_release_nic_access(priv);
588 spin_unlock_irqrestore(&priv->lock, flags);
589
590 iwl5000_send_wimax_coex(priv);
591
592 return 0;
593 }
594
595 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
596 {
597 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
598 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
599 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
600 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
601 return -EINVAL;
602 }
603
604 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
605 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
606 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
607 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
608 if (priv->cfg->mod_params->amsdu_size_8K)
609 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
610 else
611 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
612 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
613 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
614 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
615 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
616 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
617 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
618 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
619 BIT(IEEE80211_BAND_5GHZ);
620 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
621 priv->hw_params.sens = &iwl5000_sensitivity;
622 #endif
623
624 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
625 case CSR_HW_REV_TYPE_5100:
626 case CSR_HW_REV_TYPE_5150:
627 priv->hw_params.tx_chains_num = 1;
628 priv->hw_params.rx_chains_num = 2;
629 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
630 priv->hw_params.valid_tx_ant = ANT_A;
631 priv->hw_params.valid_rx_ant = ANT_AB;
632 break;
633 case CSR_HW_REV_TYPE_5300:
634 case CSR_HW_REV_TYPE_5350:
635 priv->hw_params.tx_chains_num = 3;
636 priv->hw_params.rx_chains_num = 3;
637 priv->hw_params.valid_tx_ant = ANT_ABC;
638 priv->hw_params.valid_rx_ant = ANT_ABC;
639 break;
640 }
641
642 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
643 case CSR_HW_REV_TYPE_5100:
644 case CSR_HW_REV_TYPE_5300:
645 /* 5X00 wants in Celsius */
646 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
647 break;
648 case CSR_HW_REV_TYPE_5150:
649 case CSR_HW_REV_TYPE_5350:
650 /* 5X50 wants in Kelvin */
651 priv->hw_params.ct_kill_threshold =
652 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
653 break;
654 }
655
656 return 0;
657 }
658
659 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
660 {
661 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
662 sizeof(struct iwl5000_shared),
663 &priv->shared_phys);
664 if (!priv->shared_virt)
665 return -ENOMEM;
666
667 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
668
669 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
670
671 return 0;
672 }
673
674 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
675 {
676 if (priv->shared_virt)
677 pci_free_consistent(priv->pci_dev,
678 sizeof(struct iwl5000_shared),
679 priv->shared_virt,
680 priv->shared_phys);
681 }
682
683 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
684 {
685 struct iwl5000_shared *s = priv->shared_virt;
686 return le32_to_cpu(s->rb_closed) & 0xFFF;
687 }
688
689 /**
690 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
691 */
692 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
693 struct iwl_tx_queue *txq,
694 u16 byte_cnt)
695 {
696 struct iwl5000_shared *shared_data = priv->shared_virt;
697 int txq_id = txq->q.id;
698 u8 sec_ctl = 0;
699 u8 sta = 0;
700 int len;
701
702 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
703
704 if (txq_id != IWL_CMD_QUEUE_NUM) {
705 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
706 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
707
708 switch (sec_ctl & TX_CMD_SEC_MSK) {
709 case TX_CMD_SEC_CCM:
710 len += CCMP_MIC_LEN;
711 break;
712 case TX_CMD_SEC_TKIP:
713 len += TKIP_ICV_LEN;
714 break;
715 case TX_CMD_SEC_WEP:
716 len += WEP_IV_LEN + WEP_ICV_LEN;
717 break;
718 }
719 }
720
721 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
722 tfd_offset[txq->q.write_ptr], byte_cnt, len);
723
724 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
725 tfd_offset[txq->q.write_ptr], sta_id, sta);
726
727 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
728 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
729 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
730 byte_cnt, len);
731 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
732 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
733 sta_id, sta);
734 }
735 }
736
737 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
738 {
739 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
740 memcpy(data, cmd, size);
741 return size;
742 }
743
744
745 static int iwl5000_disable_tx_fifo(struct iwl_priv *priv)
746 {
747 unsigned long flags;
748 int ret;
749
750 spin_lock_irqsave(&priv->lock, flags);
751
752 ret = iwl_grab_nic_access(priv);
753 if (unlikely(ret)) {
754 IWL_ERROR("Tx fifo reset failed");
755 spin_unlock_irqrestore(&priv->lock, flags);
756 return ret;
757 }
758
759 iwl_write_prph(priv, IWL50_SCD_TXFACT, 0);
760 iwl_release_nic_access(priv);
761 spin_unlock_irqrestore(&priv->lock, flags);
762
763 return 0;
764 }
765
766 /* Currently 5000 is the supperset of everything */
767 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
768 {
769 return len;
770 }
771
772 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
773 {
774 }
775
776 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
777 {
778 return (addr >= RTC_DATA_LOWER_BOUND) &&
779 (addr < IWL50_RTC_DATA_UPPER_BOUND);
780 }
781
782 static struct iwl_hcmd_ops iwl5000_hcmd = {
783 };
784
785 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
786 .get_hcmd_size = iwl5000_get_hcmd_size,
787 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
788 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
789 .gain_computation = iwl5000_gain_computation,
790 .chain_noise_reset = iwl5000_chain_noise_reset,
791 #endif
792 };
793
794 static struct iwl_lib_ops iwl5000_lib = {
795 .set_hw_params = iwl5000_hw_set_hw_params,
796 .alloc_shared_mem = iwl5000_alloc_shared_mem,
797 .free_shared_mem = iwl5000_free_shared_mem,
798 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
799 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
800 .disable_tx_fifo = iwl5000_disable_tx_fifo,
801 .rx_handler_setup = iwl5000_rx_handler_setup,
802 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
803 .load_ucode = iwl5000_load_ucode,
804 .init_alive_start = iwl5000_init_alive_start,
805 .alive_notify = iwl5000_alive_notify,
806 .apm_ops = {
807 .init = iwl5000_apm_init,
808 .config = iwl5000_nic_config,
809 .set_pwr_src = iwl4965_set_pwr_src,
810 },
811 .eeprom_ops = {
812 .regulatory_bands = {
813 EEPROM_5000_REG_BAND_1_CHANNELS,
814 EEPROM_5000_REG_BAND_2_CHANNELS,
815 EEPROM_5000_REG_BAND_3_CHANNELS,
816 EEPROM_5000_REG_BAND_4_CHANNELS,
817 EEPROM_5000_REG_BAND_5_CHANNELS,
818 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
819 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
820 },
821 .verify_signature = iwlcore_eeprom_verify_signature,
822 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
823 .release_semaphore = iwlcore_eeprom_release_semaphore,
824 .check_version = iwl5000_eeprom_check_version,
825 .query_addr = iwl5000_eeprom_query_addr,
826 },
827 };
828
829 static struct iwl_ops iwl5000_ops = {
830 .lib = &iwl5000_lib,
831 .hcmd = &iwl5000_hcmd,
832 .utils = &iwl5000_hcmd_utils,
833 };
834
835 static struct iwl_mod_params iwl50_mod_params = {
836 .num_of_queues = IWL50_NUM_QUEUES,
837 .enable_qos = 1,
838 .amsdu_size_8K = 1,
839 .restart_fw = 1,
840 /* the rest are 0 by default */
841 };
842
843
844 struct iwl_cfg iwl5300_agn_cfg = {
845 .name = "5300AGN",
846 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
847 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
848 .ops = &iwl5000_ops,
849 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
850 .mod_params = &iwl50_mod_params,
851 };
852
853 struct iwl_cfg iwl5100_agn_cfg = {
854 .name = "5100AGN",
855 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
856 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
857 .ops = &iwl5000_ops,
858 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
859 .mod_params = &iwl50_mod_params,
860 };
861
862 struct iwl_cfg iwl5350_agn_cfg = {
863 .name = "5350AGN",
864 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
865 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
866 .ops = &iwl5000_ops,
867 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
868 .mod_params = &iwl50_mod_params,
869 };
870
871 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
872 MODULE_PARM_DESC(disable50,
873 "manually disable the 50XX radio (default 0 [radio on])");
874 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
875 MODULE_PARM_DESC(swcrypto50,
876 "using software crypto engine (default 0 [hardware])\n");
877 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
878 MODULE_PARM_DESC(debug50, "50XX debug output mask");
879 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
880 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
881 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
882 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
883 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
884 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
885 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
886 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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