1 /******************************************************************************
3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
40 #include "iwl-eeprom.h"
45 #include "iwl-helpers.h"
46 #include "iwl-agn-led.h"
47 #include "iwl-5000-hw.h"
48 #include "iwl-6000-hw.h"
50 /* Highest firmware API version supported */
51 #define IWL5000_UCODE_API_MAX 2
52 #define IWL5150_UCODE_API_MAX 2
54 /* Lowest firmware API version supported */
55 #define IWL5000_UCODE_API_MIN 1
56 #define IWL5150_UCODE_API_MIN 1
58 #define IWL5000_FW_PRE "iwlwifi-5000-"
59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
62 #define IWL5150_FW_PRE "iwlwifi-5150-"
63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
66 static const u16 iwl5000_default_queue_to_tx_fifo
[] = {
76 /* NIC configuration for 5000 series */
77 void iwl5000_nic_config(struct iwl_priv
*priv
)
82 spin_lock_irqsave(&priv
->lock
, flags
);
84 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
86 /* write radio config values to register */
87 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) < EEPROM_RF_CONFIG_TYPE_MAX
)
88 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
89 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
90 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
91 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
93 /* set CSR_HW_CONFIG_REG for uCode use */
94 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
95 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
96 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);
98 /* W/A : NIC is stuck in a reset state after Early PCIe power off
99 * (PCIe power is lost before PERST# is asserted),
100 * causing ME FW to lose ownership and not being able to obtain it back.
102 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
103 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
,
104 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
);
107 spin_unlock_irqrestore(&priv
->lock
, flags
);
114 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
118 if ((address
& INDIRECT_ADDRESS
) == 0)
121 switch (address
& INDIRECT_TYPE_MSK
) {
123 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_HOST
);
125 case INDIRECT_GENERAL
:
126 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_GENERAL
);
128 case INDIRECT_REGULATORY
:
129 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_REGULATORY
);
131 case INDIRECT_CALIBRATION
:
132 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_CALIBRATION
);
134 case INDIRECT_PROCESS_ADJST
:
135 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_PROCESS_ADJST
);
137 case INDIRECT_OTHERS
:
138 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_OTHERS
);
141 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
142 address
& INDIRECT_TYPE_MSK
);
146 /* translate the offset from words to byte */
147 return (address
& ADDRESS_MSK
) + (offset
<< 1);
150 u16
iwl5000_eeprom_calib_version(struct iwl_priv
*priv
)
152 struct iwl_eeprom_calib_hdr
{
158 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
159 EEPROM_5000_CALIB_ALL
);
164 static void iwl5000_gain_computation(struct iwl_priv
*priv
,
165 u32 average_noise
[NUM_RX_CHAINS
],
166 u16 min_average_noise_antenna_i
,
167 u32 min_average_noise
,
172 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
175 * Find Gain Code for the chains based on "default chain"
177 for (i
= default_chain
+ 1; i
< NUM_RX_CHAINS
; i
++) {
178 if ((data
->disconn_array
[i
])) {
179 data
->delta_gain_code
[i
] = 0;
182 delta_g
= (1000 * ((s32
)average_noise
[default_chain
] -
183 (s32
)average_noise
[i
])) / 1500;
184 /* bound gain by 2 bits value max, 3rd bit is sign */
185 data
->delta_gain_code
[i
] =
186 min(abs(delta_g
), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE
);
189 /* set negative sign */
190 data
->delta_gain_code
[i
] |= (1 << 2);
193 IWL_DEBUG_CALIB(priv
, "Delta gains: ANT_B = %d ANT_C = %d\n",
194 data
->delta_gain_code
[1], data
->delta_gain_code
[2]);
196 if (!data
->radio_write
) {
197 struct iwl_calib_chain_noise_gain_cmd cmd
;
199 memset(&cmd
, 0, sizeof(cmd
));
201 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD
;
202 cmd
.hdr
.first_group
= 0;
203 cmd
.hdr
.groups_num
= 1;
204 cmd
.hdr
.data_valid
= 1;
205 cmd
.delta_gain_1
= data
->delta_gain_code
[1];
206 cmd
.delta_gain_2
= data
->delta_gain_code
[2];
207 iwl_send_cmd_pdu_async(priv
, REPLY_PHY_CALIBRATION_CMD
,
208 sizeof(cmd
), &cmd
, NULL
);
210 data
->radio_write
= 1;
211 data
->state
= IWL_CHAIN_NOISE_CALIBRATED
;
214 data
->chain_noise_a
= 0;
215 data
->chain_noise_b
= 0;
216 data
->chain_noise_c
= 0;
217 data
->chain_signal_a
= 0;
218 data
->chain_signal_b
= 0;
219 data
->chain_signal_c
= 0;
220 data
->beacon_count
= 0;
223 static void iwl5000_chain_noise_reset(struct iwl_priv
*priv
)
225 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
228 if ((data
->state
== IWL_CHAIN_NOISE_ALIVE
) && iwl_is_associated(priv
)) {
229 struct iwl_calib_chain_noise_reset_cmd cmd
;
230 memset(&cmd
, 0, sizeof(cmd
));
232 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD
;
233 cmd
.hdr
.first_group
= 0;
234 cmd
.hdr
.groups_num
= 1;
235 cmd
.hdr
.data_valid
= 1;
236 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
240 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
241 data
->state
= IWL_CHAIN_NOISE_ACCUMULATE
;
242 IWL_DEBUG_CALIB(priv
, "Run chain_noise_calibrate\n");
246 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info
*info
,
249 if ((info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ||
250 (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
))
251 *tx_flags
|= TX_CMD_FLG_RTS_CTS_MSK
;
253 *tx_flags
&= ~TX_CMD_FLG_RTS_CTS_MSK
;
256 static struct iwl_sensitivity_ranges iwl5000_sensitivity
= {
258 .max_nrg_cck
= 0, /* not used, set to 0 */
259 .auto_corr_min_ofdm
= 90,
260 .auto_corr_min_ofdm_mrc
= 170,
261 .auto_corr_min_ofdm_x1
= 120,
262 .auto_corr_min_ofdm_mrc_x1
= 240,
264 .auto_corr_max_ofdm
= 120,
265 .auto_corr_max_ofdm_mrc
= 210,
266 .auto_corr_max_ofdm_x1
= 120,
267 .auto_corr_max_ofdm_mrc_x1
= 240,
269 .auto_corr_min_cck
= 125,
270 .auto_corr_max_cck
= 200,
271 .auto_corr_min_cck_mrc
= 170,
272 .auto_corr_max_cck_mrc
= 400,
276 .barker_corr_th_min
= 190,
277 .barker_corr_th_min_mrc
= 390,
281 static struct iwl_sensitivity_ranges iwl5150_sensitivity
= {
283 .max_nrg_cck
= 0, /* not used, set to 0 */
284 .auto_corr_min_ofdm
= 90,
285 .auto_corr_min_ofdm_mrc
= 170,
286 .auto_corr_min_ofdm_x1
= 105,
287 .auto_corr_min_ofdm_mrc_x1
= 220,
289 .auto_corr_max_ofdm
= 120,
290 .auto_corr_max_ofdm_mrc
= 210,
291 /* max = min for performance bug in 5150 DSP */
292 .auto_corr_max_ofdm_x1
= 105,
293 .auto_corr_max_ofdm_mrc_x1
= 220,
295 .auto_corr_min_cck
= 125,
296 .auto_corr_max_cck
= 200,
297 .auto_corr_min_cck_mrc
= 170,
298 .auto_corr_max_cck_mrc
= 400,
302 .barker_corr_th_min
= 190,
303 .barker_corr_th_min_mrc
= 390,
307 const u8
*iwl5000_eeprom_query_addr(const struct iwl_priv
*priv
,
310 u32 address
= eeprom_indirect_address(priv
, offset
);
311 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
312 return &priv
->eeprom
[address
];
315 static void iwl5150_set_ct_threshold(struct iwl_priv
*priv
)
317 const s32 volt2temp_coef
= IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF
;
318 s32 threshold
= (s32
)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY
) -
319 iwl_temp_calib_to_offset(priv
);
321 priv
->hw_params
.ct_kill_threshold
= threshold
* volt2temp_coef
;
324 static void iwl5000_set_ct_threshold(struct iwl_priv
*priv
)
327 priv
->hw_params
.ct_kill_threshold
= CT_KILL_THRESHOLD_LEGACY
;
333 static int iwl5000_set_Xtal_calib(struct iwl_priv
*priv
)
335 struct iwl_calib_xtal_freq_cmd cmd
;
337 (__le16
*)iwl_eeprom_query_addr(priv
, EEPROM_5000_XTAL
);
339 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
;
340 cmd
.hdr
.first_group
= 0;
341 cmd
.hdr
.groups_num
= 1;
342 cmd
.hdr
.data_valid
= 1;
343 cmd
.cap_pin1
= le16_to_cpu(xtal_calib
[0]);
344 cmd
.cap_pin2
= le16_to_cpu(xtal_calib
[1]);
345 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_XTAL
],
346 (u8
*)&cmd
, sizeof(cmd
));
349 static int iwl5000_send_calib_cfg(struct iwl_priv
*priv
)
351 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
352 struct iwl_host_cmd cmd
= {
353 .id
= CALIBRATION_CFG_CMD
,
354 .len
= sizeof(struct iwl_calib_cfg_cmd
),
355 .data
= &calib_cfg_cmd
,
358 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
359 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
360 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
361 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
362 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
364 return iwl_send_cmd(priv
, &cmd
);
367 static void iwl5000_rx_calib_result(struct iwl_priv
*priv
,
368 struct iwl_rx_mem_buffer
*rxb
)
370 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
371 struct iwl_calib_hdr
*hdr
= (struct iwl_calib_hdr
*)pkt
->u
.raw
;
372 int len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
375 /* reduce the size of the length field itself */
378 /* Define the order in which the results will be sent to the runtime
379 * uCode. iwl_send_calib_results sends them in a row according to their
380 * index. We sort them here */
381 switch (hdr
->op_code
) {
382 case IWL_PHY_CALIBRATE_DC_CMD
:
383 index
= IWL_CALIB_DC
;
385 case IWL_PHY_CALIBRATE_LO_CMD
:
386 index
= IWL_CALIB_LO
;
388 case IWL_PHY_CALIBRATE_TX_IQ_CMD
:
389 index
= IWL_CALIB_TX_IQ
;
391 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
392 index
= IWL_CALIB_TX_IQ_PERD
;
394 case IWL_PHY_CALIBRATE_BASE_BAND_CMD
:
395 index
= IWL_CALIB_BASE_BAND
;
398 IWL_ERR(priv
, "Unknown calibration notification %d\n",
402 iwl_calib_set(&priv
->calib_results
[index
], pkt
->u
.raw
, len
);
405 static void iwl5000_rx_calib_complete(struct iwl_priv
*priv
,
406 struct iwl_rx_mem_buffer
*rxb
)
408 IWL_DEBUG_INFO(priv
, "Init. calibration is completed, restarting fw.\n");
409 queue_work(priv
->workqueue
, &priv
->restart
);
415 static int iwl5000_load_section(struct iwl_priv
*priv
, const char *name
,
416 struct fw_desc
*image
, u32 dst_addr
)
418 dma_addr_t phy_addr
= image
->p_addr
;
419 u32 byte_cnt
= image
->len
;
422 priv
->ucode_write_complete
= 0;
424 iwl_write_direct32(priv
,
425 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
426 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
428 iwl_write_direct32(priv
,
429 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
431 iwl_write_direct32(priv
,
432 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
433 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
435 iwl_write_direct32(priv
,
436 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
437 (iwl_get_dma_hi_addr(phy_addr
)
438 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
440 iwl_write_direct32(priv
,
441 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
442 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
443 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
444 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
446 iwl_write_direct32(priv
,
447 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
448 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
449 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
450 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
452 IWL_DEBUG_INFO(priv
, "%s uCode section being loaded...\n", name
);
453 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
454 priv
->ucode_write_complete
, 5 * HZ
);
455 if (ret
== -ERESTARTSYS
) {
456 IWL_ERR(priv
, "Could not load the %s uCode section due "
457 "to interrupt\n", name
);
461 IWL_ERR(priv
, "Could not load the %s uCode section\n",
469 static int iwl5000_load_given_ucode(struct iwl_priv
*priv
,
470 struct fw_desc
*inst_image
,
471 struct fw_desc
*data_image
)
475 ret
= iwl5000_load_section(priv
, "INST", inst_image
,
476 IWL50_RTC_INST_LOWER_BOUND
);
480 return iwl5000_load_section(priv
, "DATA", data_image
,
481 IWL50_RTC_DATA_LOWER_BOUND
);
484 int iwl5000_load_ucode(struct iwl_priv
*priv
)
488 /* check whether init ucode should be loaded, or rather runtime ucode */
489 if (priv
->ucode_init
.len
&& (priv
->ucode_type
== UCODE_NONE
)) {
490 IWL_DEBUG_INFO(priv
, "Init ucode found. Loading init ucode...\n");
491 ret
= iwl5000_load_given_ucode(priv
,
492 &priv
->ucode_init
, &priv
->ucode_init_data
);
494 IWL_DEBUG_INFO(priv
, "Init ucode load complete.\n");
495 priv
->ucode_type
= UCODE_INIT
;
498 IWL_DEBUG_INFO(priv
, "Init ucode not found, or already loaded. "
499 "Loading runtime ucode...\n");
500 ret
= iwl5000_load_given_ucode(priv
,
501 &priv
->ucode_code
, &priv
->ucode_data
);
503 IWL_DEBUG_INFO(priv
, "Runtime ucode load complete.\n");
504 priv
->ucode_type
= UCODE_RT
;
511 void iwl5000_init_alive_start(struct iwl_priv
*priv
)
515 /* Check alive response for "valid" sign from uCode */
516 if (priv
->card_alive_init
.is_valid
!= UCODE_VALID_OK
) {
517 /* We had an error bringing up the hardware, so take it
518 * all the way back down so we can try again */
519 IWL_DEBUG_INFO(priv
, "Initialize Alive failed.\n");
523 /* initialize uCode was loaded... verify inst image.
524 * This is a paranoid check, because we would not have gotten the
525 * "initialize" alive if code weren't properly loaded. */
526 if (iwl_verify_ucode(priv
)) {
527 /* Runtime instruction load was bad;
528 * take it all the way back down so we can try again */
529 IWL_DEBUG_INFO(priv
, "Bad \"initialize\" uCode load.\n");
533 iwl_clear_stations_table(priv
);
534 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
537 "Could not complete ALIVE transition: %d\n", ret
);
541 iwl5000_send_calib_cfg(priv
);
545 /* real restart (first load init_ucode) */
546 queue_work(priv
->workqueue
, &priv
->restart
);
549 static void iwl5000_set_wr_ptrs(struct iwl_priv
*priv
,
550 int txq_id
, u32 index
)
552 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
553 (index
& 0xff) | (txq_id
<< 8));
554 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(txq_id
), index
);
557 static void iwl5000_tx_queue_set_status(struct iwl_priv
*priv
,
558 struct iwl_tx_queue
*txq
,
559 int tx_fifo_id
, int scd_retry
)
561 int txq_id
= txq
->q
.id
;
562 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
) ? 1 : 0;
564 iwl_write_prph(priv
, IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
565 (active
<< IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
566 (tx_fifo_id
<< IWL50_SCD_QUEUE_STTS_REG_POS_TXF
) |
567 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL
) |
568 IWL50_SCD_QUEUE_STTS_REG_MSK
);
570 txq
->sched_retry
= scd_retry
;
572 IWL_DEBUG_INFO(priv
, "%s %s Queue %d on AC %d\n",
573 active
? "Activate" : "Deactivate",
574 scd_retry
? "BA" : "AC", txq_id
, tx_fifo_id
);
577 int iwl5000_alive_notify(struct iwl_priv
*priv
)
584 spin_lock_irqsave(&priv
->lock
, flags
);
586 priv
->scd_base_addr
= iwl_read_prph(priv
, IWL50_SCD_SRAM_BASE_ADDR
);
587 a
= priv
->scd_base_addr
+ IWL50_SCD_CONTEXT_DATA_OFFSET
;
588 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TX_STTS_BITMAP_OFFSET
;
590 iwl_write_targ_mem(priv
, a
, 0);
591 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TRANSLATE_TBL_OFFSET
;
593 iwl_write_targ_mem(priv
, a
, 0);
594 for (; a
< priv
->scd_base_addr
+
595 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv
->hw_params
.max_txq_num
); a
+= 4)
596 iwl_write_targ_mem(priv
, a
, 0);
598 iwl_write_prph(priv
, IWL50_SCD_DRAM_BASE_ADDR
,
599 priv
->scd_bc_tbls
.dma
>> 10);
601 /* Enable DMA channel */
602 for (chan
= 0; chan
< FH50_TCSR_CHNL_NUM
; chan
++)
603 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
604 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
605 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
607 /* Update FH chicken bits */
608 reg_val
= iwl_read_direct32(priv
, FH_TX_CHICKEN_BITS_REG
);
609 iwl_write_direct32(priv
, FH_TX_CHICKEN_BITS_REG
,
610 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
612 iwl_write_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
,
613 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv
->hw_params
.max_txq_num
));
614 iwl_write_prph(priv
, IWL50_SCD_AGGR_SEL
, 0);
616 /* initiate the queues */
617 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++) {
618 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(i
), 0);
619 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
620 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
621 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
622 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
623 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
) +
626 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
627 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
629 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
630 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
633 iwl_write_prph(priv
, IWL50_SCD_INTERRUPT_MASK
,
634 IWL_MASK(0, priv
->hw_params
.max_txq_num
));
636 /* Activate all Tx DMA/FIFO channels */
637 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, IWL_MASK(0, 7));
639 iwl5000_set_wr_ptrs(priv
, IWL_CMD_QUEUE_NUM
, 0);
641 /* map qos queues to fifos one-to-one */
642 for (i
= 0; i
< ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo
); i
++) {
643 int ac
= iwl5000_default_queue_to_tx_fifo
[i
];
644 iwl_txq_ctx_activate(priv
, i
);
645 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[i
], ac
, 0);
649 * TODO - need to initialize these queues and map them to FIFOs
650 * in the loop above, not only mark them as active. We do this
651 * because we want the first aggregation queue to be queue #10,
652 * but do not use 8 or 9 otherwise yet.
654 iwl_txq_ctx_activate(priv
, 7);
655 iwl_txq_ctx_activate(priv
, 8);
656 iwl_txq_ctx_activate(priv
, 9);
658 spin_unlock_irqrestore(&priv
->lock
, flags
);
661 iwl_send_wimax_coex(priv
);
663 iwl5000_set_Xtal_calib(priv
);
664 iwl_send_calib_results(priv
);
669 int iwl5000_hw_set_hw_params(struct iwl_priv
*priv
)
671 if (priv
->cfg
->mod_params
->num_of_queues
>= IWL_MIN_NUM_QUEUES
&&
672 priv
->cfg
->mod_params
->num_of_queues
<= IWL50_NUM_QUEUES
)
673 priv
->cfg
->num_of_queues
=
674 priv
->cfg
->mod_params
->num_of_queues
;
676 priv
->hw_params
.max_txq_num
= priv
->cfg
->num_of_queues
;
677 priv
->hw_params
.dma_chnl_num
= FH50_TCSR_CHNL_NUM
;
678 priv
->hw_params
.scd_bc_tbls_size
=
679 priv
->cfg
->num_of_queues
*
680 sizeof(struct iwl5000_scd_bc_tbl
);
681 priv
->hw_params
.tfd_size
= sizeof(struct iwl_tfd
);
682 priv
->hw_params
.max_stations
= IWL5000_STATION_COUNT
;
683 priv
->hw_params
.bcast_sta_id
= IWL5000_BROADCAST_ID
;
685 priv
->hw_params
.max_data_size
= IWL50_RTC_DATA_SIZE
;
686 priv
->hw_params
.max_inst_size
= IWL50_RTC_INST_SIZE
;
688 priv
->hw_params
.max_bsm_size
= 0;
689 priv
->hw_params
.ht40_channel
= BIT(IEEE80211_BAND_2GHZ
) |
690 BIT(IEEE80211_BAND_5GHZ
);
691 priv
->hw_params
.rx_wrt_ptr_reg
= FH_RSCSR_CHNL0_WPTR
;
693 priv
->hw_params
.tx_chains_num
= num_of_ant(priv
->cfg
->valid_tx_ant
);
694 priv
->hw_params
.rx_chains_num
= num_of_ant(priv
->cfg
->valid_rx_ant
);
695 priv
->hw_params
.valid_tx_ant
= priv
->cfg
->valid_tx_ant
;
696 priv
->hw_params
.valid_rx_ant
= priv
->cfg
->valid_rx_ant
;
698 if (priv
->cfg
->ops
->lib
->temp_ops
.set_ct_kill
)
699 priv
->cfg
->ops
->lib
->temp_ops
.set_ct_kill(priv
);
701 /* Set initial sensitivity parameters */
702 /* Set initial calibration set */
703 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
704 case CSR_HW_REV_TYPE_5150
:
705 priv
->hw_params
.sens
= &iwl5150_sensitivity
;
706 priv
->hw_params
.calib_init_cfg
=
709 BIT(IWL_CALIB_TX_IQ
) |
710 BIT(IWL_CALIB_BASE_BAND
);
714 priv
->hw_params
.sens
= &iwl5000_sensitivity
;
715 priv
->hw_params
.calib_init_cfg
=
716 BIT(IWL_CALIB_XTAL
) |
718 BIT(IWL_CALIB_TX_IQ
) |
719 BIT(IWL_CALIB_TX_IQ_PERD
) |
720 BIT(IWL_CALIB_BASE_BAND
);
728 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
730 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
731 struct iwl_tx_queue
*txq
,
734 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
735 int write_ptr
= txq
->q
.write_ptr
;
736 int txq_id
= txq
->q
.id
;
739 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
742 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
744 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
745 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
746 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
748 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
752 case TX_CMD_SEC_TKIP
:
756 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
761 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
763 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
765 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
767 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
770 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
771 struct iwl_tx_queue
*txq
)
773 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
774 int txq_id
= txq
->q
.id
;
775 int read_ptr
= txq
->q
.read_ptr
;
779 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
781 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
782 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
784 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
785 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
787 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
789 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
792 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv
*priv
, u16 ra_tid
,
799 scd_q2ratid
= ra_tid
& IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
801 tbl_dw_addr
= priv
->scd_base_addr
+
802 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id
);
804 tbl_dw
= iwl_read_targ_mem(priv
, tbl_dw_addr
);
807 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
809 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
811 iwl_write_targ_mem(priv
, tbl_dw_addr
, tbl_dw
);
815 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv
*priv
, u16 txq_id
)
817 /* Simply stop the queue, but don't change any configuration;
818 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
820 IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
821 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
822 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
825 int iwl5000_txq_agg_enable(struct iwl_priv
*priv
, int txq_id
,
826 int tx_fifo
, int sta_id
, int tid
, u16 ssn_idx
)
831 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
832 (IWL50_FIRST_AMPDU_QUEUE
+ priv
->cfg
->num_of_ampdu_queues
835 "queue number out of range: %d, must be %d to %d\n",
836 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
837 IWL50_FIRST_AMPDU_QUEUE
+
838 priv
->cfg
->num_of_ampdu_queues
- 1);
842 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
844 /* Modify device's station table to Tx this TID */
845 iwl_sta_tx_modify_enable_tid(priv
, sta_id
, tid
);
847 spin_lock_irqsave(&priv
->lock
, flags
);
849 /* Stop this Tx queue before configuring it */
850 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
852 /* Map receiver-address / traffic-ID to this queue */
853 iwl5000_tx_queue_set_q2ratid(priv
, ra_tid
, txq_id
);
855 /* Set this queue as a chain-building queue */
856 iwl_set_bits_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
858 /* enable aggregations for the queue */
859 iwl_set_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1<<txq_id
));
861 /* Place first TFD at index corresponding to start sequence number.
862 * Assumes that ssn_idx is valid (!= 0xFFF) */
863 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
864 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
865 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
867 /* Set up Tx window size and frame limit for this queue */
868 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
869 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
872 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
873 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
875 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
876 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
878 iwl_set_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
880 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
881 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 1);
883 spin_unlock_irqrestore(&priv
->lock
, flags
);
888 int iwl5000_txq_agg_disable(struct iwl_priv
*priv
, u16 txq_id
,
889 u16 ssn_idx
, u8 tx_fifo
)
891 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
892 (IWL50_FIRST_AMPDU_QUEUE
+ priv
->cfg
->num_of_ampdu_queues
895 "queue number out of range: %d, must be %d to %d\n",
896 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
897 IWL50_FIRST_AMPDU_QUEUE
+
898 priv
->cfg
->num_of_ampdu_queues
- 1);
902 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
904 iwl_clear_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1 << txq_id
));
906 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
907 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
908 /* supposes that ssn_idx is valid (!= 0xFFF) */
909 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
911 iwl_clear_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
912 iwl_txq_ctx_deactivate(priv
, txq_id
);
913 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 0);
918 u16
iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
920 u16 size
= (u16
)sizeof(struct iwl_addsta_cmd
);
921 struct iwl_addsta_cmd
*addsta
= (struct iwl_addsta_cmd
*)data
;
922 memcpy(addsta
, cmd
, size
);
923 /* resrved in 5000 */
924 addsta
->rate_n_flags
= cpu_to_le16(0);
930 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
931 * must be called under priv->lock and mac access
933 void iwl5000_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
935 iwl_write_prph(priv
, IWL50_SCD_TXFACT
, mask
);
939 static inline u32
iwl5000_get_scd_ssn(struct iwl5000_tx_resp
*tx_resp
)
941 return le32_to_cpup((__le32
*)&tx_resp
->status
+
942 tx_resp
->frame_count
) & MAX_SN
;
945 static int iwl5000_tx_status_reply_tx(struct iwl_priv
*priv
,
946 struct iwl_ht_agg
*agg
,
947 struct iwl5000_tx_resp
*tx_resp
,
948 int txq_id
, u16 start_idx
)
951 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
952 struct ieee80211_tx_info
*info
= NULL
;
953 struct ieee80211_hdr
*hdr
= NULL
;
954 u32 rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
958 if (agg
->wait_for_ba
)
959 IWL_DEBUG_TX_REPLY(priv
, "got tx response w/o block-ack\n");
961 agg
->frame_count
= tx_resp
->frame_count
;
962 agg
->start_idx
= start_idx
;
963 agg
->rate_n_flags
= rate_n_flags
;
966 /* # frames attempted by Tx command */
967 if (agg
->frame_count
== 1) {
968 /* Only one frame was attempted; no block-ack will arrive */
969 status
= le16_to_cpu(frame_status
[0].status
);
972 /* FIXME: code repetition */
973 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, StartIdx=%d idx=%d\n",
974 agg
->frame_count
, agg
->start_idx
, idx
);
976 info
= IEEE80211_SKB_CB(priv
->txq
[txq_id
].txb
[idx
].skb
[0]);
977 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
978 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
979 info
->flags
|= iwl_tx_status_to_mac80211(status
);
980 iwl_hwrate_to_tx_control(priv
, rate_n_flags
, info
);
982 /* FIXME: code repetition end */
984 IWL_DEBUG_TX_REPLY(priv
, "1 Frame 0x%x failure :%d\n",
985 status
& 0xff, tx_resp
->failure_frame
);
986 IWL_DEBUG_TX_REPLY(priv
, "Rate Info rate_n_flags=%x\n", rate_n_flags
);
988 agg
->wait_for_ba
= 0;
990 /* Two or more frames were attempted; expect block-ack */
992 int start
= agg
->start_idx
;
994 /* Construct bit-map of pending frames within Tx window */
995 for (i
= 0; i
< agg
->frame_count
; i
++) {
997 status
= le16_to_cpu(frame_status
[i
].status
);
998 seq
= le16_to_cpu(frame_status
[i
].sequence
);
999 idx
= SEQ_TO_INDEX(seq
);
1000 txq_id
= SEQ_TO_QUEUE(seq
);
1002 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
1003 AGG_TX_STATE_ABORT_MSK
))
1006 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, txq_id=%d idx=%d\n",
1007 agg
->frame_count
, txq_id
, idx
);
1009 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
1012 "BUG_ON idx doesn't point to valid skb"
1013 " idx=%d, txq_id=%d\n", idx
, txq_id
);
1017 sc
= le16_to_cpu(hdr
->seq_ctrl
);
1018 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
1020 "BUG_ON idx doesn't match seq control"
1021 " idx=%d, seq_idx=%d, seq=%d\n",
1027 IWL_DEBUG_TX_REPLY(priv
, "AGG Frame i=%d idx %d seq=%d\n",
1028 i
, idx
, SEQ_TO_SN(sc
));
1032 sh
= (start
- idx
) + 0xff;
1033 bitmap
= bitmap
<< sh
;
1036 } else if (sh
< -64)
1037 sh
= 0xff - (start
- idx
);
1041 bitmap
= bitmap
<< sh
;
1044 bitmap
|= 1ULL << sh
;
1045 IWL_DEBUG_TX_REPLY(priv
, "start=%d bitmap=0x%llx\n",
1046 start
, (unsigned long long)bitmap
);
1049 agg
->bitmap
= bitmap
;
1050 agg
->start_idx
= start
;
1051 IWL_DEBUG_TX_REPLY(priv
, "Frames %d start_idx=%d bitmap=0x%llx\n",
1052 agg
->frame_count
, agg
->start_idx
,
1053 (unsigned long long)agg
->bitmap
);
1056 agg
->wait_for_ba
= 1;
1061 static void iwl5000_rx_reply_tx(struct iwl_priv
*priv
,
1062 struct iwl_rx_mem_buffer
*rxb
)
1064 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1065 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1066 int txq_id
= SEQ_TO_QUEUE(sequence
);
1067 int index
= SEQ_TO_INDEX(sequence
);
1068 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1069 struct ieee80211_tx_info
*info
;
1070 struct iwl5000_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
1071 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
1076 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
1077 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
1078 "is out of range [0-%d] %d %d\n", txq_id
,
1079 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
1084 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
1085 memset(&info
->status
, 0, sizeof(info
->status
));
1087 tid
= (tx_resp
->ra_tid
& IWL50_TX_RES_TID_MSK
) >> IWL50_TX_RES_TID_POS
;
1088 sta_id
= (tx_resp
->ra_tid
& IWL50_TX_RES_RA_MSK
) >> IWL50_TX_RES_RA_POS
;
1090 if (txq
->sched_retry
) {
1091 const u32 scd_ssn
= iwl5000_get_scd_ssn(tx_resp
);
1092 struct iwl_ht_agg
*agg
= NULL
;
1094 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1096 iwl5000_tx_status_reply_tx(priv
, agg
, tx_resp
, txq_id
, index
);
1098 /* check if BAR is needed */
1099 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
))
1100 info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1102 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
1103 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
1104 IWL_DEBUG_TX_REPLY(priv
, "Retry scheduler reclaim "
1105 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1106 scd_ssn
, index
, txq_id
, txq
->swq_id
);
1108 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1109 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1111 if (priv
->mac80211_registered
&&
1112 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1113 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
)) {
1114 if (agg
->state
== IWL_AGG_OFF
)
1115 iwl_wake_queue(priv
, txq_id
);
1117 iwl_wake_queue(priv
, txq
->swq_id
);
1121 BUG_ON(txq_id
!= txq
->swq_id
);
1123 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
1124 info
->flags
|= iwl_tx_status_to_mac80211(status
);
1125 iwl_hwrate_to_tx_control(priv
,
1126 le32_to_cpu(tx_resp
->rate_n_flags
),
1129 IWL_DEBUG_TX_REPLY(priv
, "TXQ %d status %s (0x%08x) rate_n_flags "
1130 "0x%x retries %d\n",
1132 iwl_get_tx_fail_reason(status
), status
,
1133 le32_to_cpu(tx_resp
->rate_n_flags
),
1134 tx_resp
->failure_frame
);
1136 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1137 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1138 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1140 if (priv
->mac80211_registered
&&
1141 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
))
1142 iwl_wake_queue(priv
, txq_id
);
1145 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1146 iwl_txq_check_empty(priv
, sta_id
, tid
, txq_id
);
1148 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
1149 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1152 /* Currently 5000 is the superset of everything */
1153 u16
iwl5000_get_hcmd_size(u8 cmd_id
, u16 len
)
1158 void iwl5000_setup_deferred_work(struct iwl_priv
*priv
)
1160 /* in 5000 the tx power calibration is done in uCode */
1161 priv
->disable_tx_power_cal
= 1;
1164 void iwl5000_rx_handler_setup(struct iwl_priv
*priv
)
1166 /* init calibration handlers */
1167 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
1168 iwl5000_rx_calib_result
;
1169 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
1170 iwl5000_rx_calib_complete
;
1171 priv
->rx_handlers
[REPLY_TX
] = iwl5000_rx_reply_tx
;
1175 int iwl5000_hw_valid_rtc_data_addr(u32 addr
)
1177 return (addr
>= IWL50_RTC_DATA_LOWER_BOUND
) &&
1178 (addr
< IWL50_RTC_DATA_UPPER_BOUND
);
1181 static int iwl5000_send_rxon_assoc(struct iwl_priv
*priv
)
1184 struct iwl5000_rxon_assoc_cmd rxon_assoc
;
1185 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1186 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1188 if ((rxon1
->flags
== rxon2
->flags
) &&
1189 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1190 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1191 (rxon1
->ofdm_ht_single_stream_basic_rates
==
1192 rxon2
->ofdm_ht_single_stream_basic_rates
) &&
1193 (rxon1
->ofdm_ht_dual_stream_basic_rates
==
1194 rxon2
->ofdm_ht_dual_stream_basic_rates
) &&
1195 (rxon1
->ofdm_ht_triple_stream_basic_rates
==
1196 rxon2
->ofdm_ht_triple_stream_basic_rates
) &&
1197 (rxon1
->acquisition_data
== rxon2
->acquisition_data
) &&
1198 (rxon1
->rx_chain
== rxon2
->rx_chain
) &&
1199 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1200 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1204 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1205 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1206 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1207 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1208 rxon_assoc
.reserved1
= 0;
1209 rxon_assoc
.reserved2
= 0;
1210 rxon_assoc
.reserved3
= 0;
1211 rxon_assoc
.ofdm_ht_single_stream_basic_rates
=
1212 priv
->staging_rxon
.ofdm_ht_single_stream_basic_rates
;
1213 rxon_assoc
.ofdm_ht_dual_stream_basic_rates
=
1214 priv
->staging_rxon
.ofdm_ht_dual_stream_basic_rates
;
1215 rxon_assoc
.rx_chain_select_flags
= priv
->staging_rxon
.rx_chain
;
1216 rxon_assoc
.ofdm_ht_triple_stream_basic_rates
=
1217 priv
->staging_rxon
.ofdm_ht_triple_stream_basic_rates
;
1218 rxon_assoc
.acquisition_data
= priv
->staging_rxon
.acquisition_data
;
1220 ret
= iwl_send_cmd_pdu_async(priv
, REPLY_RXON_ASSOC
,
1221 sizeof(rxon_assoc
), &rxon_assoc
, NULL
);
1227 int iwl5000_send_tx_power(struct iwl_priv
*priv
)
1229 struct iwl5000_tx_power_dbm_cmd tx_power_cmd
;
1232 /* half dBm need to multiply */
1233 tx_power_cmd
.global_lmt
= (s8
)(2 * priv
->tx_power_user_lmt
);
1235 if (priv
->tx_power_lmt_in_half_dbm
&&
1236 priv
->tx_power_lmt_in_half_dbm
< tx_power_cmd
.global_lmt
) {
1238 * For the newer devices which using enhanced/extend tx power
1239 * table in EEPROM, the format is in half dBm. driver need to
1240 * convert to dBm format before report to mac80211.
1241 * By doing so, there is a possibility of 1/2 dBm resolution
1242 * lost. driver will perform "round-up" operation before
1243 * reporting, but it will cause 1/2 dBm tx power over the
1244 * regulatory limit. Perform the checking here, if the
1245 * "tx_power_user_lmt" is higher than EEPROM value (in
1246 * half-dBm format), lower the tx power based on EEPROM
1248 tx_power_cmd
.global_lmt
= priv
->tx_power_lmt_in_half_dbm
;
1250 tx_power_cmd
.flags
= IWL50_TX_POWER_NO_CLOSED
;
1251 tx_power_cmd
.srv_chan_lmt
= IWL50_TX_POWER_AUTO
;
1253 if (IWL_UCODE_API(priv
->ucode_ver
) == 1)
1254 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD_V1
;
1256 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD
;
1258 return iwl_send_cmd_pdu_async(priv
, tx_ant_cfg_cmd
,
1259 sizeof(tx_power_cmd
), &tx_power_cmd
,
1263 void iwl5000_temperature(struct iwl_priv
*priv
)
1265 /* store temperature from statistics (in Celsius) */
1266 priv
->temperature
= le32_to_cpu(priv
->statistics
.general
.temperature
);
1267 iwl_tt_handler(priv
);
1270 static void iwl5150_temperature(struct iwl_priv
*priv
)
1273 s32 offset
= iwl_temp_calib_to_offset(priv
);
1275 vt
= le32_to_cpu(priv
->statistics
.general
.temperature
);
1276 vt
= vt
/ IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF
+ offset
;
1277 /* now vt hold the temperature in Kelvin */
1278 priv
->temperature
= KELVIN_TO_CELSIUS(vt
);
1279 iwl_tt_handler(priv
);
1282 /* Calc max signal level (dBm) among 3 possible receivers */
1283 int iwl5000_calc_rssi(struct iwl_priv
*priv
,
1284 struct iwl_rx_phy_res
*rx_resp
)
1286 /* data from PHY/DSP regarding signal strength, etc.,
1287 * contents are always there, not configurable by host
1289 struct iwl5000_non_cfg_phy
*ncphy
=
1290 (struct iwl5000_non_cfg_phy
*)rx_resp
->non_cfg_phy_buf
;
1291 u32 val
, rssi_a
, rssi_b
, rssi_c
, max_rssi
;
1294 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_AGC_IDX
]);
1295 agc
= (val
& IWL50_OFDM_AGC_MSK
) >> IWL50_OFDM_AGC_BIT_POS
;
1297 /* Find max rssi among 3 possible receivers.
1298 * These values are measured by the digital signal processor (DSP).
1299 * They should stay fairly constant even as the signal strength varies,
1300 * if the radio's automatic gain control (AGC) is working right.
1301 * AGC value (see below) will provide the "interesting" info.
1303 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_AB_IDX
]);
1304 rssi_a
= (val
& IWL50_OFDM_RSSI_A_MSK
) >> IWL50_OFDM_RSSI_A_BIT_POS
;
1305 rssi_b
= (val
& IWL50_OFDM_RSSI_B_MSK
) >> IWL50_OFDM_RSSI_B_BIT_POS
;
1306 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_C_IDX
]);
1307 rssi_c
= (val
& IWL50_OFDM_RSSI_C_MSK
) >> IWL50_OFDM_RSSI_C_BIT_POS
;
1309 max_rssi
= max_t(u32
, rssi_a
, rssi_b
);
1310 max_rssi
= max_t(u32
, max_rssi
, rssi_c
);
1312 IWL_DEBUG_STATS(priv
, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1313 rssi_a
, rssi_b
, rssi_c
, max_rssi
, agc
);
1315 /* dBm = max_rssi dB - agc dB - constant.
1316 * Higher AGC (higher radio gain) means lower signal. */
1317 return max_rssi
- agc
- IWL49_RSSI_OFFSET
;
1320 static int iwl5000_send_tx_ant_config(struct iwl_priv
*priv
, u8 valid_tx_ant
)
1322 struct iwl_tx_ant_config_cmd tx_ant_cmd
= {
1323 .valid
= cpu_to_le32(valid_tx_ant
),
1326 if (IWL_UCODE_API(priv
->ucode_ver
) > 1) {
1327 IWL_DEBUG_HC(priv
, "select valid tx ant: %u\n", valid_tx_ant
);
1328 return iwl_send_cmd_pdu(priv
, TX_ANT_CONFIGURATION_CMD
,
1329 sizeof(struct iwl_tx_ant_config_cmd
),
1332 IWL_DEBUG_HC(priv
, "TX_ANT_CONFIGURATION_CMD not supported\n");
1338 #define IWL5000_UCODE_GET(item) \
1339 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1343 return le32_to_cpu(ucode->u.v1.item); \
1344 return le32_to_cpu(ucode->u.v2.item); \
1347 static u32
iwl5000_ucode_get_header_size(u32 api_ver
)
1350 return UCODE_HEADER_SIZE(1);
1351 return UCODE_HEADER_SIZE(2);
1354 static u32
iwl5000_ucode_get_build(const struct iwl_ucode_header
*ucode
,
1359 return le32_to_cpu(ucode
->u
.v2
.build
);
1362 static u8
*iwl5000_ucode_get_data(const struct iwl_ucode_header
*ucode
,
1366 return (u8
*) ucode
->u
.v1
.data
;
1367 return (u8
*) ucode
->u
.v2
.data
;
1370 IWL5000_UCODE_GET(inst_size
);
1371 IWL5000_UCODE_GET(data_size
);
1372 IWL5000_UCODE_GET(init_size
);
1373 IWL5000_UCODE_GET(init_data_size
);
1374 IWL5000_UCODE_GET(boot_size
);
1376 static int iwl5000_hw_channel_switch(struct iwl_priv
*priv
, u16 channel
)
1378 struct iwl5000_channel_switch_cmd cmd
;
1379 const struct iwl_channel_info
*ch_info
;
1380 struct iwl_host_cmd hcmd
= {
1381 .id
= REPLY_CHANNEL_SWITCH
,
1383 .flags
= CMD_SIZE_HUGE
,
1387 IWL_DEBUG_11H(priv
, "channel switch from %d to %d\n",
1388 priv
->active_rxon
.channel
, channel
);
1389 cmd
.band
= priv
->band
== IEEE80211_BAND_2GHZ
;
1390 cmd
.channel
= cpu_to_le16(channel
);
1391 cmd
.rxon_flags
= priv
->staging_rxon
.flags
;
1392 cmd
.rxon_filter_flags
= priv
->staging_rxon
.filter_flags
;
1393 cmd
.switch_time
= cpu_to_le32(priv
->ucode_beacon_time
);
1394 ch_info
= iwl_get_channel_info(priv
, priv
->band
, channel
);
1396 cmd
.expect_beacon
= is_channel_radar(ch_info
);
1398 IWL_ERR(priv
, "invalid channel switch from %u to %u\n",
1399 priv
->active_rxon
.channel
, channel
);
1402 priv
->switch_rxon
.channel
= cpu_to_le16(channel
);
1403 priv
->switch_rxon
.switch_in_progress
= true;
1405 return iwl_send_cmd_sync(priv
, &hcmd
);
1408 struct iwl_hcmd_ops iwl5000_hcmd
= {
1409 .rxon_assoc
= iwl5000_send_rxon_assoc
,
1410 .commit_rxon
= iwl_commit_rxon
,
1411 .set_rxon_chain
= iwl_set_rxon_chain
,
1412 .set_tx_ant
= iwl5000_send_tx_ant_config
,
1415 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils
= {
1416 .get_hcmd_size
= iwl5000_get_hcmd_size
,
1417 .build_addsta_hcmd
= iwl5000_build_addsta_hcmd
,
1418 .gain_computation
= iwl5000_gain_computation
,
1419 .chain_noise_reset
= iwl5000_chain_noise_reset
,
1420 .rts_tx_cmd_flag
= iwl5000_rts_tx_cmd_flag
,
1421 .calc_rssi
= iwl5000_calc_rssi
,
1424 struct iwl_ucode_ops iwl5000_ucode
= {
1425 .get_header_size
= iwl5000_ucode_get_header_size
,
1426 .get_build
= iwl5000_ucode_get_build
,
1427 .get_inst_size
= iwl5000_ucode_get_inst_size
,
1428 .get_data_size
= iwl5000_ucode_get_data_size
,
1429 .get_init_size
= iwl5000_ucode_get_init_size
,
1430 .get_init_data_size
= iwl5000_ucode_get_init_data_size
,
1431 .get_boot_size
= iwl5000_ucode_get_boot_size
,
1432 .get_data
= iwl5000_ucode_get_data
,
1435 struct iwl_lib_ops iwl5000_lib
= {
1436 .set_hw_params
= iwl5000_hw_set_hw_params
,
1437 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1438 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1439 .txq_set_sched
= iwl5000_txq_set_sched
,
1440 .txq_agg_enable
= iwl5000_txq_agg_enable
,
1441 .txq_agg_disable
= iwl5000_txq_agg_disable
,
1442 .txq_attach_buf_to_tfd
= iwl_hw_txq_attach_buf_to_tfd
,
1443 .txq_free_tfd
= iwl_hw_txq_free_tfd
,
1444 .txq_init
= iwl_hw_tx_queue_init
,
1445 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1446 .setup_deferred_work
= iwl5000_setup_deferred_work
,
1447 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1448 .dump_nic_event_log
= iwl_dump_nic_event_log
,
1449 .dump_nic_error_log
= iwl_dump_nic_error_log
,
1450 .dump_csr
= iwl_dump_csr
,
1451 .dump_fh
= iwl_dump_fh
,
1452 .load_ucode
= iwl5000_load_ucode
,
1453 .init_alive_start
= iwl5000_init_alive_start
,
1454 .alive_notify
= iwl5000_alive_notify
,
1455 .send_tx_power
= iwl5000_send_tx_power
,
1456 .update_chain_flags
= iwl_update_chain_flags
,
1457 .set_channel_switch
= iwl5000_hw_channel_switch
,
1459 .init
= iwl_apm_init
,
1460 .stop
= iwl_apm_stop
,
1461 .config
= iwl5000_nic_config
,
1462 .set_pwr_src
= iwl_set_pwr_src
,
1465 .regulatory_bands
= {
1466 EEPROM_5000_REG_BAND_1_CHANNELS
,
1467 EEPROM_5000_REG_BAND_2_CHANNELS
,
1468 EEPROM_5000_REG_BAND_3_CHANNELS
,
1469 EEPROM_5000_REG_BAND_4_CHANNELS
,
1470 EEPROM_5000_REG_BAND_5_CHANNELS
,
1471 EEPROM_5000_REG_BAND_24_HT40_CHANNELS
,
1472 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1474 .verify_signature
= iwlcore_eeprom_verify_signature
,
1475 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1476 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1477 .calib_version
= iwl5000_eeprom_calib_version
,
1478 .query_addr
= iwl5000_eeprom_query_addr
,
1480 .post_associate
= iwl_post_associate
,
1482 .config_ap
= iwl_config_ap
,
1484 .temperature
= iwl5000_temperature
,
1485 .set_ct_kill
= iwl5000_set_ct_threshold
,
1487 .add_bcast_station
= iwl_add_bcast_station
,
1490 static struct iwl_lib_ops iwl5150_lib
= {
1491 .set_hw_params
= iwl5000_hw_set_hw_params
,
1492 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1493 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1494 .txq_set_sched
= iwl5000_txq_set_sched
,
1495 .txq_agg_enable
= iwl5000_txq_agg_enable
,
1496 .txq_agg_disable
= iwl5000_txq_agg_disable
,
1497 .txq_attach_buf_to_tfd
= iwl_hw_txq_attach_buf_to_tfd
,
1498 .txq_free_tfd
= iwl_hw_txq_free_tfd
,
1499 .txq_init
= iwl_hw_tx_queue_init
,
1500 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1501 .setup_deferred_work
= iwl5000_setup_deferred_work
,
1502 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1503 .dump_nic_event_log
= iwl_dump_nic_event_log
,
1504 .dump_nic_error_log
= iwl_dump_nic_error_log
,
1505 .dump_csr
= iwl_dump_csr
,
1506 .load_ucode
= iwl5000_load_ucode
,
1507 .init_alive_start
= iwl5000_init_alive_start
,
1508 .alive_notify
= iwl5000_alive_notify
,
1509 .send_tx_power
= iwl5000_send_tx_power
,
1510 .update_chain_flags
= iwl_update_chain_flags
,
1511 .set_channel_switch
= iwl5000_hw_channel_switch
,
1513 .init
= iwl_apm_init
,
1514 .stop
= iwl_apm_stop
,
1515 .config
= iwl5000_nic_config
,
1516 .set_pwr_src
= iwl_set_pwr_src
,
1519 .regulatory_bands
= {
1520 EEPROM_5000_REG_BAND_1_CHANNELS
,
1521 EEPROM_5000_REG_BAND_2_CHANNELS
,
1522 EEPROM_5000_REG_BAND_3_CHANNELS
,
1523 EEPROM_5000_REG_BAND_4_CHANNELS
,
1524 EEPROM_5000_REG_BAND_5_CHANNELS
,
1525 EEPROM_5000_REG_BAND_24_HT40_CHANNELS
,
1526 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1528 .verify_signature
= iwlcore_eeprom_verify_signature
,
1529 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1530 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1531 .calib_version
= iwl5000_eeprom_calib_version
,
1532 .query_addr
= iwl5000_eeprom_query_addr
,
1534 .post_associate
= iwl_post_associate
,
1536 .config_ap
= iwl_config_ap
,
1538 .temperature
= iwl5150_temperature
,
1539 .set_ct_kill
= iwl5150_set_ct_threshold
,
1541 .add_bcast_station
= iwl_add_bcast_station
,
1544 static const struct iwl_ops iwl5000_ops
= {
1545 .ucode
= &iwl5000_ucode
,
1546 .lib
= &iwl5000_lib
,
1547 .hcmd
= &iwl5000_hcmd
,
1548 .utils
= &iwl5000_hcmd_utils
,
1549 .led
= &iwlagn_led_ops
,
1552 static const struct iwl_ops iwl5150_ops
= {
1553 .ucode
= &iwl5000_ucode
,
1554 .lib
= &iwl5150_lib
,
1555 .hcmd
= &iwl5000_hcmd
,
1556 .utils
= &iwl5000_hcmd_utils
,
1557 .led
= &iwlagn_led_ops
,
1560 struct iwl_mod_params iwl50_mod_params
= {
1563 /* the rest are 0 by default */
1567 struct iwl_cfg iwl5300_agn_cfg
= {
1569 .fw_name_pre
= IWL5000_FW_PRE
,
1570 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1571 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1572 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1573 .ops
= &iwl5000_ops
,
1574 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1575 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1576 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1577 .num_of_queues
= IWL50_NUM_QUEUES
,
1578 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1579 .mod_params
= &iwl50_mod_params
,
1580 .valid_tx_ant
= ANT_ABC
,
1581 .valid_rx_ant
= ANT_ABC
,
1582 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1585 .ht_greenfield_support
= true,
1586 .led_compensation
= 51,
1587 .use_rts_for_ht
= true, /* use rts/cts protection */
1588 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1589 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1592 struct iwl_cfg iwl5100_bgn_cfg
= {
1594 .fw_name_pre
= IWL5000_FW_PRE
,
1595 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1596 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1597 .sku
= IWL_SKU_G
|IWL_SKU_N
,
1598 .ops
= &iwl5000_ops
,
1599 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1600 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1601 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1602 .num_of_queues
= IWL50_NUM_QUEUES
,
1603 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1604 .mod_params
= &iwl50_mod_params
,
1605 .valid_tx_ant
= ANT_B
,
1606 .valid_rx_ant
= ANT_AB
,
1607 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1610 .ht_greenfield_support
= true,
1611 .led_compensation
= 51,
1612 .use_rts_for_ht
= true, /* use rts/cts protection */
1613 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1614 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1617 struct iwl_cfg iwl5100_abg_cfg
= {
1619 .fw_name_pre
= IWL5000_FW_PRE
,
1620 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1621 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1622 .sku
= IWL_SKU_A
|IWL_SKU_G
,
1623 .ops
= &iwl5000_ops
,
1624 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1625 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1626 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1627 .num_of_queues
= IWL50_NUM_QUEUES
,
1628 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1629 .mod_params
= &iwl50_mod_params
,
1630 .valid_tx_ant
= ANT_B
,
1631 .valid_rx_ant
= ANT_AB
,
1632 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1635 .led_compensation
= 51,
1636 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1637 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1640 struct iwl_cfg iwl5100_agn_cfg
= {
1642 .fw_name_pre
= IWL5000_FW_PRE
,
1643 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1644 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1645 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1646 .ops
= &iwl5000_ops
,
1647 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1648 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1649 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1650 .num_of_queues
= IWL50_NUM_QUEUES
,
1651 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1652 .mod_params
= &iwl50_mod_params
,
1653 .valid_tx_ant
= ANT_B
,
1654 .valid_rx_ant
= ANT_AB
,
1655 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1658 .ht_greenfield_support
= true,
1659 .led_compensation
= 51,
1660 .use_rts_for_ht
= true, /* use rts/cts protection */
1661 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1662 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1665 struct iwl_cfg iwl5350_agn_cfg
= {
1667 .fw_name_pre
= IWL5000_FW_PRE
,
1668 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1669 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1670 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1671 .ops
= &iwl5000_ops
,
1672 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1673 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1674 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1675 .num_of_queues
= IWL50_NUM_QUEUES
,
1676 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1677 .mod_params
= &iwl50_mod_params
,
1678 .valid_tx_ant
= ANT_ABC
,
1679 .valid_rx_ant
= ANT_ABC
,
1680 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1683 .ht_greenfield_support
= true,
1684 .led_compensation
= 51,
1685 .use_rts_for_ht
= true, /* use rts/cts protection */
1686 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1687 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1690 struct iwl_cfg iwl5150_agn_cfg
= {
1692 .fw_name_pre
= IWL5150_FW_PRE
,
1693 .ucode_api_max
= IWL5150_UCODE_API_MAX
,
1694 .ucode_api_min
= IWL5150_UCODE_API_MIN
,
1695 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1696 .ops
= &iwl5150_ops
,
1697 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1698 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1699 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1700 .num_of_queues
= IWL50_NUM_QUEUES
,
1701 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1702 .mod_params
= &iwl50_mod_params
,
1703 .valid_tx_ant
= ANT_A
,
1704 .valid_rx_ant
= ANT_AB
,
1705 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1708 .ht_greenfield_support
= true,
1709 .led_compensation
= 51,
1710 .use_rts_for_ht
= true, /* use rts/cts protection */
1711 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1712 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1715 struct iwl_cfg iwl5150_abg_cfg
= {
1717 .fw_name_pre
= IWL5150_FW_PRE
,
1718 .ucode_api_max
= IWL5150_UCODE_API_MAX
,
1719 .ucode_api_min
= IWL5150_UCODE_API_MIN
,
1720 .sku
= IWL_SKU_A
|IWL_SKU_G
,
1721 .ops
= &iwl5150_ops
,
1722 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1723 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1724 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1725 .num_of_queues
= IWL50_NUM_QUEUES
,
1726 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1727 .mod_params
= &iwl50_mod_params
,
1728 .valid_tx_ant
= ANT_A
,
1729 .valid_rx_ant
= ANT_AB
,
1730 .pll_cfg_val
= CSR50_ANA_PLL_CFG_VAL
,
1733 .led_compensation
= 51,
1734 .chain_noise_num_beacons
= IWL_CAL_NUM_BEACONS
,
1735 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
,
1738 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX
));
1739 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX
));
1741 module_param_named(swcrypto50
, iwl50_mod_params
.sw_crypto
, bool, S_IRUGO
);
1742 MODULE_PARM_DESC(swcrypto50
,
1743 "using software crypto engine (default 0 [hardware])\n");
1744 module_param_named(queues_num50
, iwl50_mod_params
.num_of_queues
, int, S_IRUGO
);
1745 MODULE_PARM_DESC(queues_num50
, "number of hw queues in 50xx series");
1746 module_param_named(11n_disable50
, iwl50_mod_params
.disable_11n
, int, S_IRUGO
);
1747 MODULE_PARM_DESC(11n_disable50
, "disable 50XX 11n functionality");
1748 module_param_named(amsdu_size_8K50
, iwl50_mod_params
.amsdu_size_8K
,
1750 MODULE_PARM_DESC(amsdu_size_8K50
, "enable 8K amsdu size in 50XX series");
1751 module_param_named(fw_restart50
, iwl50_mod_params
.restart_fw
, int, S_IRUGO
);
1752 MODULE_PARM_DESC(fw_restart50
, "restart firmware in case of error");