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iwlwifi: move txq_ctx_stop into iwl-tx.c
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/version.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46
47 #define IWL5000_UCODE_API "-1"
48
49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
50 IWL_TX_FIFO_AC3,
51 IWL_TX_FIFO_AC2,
52 IWL_TX_FIFO_AC1,
53 IWL_TX_FIFO_AC0,
54 IWL50_CMD_FIFO_NUM,
55 IWL_TX_FIFO_HCCA_1,
56 IWL_TX_FIFO_HCCA_2
57 };
58
59 /* FIXME: same implementation as 4965 */
60 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
61 {
62 int ret = 0;
63 unsigned long flags;
64
65 spin_lock_irqsave(&priv->lock, flags);
66
67 /* set stop master bit */
68 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
69
70 ret = iwl_poll_bit(priv, CSR_RESET,
71 CSR_RESET_REG_FLAG_MASTER_DISABLED,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
73 if (ret < 0)
74 goto out;
75
76 out:
77 spin_unlock_irqrestore(&priv->lock, flags);
78 IWL_DEBUG_INFO("stop master\n");
79
80 return ret;
81 }
82
83
84 static int iwl5000_apm_init(struct iwl_priv *priv)
85 {
86 int ret = 0;
87
88 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
89 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
90
91 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
92 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
93 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
94
95 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
96
97 /* set "initialization complete" bit to move adapter
98 * D0U* --> D0A* state */
99 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
100
101 /* wait for clock stabilization */
102 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
105 if (ret < 0) {
106 IWL_DEBUG_INFO("Failed to init the card\n");
107 return ret;
108 }
109
110 ret = iwl_grab_nic_access(priv);
111 if (ret)
112 return ret;
113
114 /* enable DMA */
115 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
116
117 udelay(20);
118
119 /* disable L1-Active */
120 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
121 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
122
123 iwl_release_nic_access(priv);
124
125 return ret;
126 }
127
128 /* FIXME: this is indentical to 4965 */
129 static void iwl5000_apm_stop(struct iwl_priv *priv)
130 {
131 unsigned long flags;
132
133 iwl5000_apm_stop_master(priv);
134
135 spin_lock_irqsave(&priv->lock, flags);
136
137 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
138
139 udelay(10);
140
141 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
142
143 spin_unlock_irqrestore(&priv->lock, flags);
144 }
145
146
147 static int iwl5000_apm_reset(struct iwl_priv *priv)
148 {
149 int ret = 0;
150 unsigned long flags;
151
152 iwl5000_apm_stop_master(priv);
153
154 spin_lock_irqsave(&priv->lock, flags);
155
156 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
157
158 udelay(10);
159
160
161 /* FIXME: put here L1A -L0S w/a */
162
163 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
164
165 /* set "initialization complete" bit to move adapter
166 * D0U* --> D0A* state */
167 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
168
169 /* wait for clock stabilization */
170 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
171 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
173 if (ret < 0) {
174 IWL_DEBUG_INFO("Failed to init the card\n");
175 goto out;
176 }
177
178 ret = iwl_grab_nic_access(priv);
179 if (ret)
180 goto out;
181
182 /* enable DMA */
183 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
184
185 udelay(20);
186
187 /* disable L1-Active */
188 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
189 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
190
191 iwl_release_nic_access(priv);
192
193 out:
194 spin_unlock_irqrestore(&priv->lock, flags);
195
196 return ret;
197 }
198
199
200 static void iwl5000_nic_config(struct iwl_priv *priv)
201 {
202 unsigned long flags;
203 u16 radio_cfg;
204 u8 val_link;
205
206 spin_lock_irqsave(&priv->lock, flags);
207
208 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
209
210 /* L1 is enabled by BIOS */
211 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
212 /* diable L0S disabled L1A enabled */
213 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
214 else
215 /* L0S enabled L1A disabled */
216 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
217
218 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
219
220 /* write radio config values to register */
221 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
222 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
223 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
224 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
225 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
226
227 /* set CSR_HW_CONFIG_REG for uCode use */
228 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
229 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
230 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
231
232 spin_unlock_irqrestore(&priv->lock, flags);
233 }
234
235
236
237 /*
238 * EEPROM
239 */
240 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
241 {
242 u16 offset = 0;
243
244 if ((address & INDIRECT_ADDRESS) == 0)
245 return address;
246
247 switch (address & INDIRECT_TYPE_MSK) {
248 case INDIRECT_HOST:
249 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
250 break;
251 case INDIRECT_GENERAL:
252 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
253 break;
254 case INDIRECT_REGULATORY:
255 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
256 break;
257 case INDIRECT_CALIBRATION:
258 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
259 break;
260 case INDIRECT_PROCESS_ADJST:
261 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
262 break;
263 case INDIRECT_OTHERS:
264 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
265 break;
266 default:
267 IWL_ERROR("illegal indirect type: 0x%X\n",
268 address & INDIRECT_TYPE_MSK);
269 break;
270 }
271
272 /* translate the offset from words to byte */
273 return (address & ADDRESS_MSK) + (offset << 1);
274 }
275
276 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
277 {
278 u16 eeprom_ver;
279 struct iwl_eeprom_calib_hdr {
280 u8 version;
281 u8 pa_type;
282 u16 voltage;
283 } *hdr;
284
285 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
286
287 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
288 EEPROM_5000_CALIB_ALL);
289
290 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
291 hdr->version < EEPROM_5000_TX_POWER_VERSION)
292 goto err;
293
294 return 0;
295 err:
296 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
297 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
298 hdr->version, EEPROM_5000_TX_POWER_VERSION);
299 return -EINVAL;
300
301 }
302
303 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
304
305 static void iwl5000_gain_computation(struct iwl_priv *priv,
306 u32 average_noise[NUM_RX_CHAINS],
307 u16 min_average_noise_antenna_i,
308 u32 min_average_noise)
309 {
310 int i;
311 s32 delta_g;
312 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
313
314 /* Find Gain Code for the antennas B and C */
315 for (i = 1; i < NUM_RX_CHAINS; i++) {
316 if ((data->disconn_array[i])) {
317 data->delta_gain_code[i] = 0;
318 continue;
319 }
320 delta_g = (1000 * ((s32)average_noise[0] -
321 (s32)average_noise[i])) / 1500;
322 /* bound gain by 2 bits value max, 3rd bit is sign */
323 data->delta_gain_code[i] =
324 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
325
326 if (delta_g < 0)
327 /* set negative sign */
328 data->delta_gain_code[i] |= (1 << 2);
329 }
330
331 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
332 data->delta_gain_code[1], data->delta_gain_code[2]);
333
334 if (!data->radio_write) {
335 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
336 memset(&cmd, 0, sizeof(cmd));
337
338 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
339 cmd.delta_gain_1 = data->delta_gain_code[1];
340 cmd.delta_gain_2 = data->delta_gain_code[2];
341 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
342 sizeof(cmd), &cmd, NULL);
343
344 data->radio_write = 1;
345 data->state = IWL_CHAIN_NOISE_CALIBRATED;
346 }
347
348 data->chain_noise_a = 0;
349 data->chain_noise_b = 0;
350 data->chain_noise_c = 0;
351 data->chain_signal_a = 0;
352 data->chain_signal_b = 0;
353 data->chain_signal_c = 0;
354 data->beacon_count = 0;
355 }
356
357
358 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
359 {
360 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
361
362 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
363 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
364
365 memset(&cmd, 0, sizeof(cmd));
366 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
367 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
368 sizeof(cmd), &cmd))
369 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
370 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
371 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
372 }
373 }
374
375 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
376 .min_nrg_cck = 95,
377 .max_nrg_cck = 0,
378 .auto_corr_min_ofdm = 90,
379 .auto_corr_min_ofdm_mrc = 170,
380 .auto_corr_min_ofdm_x1 = 120,
381 .auto_corr_min_ofdm_mrc_x1 = 240,
382
383 .auto_corr_max_ofdm = 120,
384 .auto_corr_max_ofdm_mrc = 210,
385 .auto_corr_max_ofdm_x1 = 155,
386 .auto_corr_max_ofdm_mrc_x1 = 290,
387
388 .auto_corr_min_cck = 125,
389 .auto_corr_max_cck = 200,
390 .auto_corr_min_cck_mrc = 170,
391 .auto_corr_max_cck_mrc = 400,
392 .nrg_th_cck = 95,
393 .nrg_th_ofdm = 95,
394 };
395
396 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
397
398 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
399 size_t offset)
400 {
401 u32 address = eeprom_indirect_address(priv, offset);
402 BUG_ON(address >= priv->cfg->eeprom_size);
403 return &priv->eeprom[address];
404 }
405
406 /*
407 * ucode
408 */
409 static int iwl5000_load_section(struct iwl_priv *priv,
410 struct fw_desc *image,
411 u32 dst_addr)
412 {
413 int ret = 0;
414 unsigned long flags;
415
416 dma_addr_t phy_addr = image->p_addr;
417 u32 byte_cnt = image->len;
418
419 spin_lock_irqsave(&priv->lock, flags);
420 ret = iwl_grab_nic_access(priv);
421 if (ret) {
422 spin_unlock_irqrestore(&priv->lock, flags);
423 return ret;
424 }
425
426 iwl_write_direct32(priv,
427 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
428 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
429
430 iwl_write_direct32(priv,
431 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
432
433 iwl_write_direct32(priv,
434 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
435 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
436
437 /* FIME: write the MSB of the phy_addr in CTRL1
438 * iwl_write_direct32(priv,
439 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
440 ((phy_addr & MSB_MSK)
441 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
442 */
443 iwl_write_direct32(priv,
444 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
445 iwl_write_direct32(priv,
446 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
447 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
448 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
449 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
450
451 iwl_write_direct32(priv,
452 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
453 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
454 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
455 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
456
457 iwl_release_nic_access(priv);
458 spin_unlock_irqrestore(&priv->lock, flags);
459 return 0;
460 }
461
462 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
463 struct fw_desc *inst_image,
464 struct fw_desc *data_image)
465 {
466 int ret = 0;
467
468 ret = iwl5000_load_section(
469 priv, inst_image, RTC_INST_LOWER_BOUND);
470 if (ret)
471 return ret;
472
473 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
474 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
475 priv->ucode_write_complete, 5 * HZ);
476 if (ret == -ERESTARTSYS) {
477 IWL_ERROR("Could not load the INST uCode section due "
478 "to interrupt\n");
479 return ret;
480 }
481 if (!ret) {
482 IWL_ERROR("Could not load the INST uCode section\n");
483 return -ETIMEDOUT;
484 }
485
486 priv->ucode_write_complete = 0;
487
488 ret = iwl5000_load_section(
489 priv, data_image, RTC_DATA_LOWER_BOUND);
490 if (ret)
491 return ret;
492
493 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
494
495 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
496 priv->ucode_write_complete, 5 * HZ);
497 if (ret == -ERESTARTSYS) {
498 IWL_ERROR("Could not load the INST uCode section due "
499 "to interrupt\n");
500 return ret;
501 } else if (!ret) {
502 IWL_ERROR("Could not load the DATA uCode section\n");
503 return -ETIMEDOUT;
504 } else
505 ret = 0;
506
507 priv->ucode_write_complete = 0;
508
509 return ret;
510 }
511
512 static int iwl5000_load_ucode(struct iwl_priv *priv)
513 {
514 int ret = 0;
515
516 /* check whether init ucode should be loaded, or rather runtime ucode */
517 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
518 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
519 ret = iwl5000_load_given_ucode(priv,
520 &priv->ucode_init, &priv->ucode_init_data);
521 if (!ret) {
522 IWL_DEBUG_INFO("Init ucode load complete.\n");
523 priv->ucode_type = UCODE_INIT;
524 }
525 } else {
526 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
527 "Loading runtime ucode...\n");
528 ret = iwl5000_load_given_ucode(priv,
529 &priv->ucode_code, &priv->ucode_data);
530 if (!ret) {
531 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
532 priv->ucode_type = UCODE_RT;
533 }
534 }
535
536 return ret;
537 }
538
539 static void iwl5000_init_alive_start(struct iwl_priv *priv)
540 {
541 int ret = 0;
542
543 /* Check alive response for "valid" sign from uCode */
544 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
545 /* We had an error bringing up the hardware, so take it
546 * all the way back down so we can try again */
547 IWL_DEBUG_INFO("Initialize Alive failed.\n");
548 goto restart;
549 }
550
551 /* initialize uCode was loaded... verify inst image.
552 * This is a paranoid check, because we would not have gotten the
553 * "initialize" alive if code weren't properly loaded. */
554 if (iwl_verify_ucode(priv)) {
555 /* Runtime instruction load was bad;
556 * take it all the way back down so we can try again */
557 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
558 goto restart;
559 }
560
561 iwlcore_clear_stations_table(priv);
562 ret = priv->cfg->ops->lib->alive_notify(priv);
563 if (ret) {
564 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
565 goto restart;
566 }
567
568 return;
569
570 restart:
571 /* real restart (first load init_ucode) */
572 queue_work(priv->workqueue, &priv->restart);
573 }
574
575 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
576 int txq_id, u32 index)
577 {
578 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
579 (index & 0xff) | (txq_id << 8));
580 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
581 }
582
583 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
584 struct iwl_tx_queue *txq,
585 int tx_fifo_id, int scd_retry)
586 {
587 int txq_id = txq->q.id;
588 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
589
590 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
591 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
592 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
593 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
594 IWL50_SCD_QUEUE_STTS_REG_MSK);
595
596 txq->sched_retry = scd_retry;
597
598 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
599 active ? "Activate" : "Deactivate",
600 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
601 }
602
603 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
604 {
605 struct iwl_wimax_coex_cmd coex_cmd;
606
607 memset(&coex_cmd, 0, sizeof(coex_cmd));
608
609 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
610 sizeof(coex_cmd), &coex_cmd);
611 }
612
613 static int iwl5000_alive_notify(struct iwl_priv *priv)
614 {
615 u32 a;
616 int i = 0;
617 unsigned long flags;
618 int ret;
619
620 spin_lock_irqsave(&priv->lock, flags);
621
622 ret = iwl_grab_nic_access(priv);
623 if (ret) {
624 spin_unlock_irqrestore(&priv->lock, flags);
625 return ret;
626 }
627
628 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
629 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
630 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
631 a += 4)
632 iwl_write_targ_mem(priv, a, 0);
633 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
634 a += 4)
635 iwl_write_targ_mem(priv, a, 0);
636 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
637 iwl_write_targ_mem(priv, a, 0);
638
639 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
640 (priv->shared_phys +
641 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
642 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
643 IWL50_SCD_QUEUECHAIN_SEL_ALL(
644 priv->hw_params.max_txq_num));
645 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
646
647 /* initiate the queues */
648 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
649 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
650 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
651 iwl_write_targ_mem(priv, priv->scd_base_addr +
652 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
653 iwl_write_targ_mem(priv, priv->scd_base_addr +
654 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
655 sizeof(u32),
656 ((SCD_WIN_SIZE <<
657 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
658 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
659 ((SCD_FRAME_LIMIT <<
660 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
661 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
662 }
663
664 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
665 IWL_MASK(0, priv->hw_params.max_txq_num));
666
667 /* Activate all Tx DMA/FIFO channels */
668 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
669
670 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
671 /* map qos queues to fifos one-to-one */
672 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
673 int ac = iwl5000_default_queue_to_tx_fifo[i];
674 iwl_txq_ctx_activate(priv, i);
675 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
676 }
677 /* TODO - need to initialize those FIFOs inside the loop above,
678 * not only mark them as active */
679 iwl_txq_ctx_activate(priv, 4);
680 iwl_txq_ctx_activate(priv, 7);
681 iwl_txq_ctx_activate(priv, 8);
682 iwl_txq_ctx_activate(priv, 9);
683
684 iwl_release_nic_access(priv);
685 spin_unlock_irqrestore(&priv->lock, flags);
686
687 iwl5000_send_wimax_coex(priv);
688
689 return 0;
690 }
691
692 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
693 {
694 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
695 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
696 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
697 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
698 return -EINVAL;
699 }
700
701 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
702 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
703 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
704 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
705 if (priv->cfg->mod_params->amsdu_size_8K)
706 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
707 else
708 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
709 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
710 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
711 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
712 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
713 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
714 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
715 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
716 BIT(IEEE80211_BAND_5GHZ);
717 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
718 priv->hw_params.sens = &iwl5000_sensitivity;
719 #endif
720
721 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
722 case CSR_HW_REV_TYPE_5100:
723 case CSR_HW_REV_TYPE_5150:
724 priv->hw_params.tx_chains_num = 1;
725 priv->hw_params.rx_chains_num = 2;
726 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
727 priv->hw_params.valid_tx_ant = ANT_A;
728 priv->hw_params.valid_rx_ant = ANT_AB;
729 break;
730 case CSR_HW_REV_TYPE_5300:
731 case CSR_HW_REV_TYPE_5350:
732 priv->hw_params.tx_chains_num = 3;
733 priv->hw_params.rx_chains_num = 3;
734 priv->hw_params.valid_tx_ant = ANT_ABC;
735 priv->hw_params.valid_rx_ant = ANT_ABC;
736 break;
737 }
738
739 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
740 case CSR_HW_REV_TYPE_5100:
741 case CSR_HW_REV_TYPE_5300:
742 /* 5X00 wants in Celsius */
743 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
744 break;
745 case CSR_HW_REV_TYPE_5150:
746 case CSR_HW_REV_TYPE_5350:
747 /* 5X50 wants in Kelvin */
748 priv->hw_params.ct_kill_threshold =
749 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
750 break;
751 }
752
753 return 0;
754 }
755
756 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
757 {
758 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
759 sizeof(struct iwl5000_shared),
760 &priv->shared_phys);
761 if (!priv->shared_virt)
762 return -ENOMEM;
763
764 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
765
766 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
767
768 return 0;
769 }
770
771 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
772 {
773 if (priv->shared_virt)
774 pci_free_consistent(priv->pci_dev,
775 sizeof(struct iwl5000_shared),
776 priv->shared_virt,
777 priv->shared_phys);
778 }
779
780 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
781 {
782 struct iwl5000_shared *s = priv->shared_virt;
783 return le32_to_cpu(s->rb_closed) & 0xFFF;
784 }
785
786 /**
787 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
788 */
789 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
790 struct iwl_tx_queue *txq,
791 u16 byte_cnt)
792 {
793 struct iwl5000_shared *shared_data = priv->shared_virt;
794 int txq_id = txq->q.id;
795 u8 sec_ctl = 0;
796 u8 sta = 0;
797 int len;
798
799 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
800
801 if (txq_id != IWL_CMD_QUEUE_NUM) {
802 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
803 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
804
805 switch (sec_ctl & TX_CMD_SEC_MSK) {
806 case TX_CMD_SEC_CCM:
807 len += CCMP_MIC_LEN;
808 break;
809 case TX_CMD_SEC_TKIP:
810 len += TKIP_ICV_LEN;
811 break;
812 case TX_CMD_SEC_WEP:
813 len += WEP_IV_LEN + WEP_ICV_LEN;
814 break;
815 }
816 }
817
818 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
819 tfd_offset[txq->q.write_ptr], byte_cnt, len);
820
821 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
822 tfd_offset[txq->q.write_ptr], sta_id, sta);
823
824 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
825 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
826 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
827 byte_cnt, len);
828 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
829 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
830 sta_id, sta);
831 }
832 }
833
834 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
835 {
836 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
837 memcpy(data, cmd, size);
838 return size;
839 }
840
841
842 /*
843 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
844 * must be called under priv->lock and mac access
845 */
846 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
847 {
848 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
849 }
850
851 /* Currently 5000 is the supperset of everything */
852 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
853 {
854 return len;
855 }
856
857 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
858 {
859 }
860
861 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
862 {
863 return (addr >= RTC_DATA_LOWER_BOUND) &&
864 (addr < IWL50_RTC_DATA_UPPER_BOUND);
865 }
866
867 static struct iwl_hcmd_ops iwl5000_hcmd = {
868 };
869
870 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
871 .get_hcmd_size = iwl5000_get_hcmd_size,
872 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
873 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
874 .gain_computation = iwl5000_gain_computation,
875 .chain_noise_reset = iwl5000_chain_noise_reset,
876 #endif
877 };
878
879 static struct iwl_lib_ops iwl5000_lib = {
880 .set_hw_params = iwl5000_hw_set_hw_params,
881 .alloc_shared_mem = iwl5000_alloc_shared_mem,
882 .free_shared_mem = iwl5000_free_shared_mem,
883 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
884 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
885 .txq_set_sched = iwl5000_txq_set_sched,
886 .rx_handler_setup = iwl5000_rx_handler_setup,
887 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
888 .load_ucode = iwl5000_load_ucode,
889 .init_alive_start = iwl5000_init_alive_start,
890 .alive_notify = iwl5000_alive_notify,
891 .apm_ops = {
892 .init = iwl5000_apm_init,
893 .reset = iwl5000_apm_reset,
894 .stop = iwl5000_apm_stop,
895 .config = iwl5000_nic_config,
896 .set_pwr_src = iwl4965_set_pwr_src,
897 },
898 .eeprom_ops = {
899 .regulatory_bands = {
900 EEPROM_5000_REG_BAND_1_CHANNELS,
901 EEPROM_5000_REG_BAND_2_CHANNELS,
902 EEPROM_5000_REG_BAND_3_CHANNELS,
903 EEPROM_5000_REG_BAND_4_CHANNELS,
904 EEPROM_5000_REG_BAND_5_CHANNELS,
905 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
906 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
907 },
908 .verify_signature = iwlcore_eeprom_verify_signature,
909 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
910 .release_semaphore = iwlcore_eeprom_release_semaphore,
911 .check_version = iwl5000_eeprom_check_version,
912 .query_addr = iwl5000_eeprom_query_addr,
913 },
914 };
915
916 static struct iwl_ops iwl5000_ops = {
917 .lib = &iwl5000_lib,
918 .hcmd = &iwl5000_hcmd,
919 .utils = &iwl5000_hcmd_utils,
920 };
921
922 static struct iwl_mod_params iwl50_mod_params = {
923 .num_of_queues = IWL50_NUM_QUEUES,
924 .enable_qos = 1,
925 .amsdu_size_8K = 1,
926 .restart_fw = 1,
927 /* the rest are 0 by default */
928 };
929
930
931 struct iwl_cfg iwl5300_agn_cfg = {
932 .name = "5300AGN",
933 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
934 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
935 .ops = &iwl5000_ops,
936 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
937 .mod_params = &iwl50_mod_params,
938 };
939
940 struct iwl_cfg iwl5100_agn_cfg = {
941 .name = "5100AGN",
942 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
943 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
944 .ops = &iwl5000_ops,
945 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
946 .mod_params = &iwl50_mod_params,
947 };
948
949 struct iwl_cfg iwl5350_agn_cfg = {
950 .name = "5350AGN",
951 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
952 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
953 .ops = &iwl5000_ops,
954 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
955 .mod_params = &iwl50_mod_params,
956 };
957
958 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
959 MODULE_PARM_DESC(disable50,
960 "manually disable the 50XX radio (default 0 [radio on])");
961 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
962 MODULE_PARM_DESC(swcrypto50,
963 "using software crypto engine (default 0 [hardware])\n");
964 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
965 MODULE_PARM_DESC(debug50, "50XX debug output mask");
966 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
967 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
968 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
969 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
970 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
971 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
972 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
973 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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