1 /******************************************************************************
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/version.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
40 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
47 #define IWL5000_UCODE_API "-1"
49 static const u16 iwl5000_default_queue_to_tx_fifo
[] = {
59 /* FIXME: same implementation as 4965 */
60 static int iwl5000_apm_stop_master(struct iwl_priv
*priv
)
65 spin_lock_irqsave(&priv
->lock
, flags
);
67 /* set stop master bit */
68 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
70 ret
= iwl_poll_bit(priv
, CSR_RESET
,
71 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
77 spin_unlock_irqrestore(&priv
->lock
, flags
);
78 IWL_DEBUG_INFO("stop master\n");
84 static int iwl5000_apm_init(struct iwl_priv
*priv
)
88 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
89 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
91 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
92 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
93 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
95 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
97 /* set "initialization complete" bit to move adapter
98 * D0U* --> D0A* state */
99 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
101 /* wait for clock stabilization */
102 ret
= iwl_poll_bit(priv
, CSR_GP_CNTRL
,
103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
106 IWL_DEBUG_INFO("Failed to init the card\n");
110 ret
= iwl_grab_nic_access(priv
);
115 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
119 /* disable L1-Active */
120 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
121 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
123 iwl_release_nic_access(priv
);
128 /* FIXME: this is indentical to 4965 */
129 static void iwl5000_apm_stop(struct iwl_priv
*priv
)
133 iwl5000_apm_stop_master(priv
);
135 spin_lock_irqsave(&priv
->lock
, flags
);
137 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
141 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
143 spin_unlock_irqrestore(&priv
->lock
, flags
);
147 static int iwl5000_apm_reset(struct iwl_priv
*priv
)
152 iwl5000_apm_stop_master(priv
);
154 spin_lock_irqsave(&priv
->lock
, flags
);
156 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
161 /* FIXME: put here L1A -L0S w/a */
163 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
165 /* set "initialization complete" bit to move adapter
166 * D0U* --> D0A* state */
167 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
169 /* wait for clock stabilization */
170 ret
= iwl_poll_bit(priv
, CSR_GP_CNTRL
,
171 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
174 IWL_DEBUG_INFO("Failed to init the card\n");
178 ret
= iwl_grab_nic_access(priv
);
183 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
187 /* disable L1-Active */
188 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
189 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
191 iwl_release_nic_access(priv
);
194 spin_unlock_irqrestore(&priv
->lock
, flags
);
200 static void iwl5000_nic_config(struct iwl_priv
*priv
)
206 spin_lock_irqsave(&priv
->lock
, flags
);
208 pci_read_config_byte(priv
->pci_dev
, PCI_LINK_CTRL
, &val_link
);
210 /* L1 is enabled by BIOS */
211 if ((val_link
& PCI_LINK_VAL_L1_EN
) == PCI_LINK_VAL_L1_EN
)
212 /* diable L0S disabled L1A enabled */
213 iwl_set_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
215 /* L0S enabled L1A disabled */
216 iwl_clear_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
218 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
220 /* write radio config values to register */
221 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) < EEPROM_5000_RF_CFG_TYPE_MAX
)
222 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
223 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
224 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
225 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
227 /* set CSR_HW_CONFIG_REG for uCode use */
228 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
229 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
230 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);
232 spin_unlock_irqrestore(&priv
->lock
, flags
);
240 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
244 if ((address
& INDIRECT_ADDRESS
) == 0)
247 switch (address
& INDIRECT_TYPE_MSK
) {
249 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_HOST
);
251 case INDIRECT_GENERAL
:
252 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_GENERAL
);
254 case INDIRECT_REGULATORY
:
255 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_REGULATORY
);
257 case INDIRECT_CALIBRATION
:
258 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_CALIBRATION
);
260 case INDIRECT_PROCESS_ADJST
:
261 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_PROCESS_ADJST
);
263 case INDIRECT_OTHERS
:
264 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_OTHERS
);
267 IWL_ERROR("illegal indirect type: 0x%X\n",
268 address
& INDIRECT_TYPE_MSK
);
272 /* translate the offset from words to byte */
273 return (address
& ADDRESS_MSK
) + (offset
<< 1);
276 static int iwl5000_eeprom_check_version(struct iwl_priv
*priv
)
279 struct iwl_eeprom_calib_hdr
{
285 eeprom_ver
= iwl_eeprom_query16(priv
, EEPROM_VERSION
);
287 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
288 EEPROM_5000_CALIB_ALL
);
290 if (eeprom_ver
< EEPROM_5000_EEPROM_VERSION
||
291 hdr
->version
< EEPROM_5000_TX_POWER_VERSION
)
296 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
297 eeprom_ver
, EEPROM_5000_EEPROM_VERSION
,
298 hdr
->version
, EEPROM_5000_TX_POWER_VERSION
);
303 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
305 static void iwl5000_gain_computation(struct iwl_priv
*priv
,
306 u32 average_noise
[NUM_RX_CHAINS
],
307 u16 min_average_noise_antenna_i
,
308 u32 min_average_noise
)
312 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
314 /* Find Gain Code for the antennas B and C */
315 for (i
= 1; i
< NUM_RX_CHAINS
; i
++) {
316 if ((data
->disconn_array
[i
])) {
317 data
->delta_gain_code
[i
] = 0;
320 delta_g
= (1000 * ((s32
)average_noise
[0] -
321 (s32
)average_noise
[i
])) / 1500;
322 /* bound gain by 2 bits value max, 3rd bit is sign */
323 data
->delta_gain_code
[i
] =
324 min(abs(delta_g
), CHAIN_NOISE_MAX_DELTA_GAIN_CODE
);
327 /* set negative sign */
328 data
->delta_gain_code
[i
] |= (1 << 2);
331 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
332 data
->delta_gain_code
[1], data
->delta_gain_code
[2]);
334 if (!data
->radio_write
) {
335 struct iwl5000_calibration_chain_noise_gain_cmd cmd
;
336 memset(&cmd
, 0, sizeof(cmd
));
338 cmd
.op_code
= IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD
;
339 cmd
.delta_gain_1
= data
->delta_gain_code
[1];
340 cmd
.delta_gain_2
= data
->delta_gain_code
[2];
341 iwl_send_cmd_pdu_async(priv
, REPLY_PHY_CALIBRATION_CMD
,
342 sizeof(cmd
), &cmd
, NULL
);
344 data
->radio_write
= 1;
345 data
->state
= IWL_CHAIN_NOISE_CALIBRATED
;
348 data
->chain_noise_a
= 0;
349 data
->chain_noise_b
= 0;
350 data
->chain_noise_c
= 0;
351 data
->chain_signal_a
= 0;
352 data
->chain_signal_b
= 0;
353 data
->chain_signal_c
= 0;
354 data
->beacon_count
= 0;
358 static void iwl5000_chain_noise_reset(struct iwl_priv
*priv
)
360 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
362 if ((data
->state
== IWL_CHAIN_NOISE_ALIVE
) && iwl_is_associated(priv
)) {
363 struct iwl5000_calibration_chain_noise_reset_cmd cmd
;
365 memset(&cmd
, 0, sizeof(cmd
));
366 cmd
.op_code
= IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD
;
367 if (iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
369 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
370 data
->state
= IWL_CHAIN_NOISE_ACCUMULATE
;
371 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
375 static struct iwl_sensitivity_ranges iwl5000_sensitivity
= {
378 .auto_corr_min_ofdm
= 90,
379 .auto_corr_min_ofdm_mrc
= 170,
380 .auto_corr_min_ofdm_x1
= 120,
381 .auto_corr_min_ofdm_mrc_x1
= 240,
383 .auto_corr_max_ofdm
= 120,
384 .auto_corr_max_ofdm_mrc
= 210,
385 .auto_corr_max_ofdm_x1
= 155,
386 .auto_corr_max_ofdm_mrc_x1
= 290,
388 .auto_corr_min_cck
= 125,
389 .auto_corr_max_cck
= 200,
390 .auto_corr_min_cck_mrc
= 170,
391 .auto_corr_max_cck_mrc
= 400,
396 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
400 static const u8
*iwl5000_eeprom_query_addr(const struct iwl_priv
*priv
,
403 u32 address
= eeprom_indirect_address(priv
, offset
);
404 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
405 return &priv
->eeprom
[address
];
411 static int iwl5000_send_Xtal_calib(struct iwl_priv
*priv
)
413 u16
*xtal_calib
= (u16
*)iwl_eeprom_query_addr(priv
, EEPROM_5000_XTAL
);
415 struct iwl5000_calibration cal_cmd
= {
416 .op_code
= IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
,
423 return iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
424 sizeof(cal_cmd
), &cal_cmd
);
427 static int iwl5000_send_calib_results(struct iwl_priv
*priv
)
431 if (priv
->calib_results
.lo_res
)
432 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
433 priv
->calib_results
.lo_res_len
,
434 priv
->calib_results
.lo_res
);
439 if (priv
->calib_results
.tx_iq_res
)
440 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
441 priv
->calib_results
.tx_iq_res_len
,
442 priv
->calib_results
.tx_iq_res
);
447 if (priv
->calib_results
.tx_iq_perd_res
)
448 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
449 priv
->calib_results
.tx_iq_perd_res_len
,
450 priv
->calib_results
.tx_iq_perd_res
);
456 IWL_ERROR("Error %d\n", ret
);
460 static int iwl5000_send_calib_cfg(struct iwl_priv
*priv
)
462 struct iwl5000_calib_cfg_cmd calib_cfg_cmd
;
463 struct iwl_host_cmd cmd
= {
464 .id
= CALIBRATION_CFG_CMD
,
465 .len
= sizeof(struct iwl5000_calib_cfg_cmd
),
466 .data
= &calib_cfg_cmd
,
469 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
470 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
471 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
472 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
473 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
475 return iwl_send_cmd(priv
, &cmd
);
478 static void iwl5000_rx_calib_result(struct iwl_priv
*priv
,
479 struct iwl_rx_mem_buffer
*rxb
)
481 struct iwl_rx_packet
*pkt
= (void *)rxb
->skb
->data
;
482 struct iwl5000_calib_hdr
*hdr
= (struct iwl5000_calib_hdr
*)pkt
->u
.raw
;
483 int len
= le32_to_cpu(pkt
->len
) & FH_RSCSR_FRAME_SIZE_MSK
;
485 iwl_free_calib_results(priv
);
487 /* reduce the size of the length field itself */
490 switch (hdr
->op_code
) {
491 case IWL5000_PHY_CALIBRATE_LO_CMD
:
492 priv
->calib_results
.lo_res
= kzalloc(len
, GFP_ATOMIC
);
493 priv
->calib_results
.lo_res_len
= len
;
494 memcpy(priv
->calib_results
.lo_res
, pkt
->u
.raw
, len
);
496 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD
:
497 priv
->calib_results
.tx_iq_res
= kzalloc(len
, GFP_ATOMIC
);
498 priv
->calib_results
.tx_iq_res_len
= len
;
499 memcpy(priv
->calib_results
.tx_iq_res
, pkt
->u
.raw
, len
);
501 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
502 priv
->calib_results
.tx_iq_perd_res
= kzalloc(len
, GFP_ATOMIC
);
503 priv
->calib_results
.tx_iq_perd_res_len
= len
;
504 memcpy(priv
->calib_results
.tx_iq_perd_res
, pkt
->u
.raw
, len
);
507 IWL_ERROR("Unknown calibration notification %d\n",
513 static void iwl5000_rx_calib_complete(struct iwl_priv
*priv
,
514 struct iwl_rx_mem_buffer
*rxb
)
516 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
517 queue_work(priv
->workqueue
, &priv
->restart
);
523 static int iwl5000_load_section(struct iwl_priv
*priv
,
524 struct fw_desc
*image
,
530 dma_addr_t phy_addr
= image
->p_addr
;
531 u32 byte_cnt
= image
->len
;
533 spin_lock_irqsave(&priv
->lock
, flags
);
534 ret
= iwl_grab_nic_access(priv
);
536 spin_unlock_irqrestore(&priv
->lock
, flags
);
540 iwl_write_direct32(priv
,
541 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
542 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
544 iwl_write_direct32(priv
,
545 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
547 iwl_write_direct32(priv
,
548 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
549 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
551 /* FIME: write the MSB of the phy_addr in CTRL1
552 * iwl_write_direct32(priv,
553 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
554 ((phy_addr & MSB_MSK)
555 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
557 iwl_write_direct32(priv
,
558 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
), byte_cnt
);
559 iwl_write_direct32(priv
,
560 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
561 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
562 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
563 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
565 iwl_write_direct32(priv
,
566 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
567 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
568 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL
|
569 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
571 iwl_release_nic_access(priv
);
572 spin_unlock_irqrestore(&priv
->lock
, flags
);
576 static int iwl5000_load_given_ucode(struct iwl_priv
*priv
,
577 struct fw_desc
*inst_image
,
578 struct fw_desc
*data_image
)
582 ret
= iwl5000_load_section(
583 priv
, inst_image
, RTC_INST_LOWER_BOUND
);
587 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
588 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
589 priv
->ucode_write_complete
, 5 * HZ
);
590 if (ret
== -ERESTARTSYS
) {
591 IWL_ERROR("Could not load the INST uCode section due "
596 IWL_ERROR("Could not load the INST uCode section\n");
600 priv
->ucode_write_complete
= 0;
602 ret
= iwl5000_load_section(
603 priv
, data_image
, RTC_DATA_LOWER_BOUND
);
607 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
609 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
610 priv
->ucode_write_complete
, 5 * HZ
);
611 if (ret
== -ERESTARTSYS
) {
612 IWL_ERROR("Could not load the INST uCode section due "
616 IWL_ERROR("Could not load the DATA uCode section\n");
621 priv
->ucode_write_complete
= 0;
626 static int iwl5000_load_ucode(struct iwl_priv
*priv
)
630 /* check whether init ucode should be loaded, or rather runtime ucode */
631 if (priv
->ucode_init
.len
&& (priv
->ucode_type
== UCODE_NONE
)) {
632 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
633 ret
= iwl5000_load_given_ucode(priv
,
634 &priv
->ucode_init
, &priv
->ucode_init_data
);
636 IWL_DEBUG_INFO("Init ucode load complete.\n");
637 priv
->ucode_type
= UCODE_INIT
;
640 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
641 "Loading runtime ucode...\n");
642 ret
= iwl5000_load_given_ucode(priv
,
643 &priv
->ucode_code
, &priv
->ucode_data
);
645 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
646 priv
->ucode_type
= UCODE_RT
;
653 static void iwl5000_init_alive_start(struct iwl_priv
*priv
)
657 /* Check alive response for "valid" sign from uCode */
658 if (priv
->card_alive_init
.is_valid
!= UCODE_VALID_OK
) {
659 /* We had an error bringing up the hardware, so take it
660 * all the way back down so we can try again */
661 IWL_DEBUG_INFO("Initialize Alive failed.\n");
665 /* initialize uCode was loaded... verify inst image.
666 * This is a paranoid check, because we would not have gotten the
667 * "initialize" alive if code weren't properly loaded. */
668 if (iwl_verify_ucode(priv
)) {
669 /* Runtime instruction load was bad;
670 * take it all the way back down so we can try again */
671 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
675 iwlcore_clear_stations_table(priv
);
676 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
678 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret
);
682 iwl5000_send_calib_cfg(priv
);
686 /* real restart (first load init_ucode) */
687 queue_work(priv
->workqueue
, &priv
->restart
);
690 static void iwl5000_set_wr_ptrs(struct iwl_priv
*priv
,
691 int txq_id
, u32 index
)
693 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
694 (index
& 0xff) | (txq_id
<< 8));
695 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(txq_id
), index
);
698 static void iwl5000_tx_queue_set_status(struct iwl_priv
*priv
,
699 struct iwl_tx_queue
*txq
,
700 int tx_fifo_id
, int scd_retry
)
702 int txq_id
= txq
->q
.id
;
703 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
)?1:0;
705 iwl_write_prph(priv
, IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
706 (active
<< IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
707 (tx_fifo_id
<< IWL50_SCD_QUEUE_STTS_REG_POS_TXF
) |
708 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL
) |
709 IWL50_SCD_QUEUE_STTS_REG_MSK
);
711 txq
->sched_retry
= scd_retry
;
713 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
714 active
? "Activate" : "Deactivate",
715 scd_retry
? "BA" : "AC", txq_id
, tx_fifo_id
);
718 static int iwl5000_send_wimax_coex(struct iwl_priv
*priv
)
720 struct iwl_wimax_coex_cmd coex_cmd
;
722 memset(&coex_cmd
, 0, sizeof(coex_cmd
));
724 return iwl_send_cmd_pdu(priv
, COEX_PRIORITY_TABLE_CMD
,
725 sizeof(coex_cmd
), &coex_cmd
);
728 static int iwl5000_alive_notify(struct iwl_priv
*priv
)
735 spin_lock_irqsave(&priv
->lock
, flags
);
737 ret
= iwl_grab_nic_access(priv
);
739 spin_unlock_irqrestore(&priv
->lock
, flags
);
743 priv
->scd_base_addr
= iwl_read_prph(priv
, IWL50_SCD_SRAM_BASE_ADDR
);
744 a
= priv
->scd_base_addr
+ IWL50_SCD_CONTEXT_DATA_OFFSET
;
745 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TX_STTS_BITMAP_OFFSET
;
747 iwl_write_targ_mem(priv
, a
, 0);
748 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TRANSLATE_TBL_OFFSET
;
750 iwl_write_targ_mem(priv
, a
, 0);
751 for (; a
< sizeof(u16
) * priv
->hw_params
.max_txq_num
; a
+= 4)
752 iwl_write_targ_mem(priv
, a
, 0);
754 iwl_write_prph(priv
, IWL50_SCD_DRAM_BASE_ADDR
,
756 offsetof(struct iwl5000_shared
, queues_byte_cnt_tbls
)) >> 10);
757 iwl_write_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
,
758 IWL50_SCD_QUEUECHAIN_SEL_ALL(
759 priv
->hw_params
.max_txq_num
));
760 iwl_write_prph(priv
, IWL50_SCD_AGGR_SEL
, 0);
762 /* initiate the queues */
763 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++) {
764 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(i
), 0);
765 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
766 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
767 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
768 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
769 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
) +
772 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
773 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
775 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
776 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
779 iwl_write_prph(priv
, IWL50_SCD_INTERRUPT_MASK
,
780 IWL_MASK(0, priv
->hw_params
.max_txq_num
));
782 /* Activate all Tx DMA/FIFO channels */
783 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, IWL_MASK(0, 7));
785 iwl5000_set_wr_ptrs(priv
, IWL_CMD_QUEUE_NUM
, 0);
786 /* map qos queues to fifos one-to-one */
787 for (i
= 0; i
< ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo
); i
++) {
788 int ac
= iwl5000_default_queue_to_tx_fifo
[i
];
789 iwl_txq_ctx_activate(priv
, i
);
790 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[i
], ac
, 0);
792 /* TODO - need to initialize those FIFOs inside the loop above,
793 * not only mark them as active */
794 iwl_txq_ctx_activate(priv
, 4);
795 iwl_txq_ctx_activate(priv
, 7);
796 iwl_txq_ctx_activate(priv
, 8);
797 iwl_txq_ctx_activate(priv
, 9);
799 iwl_release_nic_access(priv
);
800 spin_unlock_irqrestore(&priv
->lock
, flags
);
803 iwl5000_send_wimax_coex(priv
);
805 iwl5000_send_Xtal_calib(priv
);
807 if (priv
->ucode_type
== UCODE_RT
) {
808 iwl5000_send_calib_results(priv
);
809 set_bit(STATUS_READY
, &priv
->status
);
816 static int iwl5000_hw_set_hw_params(struct iwl_priv
*priv
)
818 if ((priv
->cfg
->mod_params
->num_of_queues
> IWL50_NUM_QUEUES
) ||
819 (priv
->cfg
->mod_params
->num_of_queues
< IWL_MIN_NUM_QUEUES
)) {
820 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
821 IWL_MIN_NUM_QUEUES
, IWL50_NUM_QUEUES
);
825 priv
->hw_params
.max_txq_num
= priv
->cfg
->mod_params
->num_of_queues
;
826 priv
->hw_params
.sw_crypto
= priv
->cfg
->mod_params
->sw_crypto
;
827 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
828 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
829 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
830 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_8K
;
832 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_4K
;
833 priv
->hw_params
.max_pkt_size
= priv
->hw_params
.rx_buf_size
- 256;
834 priv
->hw_params
.max_stations
= IWL5000_STATION_COUNT
;
835 priv
->hw_params
.bcast_sta_id
= IWL5000_BROADCAST_ID
;
836 priv
->hw_params
.max_data_size
= IWL50_RTC_DATA_SIZE
;
837 priv
->hw_params
.max_inst_size
= IWL50_RTC_INST_SIZE
;
838 priv
->hw_params
.max_bsm_size
= BSM_SRAM_SIZE
;
839 priv
->hw_params
.fat_channel
= BIT(IEEE80211_BAND_2GHZ
) |
840 BIT(IEEE80211_BAND_5GHZ
);
841 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
842 priv
->hw_params
.sens
= &iwl5000_sensitivity
;
845 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
846 case CSR_HW_REV_TYPE_5100
:
847 case CSR_HW_REV_TYPE_5150
:
848 priv
->hw_params
.tx_chains_num
= 1;
849 priv
->hw_params
.rx_chains_num
= 2;
850 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
851 priv
->hw_params
.valid_tx_ant
= ANT_A
;
852 priv
->hw_params
.valid_rx_ant
= ANT_AB
;
854 case CSR_HW_REV_TYPE_5300
:
855 case CSR_HW_REV_TYPE_5350
:
856 priv
->hw_params
.tx_chains_num
= 3;
857 priv
->hw_params
.rx_chains_num
= 3;
858 priv
->hw_params
.valid_tx_ant
= ANT_ABC
;
859 priv
->hw_params
.valid_rx_ant
= ANT_ABC
;
863 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
864 case CSR_HW_REV_TYPE_5100
:
865 case CSR_HW_REV_TYPE_5300
:
866 /* 5X00 wants in Celsius */
867 priv
->hw_params
.ct_kill_threshold
= CT_KILL_THRESHOLD
;
869 case CSR_HW_REV_TYPE_5150
:
870 case CSR_HW_REV_TYPE_5350
:
871 /* 5X50 wants in Kelvin */
872 priv
->hw_params
.ct_kill_threshold
=
873 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD
);
880 static int iwl5000_alloc_shared_mem(struct iwl_priv
*priv
)
882 priv
->shared_virt
= pci_alloc_consistent(priv
->pci_dev
,
883 sizeof(struct iwl5000_shared
),
885 if (!priv
->shared_virt
)
888 memset(priv
->shared_virt
, 0, sizeof(struct iwl5000_shared
));
890 priv
->rb_closed_offset
= offsetof(struct iwl5000_shared
, rb_closed
);
895 static void iwl5000_free_shared_mem(struct iwl_priv
*priv
)
897 if (priv
->shared_virt
)
898 pci_free_consistent(priv
->pci_dev
,
899 sizeof(struct iwl5000_shared
),
904 static int iwl5000_shared_mem_rx_idx(struct iwl_priv
*priv
)
906 struct iwl5000_shared
*s
= priv
->shared_virt
;
907 return le32_to_cpu(s
->rb_closed
) & 0xFFF;
911 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
913 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
914 struct iwl_tx_queue
*txq
,
917 struct iwl5000_shared
*shared_data
= priv
->shared_virt
;
918 int txq_id
= txq
->q
.id
;
923 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
925 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
926 sta
= txq
->cmd
[txq
->q
.write_ptr
].cmd
.tx
.sta_id
;
927 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
].cmd
.tx
.sec_ctl
;
929 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
933 case TX_CMD_SEC_TKIP
:
937 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
942 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
943 tfd_offset
[txq
->q
.write_ptr
], byte_cnt
, len
);
945 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
946 tfd_offset
[txq
->q
.write_ptr
], sta_id
, sta
);
948 if (txq
->q
.write_ptr
< IWL50_MAX_WIN_SIZE
) {
949 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
950 tfd_offset
[IWL50_QUEUE_SIZE
+ txq
->q
.write_ptr
],
952 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
953 tfd_offset
[IWL50_QUEUE_SIZE
+ txq
->q
.write_ptr
],
958 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
959 struct iwl_tx_queue
*txq
)
961 int txq_id
= txq
->q
.id
;
962 struct iwl5000_shared
*shared_data
= priv
->shared_virt
;
965 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
966 sta
= txq
->cmd
[txq
->q
.read_ptr
].cmd
.tx
.sta_id
;
968 shared_data
->queues_byte_cnt_tbls
[txq_id
].tfd_offset
[txq
->q
.read_ptr
].
969 val
= cpu_to_le16(1 | (sta
<< 12));
971 if (txq
->q
.write_ptr
< IWL50_MAX_WIN_SIZE
) {
972 shared_data
->queues_byte_cnt_tbls
[txq_id
].
973 tfd_offset
[IWL50_QUEUE_SIZE
+ txq
->q
.read_ptr
].
974 val
= cpu_to_le16(1 | (sta
<< 12));
978 static u16
iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
980 u16 size
= (u16
)sizeof(struct iwl_addsta_cmd
);
981 memcpy(data
, cmd
, size
);
987 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
988 * must be called under priv->lock and mac access
990 static void iwl5000_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
992 iwl_write_prph(priv
, IWL50_SCD_TXFACT
, mask
);
996 static inline u32
iwl5000_get_scd_ssn(struct iwl5000_tx_resp
*tx_resp
)
998 __le32
*scd_ssn
= (__le32
*)((u32
*)&tx_resp
->status
+
999 tx_resp
->frame_count
);
1000 return le32_to_cpu(*scd_ssn
) & MAX_SN
;
1004 static int iwl5000_tx_status_reply_tx(struct iwl_priv
*priv
,
1005 struct iwl_ht_agg
*agg
,
1006 struct iwl5000_tx_resp
*tx_resp
,
1010 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
1011 struct ieee80211_tx_info
*info
= NULL
;
1012 struct ieee80211_hdr
*hdr
= NULL
;
1017 if (agg
->wait_for_ba
)
1018 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1020 agg
->frame_count
= tx_resp
->frame_count
;
1021 agg
->start_idx
= start_idx
;
1022 agg
->rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
1025 /* # frames attempted by Tx command */
1026 if (agg
->frame_count
== 1) {
1027 /* Only one frame was attempted; no block-ack will arrive */
1028 status
= le16_to_cpu(frame_status
[0].status
);
1029 seq
= le16_to_cpu(frame_status
[0].sequence
);
1030 idx
= SEQ_TO_INDEX(seq
);
1031 txq_id
= SEQ_TO_QUEUE(seq
);
1033 /* FIXME: code repetition */
1034 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1035 agg
->frame_count
, agg
->start_idx
, idx
);
1037 info
= IEEE80211_SKB_CB(priv
->txq
[txq_id
].txb
[idx
].skb
[0]);
1038 info
->status
.retry_count
= tx_resp
->failure_frame
;
1039 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
1040 info
->flags
|= iwl_is_tx_success(status
)?
1041 IEEE80211_TX_STAT_ACK
: 0;
1042 iwl4965_hwrate_to_tx_control(priv
,
1043 le32_to_cpu(tx_resp
->rate_n_flags
),
1045 /* FIXME: code repetition end */
1047 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1048 status
& 0xff, tx_resp
->failure_frame
);
1049 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
1050 iwl4965_hw_get_rate_n_flags(tx_resp
->rate_n_flags
));
1052 agg
->wait_for_ba
= 0;
1054 /* Two or more frames were attempted; expect block-ack */
1056 int start
= agg
->start_idx
;
1058 /* Construct bit-map of pending frames within Tx window */
1059 for (i
= 0; i
< agg
->frame_count
; i
++) {
1061 status
= le16_to_cpu(frame_status
[i
].status
);
1062 seq
= le16_to_cpu(frame_status
[i
].sequence
);
1063 idx
= SEQ_TO_INDEX(seq
);
1064 txq_id
= SEQ_TO_QUEUE(seq
);
1066 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
1067 AGG_TX_STATE_ABORT_MSK
))
1070 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1071 agg
->frame_count
, txq_id
, idx
);
1073 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
1075 sc
= le16_to_cpu(hdr
->seq_ctrl
);
1076 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
1077 IWL_ERROR("BUG_ON idx doesn't match seq control"
1078 " idx=%d, seq_idx=%d, seq=%d\n",
1084 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1085 i
, idx
, SEQ_TO_SN(sc
));
1089 sh
= (start
- idx
) + 0xff;
1090 bitmap
= bitmap
<< sh
;
1093 } else if (sh
< -64)
1094 sh
= 0xff - (start
- idx
);
1098 bitmap
= bitmap
<< sh
;
1101 bitmap
|= (1 << sh
);
1102 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1103 start
, (u32
)(bitmap
& 0xFFFFFFFF));
1106 agg
->bitmap
= bitmap
;
1107 agg
->start_idx
= start
;
1108 agg
->rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
1109 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1110 agg
->frame_count
, agg
->start_idx
,
1111 (unsigned long long)agg
->bitmap
);
1114 agg
->wait_for_ba
= 1;
1119 static void iwl5000_rx_reply_tx(struct iwl_priv
*priv
,
1120 struct iwl_rx_mem_buffer
*rxb
)
1122 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1123 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1124 int txq_id
= SEQ_TO_QUEUE(sequence
);
1125 int index
= SEQ_TO_INDEX(sequence
);
1126 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1127 struct ieee80211_tx_info
*info
;
1128 struct iwl5000_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
1129 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
1130 #ifdef CONFIG_IWL4965_HT
1131 int tid
= MAX_TID_COUNT
, sta_id
= IWL_INVALID_STATION
;
1133 struct ieee80211_hdr
*hdr
;
1137 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
1138 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1139 "is out of range [0-%d] %d %d\n", txq_id
,
1140 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
1145 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
1146 memset(&info
->status
, 0, sizeof(info
->status
));
1148 #ifdef CONFIG_IWL4965_HT
1149 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, index
);
1150 fc
= le16_to_cpu(hdr
->frame_control
);
1151 if (ieee80211_is_qos_data(fc
)) {
1152 qc
= ieee80211_get_qos_ctrl(hdr
, ieee80211_get_hdrlen(fc
));
1156 sta_id
= iwl_get_ra_sta_id(priv
, hdr
);
1157 if (txq
->sched_retry
&& unlikely(sta_id
== IWL_INVALID_STATION
)) {
1158 IWL_ERROR("Station not known\n");
1162 if (txq
->sched_retry
) {
1163 const u32 scd_ssn
= iwl5000_get_scd_ssn(tx_resp
);
1164 struct iwl_ht_agg
*agg
= NULL
;
1169 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1171 iwl5000_tx_status_reply_tx(priv
, agg
, tx_resp
, index
);
1173 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
)) {
1174 /* TODO: send BAR */
1177 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
1179 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
1180 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1181 "%d index %d\n", scd_ssn
, index
);
1182 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1183 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1185 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1186 txq_id
>= 0 && priv
->mac80211_registered
&&
1187 agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
) {
1188 /* calculate mac80211 ampdu sw queue to wake */
1189 ampdu_q
= txq_id
- IWL_BACK_QUEUE_FIRST_ID
+
1191 if (agg
->state
== IWL_AGG_OFF
)
1192 ieee80211_wake_queue(priv
->hw
, txq_id
);
1194 ieee80211_wake_queue(priv
->hw
, ampdu_q
);
1196 iwl4965_check_empty_hw_queue(priv
, sta_id
, tid
, txq_id
);
1199 #endif /* CONFIG_IWL4965_HT */
1201 info
->status
.retry_count
= tx_resp
->failure_frame
;
1202 info
->flags
= iwl_is_tx_success(status
) ? IEEE80211_TX_STAT_ACK
: 0;
1203 iwl4965_hwrate_to_tx_control(priv
, le32_to_cpu(tx_resp
->rate_n_flags
),
1206 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
1207 "retries %d\n", txq_id
, iwl_get_tx_fail_reason(status
),
1208 status
, le32_to_cpu(tx_resp
->rate_n_flags
),
1209 tx_resp
->failure_frame
);
1211 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index
);
1212 #ifdef CONFIG_IWL4965_HT
1214 int freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1215 if (tid
!= MAX_TID_COUNT
)
1216 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1217 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1218 (txq_id
>= 0) && priv
->mac80211_registered
)
1219 ieee80211_wake_queue(priv
->hw
, txq_id
);
1220 if (tid
!= MAX_TID_COUNT
)
1221 iwl4965_check_empty_hw_queue(priv
, sta_id
, tid
, txq_id
);
1224 #endif /* CONFIG_IWL4965_HT */
1226 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
1227 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1230 /* Currently 5000 is the supperset of everything */
1231 static u16
iwl5000_get_hcmd_size(u8 cmd_id
, u16 len
)
1236 static void iwl5000_rx_handler_setup(struct iwl_priv
*priv
)
1238 /* init calibration handlers */
1239 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
1240 iwl5000_rx_calib_result
;
1241 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
1242 iwl5000_rx_calib_complete
;
1243 priv
->rx_handlers
[REPLY_TX
] = iwl5000_rx_reply_tx
;
1247 static int iwl5000_hw_valid_rtc_data_addr(u32 addr
)
1249 return (addr
>= RTC_DATA_LOWER_BOUND
) &&
1250 (addr
< IWL50_RTC_DATA_UPPER_BOUND
);
1253 static int iwl5000_send_rxon_assoc(struct iwl_priv
*priv
)
1256 struct iwl5000_rxon_assoc_cmd rxon_assoc
;
1257 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1258 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1260 if ((rxon1
->flags
== rxon2
->flags
) &&
1261 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1262 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1263 (rxon1
->ofdm_ht_single_stream_basic_rates
==
1264 rxon2
->ofdm_ht_single_stream_basic_rates
) &&
1265 (rxon1
->ofdm_ht_dual_stream_basic_rates
==
1266 rxon2
->ofdm_ht_dual_stream_basic_rates
) &&
1267 (rxon1
->ofdm_ht_triple_stream_basic_rates
==
1268 rxon2
->ofdm_ht_triple_stream_basic_rates
) &&
1269 (rxon1
->acquisition_data
== rxon2
->acquisition_data
) &&
1270 (rxon1
->rx_chain
== rxon2
->rx_chain
) &&
1271 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1272 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1276 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1277 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1278 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1279 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1280 rxon_assoc
.reserved1
= 0;
1281 rxon_assoc
.reserved2
= 0;
1282 rxon_assoc
.reserved3
= 0;
1283 rxon_assoc
.ofdm_ht_single_stream_basic_rates
=
1284 priv
->staging_rxon
.ofdm_ht_single_stream_basic_rates
;
1285 rxon_assoc
.ofdm_ht_dual_stream_basic_rates
=
1286 priv
->staging_rxon
.ofdm_ht_dual_stream_basic_rates
;
1287 rxon_assoc
.rx_chain_select_flags
= priv
->staging_rxon
.rx_chain
;
1288 rxon_assoc
.ofdm_ht_triple_stream_basic_rates
=
1289 priv
->staging_rxon
.ofdm_ht_triple_stream_basic_rates
;
1290 rxon_assoc
.acquisition_data
= priv
->staging_rxon
.acquisition_data
;
1292 ret
= iwl_send_cmd_pdu_async(priv
, REPLY_RXON_ASSOC
,
1293 sizeof(rxon_assoc
), &rxon_assoc
, NULL
);
1300 static struct iwl_hcmd_ops iwl5000_hcmd
= {
1301 .rxon_assoc
= iwl5000_send_rxon_assoc
,
1304 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils
= {
1305 .get_hcmd_size
= iwl5000_get_hcmd_size
,
1306 .build_addsta_hcmd
= iwl5000_build_addsta_hcmd
,
1307 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
1308 .gain_computation
= iwl5000_gain_computation
,
1309 .chain_noise_reset
= iwl5000_chain_noise_reset
,
1313 static struct iwl_lib_ops iwl5000_lib
= {
1314 .set_hw_params
= iwl5000_hw_set_hw_params
,
1315 .alloc_shared_mem
= iwl5000_alloc_shared_mem
,
1316 .free_shared_mem
= iwl5000_free_shared_mem
,
1317 .shared_mem_rx_idx
= iwl5000_shared_mem_rx_idx
,
1318 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1319 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1320 .txq_set_sched
= iwl5000_txq_set_sched
,
1321 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1322 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1323 .load_ucode
= iwl5000_load_ucode
,
1324 .init_alive_start
= iwl5000_init_alive_start
,
1325 .alive_notify
= iwl5000_alive_notify
,
1327 .init
= iwl5000_apm_init
,
1328 .reset
= iwl5000_apm_reset
,
1329 .stop
= iwl5000_apm_stop
,
1330 .config
= iwl5000_nic_config
,
1331 .set_pwr_src
= iwl4965_set_pwr_src
,
1334 .regulatory_bands
= {
1335 EEPROM_5000_REG_BAND_1_CHANNELS
,
1336 EEPROM_5000_REG_BAND_2_CHANNELS
,
1337 EEPROM_5000_REG_BAND_3_CHANNELS
,
1338 EEPROM_5000_REG_BAND_4_CHANNELS
,
1339 EEPROM_5000_REG_BAND_5_CHANNELS
,
1340 EEPROM_5000_REG_BAND_24_FAT_CHANNELS
,
1341 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1343 .verify_signature
= iwlcore_eeprom_verify_signature
,
1344 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1345 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1346 .check_version
= iwl5000_eeprom_check_version
,
1347 .query_addr
= iwl5000_eeprom_query_addr
,
1351 static struct iwl_ops iwl5000_ops
= {
1352 .lib
= &iwl5000_lib
,
1353 .hcmd
= &iwl5000_hcmd
,
1354 .utils
= &iwl5000_hcmd_utils
,
1357 static struct iwl_mod_params iwl50_mod_params
= {
1358 .num_of_queues
= IWL50_NUM_QUEUES
,
1362 /* the rest are 0 by default */
1366 struct iwl_cfg iwl5300_agn_cfg
= {
1368 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
1369 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1370 .ops
= &iwl5000_ops
,
1371 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1372 .mod_params
= &iwl50_mod_params
,
1375 struct iwl_cfg iwl5100_agn_cfg
= {
1377 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
1378 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1379 .ops
= &iwl5000_ops
,
1380 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1381 .mod_params
= &iwl50_mod_params
,
1384 struct iwl_cfg iwl5350_agn_cfg
= {
1386 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
1387 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1388 .ops
= &iwl5000_ops
,
1389 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1390 .mod_params
= &iwl50_mod_params
,
1393 module_param_named(disable50
, iwl50_mod_params
.disable
, int, 0444);
1394 MODULE_PARM_DESC(disable50
,
1395 "manually disable the 50XX radio (default 0 [radio on])");
1396 module_param_named(swcrypto50
, iwl50_mod_params
.sw_crypto
, bool, 0444);
1397 MODULE_PARM_DESC(swcrypto50
,
1398 "using software crypto engine (default 0 [hardware])\n");
1399 module_param_named(debug50
, iwl50_mod_params
.debug
, int, 0444);
1400 MODULE_PARM_DESC(debug50
, "50XX debug output mask");
1401 module_param_named(queues_num50
, iwl50_mod_params
.num_of_queues
, int, 0444);
1402 MODULE_PARM_DESC(queues_num50
, "number of hw queues in 50xx series");
1403 module_param_named(qos_enable50
, iwl50_mod_params
.enable_qos
, int, 0444);
1404 MODULE_PARM_DESC(qos_enable50
, "enable all 50XX QoS functionality");
1405 module_param_named(amsdu_size_8K50
, iwl50_mod_params
.amsdu_size_8K
, int, 0444);
1406 MODULE_PARM_DESC(amsdu_size_8K50
, "enable 8K amsdu size in 50XX series");
1407 module_param_named(fw_restart50
, iwl50_mod_params
.restart_fw
, int, 0444);
1408 MODULE_PARM_DESC(fw_restart50
, "restart firmware in case of error");