drivers/net/wireless/iwlwifi/iwl-agn-ict.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/sched.h>
  33 #include <net/mac80211.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-agn.h"
  38 #include "iwl-helpers.h"
  39
  40 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  41
  42 /* Free dram table */
  43 void iwl_free_isr_ict(struct iwl_priv *priv)
  44 {
  45         if (priv->_agn.ict_tbl_vir) {
  46                 dma_free_coherent(&priv->pci_dev->dev,
  47                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
  48                                   priv->_agn.ict_tbl_vir,
  49                                   priv->_agn.ict_tbl_dma);
  50                 priv->_agn.ict_tbl_vir = NULL;
  51         }
  52 }
  53
  54
  55 /* allocate dram shared table it is a PAGE_SIZE aligned
  56  * also reset all data related to ICT table interrupt.
  57  */
  58 int iwl_alloc_isr_ict(struct iwl_priv *priv)
  59 {
  60
  61         if (priv->cfg->use_isr_legacy)
  62                 return 0;
  63         /* allocate shrared data table */
  64         priv->_agn.ict_tbl_vir =
  65                 dma_alloc_coherent(&priv->pci_dev->dev,
  66                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
  67                                    &priv->_agn.ict_tbl_dma, GFP_KERNEL);
  68         if (!priv->_agn.ict_tbl_vir)
  69                 return -ENOMEM;
  70
  71         /* align table to PAGE_SIZE boundry */
  72         priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE);
  73
  74         IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  75                              (unsigned long long)priv->_agn.ict_tbl_dma,
  76                              (unsigned long long)priv->_agn.aligned_ict_tbl_dma,
  77                         (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
  78
  79         priv->_agn.ict_tbl =  priv->_agn.ict_tbl_vir +
  80                           (priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma);
  81
  82         IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  83                              priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir,
  84                         (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
  85
  86         /* reset table and index to all 0 */
  87         memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  88         priv->_agn.ict_index = 0;
  89
  90         /* add periodic RX interrupt */
  91         priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  92         return 0;
  93 }
  94
  95 /* Device is going up inform it about using ICT interrupt table,
  96  * also we need to tell the driver to start using ICT interrupt.
  97  */
  98 int iwl_reset_ict(struct iwl_priv *priv)
  99 {
 100         u32 val;
 101         unsigned long flags;
 102
 103         if (!priv->_agn.ict_tbl_vir)
 104                 return 0;
 105
 106         spin_lock_irqsave(&priv->lock, flags);
 107         iwl_disable_interrupts(priv);
 108
 109         memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
 110
 111         val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT;
 112
 113         val |= CSR_DRAM_INT_TBL_ENABLE;
 114         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 115
 116         IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
 117                         "aligned dma address %Lx\n",
 118                         val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma);
 119
 120         iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
 121         priv->_agn.use_ict = true;
 122         priv->_agn.ict_index = 0;
 123         iwl_write32(priv, CSR_INT, priv->inta_mask);
 124         iwl_enable_interrupts(priv);
 125         spin_unlock_irqrestore(&priv->lock, flags);
 126
 127         return 0;
 128 }
 129
 130 /* Device is going down disable ict interrupt usage */
 131 void iwl_disable_ict(struct iwl_priv *priv)
 132 {
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&priv->lock, flags);
 136         priv->_agn.use_ict = false;
 137         spin_unlock_irqrestore(&priv->lock, flags);
 138 }
 139
 140 static irqreturn_t iwl_isr(int irq, void *data)
 141 {
 142         struct iwl_priv *priv = data;
 143         u32 inta, inta_mask;
 144         unsigned long flags;
 145 #ifdef CONFIG_IWLWIFI_DEBUG
 146         u32 inta_fh;
 147 #endif
 148         if (!priv)
 149                 return IRQ_NONE;
 150
 151         spin_lock_irqsave(&priv->lock, flags);
 152
 153         /* Disable (but don't clear!) interrupts here to avoid
 154          *    back-to-back ISRs and sporadic interrupts from our NIC.
 155          * If we have something to service, the tasklet will re-enable ints.
 156          * If we *don't* have something, we'll re-enable before leaving here. */
 157         inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
 158         iwl_write32(priv, CSR_INT_MASK, 0x00000000);
 159
 160         /* Discover which interrupts are active/pending */
 161         inta = iwl_read32(priv, CSR_INT);
 162
 163         /* Ignore interrupt if there's nothing in NIC to service.
 164          * This may be due to IRQ shared with another device,
 165          * or due to sporadic interrupts thrown from our NIC. */
 166         if (!inta) {
 167                 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
 168                 goto none;
 169         }
 170
 171         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 172                 /* Hardware disappeared. It might have already raised
 173                  * an interrupt */
 174                 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 175                 goto unplugged;
 176         }
 177
 178 #ifdef CONFIG_IWLWIFI_DEBUG
 179         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
 180                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
 181                 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
 182                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 183         }
 184 #endif
 185
 186         priv->_agn.inta |= inta;
 187         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 188         if (likely(inta))
 189                 tasklet_schedule(&priv->irq_tasklet);
 190         else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
 191                 iwl_enable_interrupts(priv);
 192
 193  unplugged:
 194         spin_unlock_irqrestore(&priv->lock, flags);
 195         return IRQ_HANDLED;
 196
 197  none:
 198         /* re-enable interrupts here since we don't have anything to service. */
 199         /* only Re-enable if diabled by irq  and no schedules tasklet. */
 200         if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
 201                 iwl_enable_interrupts(priv);
 202
 203         spin_unlock_irqrestore(&priv->lock, flags);
 204         return IRQ_NONE;
 205 }
 206
 207 /* interrupt handler using ict table, with this interrupt driver will
 208  * stop using INTA register to get device's interrupt, reading this register
 209  * is expensive, device will write interrupts in ICT dram table, increment
 210  * index then will fire interrupt to driver, driver will OR all ICT table
 211  * entries from current index up to table entry with 0 value. the result is
 212  * the interrupt we need to service, driver will set the entries back to 0 and
 213  * set index.
 214  */
 215 irqreturn_t iwl_isr_ict(int irq, void *data)
 216 {
 217         struct iwl_priv *priv = data;
 218         u32 inta, inta_mask;
 219         u32 val = 0;
 220         unsigned long flags;
 221
 222         if (!priv)
 223                 return IRQ_NONE;
 224
 225         /* dram interrupt table not set yet,
 226          * use legacy interrupt.
 227          */
 228         if (!priv->_agn.use_ict)
 229                 return iwl_isr(irq, data);
 230
 231         spin_lock_irqsave(&priv->lock, flags);
 232
 233         /* Disable (but don't clear!) interrupts here to avoid
 234          * back-to-back ISRs and sporadic interrupts from our NIC.
 235          * If we have something to service, the tasklet will re-enable ints.
 236          * If we *don't* have something, we'll re-enable before leaving here.
 237          */
 238         inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
 239         iwl_write32(priv, CSR_INT_MASK, 0x00000000);
 240
 241
 242         /* Ignore interrupt if there's nothing in NIC to service.
 243          * This may be due to IRQ shared with another device,
 244          * or due to sporadic interrupts thrown from our NIC. */
 245         if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) {
 246                 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
 247                 goto none;
 248         }
 249
 250         /* read all entries that not 0 start with ict_index */
 251         while (priv->_agn.ict_tbl[priv->_agn.ict_index]) {
 252
 253                 val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]);
 254                 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
 255                                 priv->_agn.ict_index,
 256                                 le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]));
 257                 priv->_agn.ict_tbl[priv->_agn.ict_index] = 0;
 258                 priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index,
 259                                                      ICT_COUNT);
 260
 261         }
 262
 263         /* We should not get this value, just ignore it. */
 264         if (val == 0xffffffff)
 265                 val = 0;
 266
 267         /*
 268          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
 269          * (bit 15 before shifting it to 31) to clear when using interrupt
 270          * coalescing. fortunately, bits 18 and 19 stay set when this happens
 271          * so we use them to decide on the real state of the Rx bit.
 272          * In order words, bit 15 is set if bit 18 or bit 19 are set.
 273          */
 274         if (val & 0xC0000)
 275                 val |= 0x8000;
 276
 277         inta = (0xff & val) | ((0xff00 & val) << 16);
 278         IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
 279                         inta, inta_mask, val);
 280
 281         inta &= priv->inta_mask;
 282         priv->_agn.inta |= inta;
 283
 284         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 285         if (likely(inta))
 286                 tasklet_schedule(&priv->irq_tasklet);
 287         else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) {
 288                 /* Allow interrupt if was disabled by this handler and
 289                  * no tasklet was schedules, We should not enable interrupt,
 290                  * tasklet will enable it.
 291                  */
 292                 iwl_enable_interrupts(priv);
 293         }
 294
 295         spin_unlock_irqrestore(&priv->lock, flags);
 296         return IRQ_HANDLED;
 297
 298  none:
 299         /* re-enable interrupts here since we don't have anything to service.
 300          * only Re-enable if disabled by irq.
 301          */
 302         if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
 303                 iwl_enable_interrupts(priv);
 304
 305         spin_unlock_irqrestore(&priv->lock, flags);
 306         return IRQ_NONE;
 307 }