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[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_FW_DROP:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_STA_COLOR_MISMATCH_DROP:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_set_tx_status(struct iwl_priv *priv,
127 struct ieee80211_tx_info *info,
128 struct iwl5000_tx_resp *tx_resp,
129 int txq_id, bool is_agg)
130 {
131 u16 status = le16_to_cpu(tx_resp->status.status);
132
133 info->status.rates[0].count = tx_resp->failure_frame + 1;
134 if (is_agg)
135 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
136 info->flags |= iwl_tx_status_to_mac80211(status);
137 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
138 info);
139 if (!iwl_is_tx_success(status))
140 iwlagn_count_tx_err_status(priv, status);
141
142 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
143 "0x%x retries %d\n",
144 txq_id,
145 iwl_get_tx_fail_reason(status), status,
146 le32_to_cpu(tx_resp->rate_n_flags),
147 tx_resp->failure_frame);
148 }
149
150 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
151 struct iwl_ht_agg *agg,
152 struct iwl5000_tx_resp *tx_resp,
153 int txq_id, u16 start_idx)
154 {
155 u16 status;
156 struct agg_tx_status *frame_status = &tx_resp->status;
157 struct ieee80211_hdr *hdr = NULL;
158 int i, sh, idx;
159 u16 seq;
160
161 if (agg->wait_for_ba)
162 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
163
164 agg->frame_count = tx_resp->frame_count;
165 agg->start_idx = start_idx;
166 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
167 agg->bitmap = 0;
168
169 /* # frames attempted by Tx command */
170 if (agg->frame_count == 1) {
171 /* Only one frame was attempted; no block-ack will arrive */
172 idx = start_idx;
173
174 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
175 agg->frame_count, agg->start_idx, idx);
176 iwlagn_set_tx_status(priv,
177 IEEE80211_SKB_CB(
178 priv->txq[txq_id].txb[idx].skb),
179 tx_resp, txq_id, true);
180 agg->wait_for_ba = 0;
181 } else {
182 /* Two or more frames were attempted; expect block-ack */
183 u64 bitmap = 0;
184
185 /*
186 * Start is the lowest frame sent. It may not be the first
187 * frame in the batch; we figure this out dynamically during
188 * the following loop.
189 */
190 int start = agg->start_idx;
191
192 /* Construct bit-map of pending frames within Tx window */
193 for (i = 0; i < agg->frame_count; i++) {
194 u16 sc;
195 status = le16_to_cpu(frame_status[i].status);
196 seq = le16_to_cpu(frame_status[i].sequence);
197 idx = SEQ_TO_INDEX(seq);
198 txq_id = SEQ_TO_QUEUE(seq);
199
200 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
201 AGG_TX_STATE_ABORT_MSK))
202 continue;
203
204 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
205 agg->frame_count, txq_id, idx);
206
207 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
208 if (!hdr) {
209 IWL_ERR(priv,
210 "BUG_ON idx doesn't point to valid skb"
211 " idx=%d, txq_id=%d\n", idx, txq_id);
212 return -1;
213 }
214
215 sc = le16_to_cpu(hdr->seq_ctrl);
216 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
217 IWL_ERR(priv,
218 "BUG_ON idx doesn't match seq control"
219 " idx=%d, seq_idx=%d, seq=%d\n",
220 idx, SEQ_TO_SN(sc),
221 hdr->seq_ctrl);
222 return -1;
223 }
224
225 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
226 i, idx, SEQ_TO_SN(sc));
227
228 /*
229 * sh -> how many frames ahead of the starting frame is
230 * the current one?
231 *
232 * Note that all frames sent in the batch must be in a
233 * 64-frame window, so this number should be in [0,63].
234 * If outside of this window, then we've found a new
235 * "first" frame in the batch and need to change start.
236 */
237 sh = idx - start;
238
239 /*
240 * If >= 64, out of window. start must be at the front
241 * of the circular buffer, idx must be near the end of
242 * the buffer, and idx is the new "first" frame. Shift
243 * the indices around.
244 */
245 if (sh >= 64) {
246 /* Shift bitmap by start - idx, wrapped */
247 sh = 0x100 - idx + start;
248 bitmap = bitmap << sh;
249 /* Now idx is the new start so sh = 0 */
250 sh = 0;
251 start = idx;
252 /*
253 * If <= -64 then wraps the 256-pkt circular buffer
254 * (e.g., start = 255 and idx = 0, sh should be 1)
255 */
256 } else if (sh <= -64) {
257 sh = 0x100 - start + idx;
258 /*
259 * If < 0 but > -64, out of window. idx is before start
260 * but not wrapped. Shift the indices around.
261 */
262 } else if (sh < 0) {
263 /* Shift by how far start is ahead of idx */
264 sh = start - idx;
265 bitmap = bitmap << sh;
266 /* Now idx is the new start so sh = 0 */
267 start = idx;
268 sh = 0;
269 }
270 /* Sequence number start + sh was sent in this batch */
271 bitmap |= 1ULL << sh;
272 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
273 start, (unsigned long long)bitmap);
274 }
275
276 /*
277 * Store the bitmap and possibly the new start, if we wrapped
278 * the buffer above
279 */
280 agg->bitmap = bitmap;
281 agg->start_idx = start;
282 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
283 agg->frame_count, agg->start_idx,
284 (unsigned long long)agg->bitmap);
285
286 if (bitmap)
287 agg->wait_for_ba = 1;
288 }
289 return 0;
290 }
291
292 void iwl_check_abort_status(struct iwl_priv *priv,
293 u8 frame_count, u32 status)
294 {
295 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
296 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
297 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
298 queue_work(priv->workqueue, &priv->tx_flush);
299 }
300 }
301
302 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
303 struct iwl_rx_mem_buffer *rxb)
304 {
305 struct iwl_rx_packet *pkt = rxb_addr(rxb);
306 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
307 int txq_id = SEQ_TO_QUEUE(sequence);
308 int index = SEQ_TO_INDEX(sequence);
309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
310 struct ieee80211_tx_info *info;
311 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
312 u32 status = le16_to_cpu(tx_resp->status.status);
313 int tid;
314 int sta_id;
315 int freed;
316 unsigned long flags;
317
318 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
319 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
320 "is out of range [0-%d] %d %d\n", txq_id,
321 index, txq->q.n_bd, txq->q.write_ptr,
322 txq->q.read_ptr);
323 return;
324 }
325
326 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
327 memset(&info->status, 0, sizeof(info->status));
328
329 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
330 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
331
332 spin_lock_irqsave(&priv->sta_lock, flags);
333 if (txq->sched_retry) {
334 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
335 struct iwl_ht_agg *agg;
336
337 agg = &priv->stations[sta_id].tid[tid].agg;
338 /*
339 * If the BT kill count is non-zero, we'll get this
340 * notification again.
341 */
342 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
343 priv->cfg->advanced_bt_coexist) {
344 IWL_WARN(priv, "receive reply tx with bt_kill\n");
345 }
346 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
347
348 /* check if BAR is needed */
349 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
350 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
351
352 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
353 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
354 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
355 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
356 scd_ssn , index, txq_id, txq->swq_id);
357
358 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
359 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
360
361 if (priv->mac80211_registered &&
362 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
363 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
364 if (agg->state == IWL_AGG_OFF)
365 iwl_wake_queue(priv, txq_id);
366 else
367 iwl_wake_queue(priv, txq->swq_id);
368 }
369 }
370 } else {
371 BUG_ON(txq_id != txq->swq_id);
372 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
373 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
374 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
375
376 if (priv->mac80211_registered &&
377 (iwl_queue_space(&txq->q) > txq->q.low_mark))
378 iwl_wake_queue(priv, txq_id);
379 }
380
381 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
382
383 iwl_check_abort_status(priv, tx_resp->frame_count, status);
384 spin_unlock_irqrestore(&priv->sta_lock, flags);
385 }
386
387 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
388 {
389 /* init calibration handlers */
390 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
391 iwlagn_rx_calib_result;
392 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
393 iwlagn_rx_calib_complete;
394 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
395 }
396
397 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
398 {
399 /* in agn, the tx power calibration is done in uCode */
400 priv->disable_tx_power_cal = 1;
401 }
402
403 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
404 {
405 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
406 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
407 }
408
409 int iwlagn_send_tx_power(struct iwl_priv *priv)
410 {
411 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
412 u8 tx_ant_cfg_cmd;
413
414 /* half dBm need to multiply */
415 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
416
417 if (priv->tx_power_lmt_in_half_dbm &&
418 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
419 /*
420 * For the newer devices which using enhanced/extend tx power
421 * table in EEPROM, the format is in half dBm. driver need to
422 * convert to dBm format before report to mac80211.
423 * By doing so, there is a possibility of 1/2 dBm resolution
424 * lost. driver will perform "round-up" operation before
425 * reporting, but it will cause 1/2 dBm tx power over the
426 * regulatory limit. Perform the checking here, if the
427 * "tx_power_user_lmt" is higher than EEPROM value (in
428 * half-dBm format), lower the tx power based on EEPROM
429 */
430 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
431 }
432 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
433 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
434
435 if (IWL_UCODE_API(priv->ucode_ver) == 1)
436 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
437 else
438 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
439
440 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
441 sizeof(tx_power_cmd), &tx_power_cmd,
442 NULL);
443 }
444
445 void iwlagn_temperature(struct iwl_priv *priv)
446 {
447 /* store temperature from statistics (in Celsius) */
448 priv->temperature =
449 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
450 iwl_tt_handler(priv);
451 }
452
453 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
454 {
455 struct iwl_eeprom_calib_hdr {
456 u8 version;
457 u8 pa_type;
458 u16 voltage;
459 } *hdr;
460
461 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
462 EEPROM_CALIB_ALL);
463 return hdr->version;
464
465 }
466
467 /*
468 * EEPROM
469 */
470 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
471 {
472 u16 offset = 0;
473
474 if ((address & INDIRECT_ADDRESS) == 0)
475 return address;
476
477 switch (address & INDIRECT_TYPE_MSK) {
478 case INDIRECT_HOST:
479 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
480 break;
481 case INDIRECT_GENERAL:
482 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
483 break;
484 case INDIRECT_REGULATORY:
485 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
486 break;
487 case INDIRECT_CALIBRATION:
488 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
489 break;
490 case INDIRECT_PROCESS_ADJST:
491 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
492 break;
493 case INDIRECT_OTHERS:
494 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
495 break;
496 default:
497 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
498 address & INDIRECT_TYPE_MSK);
499 break;
500 }
501
502 /* translate the offset from words to byte */
503 return (address & ADDRESS_MSK) + (offset << 1);
504 }
505
506 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
507 size_t offset)
508 {
509 u32 address = eeprom_indirect_address(priv, offset);
510 BUG_ON(address >= priv->cfg->eeprom_size);
511 return &priv->eeprom[address];
512 }
513
514 struct iwl_mod_params iwlagn_mod_params = {
515 .amsdu_size_8K = 1,
516 .restart_fw = 1,
517 /* the rest are 0 by default */
518 };
519
520 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
521 {
522 unsigned long flags;
523 int i;
524 spin_lock_irqsave(&rxq->lock, flags);
525 INIT_LIST_HEAD(&rxq->rx_free);
526 INIT_LIST_HEAD(&rxq->rx_used);
527 /* Fill the rx_used queue with _all_ of the Rx buffers */
528 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
529 /* In the reset function, these buffers may have been allocated
530 * to an SKB, so we need to unmap and free potential storage */
531 if (rxq->pool[i].page != NULL) {
532 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
533 PAGE_SIZE << priv->hw_params.rx_page_order,
534 PCI_DMA_FROMDEVICE);
535 __iwl_free_pages(priv, rxq->pool[i].page);
536 rxq->pool[i].page = NULL;
537 }
538 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
539 }
540
541 for (i = 0; i < RX_QUEUE_SIZE; i++)
542 rxq->queue[i] = NULL;
543
544 /* Set us so that we have processed and used all buffers, but have
545 * not restocked the Rx queue with fresh buffers */
546 rxq->read = rxq->write = 0;
547 rxq->write_actual = 0;
548 rxq->free_count = 0;
549 spin_unlock_irqrestore(&rxq->lock, flags);
550 }
551
552 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
553 {
554 u32 rb_size;
555 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
556 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
557
558 if (!priv->cfg->use_isr_legacy)
559 rb_timeout = RX_RB_TIMEOUT;
560
561 if (priv->cfg->mod_params->amsdu_size_8K)
562 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
563 else
564 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
565
566 /* Stop Rx DMA */
567 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
568
569 /* Reset driver's Rx queue write index */
570 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
571
572 /* Tell device where to find RBD circular buffer in DRAM */
573 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
574 (u32)(rxq->bd_dma >> 8));
575
576 /* Tell device where in DRAM to update its Rx status */
577 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
578 rxq->rb_stts_dma >> 4);
579
580 /* Enable Rx DMA
581 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
582 * the credit mechanism in 5000 HW RX FIFO
583 * Direct rx interrupts to hosts
584 * Rx buffer size 4 or 8k
585 * RB timeout 0x10
586 * 256 RBDs
587 */
588 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
589 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
590 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
591 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
592 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
593 rb_size|
594 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
595 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
596
597 /* Set interrupt coalescing timer to default (2048 usecs) */
598 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
599
600 return 0;
601 }
602
603 int iwlagn_hw_nic_init(struct iwl_priv *priv)
604 {
605 unsigned long flags;
606 struct iwl_rx_queue *rxq = &priv->rxq;
607 int ret;
608
609 /* nic_init */
610 spin_lock_irqsave(&priv->lock, flags);
611 priv->cfg->ops->lib->apm_ops.init(priv);
612
613 /* Set interrupt coalescing calibration timer to default (512 usecs) */
614 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
615
616 spin_unlock_irqrestore(&priv->lock, flags);
617
618 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
619
620 priv->cfg->ops->lib->apm_ops.config(priv);
621
622 /* Allocate the RX queue, or reset if it is already allocated */
623 if (!rxq->bd) {
624 ret = iwl_rx_queue_alloc(priv);
625 if (ret) {
626 IWL_ERR(priv, "Unable to initialize Rx queue\n");
627 return -ENOMEM;
628 }
629 } else
630 iwlagn_rx_queue_reset(priv, rxq);
631
632 iwlagn_rx_replenish(priv);
633
634 iwlagn_rx_init(priv, rxq);
635
636 spin_lock_irqsave(&priv->lock, flags);
637
638 rxq->need_update = 1;
639 iwl_rx_queue_update_write_ptr(priv, rxq);
640
641 spin_unlock_irqrestore(&priv->lock, flags);
642
643 /* Allocate or reset and init all Tx and Command queues */
644 if (!priv->txq) {
645 ret = iwlagn_txq_ctx_alloc(priv);
646 if (ret)
647 return ret;
648 } else
649 iwlagn_txq_ctx_reset(priv);
650
651 set_bit(STATUS_INIT, &priv->status);
652
653 return 0;
654 }
655
656 /**
657 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
658 */
659 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
660 dma_addr_t dma_addr)
661 {
662 return cpu_to_le32((u32)(dma_addr >> 8));
663 }
664
665 /**
666 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
667 *
668 * If there are slots in the RX queue that need to be restocked,
669 * and we have free pre-allocated buffers, fill the ranks as much
670 * as we can, pulling from rx_free.
671 *
672 * This moves the 'write' index forward to catch up with 'processed', and
673 * also updates the memory address in the firmware to reference the new
674 * target buffer.
675 */
676 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
677 {
678 struct iwl_rx_queue *rxq = &priv->rxq;
679 struct list_head *element;
680 struct iwl_rx_mem_buffer *rxb;
681 unsigned long flags;
682
683 spin_lock_irqsave(&rxq->lock, flags);
684 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
685 /* The overwritten rxb must be a used one */
686 rxb = rxq->queue[rxq->write];
687 BUG_ON(rxb && rxb->page);
688
689 /* Get next free Rx buffer, remove from free list */
690 element = rxq->rx_free.next;
691 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
692 list_del(element);
693
694 /* Point to Rx buffer via next RBD in circular buffer */
695 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
696 rxb->page_dma);
697 rxq->queue[rxq->write] = rxb;
698 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
699 rxq->free_count--;
700 }
701 spin_unlock_irqrestore(&rxq->lock, flags);
702 /* If the pre-allocated buffer pool is dropping low, schedule to
703 * refill it */
704 if (rxq->free_count <= RX_LOW_WATERMARK)
705 queue_work(priv->workqueue, &priv->rx_replenish);
706
707
708 /* If we've added more space for the firmware to place data, tell it.
709 * Increment device's write pointer in multiples of 8. */
710 if (rxq->write_actual != (rxq->write & ~0x7)) {
711 spin_lock_irqsave(&rxq->lock, flags);
712 rxq->need_update = 1;
713 spin_unlock_irqrestore(&rxq->lock, flags);
714 iwl_rx_queue_update_write_ptr(priv, rxq);
715 }
716 }
717
718 /**
719 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
720 *
721 * When moving to rx_free an SKB is allocated for the slot.
722 *
723 * Also restock the Rx queue via iwl_rx_queue_restock.
724 * This is called as a scheduled work item (except for during initialization)
725 */
726 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
727 {
728 struct iwl_rx_queue *rxq = &priv->rxq;
729 struct list_head *element;
730 struct iwl_rx_mem_buffer *rxb;
731 struct page *page;
732 unsigned long flags;
733 gfp_t gfp_mask = priority;
734
735 while (1) {
736 spin_lock_irqsave(&rxq->lock, flags);
737 if (list_empty(&rxq->rx_used)) {
738 spin_unlock_irqrestore(&rxq->lock, flags);
739 return;
740 }
741 spin_unlock_irqrestore(&rxq->lock, flags);
742
743 if (rxq->free_count > RX_LOW_WATERMARK)
744 gfp_mask |= __GFP_NOWARN;
745
746 if (priv->hw_params.rx_page_order > 0)
747 gfp_mask |= __GFP_COMP;
748
749 /* Alloc a new receive buffer */
750 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
751 if (!page) {
752 if (net_ratelimit())
753 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
754 "order: %d\n",
755 priv->hw_params.rx_page_order);
756
757 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
758 net_ratelimit())
759 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
760 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
761 rxq->free_count);
762 /* We don't reschedule replenish work here -- we will
763 * call the restock method and if it still needs
764 * more buffers it will schedule replenish */
765 return;
766 }
767
768 spin_lock_irqsave(&rxq->lock, flags);
769
770 if (list_empty(&rxq->rx_used)) {
771 spin_unlock_irqrestore(&rxq->lock, flags);
772 __free_pages(page, priv->hw_params.rx_page_order);
773 return;
774 }
775 element = rxq->rx_used.next;
776 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
777 list_del(element);
778
779 spin_unlock_irqrestore(&rxq->lock, flags);
780
781 BUG_ON(rxb->page);
782 rxb->page = page;
783 /* Get physical address of the RB */
784 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
785 PAGE_SIZE << priv->hw_params.rx_page_order,
786 PCI_DMA_FROMDEVICE);
787 /* dma address must be no more than 36 bits */
788 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
789 /* and also 256 byte aligned! */
790 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
791
792 spin_lock_irqsave(&rxq->lock, flags);
793
794 list_add_tail(&rxb->list, &rxq->rx_free);
795 rxq->free_count++;
796 priv->alloc_rxb_page++;
797
798 spin_unlock_irqrestore(&rxq->lock, flags);
799 }
800 }
801
802 void iwlagn_rx_replenish(struct iwl_priv *priv)
803 {
804 unsigned long flags;
805
806 iwlagn_rx_allocate(priv, GFP_KERNEL);
807
808 spin_lock_irqsave(&priv->lock, flags);
809 iwlagn_rx_queue_restock(priv);
810 spin_unlock_irqrestore(&priv->lock, flags);
811 }
812
813 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
814 {
815 iwlagn_rx_allocate(priv, GFP_ATOMIC);
816
817 iwlagn_rx_queue_restock(priv);
818 }
819
820 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
821 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
822 * This free routine walks the list of POOL entries and if SKB is set to
823 * non NULL it is unmapped and freed
824 */
825 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
826 {
827 int i;
828 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
829 if (rxq->pool[i].page != NULL) {
830 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
831 PAGE_SIZE << priv->hw_params.rx_page_order,
832 PCI_DMA_FROMDEVICE);
833 __iwl_free_pages(priv, rxq->pool[i].page);
834 rxq->pool[i].page = NULL;
835 }
836 }
837
838 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
839 rxq->bd_dma);
840 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
841 rxq->rb_stts, rxq->rb_stts_dma);
842 rxq->bd = NULL;
843 rxq->rb_stts = NULL;
844 }
845
846 int iwlagn_rxq_stop(struct iwl_priv *priv)
847 {
848
849 /* stop Rx DMA */
850 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
851 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
852 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
853
854 return 0;
855 }
856
857 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
858 {
859 int idx = 0;
860 int band_offset = 0;
861
862 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
863 if (rate_n_flags & RATE_MCS_HT_MSK) {
864 idx = (rate_n_flags & 0xff);
865 return idx;
866 /* Legacy rate format, search for match in table */
867 } else {
868 if (band == IEEE80211_BAND_5GHZ)
869 band_offset = IWL_FIRST_OFDM_RATE;
870 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
871 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
872 return idx - band_offset;
873 }
874
875 return -1;
876 }
877
878 /* Calc max signal level (dBm) among 3 possible receivers */
879 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
880 struct iwl_rx_phy_res *rx_resp)
881 {
882 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
883 }
884
885 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
886 {
887 u32 decrypt_out = 0;
888
889 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
890 RX_RES_STATUS_STATION_FOUND)
891 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
892 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
893
894 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
895
896 /* packet was not encrypted */
897 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
898 RX_RES_STATUS_SEC_TYPE_NONE)
899 return decrypt_out;
900
901 /* packet was encrypted with unknown alg */
902 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
903 RX_RES_STATUS_SEC_TYPE_ERR)
904 return decrypt_out;
905
906 /* decryption was not done in HW */
907 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
908 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
909 return decrypt_out;
910
911 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
912
913 case RX_RES_STATUS_SEC_TYPE_CCMP:
914 /* alg is CCM: check MIC only */
915 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
916 /* Bad MIC */
917 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
918 else
919 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
920
921 break;
922
923 case RX_RES_STATUS_SEC_TYPE_TKIP:
924 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
925 /* Bad TTAK */
926 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
927 break;
928 }
929 /* fall through if TTAK OK */
930 default:
931 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
932 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
933 else
934 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
935 break;
936 }
937
938 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
939 decrypt_in, decrypt_out);
940
941 return decrypt_out;
942 }
943
944 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
945 struct ieee80211_hdr *hdr,
946 u16 len,
947 u32 ampdu_status,
948 struct iwl_rx_mem_buffer *rxb,
949 struct ieee80211_rx_status *stats)
950 {
951 struct sk_buff *skb;
952 __le16 fc = hdr->frame_control;
953
954 /* We only process data packets if the interface is open */
955 if (unlikely(!priv->is_open)) {
956 IWL_DEBUG_DROP_LIMIT(priv,
957 "Dropping packet while interface is not open.\n");
958 return;
959 }
960
961 /* In case of HW accelerated crypto and bad decryption, drop */
962 if (!priv->cfg->mod_params->sw_crypto &&
963 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
964 return;
965
966 skb = dev_alloc_skb(128);
967 if (!skb) {
968 IWL_ERR(priv, "dev_alloc_skb failed\n");
969 return;
970 }
971
972 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
973
974 iwl_update_stats(priv, false, fc, len);
975 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
976
977 ieee80211_rx(priv->hw, skb);
978 priv->alloc_rxb_page--;
979 rxb->page = NULL;
980 }
981
982 /* Called for REPLY_RX (legacy ABG frames), or
983 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
984 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
985 struct iwl_rx_mem_buffer *rxb)
986 {
987 struct ieee80211_hdr *header;
988 struct ieee80211_rx_status rx_status;
989 struct iwl_rx_packet *pkt = rxb_addr(rxb);
990 struct iwl_rx_phy_res *phy_res;
991 __le32 rx_pkt_status;
992 struct iwl_rx_mpdu_res_start *amsdu;
993 u32 len;
994 u32 ampdu_status;
995 u32 rate_n_flags;
996
997 /**
998 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
999 * REPLY_RX: physical layer info is in this buffer
1000 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1001 * command and cached in priv->last_phy_res
1002 *
1003 * Here we set up local variables depending on which command is
1004 * received.
1005 */
1006 if (pkt->hdr.cmd == REPLY_RX) {
1007 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1008 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1009 + phy_res->cfg_phy_cnt);
1010
1011 len = le16_to_cpu(phy_res->byte_count);
1012 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1013 phy_res->cfg_phy_cnt + len);
1014 ampdu_status = le32_to_cpu(rx_pkt_status);
1015 } else {
1016 if (!priv->_agn.last_phy_res_valid) {
1017 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1018 return;
1019 }
1020 phy_res = &priv->_agn.last_phy_res;
1021 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1022 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1023 len = le16_to_cpu(amsdu->byte_count);
1024 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1025 ampdu_status = iwlagn_translate_rx_status(priv,
1026 le32_to_cpu(rx_pkt_status));
1027 }
1028
1029 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1030 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1031 phy_res->cfg_phy_cnt);
1032 return;
1033 }
1034
1035 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1036 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1037 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1038 le32_to_cpu(rx_pkt_status));
1039 return;
1040 }
1041
1042 /* This will be used in several places later */
1043 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1044
1045 /* rx_status carries information about the packet to mac80211 */
1046 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1047 rx_status.freq =
1048 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1049 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1050 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1051 rx_status.rate_idx =
1052 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1053 rx_status.flag = 0;
1054
1055 /* TSF isn't reliable. In order to allow smooth user experience,
1056 * this W/A doesn't propagate it to the mac80211 */
1057 /*rx_status.flag |= RX_FLAG_TSFT;*/
1058
1059 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1060
1061 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1062 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1063
1064 iwl_dbg_log_rx_data_frame(priv, len, header);
1065 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1066 rx_status.signal, (unsigned long long)rx_status.mactime);
1067
1068 /*
1069 * "antenna number"
1070 *
1071 * It seems that the antenna field in the phy flags value
1072 * is actually a bit field. This is undefined by radiotap,
1073 * it wants an actual antenna number but I always get "7"
1074 * for most legacy frames I receive indicating that the
1075 * same frame was received on all three RX chains.
1076 *
1077 * I think this field should be removed in favor of a
1078 * new 802.11n radiotap field "RX chains" that is defined
1079 * as a bitmask.
1080 */
1081 rx_status.antenna =
1082 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1083 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1084
1085 /* set the preamble flag if appropriate */
1086 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1087 rx_status.flag |= RX_FLAG_SHORTPRE;
1088
1089 /* Set up the HT phy flags */
1090 if (rate_n_flags & RATE_MCS_HT_MSK)
1091 rx_status.flag |= RX_FLAG_HT;
1092 if (rate_n_flags & RATE_MCS_HT40_MSK)
1093 rx_status.flag |= RX_FLAG_40MHZ;
1094 if (rate_n_flags & RATE_MCS_SGI_MSK)
1095 rx_status.flag |= RX_FLAG_SHORT_GI;
1096
1097 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1098 rxb, &rx_status);
1099 }
1100
1101 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1102 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1103 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1104 struct iwl_rx_mem_buffer *rxb)
1105 {
1106 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1107 priv->_agn.last_phy_res_valid = true;
1108 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1109 sizeof(struct iwl_rx_phy_res));
1110 }
1111
1112 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1113 struct ieee80211_vif *vif,
1114 enum ieee80211_band band,
1115 struct iwl_scan_channel *scan_ch)
1116 {
1117 const struct ieee80211_supported_band *sband;
1118 u16 passive_dwell = 0;
1119 u16 active_dwell = 0;
1120 int added = 0;
1121 u16 channel = 0;
1122
1123 sband = iwl_get_hw_mode(priv, band);
1124 if (!sband) {
1125 IWL_ERR(priv, "invalid band\n");
1126 return added;
1127 }
1128
1129 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1130 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1131
1132 if (passive_dwell <= active_dwell)
1133 passive_dwell = active_dwell + 1;
1134
1135 channel = iwl_get_single_channel_number(priv, band);
1136 if (channel) {
1137 scan_ch->channel = cpu_to_le16(channel);
1138 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1139 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1140 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1141 /* Set txpower levels to defaults */
1142 scan_ch->dsp_atten = 110;
1143 if (band == IEEE80211_BAND_5GHZ)
1144 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1145 else
1146 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1147 added++;
1148 } else
1149 IWL_ERR(priv, "no valid channel found\n");
1150 return added;
1151 }
1152
1153 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1154 struct ieee80211_vif *vif,
1155 enum ieee80211_band band,
1156 u8 is_active, u8 n_probes,
1157 struct iwl_scan_channel *scan_ch)
1158 {
1159 struct ieee80211_channel *chan;
1160 const struct ieee80211_supported_band *sband;
1161 const struct iwl_channel_info *ch_info;
1162 u16 passive_dwell = 0;
1163 u16 active_dwell = 0;
1164 int added, i;
1165 u16 channel;
1166
1167 sband = iwl_get_hw_mode(priv, band);
1168 if (!sband)
1169 return 0;
1170
1171 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1172 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1173
1174 if (passive_dwell <= active_dwell)
1175 passive_dwell = active_dwell + 1;
1176
1177 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1178 chan = priv->scan_request->channels[i];
1179
1180 if (chan->band != band)
1181 continue;
1182
1183 channel = chan->hw_value;
1184 scan_ch->channel = cpu_to_le16(channel);
1185
1186 ch_info = iwl_get_channel_info(priv, band, channel);
1187 if (!is_channel_valid(ch_info)) {
1188 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1189 channel);
1190 continue;
1191 }
1192
1193 if (!is_active || is_channel_passive(ch_info) ||
1194 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1195 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1196 else
1197 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1198
1199 if (n_probes)
1200 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1201
1202 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1203 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1204
1205 /* Set txpower levels to defaults */
1206 scan_ch->dsp_atten = 110;
1207
1208 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1209 * power level:
1210 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1211 */
1212 if (band == IEEE80211_BAND_5GHZ)
1213 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1214 else
1215 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1216
1217 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1218 channel, le32_to_cpu(scan_ch->type),
1219 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1220 "ACTIVE" : "PASSIVE",
1221 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1222 active_dwell : passive_dwell);
1223
1224 scan_ch++;
1225 added++;
1226 }
1227
1228 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1229 return added;
1230 }
1231
1232 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1233 {
1234 struct iwl_host_cmd cmd = {
1235 .id = REPLY_SCAN_CMD,
1236 .len = sizeof(struct iwl_scan_cmd),
1237 .flags = CMD_SIZE_HUGE,
1238 };
1239 struct iwl_scan_cmd *scan;
1240 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1241 u32 rate_flags = 0;
1242 u16 cmd_len;
1243 u16 rx_chain = 0;
1244 enum ieee80211_band band;
1245 u8 n_probes = 0;
1246 u8 rx_ant = priv->hw_params.valid_rx_ant;
1247 u8 rate;
1248 bool is_active = false;
1249 int chan_mod;
1250 u8 active_chains;
1251 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1252 int ret;
1253
1254 lockdep_assert_held(&priv->mutex);
1255
1256 if (vif)
1257 ctx = iwl_rxon_ctx_from_vif(vif);
1258
1259 if (!priv->scan_cmd) {
1260 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1261 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1262 if (!priv->scan_cmd) {
1263 IWL_DEBUG_SCAN(priv,
1264 "fail to allocate memory for scan\n");
1265 return -ENOMEM;
1266 }
1267 }
1268 scan = priv->scan_cmd;
1269 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1270
1271 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1272 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1273
1274 if (iwl_is_any_associated(priv)) {
1275 u16 interval = 0;
1276 u32 extra;
1277 u32 suspend_time = 100;
1278 u32 scan_suspend_time = 100;
1279 unsigned long flags;
1280
1281 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1282 spin_lock_irqsave(&priv->lock, flags);
1283 if (priv->is_internal_short_scan)
1284 interval = 0;
1285 else
1286 interval = vif->bss_conf.beacon_int;
1287 spin_unlock_irqrestore(&priv->lock, flags);
1288
1289 scan->suspend_time = 0;
1290 scan->max_out_time = cpu_to_le32(200 * 1024);
1291 if (!interval)
1292 interval = suspend_time;
1293
1294 extra = (suspend_time / interval) << 22;
1295 scan_suspend_time = (extra |
1296 ((suspend_time % interval) * 1024));
1297 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1298 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1299 scan_suspend_time, interval);
1300 }
1301
1302 if (priv->is_internal_short_scan) {
1303 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1304 } else if (priv->scan_request->n_ssids) {
1305 int i, p = 0;
1306 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1307 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1308 /* always does wildcard anyway */
1309 if (!priv->scan_request->ssids[i].ssid_len)
1310 continue;
1311 scan->direct_scan[p].id = WLAN_EID_SSID;
1312 scan->direct_scan[p].len =
1313 priv->scan_request->ssids[i].ssid_len;
1314 memcpy(scan->direct_scan[p].ssid,
1315 priv->scan_request->ssids[i].ssid,
1316 priv->scan_request->ssids[i].ssid_len);
1317 n_probes++;
1318 p++;
1319 }
1320 is_active = true;
1321 } else
1322 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1323
1324 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1325 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1326 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1327
1328 switch (priv->scan_band) {
1329 case IEEE80211_BAND_2GHZ:
1330 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1331 chan_mod = le32_to_cpu(
1332 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1333 RXON_FLG_CHANNEL_MODE_MSK)
1334 >> RXON_FLG_CHANNEL_MODE_POS;
1335 if (chan_mod == CHANNEL_MODE_PURE_40) {
1336 rate = IWL_RATE_6M_PLCP;
1337 } else {
1338 rate = IWL_RATE_1M_PLCP;
1339 rate_flags = RATE_MCS_CCK_MSK;
1340 }
1341 /*
1342 * Internal scans are passive, so we can indiscriminately set
1343 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1344 */
1345 if (priv->cfg->advanced_bt_coexist)
1346 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1347 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
1348 break;
1349 case IEEE80211_BAND_5GHZ:
1350 rate = IWL_RATE_6M_PLCP;
1351 /*
1352 * If active scanning is requested but a certain channel is
1353 * marked passive, we can do active scanning if we detect
1354 * transmissions.
1355 *
1356 * There is an issue with some firmware versions that triggers
1357 * a sysassert on a "good CRC threshold" of zero (== disabled),
1358 * on a radar channel even though this means that we should NOT
1359 * send probes.
1360 *
1361 * The "good CRC threshold" is the number of frames that we
1362 * need to receive during our dwell time on a channel before
1363 * sending out probes -- setting this to a huge value will
1364 * mean we never reach it, but at the same time work around
1365 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1366 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1367 */
1368 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1369 IWL_GOOD_CRC_TH_NEVER;
1370 break;
1371 default:
1372 IWL_WARN(priv, "Invalid scan band\n");
1373 return -EIO;
1374 }
1375
1376 band = priv->scan_band;
1377
1378 if (priv->cfg->scan_rx_antennas[band])
1379 rx_ant = priv->cfg->scan_rx_antennas[band];
1380
1381 if (priv->cfg->scan_tx_antennas[band])
1382 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1383
1384 if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) {
1385 /* operated as 1x1 in full concurrency mode */
1386 scan_tx_antennas =
1387 first_antenna(priv->cfg->scan_tx_antennas[band]);
1388 }
1389
1390 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1391 scan_tx_antennas);
1392 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1393 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1394
1395 /* In power save mode use one chain, otherwise use all chains */
1396 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1397 /* rx_ant has been set to all valid chains previously */
1398 active_chains = rx_ant &
1399 ((u8)(priv->chain_noise_data.active_chains));
1400 if (!active_chains)
1401 active_chains = rx_ant;
1402
1403 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1404 priv->chain_noise_data.active_chains);
1405
1406 rx_ant = first_antenna(active_chains);
1407 }
1408 if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) {
1409 /* operated as 1x1 in full concurrency mode */
1410 rx_ant = first_antenna(rx_ant);
1411 }
1412
1413 /* MIMO is not used here, but value is required */
1414 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1415 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1416 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1417 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1418 scan->rx_chain = cpu_to_le16(rx_chain);
1419 if (!priv->is_internal_short_scan) {
1420 cmd_len = iwl_fill_probe_req(priv,
1421 (struct ieee80211_mgmt *)scan->data,
1422 vif->addr,
1423 priv->scan_request->ie,
1424 priv->scan_request->ie_len,
1425 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1426 } else {
1427 /* use bcast addr, will not be transmitted but must be valid */
1428 cmd_len = iwl_fill_probe_req(priv,
1429 (struct ieee80211_mgmt *)scan->data,
1430 iwl_bcast_addr, NULL, 0,
1431 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1432
1433 }
1434 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1435
1436 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1437 RXON_FILTER_BCON_AWARE_MSK);
1438
1439 if (priv->is_internal_short_scan) {
1440 scan->channel_count =
1441 iwl_get_single_channel_for_scan(priv, vif, band,
1442 (void *)&scan->data[le16_to_cpu(
1443 scan->tx_cmd.len)]);
1444 } else {
1445 scan->channel_count =
1446 iwl_get_channels_for_scan(priv, vif, band,
1447 is_active, n_probes,
1448 (void *)&scan->data[le16_to_cpu(
1449 scan->tx_cmd.len)]);
1450 }
1451 if (scan->channel_count == 0) {
1452 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1453 return -EIO;
1454 }
1455
1456 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1457 scan->channel_count * sizeof(struct iwl_scan_channel);
1458 cmd.data = scan;
1459 scan->len = cpu_to_le16(cmd.len);
1460
1461 if (priv->cfg->ops->hcmd->set_pan_params) {
1462 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1463 if (ret)
1464 return ret;
1465 }
1466
1467 set_bit(STATUS_SCAN_HW, &priv->status);
1468 ret = iwl_send_cmd_sync(priv, &cmd);
1469 if (ret) {
1470 clear_bit(STATUS_SCAN_HW, &priv->status);
1471 if (priv->cfg->ops->hcmd->set_pan_params)
1472 priv->cfg->ops->hcmd->set_pan_params(priv);
1473 }
1474
1475 return ret;
1476 }
1477
1478 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1479 struct ieee80211_vif *vif, bool add)
1480 {
1481 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1482
1483 if (add)
1484 return iwl_add_bssid_station(priv, vif_priv->ctx,
1485 vif->bss_conf.bssid, true,
1486 &vif_priv->ibss_bssid_sta_id);
1487 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1488 vif->bss_conf.bssid);
1489 }
1490
1491 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1492 int sta_id, int tid, int freed)
1493 {
1494 lockdep_assert_held(&priv->sta_lock);
1495
1496 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1497 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1498 else {
1499 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1500 priv->stations[sta_id].tid[tid].tfds_in_queue,
1501 freed);
1502 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1503 }
1504 }
1505
1506 #define IWL_FLUSH_WAIT_MS 2000
1507
1508 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1509 {
1510 struct iwl_tx_queue *txq;
1511 struct iwl_queue *q;
1512 int cnt;
1513 unsigned long now = jiffies;
1514 int ret = 0;
1515
1516 /* waiting for all the tx frames complete might take a while */
1517 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1518 if (cnt == priv->cmd_queue)
1519 continue;
1520 txq = &priv->txq[cnt];
1521 q = &txq->q;
1522 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1523 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1524 msleep(1);
1525
1526 if (q->read_ptr != q->write_ptr) {
1527 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1528 ret = -ETIMEDOUT;
1529 break;
1530 }
1531 }
1532 return ret;
1533 }
1534
1535 #define IWL_TX_QUEUE_MSK 0xfffff
1536
1537 /**
1538 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1539 *
1540 * pre-requirements:
1541 * 1. acquire mutex before calling
1542 * 2. make sure rf is on and not in exit state
1543 */
1544 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1545 {
1546 struct iwl_txfifo_flush_cmd flush_cmd;
1547 struct iwl_host_cmd cmd = {
1548 .id = REPLY_TXFIFO_FLUSH,
1549 .len = sizeof(struct iwl_txfifo_flush_cmd),
1550 .flags = CMD_SYNC,
1551 .data = &flush_cmd,
1552 };
1553
1554 might_sleep();
1555
1556 memset(&flush_cmd, 0, sizeof(flush_cmd));
1557 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1558 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1559 if (priv->cfg->sku & IWL_SKU_N)
1560 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1561
1562 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1563 flush_cmd.fifo_control);
1564 flush_cmd.flush_control = cpu_to_le16(flush_control);
1565
1566 return iwl_send_cmd(priv, &cmd);
1567 }
1568
1569 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1570 {
1571 mutex_lock(&priv->mutex);
1572 ieee80211_stop_queues(priv->hw);
1573 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1574 IWL_ERR(priv, "flush request fail\n");
1575 goto done;
1576 }
1577 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1578 iwlagn_wait_tx_queue_empty(priv);
1579 done:
1580 ieee80211_wake_queues(priv->hw);
1581 mutex_unlock(&priv->mutex);
1582 }
1583
1584 /*
1585 * BT coex
1586 */
1587 /*
1588 * Macros to access the lookup table.
1589 *
1590 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1591 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1592 *
1593 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1594 *
1595 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1596 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1597 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1598 *
1599 * These macros encode that format.
1600 */
1601 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1602 wifi_txrx, wifi_sh_ant_req) \
1603 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1604 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1605
1606 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1607 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1608 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1609 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1610 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1611 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1612 wifi_sh_ant_req))))
1613 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1614 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1615 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1616 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1617 wifi_sh_ant_req))
1618 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1619 wifi_req, wifi_prio, wifi_txrx, \
1620 wifi_sh_ant_req) \
1621 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1622 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1623 wifi_sh_ant_req))
1624
1625 #define LUT_WLAN_KILL_OP(lut, op, val) \
1626 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1627 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1628 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1629 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1630 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1631 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1632 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1633 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1634 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1635 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1636 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1637 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1638 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1639
1640 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1641 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1642 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1643 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1644 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1645 wifi_req, wifi_prio, wifi_txrx, \
1646 wifi_sh_ant_req))))
1647 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1648 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1649 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1650 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1651 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1652 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1653 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1654 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1655
1656 static const __le32 iwlagn_def_3w_lookup[12] = {
1657 cpu_to_le32(0xaaaaaaaa),
1658 cpu_to_le32(0xaaaaaaaa),
1659 cpu_to_le32(0xaeaaaaaa),
1660 cpu_to_le32(0xaaaaaaaa),
1661 cpu_to_le32(0xcc00ff28),
1662 cpu_to_le32(0x0000aaaa),
1663 cpu_to_le32(0xcc00aaaa),
1664 cpu_to_le32(0x0000aaaa),
1665 cpu_to_le32(0xc0004000),
1666 cpu_to_le32(0x00004000),
1667 cpu_to_le32(0xf0005000),
1668 cpu_to_le32(0xf0004000),
1669 };
1670
1671 static const __le32 iwlagn_concurrent_lookup[12] = {
1672 cpu_to_le32(0xaaaaaaaa),
1673 cpu_to_le32(0xaaaaaaaa),
1674 cpu_to_le32(0xaaaaaaaa),
1675 cpu_to_le32(0xaaaaaaaa),
1676 cpu_to_le32(0xaaaaaaaa),
1677 cpu_to_le32(0xaaaaaaaa),
1678 cpu_to_le32(0xaaaaaaaa),
1679 cpu_to_le32(0xaaaaaaaa),
1680 cpu_to_le32(0x00000000),
1681 cpu_to_le32(0x00000000),
1682 cpu_to_le32(0x00000000),
1683 cpu_to_le32(0x00000000),
1684 };
1685
1686 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1687 {
1688 struct iwlagn_bt_cmd bt_cmd = {
1689 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1690 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1691 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1692 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1693 };
1694
1695 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1696 sizeof(bt_cmd.bt3_lookup_table));
1697
1698 bt_cmd.prio_boost = priv->cfg->bt_prio_boost;
1699 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1700 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1701 bt_cmd.valid = priv->bt_valid;
1702
1703 /*
1704 * Configure BT coex mode to "no coexistence" when the
1705 * user disabled BT coexistence, we have no interface
1706 * (might be in monitor mode), or the interface is in
1707 * IBSS mode (no proper uCode support for coex then).
1708 */
1709 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1710 bt_cmd.flags = 0;
1711 } else {
1712 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1713 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1714 if (priv->bt_ch_announce)
1715 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1716 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1717 }
1718 if (priv->bt_full_concurrent)
1719 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1720 sizeof(iwlagn_concurrent_lookup));
1721 else
1722 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1723 sizeof(iwlagn_def_3w_lookup));
1724
1725 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1726 bt_cmd.flags ? "active" : "disabled",
1727 priv->bt_full_concurrent ?
1728 "full concurrency" : "3-wire");
1729
1730 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1731 IWL_ERR(priv, "failed to send BT Coex Config\n");
1732
1733 /*
1734 * When we are doing a restart, need to also reconfigure BT
1735 * SCO to the device. If not doing a restart, bt_sco_active
1736 * will always be false, so there's no need to have an extra
1737 * variable to check for it.
1738 */
1739 if (priv->bt_sco_active) {
1740 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1741
1742 if (priv->bt_sco_active)
1743 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1744 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1745 sizeof(sco_cmd), &sco_cmd))
1746 IWL_ERR(priv, "failed to send BT SCO command\n");
1747 }
1748 }
1749
1750 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1751 {
1752 struct iwl_priv *priv =
1753 container_of(work, struct iwl_priv, bt_traffic_change_work);
1754 struct iwl_rxon_context *ctx;
1755 int smps_request = -1;
1756
1757 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1758 priv->bt_traffic_load);
1759
1760 switch (priv->bt_traffic_load) {
1761 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1762 smps_request = IEEE80211_SMPS_AUTOMATIC;
1763 break;
1764 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1765 smps_request = IEEE80211_SMPS_DYNAMIC;
1766 break;
1767 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1768 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1769 smps_request = IEEE80211_SMPS_STATIC;
1770 break;
1771 default:
1772 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1773 priv->bt_traffic_load);
1774 break;
1775 }
1776
1777 mutex_lock(&priv->mutex);
1778
1779 if (priv->cfg->ops->lib->update_chain_flags)
1780 priv->cfg->ops->lib->update_chain_flags(priv);
1781
1782 if (smps_request != -1) {
1783 for_each_context(priv, ctx) {
1784 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1785 ieee80211_request_smps(ctx->vif, smps_request);
1786 }
1787 }
1788
1789 mutex_unlock(&priv->mutex);
1790 }
1791
1792 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1793 struct iwl_bt_uart_msg *uart_msg)
1794 {
1795 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1796 "Update Req = 0x%X",
1797 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1798 BT_UART_MSG_FRAME1MSGTYPE_POS,
1799 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1800 BT_UART_MSG_FRAME1SSN_POS,
1801 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1802 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1803
1804 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1805 "Chl_SeqN = 0x%X, In band = 0x%X",
1806 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1807 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1808 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1809 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1810 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1811 BT_UART_MSG_FRAME2CHLSEQN_POS,
1812 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1813 BT_UART_MSG_FRAME2INBAND_POS);
1814
1815 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1816 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1817 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1818 BT_UART_MSG_FRAME3SCOESCO_POS,
1819 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1820 BT_UART_MSG_FRAME3SNIFF_POS,
1821 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1822 BT_UART_MSG_FRAME3A2DP_POS,
1823 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1824 BT_UART_MSG_FRAME3ACL_POS,
1825 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1826 BT_UART_MSG_FRAME3MASTER_POS,
1827 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1828 BT_UART_MSG_FRAME3OBEX_POS);
1829
1830 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1831 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1832 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1833
1834 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1835 "eSCO Retransmissions = 0x%X",
1836 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1837 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1838 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1839 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1840 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1841 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1842
1843 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1844 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1845 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1846 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1847 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1848
1849 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1850 "0x%X, Connectable = 0x%X",
1851 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1852 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1853 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1854 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1855 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1856 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1857 }
1858
1859 static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1860 struct iwl_bt_uart_msg *uart_msg)
1861 {
1862 u8 kill_ack_msk;
1863 __le32 bt_kill_ack_msg[2] = {
1864 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1865
1866 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
1867 BT_UART_MSG_FRAME3SNIFF_MSK |
1868 BT_UART_MSG_FRAME3SCOESCO_MSK) &
1869 uart_msg->frame3) == 0) ? 1 : 0;
1870 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
1871 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1872 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
1873 /* schedule to send runtime bt_config */
1874 queue_work(priv->workqueue, &priv->bt_runtime_config);
1875 }
1876
1877 }
1878
1879 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1880 struct iwl_rx_mem_buffer *rxb)
1881 {
1882 unsigned long flags;
1883 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1884 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1885 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1886 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1887 u8 last_traffic_load;
1888
1889 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1890 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1891 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1892 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1893 coex->bt_ci_compliance);
1894 iwlagn_print_uartmsg(priv, uart_msg);
1895
1896 last_traffic_load = priv->notif_bt_traffic_load;
1897 priv->notif_bt_traffic_load = coex->bt_traffic_load;
1898 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1899 if (priv->bt_status != coex->bt_status ||
1900 last_traffic_load != coex->bt_traffic_load) {
1901 if (coex->bt_status) {
1902 /* BT on */
1903 if (!priv->bt_ch_announce)
1904 priv->bt_traffic_load =
1905 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1906 else
1907 priv->bt_traffic_load =
1908 coex->bt_traffic_load;
1909 } else {
1910 /* BT off */
1911 priv->bt_traffic_load =
1912 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1913 }
1914 priv->bt_status = coex->bt_status;
1915 queue_work(priv->workqueue,
1916 &priv->bt_traffic_change_work);
1917 }
1918 if (priv->bt_sco_active !=
1919 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
1920 priv->bt_sco_active = uart_msg->frame3 &
1921 BT_UART_MSG_FRAME3SCOESCO_MSK;
1922 if (priv->bt_sco_active)
1923 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1924 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
1925 sizeof(sco_cmd), &sco_cmd, NULL);
1926 }
1927 }
1928
1929 iwlagn_set_kill_ack_msk(priv, uart_msg);
1930
1931 /* FIXME: based on notification, adjust the prio_boost */
1932
1933 spin_lock_irqsave(&priv->lock, flags);
1934 priv->bt_ci_compliance = coex->bt_ci_compliance;
1935 spin_unlock_irqrestore(&priv->lock, flags);
1936 }
1937
1938 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1939 {
1940 iwlagn_rx_handler_setup(priv);
1941 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1942 iwlagn_bt_coex_profile_notif;
1943 }
1944
1945 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1946 {
1947 iwlagn_setup_deferred_work(priv);
1948
1949 INIT_WORK(&priv->bt_traffic_change_work,
1950 iwlagn_bt_traffic_change_work);
1951 }
1952
1953 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1954 {
1955 cancel_work_sync(&priv->bt_traffic_change_work);
1956 }
Linux kernel - Deliverables
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