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iwlagn: provide heplers to access the transport ops
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42 #include "iwl-trans.h"
43
44 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
45 {
46 return le32_to_cpup((__le32 *)&tx_resp->status +
47 tx_resp->frame_count) & MAX_SN;
48 }
49
50 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
51 {
52 status &= TX_STATUS_MSK;
53
54 switch (status) {
55 case TX_STATUS_POSTPONE_DELAY:
56 priv->_agn.reply_tx_stats.pp_delay++;
57 break;
58 case TX_STATUS_POSTPONE_FEW_BYTES:
59 priv->_agn.reply_tx_stats.pp_few_bytes++;
60 break;
61 case TX_STATUS_POSTPONE_BT_PRIO:
62 priv->_agn.reply_tx_stats.pp_bt_prio++;
63 break;
64 case TX_STATUS_POSTPONE_QUIET_PERIOD:
65 priv->_agn.reply_tx_stats.pp_quiet_period++;
66 break;
67 case TX_STATUS_POSTPONE_CALC_TTAK:
68 priv->_agn.reply_tx_stats.pp_calc_ttak++;
69 break;
70 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
71 priv->_agn.reply_tx_stats.int_crossed_retry++;
72 break;
73 case TX_STATUS_FAIL_SHORT_LIMIT:
74 priv->_agn.reply_tx_stats.short_limit++;
75 break;
76 case TX_STATUS_FAIL_LONG_LIMIT:
77 priv->_agn.reply_tx_stats.long_limit++;
78 break;
79 case TX_STATUS_FAIL_FIFO_UNDERRUN:
80 priv->_agn.reply_tx_stats.fifo_underrun++;
81 break;
82 case TX_STATUS_FAIL_DRAIN_FLOW:
83 priv->_agn.reply_tx_stats.drain_flow++;
84 break;
85 case TX_STATUS_FAIL_RFKILL_FLUSH:
86 priv->_agn.reply_tx_stats.rfkill_flush++;
87 break;
88 case TX_STATUS_FAIL_LIFE_EXPIRE:
89 priv->_agn.reply_tx_stats.life_expire++;
90 break;
91 case TX_STATUS_FAIL_DEST_PS:
92 priv->_agn.reply_tx_stats.dest_ps++;
93 break;
94 case TX_STATUS_FAIL_HOST_ABORTED:
95 priv->_agn.reply_tx_stats.host_abort++;
96 break;
97 case TX_STATUS_FAIL_BT_RETRY:
98 priv->_agn.reply_tx_stats.bt_retry++;
99 break;
100 case TX_STATUS_FAIL_STA_INVALID:
101 priv->_agn.reply_tx_stats.sta_invalid++;
102 break;
103 case TX_STATUS_FAIL_FRAG_DROPPED:
104 priv->_agn.reply_tx_stats.frag_drop++;
105 break;
106 case TX_STATUS_FAIL_TID_DISABLE:
107 priv->_agn.reply_tx_stats.tid_disable++;
108 break;
109 case TX_STATUS_FAIL_FIFO_FLUSHED:
110 priv->_agn.reply_tx_stats.fifo_flush++;
111 break;
112 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
113 priv->_agn.reply_tx_stats.insuff_cf_poll++;
114 break;
115 case TX_STATUS_FAIL_PASSIVE_NO_RX:
116 priv->_agn.reply_tx_stats.fail_hw_drop++;
117 break;
118 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
119 priv->_agn.reply_tx_stats.sta_color_mismatch++;
120 break;
121 default:
122 priv->_agn.reply_tx_stats.unknown++;
123 break;
124 }
125 }
126
127 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
128 {
129 status &= AGG_TX_STATUS_MSK;
130
131 switch (status) {
132 case AGG_TX_STATE_UNDERRUN_MSK:
133 priv->_agn.reply_agg_tx_stats.underrun++;
134 break;
135 case AGG_TX_STATE_BT_PRIO_MSK:
136 priv->_agn.reply_agg_tx_stats.bt_prio++;
137 break;
138 case AGG_TX_STATE_FEW_BYTES_MSK:
139 priv->_agn.reply_agg_tx_stats.few_bytes++;
140 break;
141 case AGG_TX_STATE_ABORT_MSK:
142 priv->_agn.reply_agg_tx_stats.abort++;
143 break;
144 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
145 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
146 break;
147 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
148 priv->_agn.reply_agg_tx_stats.last_sent_try++;
149 break;
150 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
151 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
152 break;
153 case AGG_TX_STATE_SCD_QUERY_MSK:
154 priv->_agn.reply_agg_tx_stats.scd_query++;
155 break;
156 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
157 priv->_agn.reply_agg_tx_stats.bad_crc32++;
158 break;
159 case AGG_TX_STATE_RESPONSE_MSK:
160 priv->_agn.reply_agg_tx_stats.response++;
161 break;
162 case AGG_TX_STATE_DUMP_TX_MSK:
163 priv->_agn.reply_agg_tx_stats.dump_tx++;
164 break;
165 case AGG_TX_STATE_DELAY_TX_MSK:
166 priv->_agn.reply_agg_tx_stats.delay_tx++;
167 break;
168 default:
169 priv->_agn.reply_agg_tx_stats.unknown++;
170 break;
171 }
172 }
173
174 static void iwlagn_set_tx_status(struct iwl_priv *priv,
175 struct ieee80211_tx_info *info,
176 struct iwl_rxon_context *ctx,
177 struct iwlagn_tx_resp *tx_resp,
178 int txq_id, bool is_agg)
179 {
180 u16 status = le16_to_cpu(tx_resp->status.status);
181
182 info->status.rates[0].count = tx_resp->failure_frame + 1;
183 if (is_agg)
184 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
185 info->flags |= iwl_tx_status_to_mac80211(status);
186 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
187 info);
188 if (!iwl_is_tx_success(status))
189 iwlagn_count_tx_err_status(priv, status);
190
191 if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
192 iwl_is_associated_ctx(ctx) && ctx->vif &&
193 ctx->vif->type == NL80211_IFTYPE_STATION) {
194 ctx->last_tx_rejected = true;
195 iwl_stop_queue(priv, &priv->txq[txq_id]);
196 }
197
198 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
199 "0x%x retries %d\n",
200 txq_id,
201 iwl_get_tx_fail_reason(status), status,
202 le32_to_cpu(tx_resp->rate_n_flags),
203 tx_resp->failure_frame);
204 }
205
206 #ifdef CONFIG_IWLWIFI_DEBUG
207 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
208
209 const char *iwl_get_agg_tx_fail_reason(u16 status)
210 {
211 status &= AGG_TX_STATUS_MSK;
212 switch (status) {
213 case AGG_TX_STATE_TRANSMITTED:
214 return "SUCCESS";
215 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
216 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
217 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
218 AGG_TX_STATE_FAIL(ABORT_MSK);
219 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
220 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
221 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
222 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
223 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
224 AGG_TX_STATE_FAIL(RESPONSE_MSK);
225 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
226 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
227 }
228
229 return "UNKNOWN";
230 }
231 #endif /* CONFIG_IWLWIFI_DEBUG */
232
233 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
234 struct iwl_ht_agg *agg,
235 struct iwlagn_tx_resp *tx_resp,
236 int txq_id, u16 start_idx)
237 {
238 u16 status;
239 struct agg_tx_status *frame_status = &tx_resp->status;
240 struct ieee80211_hdr *hdr = NULL;
241 int i, sh, idx;
242 u16 seq;
243
244 if (agg->wait_for_ba)
245 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
246
247 agg->frame_count = tx_resp->frame_count;
248 agg->start_idx = start_idx;
249 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
250 agg->bitmap = 0;
251
252 /* # frames attempted by Tx command */
253 if (agg->frame_count == 1) {
254 struct iwl_tx_info *txb;
255
256 /* Only one frame was attempted; no block-ack will arrive */
257 idx = start_idx;
258
259 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
260 agg->frame_count, agg->start_idx, idx);
261 txb = &priv->txq[txq_id].txb[idx];
262 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
263 txb->ctx, tx_resp, txq_id, true);
264 agg->wait_for_ba = 0;
265 } else {
266 /* Two or more frames were attempted; expect block-ack */
267 u64 bitmap = 0;
268
269 /*
270 * Start is the lowest frame sent. It may not be the first
271 * frame in the batch; we figure this out dynamically during
272 * the following loop.
273 */
274 int start = agg->start_idx;
275
276 /* Construct bit-map of pending frames within Tx window */
277 for (i = 0; i < agg->frame_count; i++) {
278 u16 sc;
279 status = le16_to_cpu(frame_status[i].status);
280 seq = le16_to_cpu(frame_status[i].sequence);
281 idx = SEQ_TO_INDEX(seq);
282 txq_id = SEQ_TO_QUEUE(seq);
283
284 if (status & AGG_TX_STATUS_MSK)
285 iwlagn_count_agg_tx_err_status(priv, status);
286
287 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
288 AGG_TX_STATE_ABORT_MSK))
289 continue;
290
291 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
292 agg->frame_count, txq_id, idx);
293 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
294 "try-count (0x%08x)\n",
295 iwl_get_agg_tx_fail_reason(status),
296 status & AGG_TX_STATUS_MSK,
297 status & AGG_TX_TRY_MSK);
298
299 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
300 if (!hdr) {
301 IWL_ERR(priv,
302 "BUG_ON idx doesn't point to valid skb"
303 " idx=%d, txq_id=%d\n", idx, txq_id);
304 return -1;
305 }
306
307 sc = le16_to_cpu(hdr->seq_ctrl);
308 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
309 IWL_ERR(priv,
310 "BUG_ON idx doesn't match seq control"
311 " idx=%d, seq_idx=%d, seq=%d\n",
312 idx, SEQ_TO_SN(sc),
313 hdr->seq_ctrl);
314 return -1;
315 }
316
317 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
318 i, idx, SEQ_TO_SN(sc));
319
320 /*
321 * sh -> how many frames ahead of the starting frame is
322 * the current one?
323 *
324 * Note that all frames sent in the batch must be in a
325 * 64-frame window, so this number should be in [0,63].
326 * If outside of this window, then we've found a new
327 * "first" frame in the batch and need to change start.
328 */
329 sh = idx - start;
330
331 /*
332 * If >= 64, out of window. start must be at the front
333 * of the circular buffer, idx must be near the end of
334 * the buffer, and idx is the new "first" frame. Shift
335 * the indices around.
336 */
337 if (sh >= 64) {
338 /* Shift bitmap by start - idx, wrapped */
339 sh = 0x100 - idx + start;
340 bitmap = bitmap << sh;
341 /* Now idx is the new start so sh = 0 */
342 sh = 0;
343 start = idx;
344 /*
345 * If <= -64 then wraps the 256-pkt circular buffer
346 * (e.g., start = 255 and idx = 0, sh should be 1)
347 */
348 } else if (sh <= -64) {
349 sh = 0x100 - start + idx;
350 /*
351 * If < 0 but > -64, out of window. idx is before start
352 * but not wrapped. Shift the indices around.
353 */
354 } else if (sh < 0) {
355 /* Shift by how far start is ahead of idx */
356 sh = start - idx;
357 bitmap = bitmap << sh;
358 /* Now idx is the new start so sh = 0 */
359 start = idx;
360 sh = 0;
361 }
362 /* Sequence number start + sh was sent in this batch */
363 bitmap |= 1ULL << sh;
364 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
365 start, (unsigned long long)bitmap);
366 }
367
368 /*
369 * Store the bitmap and possibly the new start, if we wrapped
370 * the buffer above
371 */
372 agg->bitmap = bitmap;
373 agg->start_idx = start;
374 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
375 agg->frame_count, agg->start_idx,
376 (unsigned long long)agg->bitmap);
377
378 if (bitmap)
379 agg->wait_for_ba = 1;
380 }
381 return 0;
382 }
383
384 void iwl_check_abort_status(struct iwl_priv *priv,
385 u8 frame_count, u32 status)
386 {
387 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
388 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
389 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
390 queue_work(priv->workqueue, &priv->tx_flush);
391 }
392 }
393
394 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
395 struct iwl_rx_mem_buffer *rxb)
396 {
397 struct iwl_rx_packet *pkt = rxb_addr(rxb);
398 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
399 int txq_id = SEQ_TO_QUEUE(sequence);
400 int index = SEQ_TO_INDEX(sequence);
401 struct iwl_tx_queue *txq = &priv->txq[txq_id];
402 struct ieee80211_tx_info *info;
403 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
404 struct iwl_tx_info *txb;
405 u32 status = le16_to_cpu(tx_resp->status.status);
406 int tid;
407 int sta_id;
408 int freed;
409 unsigned long flags;
410
411 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
412 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
413 "index %d is out of range [0-%d] %d %d\n", __func__,
414 txq_id, index, txq->q.n_bd, txq->q.write_ptr,
415 txq->q.read_ptr);
416 return;
417 }
418
419 txq->time_stamp = jiffies;
420 txb = &txq->txb[txq->q.read_ptr];
421 info = IEEE80211_SKB_CB(txb->skb);
422 memset(&info->status, 0, sizeof(info->status));
423
424 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
425 IWLAGN_TX_RES_TID_POS;
426 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
427 IWLAGN_TX_RES_RA_POS;
428
429 spin_lock_irqsave(&priv->sta_lock, flags);
430 if (txq->sched_retry) {
431 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
432 struct iwl_ht_agg *agg;
433
434 agg = &priv->stations[sta_id].tid[tid].agg;
435 /*
436 * If the BT kill count is non-zero, we'll get this
437 * notification again.
438 */
439 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
440 priv->cfg->bt_params &&
441 priv->cfg->bt_params->advanced_bt_coexist) {
442 IWL_DEBUG_COEX(priv, "receive reply tx with bt_kill\n");
443 }
444 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
445
446 /* check if BAR is needed */
447 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
448 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
449
450 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
451 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
452 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
453 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
454 scd_ssn , index, txq_id, txq->swq_id);
455
456 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
457 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
458
459 if (priv->mac80211_registered &&
460 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
461 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
462 iwl_wake_queue(priv, txq);
463 }
464 } else {
465 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
466 txq_id, false);
467 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
468 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
469
470 if (priv->mac80211_registered &&
471 iwl_queue_space(&txq->q) > txq->q.low_mark &&
472 status != TX_STATUS_FAIL_PASSIVE_NO_RX)
473 iwl_wake_queue(priv, txq);
474 }
475
476 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
477
478 iwl_check_abort_status(priv, tx_resp->frame_count, status);
479 spin_unlock_irqrestore(&priv->sta_lock, flags);
480 }
481
482 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
483 {
484 /* init calibration handlers */
485 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
486 iwlagn_rx_calib_result;
487 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
488
489 /* set up notification wait support */
490 spin_lock_init(&priv->_agn.notif_wait_lock);
491 INIT_LIST_HEAD(&priv->_agn.notif_waits);
492 init_waitqueue_head(&priv->_agn.notif_waitq);
493 }
494
495 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
496 {
497 /*
498 * nothing need to be done here anymore
499 * still keep for future use if needed
500 */
501 }
502
503 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
504 {
505 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
506 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
507 }
508
509 int iwlagn_send_tx_power(struct iwl_priv *priv)
510 {
511 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
512 u8 tx_ant_cfg_cmd;
513
514 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
515 "TX Power requested while scanning!\n"))
516 return -EAGAIN;
517
518 /* half dBm need to multiply */
519 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
520
521 if (priv->tx_power_lmt_in_half_dbm &&
522 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
523 /*
524 * For the newer devices which using enhanced/extend tx power
525 * table in EEPROM, the format is in half dBm. driver need to
526 * convert to dBm format before report to mac80211.
527 * By doing so, there is a possibility of 1/2 dBm resolution
528 * lost. driver will perform "round-up" operation before
529 * reporting, but it will cause 1/2 dBm tx power over the
530 * regulatory limit. Perform the checking here, if the
531 * "tx_power_user_lmt" is higher than EEPROM value (in
532 * half-dBm format), lower the tx power based on EEPROM
533 */
534 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
535 }
536 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
537 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
538
539 if (IWL_UCODE_API(priv->ucode_ver) == 1)
540 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
541 else
542 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
543
544 return trans_send_cmd_pdu(priv, tx_ant_cfg_cmd, CMD_SYNC,
545 sizeof(tx_power_cmd), &tx_power_cmd);
546 }
547
548 void iwlagn_temperature(struct iwl_priv *priv)
549 {
550 /* store temperature from correct statistics (in Celsius) */
551 priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
552 iwl_tt_handler(priv);
553 }
554
555 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
556 {
557 struct iwl_eeprom_calib_hdr {
558 u8 version;
559 u8 pa_type;
560 u16 voltage;
561 } *hdr;
562
563 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
564 EEPROM_CALIB_ALL);
565 return hdr->version;
566
567 }
568
569 /*
570 * EEPROM
571 */
572 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
573 {
574 u16 offset = 0;
575
576 if ((address & INDIRECT_ADDRESS) == 0)
577 return address;
578
579 switch (address & INDIRECT_TYPE_MSK) {
580 case INDIRECT_HOST:
581 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
582 break;
583 case INDIRECT_GENERAL:
584 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
585 break;
586 case INDIRECT_REGULATORY:
587 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
588 break;
589 case INDIRECT_TXP_LIMIT:
590 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
591 break;
592 case INDIRECT_TXP_LIMIT_SIZE:
593 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
594 break;
595 case INDIRECT_CALIBRATION:
596 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
597 break;
598 case INDIRECT_PROCESS_ADJST:
599 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
600 break;
601 case INDIRECT_OTHERS:
602 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
603 break;
604 default:
605 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
606 address & INDIRECT_TYPE_MSK);
607 break;
608 }
609
610 /* translate the offset from words to byte */
611 return (address & ADDRESS_MSK) + (offset << 1);
612 }
613
614 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
615 size_t offset)
616 {
617 u32 address = eeprom_indirect_address(priv, offset);
618 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
619 return &priv->eeprom[address];
620 }
621
622 struct iwl_mod_params iwlagn_mod_params = {
623 .amsdu_size_8K = 1,
624 .restart_fw = 1,
625 .plcp_check = true,
626 .bt_coex_active = true,
627 .no_sleep_autoadjust = true,
628 .power_level = IWL_POWER_INDEX_1,
629 /* the rest are 0 by default */
630 };
631
632 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
633 {
634 u32 rb_size;
635 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
636 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
637
638 rb_timeout = RX_RB_TIMEOUT;
639
640 if (iwlagn_mod_params.amsdu_size_8K)
641 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
642 else
643 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
644
645 /* Stop Rx DMA */
646 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
647
648 /* Reset driver's Rx queue write index */
649 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
650
651 /* Tell device where to find RBD circular buffer in DRAM */
652 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
653 (u32)(rxq->bd_dma >> 8));
654
655 /* Tell device where in DRAM to update its Rx status */
656 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
657 rxq->rb_stts_dma >> 4);
658
659 /* Enable Rx DMA
660 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
661 * the credit mechanism in 5000 HW RX FIFO
662 * Direct rx interrupts to hosts
663 * Rx buffer size 4 or 8k
664 * RB timeout 0x10
665 * 256 RBDs
666 */
667 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
668 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
669 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
670 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
671 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
672 rb_size|
673 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
674 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
675
676 /* Set interrupt coalescing timer to default (2048 usecs) */
677 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
678
679 return 0;
680 }
681
682 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
683 {
684 /*
685 * (for documentation purposes)
686 * to set power to V_AUX, do:
687
688 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
689 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
690 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
691 ~APMG_PS_CTRL_MSK_PWR_SRC);
692 */
693
694 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
695 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
696 ~APMG_PS_CTRL_MSK_PWR_SRC);
697 }
698
699 int iwlagn_hw_nic_init(struct iwl_priv *priv)
700 {
701 unsigned long flags;
702 struct iwl_rx_queue *rxq = &priv->rxq;
703
704 /* nic_init */
705 spin_lock_irqsave(&priv->lock, flags);
706 priv->cfg->ops->lib->apm_ops.init(priv);
707
708 /* Set interrupt coalescing calibration timer to default (512 usecs) */
709 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
710
711 spin_unlock_irqrestore(&priv->lock, flags);
712
713 iwlagn_set_pwr_vmain(priv);
714
715 priv->cfg->ops->lib->apm_ops.config(priv);
716
717 /* Allocate the RX queue, or reset if it is already allocated */
718 trans_rx_init(priv);
719
720 iwlagn_rx_replenish(priv);
721
722 iwlagn_rx_init(priv, rxq);
723
724 spin_lock_irqsave(&priv->lock, flags);
725
726 rxq->need_update = 1;
727 iwl_rx_queue_update_write_ptr(priv, rxq);
728
729 spin_unlock_irqrestore(&priv->lock, flags);
730
731 /* Allocate or reset and init all Tx and Command queues */
732 if (trans_tx_init(priv))
733 return -ENOMEM;
734
735 if (priv->cfg->base_params->shadow_reg_enable) {
736 /* enable shadow regs in HW */
737 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
738 0x800FFFFF);
739 }
740
741 set_bit(STATUS_INIT, &priv->status);
742
743 return 0;
744 }
745
746 /**
747 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
748 */
749 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
750 dma_addr_t dma_addr)
751 {
752 return cpu_to_le32((u32)(dma_addr >> 8));
753 }
754
755 /**
756 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
757 *
758 * If there are slots in the RX queue that need to be restocked,
759 * and we have free pre-allocated buffers, fill the ranks as much
760 * as we can, pulling from rx_free.
761 *
762 * This moves the 'write' index forward to catch up with 'processed', and
763 * also updates the memory address in the firmware to reference the new
764 * target buffer.
765 */
766 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
767 {
768 struct iwl_rx_queue *rxq = &priv->rxq;
769 struct list_head *element;
770 struct iwl_rx_mem_buffer *rxb;
771 unsigned long flags;
772
773 spin_lock_irqsave(&rxq->lock, flags);
774 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
775 /* The overwritten rxb must be a used one */
776 rxb = rxq->queue[rxq->write];
777 BUG_ON(rxb && rxb->page);
778
779 /* Get next free Rx buffer, remove from free list */
780 element = rxq->rx_free.next;
781 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
782 list_del(element);
783
784 /* Point to Rx buffer via next RBD in circular buffer */
785 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
786 rxb->page_dma);
787 rxq->queue[rxq->write] = rxb;
788 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
789 rxq->free_count--;
790 }
791 spin_unlock_irqrestore(&rxq->lock, flags);
792 /* If the pre-allocated buffer pool is dropping low, schedule to
793 * refill it */
794 if (rxq->free_count <= RX_LOW_WATERMARK)
795 queue_work(priv->workqueue, &priv->rx_replenish);
796
797
798 /* If we've added more space for the firmware to place data, tell it.
799 * Increment device's write pointer in multiples of 8. */
800 if (rxq->write_actual != (rxq->write & ~0x7)) {
801 spin_lock_irqsave(&rxq->lock, flags);
802 rxq->need_update = 1;
803 spin_unlock_irqrestore(&rxq->lock, flags);
804 iwl_rx_queue_update_write_ptr(priv, rxq);
805 }
806 }
807
808 /**
809 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
810 *
811 * When moving to rx_free an SKB is allocated for the slot.
812 *
813 * Also restock the Rx queue via iwl_rx_queue_restock.
814 * This is called as a scheduled work item (except for during initialization)
815 */
816 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
817 {
818 struct iwl_rx_queue *rxq = &priv->rxq;
819 struct list_head *element;
820 struct iwl_rx_mem_buffer *rxb;
821 struct page *page;
822 unsigned long flags;
823 gfp_t gfp_mask = priority;
824
825 while (1) {
826 spin_lock_irqsave(&rxq->lock, flags);
827 if (list_empty(&rxq->rx_used)) {
828 spin_unlock_irqrestore(&rxq->lock, flags);
829 return;
830 }
831 spin_unlock_irqrestore(&rxq->lock, flags);
832
833 if (rxq->free_count > RX_LOW_WATERMARK)
834 gfp_mask |= __GFP_NOWARN;
835
836 if (priv->hw_params.rx_page_order > 0)
837 gfp_mask |= __GFP_COMP;
838
839 /* Alloc a new receive buffer */
840 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
841 if (!page) {
842 if (net_ratelimit())
843 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
844 "order: %d\n",
845 priv->hw_params.rx_page_order);
846
847 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
848 net_ratelimit())
849 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
850 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
851 rxq->free_count);
852 /* We don't reschedule replenish work here -- we will
853 * call the restock method and if it still needs
854 * more buffers it will schedule replenish */
855 return;
856 }
857
858 spin_lock_irqsave(&rxq->lock, flags);
859
860 if (list_empty(&rxq->rx_used)) {
861 spin_unlock_irqrestore(&rxq->lock, flags);
862 __free_pages(page, priv->hw_params.rx_page_order);
863 return;
864 }
865 element = rxq->rx_used.next;
866 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
867 list_del(element);
868
869 spin_unlock_irqrestore(&rxq->lock, flags);
870
871 BUG_ON(rxb->page);
872 rxb->page = page;
873 /* Get physical address of the RB */
874 rxb->page_dma = dma_map_page(priv->bus.dev, page, 0,
875 PAGE_SIZE << priv->hw_params.rx_page_order,
876 DMA_FROM_DEVICE);
877 /* dma address must be no more than 36 bits */
878 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
879 /* and also 256 byte aligned! */
880 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
881
882 spin_lock_irqsave(&rxq->lock, flags);
883
884 list_add_tail(&rxb->list, &rxq->rx_free);
885 rxq->free_count++;
886
887 spin_unlock_irqrestore(&rxq->lock, flags);
888 }
889 }
890
891 void iwlagn_rx_replenish(struct iwl_priv *priv)
892 {
893 unsigned long flags;
894
895 iwlagn_rx_allocate(priv, GFP_KERNEL);
896
897 spin_lock_irqsave(&priv->lock, flags);
898 iwlagn_rx_queue_restock(priv);
899 spin_unlock_irqrestore(&priv->lock, flags);
900 }
901
902 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
903 {
904 iwlagn_rx_allocate(priv, GFP_ATOMIC);
905
906 iwlagn_rx_queue_restock(priv);
907 }
908
909 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
910 {
911 int idx = 0;
912 int band_offset = 0;
913
914 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
915 if (rate_n_flags & RATE_MCS_HT_MSK) {
916 idx = (rate_n_flags & 0xff);
917 return idx;
918 /* Legacy rate format, search for match in table */
919 } else {
920 if (band == IEEE80211_BAND_5GHZ)
921 band_offset = IWL_FIRST_OFDM_RATE;
922 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
923 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
924 return idx - band_offset;
925 }
926
927 return -1;
928 }
929
930 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
931 struct ieee80211_vif *vif,
932 enum ieee80211_band band,
933 struct iwl_scan_channel *scan_ch)
934 {
935 const struct ieee80211_supported_band *sband;
936 u16 passive_dwell = 0;
937 u16 active_dwell = 0;
938 int added = 0;
939 u16 channel = 0;
940
941 sband = iwl_get_hw_mode(priv, band);
942 if (!sband) {
943 IWL_ERR(priv, "invalid band\n");
944 return added;
945 }
946
947 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
948 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
949
950 if (passive_dwell <= active_dwell)
951 passive_dwell = active_dwell + 1;
952
953 channel = iwl_get_single_channel_number(priv, band);
954 if (channel) {
955 scan_ch->channel = cpu_to_le16(channel);
956 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
957 scan_ch->active_dwell = cpu_to_le16(active_dwell);
958 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
959 /* Set txpower levels to defaults */
960 scan_ch->dsp_atten = 110;
961 if (band == IEEE80211_BAND_5GHZ)
962 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
963 else
964 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
965 added++;
966 } else
967 IWL_ERR(priv, "no valid channel found\n");
968 return added;
969 }
970
971 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
972 struct ieee80211_vif *vif,
973 enum ieee80211_band band,
974 u8 is_active, u8 n_probes,
975 struct iwl_scan_channel *scan_ch)
976 {
977 struct ieee80211_channel *chan;
978 const struct ieee80211_supported_band *sband;
979 const struct iwl_channel_info *ch_info;
980 u16 passive_dwell = 0;
981 u16 active_dwell = 0;
982 int added, i;
983 u16 channel;
984
985 sband = iwl_get_hw_mode(priv, band);
986 if (!sband)
987 return 0;
988
989 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
990 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
991
992 if (passive_dwell <= active_dwell)
993 passive_dwell = active_dwell + 1;
994
995 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
996 chan = priv->scan_request->channels[i];
997
998 if (chan->band != band)
999 continue;
1000
1001 channel = chan->hw_value;
1002 scan_ch->channel = cpu_to_le16(channel);
1003
1004 ch_info = iwl_get_channel_info(priv, band, channel);
1005 if (!is_channel_valid(ch_info)) {
1006 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1007 channel);
1008 continue;
1009 }
1010
1011 if (!is_active || is_channel_passive(ch_info) ||
1012 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1013 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1014 else
1015 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1016
1017 if (n_probes)
1018 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1019
1020 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1021 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1022
1023 /* Set txpower levels to defaults */
1024 scan_ch->dsp_atten = 110;
1025
1026 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1027 * power level:
1028 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1029 */
1030 if (band == IEEE80211_BAND_5GHZ)
1031 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1032 else
1033 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1034
1035 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1036 channel, le32_to_cpu(scan_ch->type),
1037 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1038 "ACTIVE" : "PASSIVE",
1039 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1040 active_dwell : passive_dwell);
1041
1042 scan_ch++;
1043 added++;
1044 }
1045
1046 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1047 return added;
1048 }
1049
1050 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1051 {
1052 struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1053
1054 if (skb->len < maxlen)
1055 maxlen = skb->len;
1056
1057 memcpy(data, skb->data, maxlen);
1058
1059 return maxlen;
1060 }
1061
1062 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1063 {
1064 struct iwl_host_cmd cmd = {
1065 .id = REPLY_SCAN_CMD,
1066 .len = { sizeof(struct iwl_scan_cmd), },
1067 .flags = CMD_SYNC,
1068 };
1069 struct iwl_scan_cmd *scan;
1070 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1071 u32 rate_flags = 0;
1072 u16 cmd_len;
1073 u16 rx_chain = 0;
1074 enum ieee80211_band band;
1075 u8 n_probes = 0;
1076 u8 rx_ant = priv->hw_params.valid_rx_ant;
1077 u8 rate;
1078 bool is_active = false;
1079 int chan_mod;
1080 u8 active_chains;
1081 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1082 int ret;
1083
1084 lockdep_assert_held(&priv->mutex);
1085
1086 if (vif)
1087 ctx = iwl_rxon_ctx_from_vif(vif);
1088
1089 if (!priv->scan_cmd) {
1090 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1091 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1092 if (!priv->scan_cmd) {
1093 IWL_DEBUG_SCAN(priv,
1094 "fail to allocate memory for scan\n");
1095 return -ENOMEM;
1096 }
1097 }
1098 scan = priv->scan_cmd;
1099 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1100
1101 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1102 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1103
1104 if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1105 iwl_is_any_associated(priv)) {
1106 u16 interval = 0;
1107 u32 extra;
1108 u32 suspend_time = 100;
1109 u32 scan_suspend_time = 100;
1110
1111 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1112 switch (priv->scan_type) {
1113 case IWL_SCAN_OFFCH_TX:
1114 WARN_ON(1);
1115 break;
1116 case IWL_SCAN_RADIO_RESET:
1117 interval = 0;
1118 break;
1119 case IWL_SCAN_NORMAL:
1120 interval = vif->bss_conf.beacon_int;
1121 break;
1122 }
1123
1124 scan->suspend_time = 0;
1125 scan->max_out_time = cpu_to_le32(200 * 1024);
1126 if (!interval)
1127 interval = suspend_time;
1128
1129 extra = (suspend_time / interval) << 22;
1130 scan_suspend_time = (extra |
1131 ((suspend_time % interval) * 1024));
1132 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1133 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1134 scan_suspend_time, interval);
1135 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1136 scan->suspend_time = 0;
1137 scan->max_out_time =
1138 cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1139 }
1140
1141 switch (priv->scan_type) {
1142 case IWL_SCAN_RADIO_RESET:
1143 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1144 break;
1145 case IWL_SCAN_NORMAL:
1146 if (priv->scan_request->n_ssids) {
1147 int i, p = 0;
1148 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1149 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1150 /* always does wildcard anyway */
1151 if (!priv->scan_request->ssids[i].ssid_len)
1152 continue;
1153 scan->direct_scan[p].id = WLAN_EID_SSID;
1154 scan->direct_scan[p].len =
1155 priv->scan_request->ssids[i].ssid_len;
1156 memcpy(scan->direct_scan[p].ssid,
1157 priv->scan_request->ssids[i].ssid,
1158 priv->scan_request->ssids[i].ssid_len);
1159 n_probes++;
1160 p++;
1161 }
1162 is_active = true;
1163 } else
1164 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1165 break;
1166 case IWL_SCAN_OFFCH_TX:
1167 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1168 break;
1169 }
1170
1171 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1172 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1173 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1174
1175 switch (priv->scan_band) {
1176 case IEEE80211_BAND_2GHZ:
1177 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1178 chan_mod = le32_to_cpu(
1179 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1180 RXON_FLG_CHANNEL_MODE_MSK)
1181 >> RXON_FLG_CHANNEL_MODE_POS;
1182 if (chan_mod == CHANNEL_MODE_PURE_40) {
1183 rate = IWL_RATE_6M_PLCP;
1184 } else {
1185 rate = IWL_RATE_1M_PLCP;
1186 rate_flags = RATE_MCS_CCK_MSK;
1187 }
1188 /*
1189 * Internal scans are passive, so we can indiscriminately set
1190 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1191 */
1192 if (priv->cfg->bt_params &&
1193 priv->cfg->bt_params->advanced_bt_coexist)
1194 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1195 break;
1196 case IEEE80211_BAND_5GHZ:
1197 rate = IWL_RATE_6M_PLCP;
1198 break;
1199 default:
1200 IWL_WARN(priv, "Invalid scan band\n");
1201 return -EIO;
1202 }
1203
1204 /*
1205 * If active scanning is requested but a certain channel is
1206 * marked passive, we can do active scanning if we detect
1207 * transmissions.
1208 *
1209 * There is an issue with some firmware versions that triggers
1210 * a sysassert on a "good CRC threshold" of zero (== disabled),
1211 * on a radar channel even though this means that we should NOT
1212 * send probes.
1213 *
1214 * The "good CRC threshold" is the number of frames that we
1215 * need to receive during our dwell time on a channel before
1216 * sending out probes -- setting this to a huge value will
1217 * mean we never reach it, but at the same time work around
1218 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1219 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1220 *
1221 * This was fixed in later versions along with some other
1222 * scan changes, and the threshold behaves as a flag in those
1223 * versions.
1224 */
1225 if (priv->new_scan_threshold_behaviour)
1226 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1227 IWL_GOOD_CRC_TH_DISABLED;
1228 else
1229 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1230 IWL_GOOD_CRC_TH_NEVER;
1231
1232 band = priv->scan_band;
1233
1234 if (priv->cfg->scan_rx_antennas[band])
1235 rx_ant = priv->cfg->scan_rx_antennas[band];
1236
1237 if (band == IEEE80211_BAND_2GHZ &&
1238 priv->cfg->bt_params &&
1239 priv->cfg->bt_params->advanced_bt_coexist) {
1240 /* transmit 2.4 GHz probes only on first antenna */
1241 scan_tx_antennas = first_antenna(scan_tx_antennas);
1242 }
1243
1244 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1245 scan_tx_antennas);
1246 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1247 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1248
1249 /* In power save mode use one chain, otherwise use all chains */
1250 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1251 /* rx_ant has been set to all valid chains previously */
1252 active_chains = rx_ant &
1253 ((u8)(priv->chain_noise_data.active_chains));
1254 if (!active_chains)
1255 active_chains = rx_ant;
1256
1257 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1258 priv->chain_noise_data.active_chains);
1259
1260 rx_ant = first_antenna(active_chains);
1261 }
1262 if (priv->cfg->bt_params &&
1263 priv->cfg->bt_params->advanced_bt_coexist &&
1264 priv->bt_full_concurrent) {
1265 /* operated as 1x1 in full concurrency mode */
1266 rx_ant = first_antenna(rx_ant);
1267 }
1268
1269 /* MIMO is not used here, but value is required */
1270 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1271 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1272 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1273 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1274 scan->rx_chain = cpu_to_le16(rx_chain);
1275 switch (priv->scan_type) {
1276 case IWL_SCAN_NORMAL:
1277 cmd_len = iwl_fill_probe_req(priv,
1278 (struct ieee80211_mgmt *)scan->data,
1279 vif->addr,
1280 priv->scan_request->ie,
1281 priv->scan_request->ie_len,
1282 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1283 break;
1284 case IWL_SCAN_RADIO_RESET:
1285 /* use bcast addr, will not be transmitted but must be valid */
1286 cmd_len = iwl_fill_probe_req(priv,
1287 (struct ieee80211_mgmt *)scan->data,
1288 iwl_bcast_addr, NULL, 0,
1289 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1290 break;
1291 case IWL_SCAN_OFFCH_TX:
1292 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1293 IWL_MAX_SCAN_SIZE
1294 - sizeof(*scan)
1295 - sizeof(struct iwl_scan_channel));
1296 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1297 break;
1298 default:
1299 BUG();
1300 }
1301 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1302
1303 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1304 RXON_FILTER_BCON_AWARE_MSK);
1305
1306 switch (priv->scan_type) {
1307 case IWL_SCAN_RADIO_RESET:
1308 scan->channel_count =
1309 iwl_get_single_channel_for_scan(priv, vif, band,
1310 (void *)&scan->data[cmd_len]);
1311 break;
1312 case IWL_SCAN_NORMAL:
1313 scan->channel_count =
1314 iwl_get_channels_for_scan(priv, vif, band,
1315 is_active, n_probes,
1316 (void *)&scan->data[cmd_len]);
1317 break;
1318 case IWL_SCAN_OFFCH_TX: {
1319 struct iwl_scan_channel *scan_ch;
1320
1321 scan->channel_count = 1;
1322
1323 scan_ch = (void *)&scan->data[cmd_len];
1324 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1325 scan_ch->channel =
1326 cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1327 scan_ch->active_dwell =
1328 cpu_to_le16(priv->_agn.offchan_tx_timeout);
1329 scan_ch->passive_dwell = 0;
1330
1331 /* Set txpower levels to defaults */
1332 scan_ch->dsp_atten = 110;
1333
1334 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1335 * power level:
1336 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1337 */
1338 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1339 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1340 else
1341 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1342 }
1343 break;
1344 }
1345
1346 if (scan->channel_count == 0) {
1347 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1348 return -EIO;
1349 }
1350
1351 cmd.len[0] += le16_to_cpu(scan->tx_cmd.len) +
1352 scan->channel_count * sizeof(struct iwl_scan_channel);
1353 cmd.data[0] = scan;
1354 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
1355 scan->len = cpu_to_le16(cmd.len[0]);
1356
1357 /* set scan bit here for PAN params */
1358 set_bit(STATUS_SCAN_HW, &priv->status);
1359
1360 ret = iwlagn_set_pan_params(priv);
1361 if (ret)
1362 return ret;
1363
1364 ret = trans_send_cmd(priv, &cmd);
1365 if (ret) {
1366 clear_bit(STATUS_SCAN_HW, &priv->status);
1367 iwlagn_set_pan_params(priv);
1368 }
1369
1370 return ret;
1371 }
1372
1373 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1374 struct ieee80211_vif *vif, bool add)
1375 {
1376 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1377
1378 if (add)
1379 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1380 vif->bss_conf.bssid,
1381 &vif_priv->ibss_bssid_sta_id);
1382 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1383 vif->bss_conf.bssid);
1384 }
1385
1386 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1387 int sta_id, int tid, int freed)
1388 {
1389 lockdep_assert_held(&priv->sta_lock);
1390
1391 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1392 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1393 else {
1394 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1395 priv->stations[sta_id].tid[tid].tfds_in_queue,
1396 freed);
1397 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1398 }
1399 }
1400
1401 #define IWL_FLUSH_WAIT_MS 2000
1402
1403 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1404 {
1405 struct iwl_tx_queue *txq;
1406 struct iwl_queue *q;
1407 int cnt;
1408 unsigned long now = jiffies;
1409 int ret = 0;
1410
1411 /* waiting for all the tx frames complete might take a while */
1412 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1413 if (cnt == priv->cmd_queue)
1414 continue;
1415 txq = &priv->txq[cnt];
1416 q = &txq->q;
1417 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1418 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1419 msleep(1);
1420
1421 if (q->read_ptr != q->write_ptr) {
1422 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1423 ret = -ETIMEDOUT;
1424 break;
1425 }
1426 }
1427 return ret;
1428 }
1429
1430 #define IWL_TX_QUEUE_MSK 0xfffff
1431
1432 /**
1433 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1434 *
1435 * pre-requirements:
1436 * 1. acquire mutex before calling
1437 * 2. make sure rf is on and not in exit state
1438 */
1439 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1440 {
1441 struct iwl_txfifo_flush_cmd flush_cmd;
1442 struct iwl_host_cmd cmd = {
1443 .id = REPLY_TXFIFO_FLUSH,
1444 .len = { sizeof(struct iwl_txfifo_flush_cmd), },
1445 .flags = CMD_SYNC,
1446 .data = { &flush_cmd, },
1447 };
1448
1449 might_sleep();
1450
1451 memset(&flush_cmd, 0, sizeof(flush_cmd));
1452 if (flush_control & BIT(IWL_RXON_CTX_BSS))
1453 flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
1454 IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
1455 IWL_SCD_MGMT_MSK;
1456 if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
1457 (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
1458 flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
1459 IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
1460 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
1461 IWL_PAN_SCD_MULTICAST_MSK;
1462
1463 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
1464 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1465
1466 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1467 flush_cmd.fifo_control);
1468 flush_cmd.flush_control = cpu_to_le16(flush_control);
1469
1470 return trans_send_cmd(priv, &cmd);
1471 }
1472
1473 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1474 {
1475 mutex_lock(&priv->mutex);
1476 ieee80211_stop_queues(priv->hw);
1477 if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
1478 IWL_ERR(priv, "flush request fail\n");
1479 goto done;
1480 }
1481 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1482 iwlagn_wait_tx_queue_empty(priv);
1483 done:
1484 ieee80211_wake_queues(priv->hw);
1485 mutex_unlock(&priv->mutex);
1486 }
1487
1488 /*
1489 * BT coex
1490 */
1491 /*
1492 * Macros to access the lookup table.
1493 *
1494 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1495 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1496 *
1497 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1498 *
1499 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1500 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1501 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1502 *
1503 * These macros encode that format.
1504 */
1505 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1506 wifi_txrx, wifi_sh_ant_req) \
1507 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1508 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1509
1510 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1511 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1512 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1513 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1514 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1515 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1516 wifi_sh_ant_req))))
1517 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1518 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1519 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1520 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1521 wifi_sh_ant_req))
1522 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1523 wifi_req, wifi_prio, wifi_txrx, \
1524 wifi_sh_ant_req) \
1525 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1526 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1527 wifi_sh_ant_req))
1528
1529 #define LUT_WLAN_KILL_OP(lut, op, val) \
1530 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1531 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1532 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1533 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1534 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1535 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1536 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1537 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1538 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1539 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1540 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1541 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1542 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1543
1544 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1545 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1546 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1547 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1548 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1549 wifi_req, wifi_prio, wifi_txrx, \
1550 wifi_sh_ant_req))))
1551 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1552 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1553 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1554 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1555 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1556 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1557 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1558 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1559
1560 static const __le32 iwlagn_def_3w_lookup[12] = {
1561 cpu_to_le32(0xaaaaaaaa),
1562 cpu_to_le32(0xaaaaaaaa),
1563 cpu_to_le32(0xaeaaaaaa),
1564 cpu_to_le32(0xaaaaaaaa),
1565 cpu_to_le32(0xcc00ff28),
1566 cpu_to_le32(0x0000aaaa),
1567 cpu_to_le32(0xcc00aaaa),
1568 cpu_to_le32(0x0000aaaa),
1569 cpu_to_le32(0xc0004000),
1570 cpu_to_le32(0x00004000),
1571 cpu_to_le32(0xf0005000),
1572 cpu_to_le32(0xf0005000),
1573 };
1574
1575 static const __le32 iwlagn_concurrent_lookup[12] = {
1576 cpu_to_le32(0xaaaaaaaa),
1577 cpu_to_le32(0xaaaaaaaa),
1578 cpu_to_le32(0xaaaaaaaa),
1579 cpu_to_le32(0xaaaaaaaa),
1580 cpu_to_le32(0xaaaaaaaa),
1581 cpu_to_le32(0xaaaaaaaa),
1582 cpu_to_le32(0xaaaaaaaa),
1583 cpu_to_le32(0xaaaaaaaa),
1584 cpu_to_le32(0x00000000),
1585 cpu_to_le32(0x00000000),
1586 cpu_to_le32(0x00000000),
1587 cpu_to_le32(0x00000000),
1588 };
1589
1590 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1591 {
1592 struct iwl_basic_bt_cmd basic = {
1593 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1594 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1595 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1596 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1597 };
1598 struct iwl6000_bt_cmd bt_cmd_6000;
1599 struct iwl2000_bt_cmd bt_cmd_2000;
1600 int ret;
1601
1602 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1603 sizeof(basic.bt3_lookup_table));
1604
1605 if (priv->cfg->bt_params) {
1606 if (priv->cfg->bt_params->bt_session_2) {
1607 bt_cmd_2000.prio_boost = cpu_to_le32(
1608 priv->cfg->bt_params->bt_prio_boost);
1609 bt_cmd_2000.tx_prio_boost = 0;
1610 bt_cmd_2000.rx_prio_boost = 0;
1611 } else {
1612 bt_cmd_6000.prio_boost =
1613 priv->cfg->bt_params->bt_prio_boost;
1614 bt_cmd_6000.tx_prio_boost = 0;
1615 bt_cmd_6000.rx_prio_boost = 0;
1616 }
1617 } else {
1618 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1619 return;
1620 }
1621
1622 basic.kill_ack_mask = priv->kill_ack_mask;
1623 basic.kill_cts_mask = priv->kill_cts_mask;
1624 basic.valid = priv->bt_valid;
1625
1626 /*
1627 * Configure BT coex mode to "no coexistence" when the
1628 * user disabled BT coexistence, we have no interface
1629 * (might be in monitor mode), or the interface is in
1630 * IBSS mode (no proper uCode support for coex then).
1631 */
1632 if (!iwlagn_mod_params.bt_coex_active ||
1633 priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1634 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1635 } else {
1636 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1637 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1638 if (priv->cfg->bt_params &&
1639 priv->cfg->bt_params->bt_sco_disable)
1640 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1641
1642 if (priv->bt_ch_announce)
1643 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1644 IWL_DEBUG_COEX(priv, "BT coex flag: 0X%x\n", basic.flags);
1645 }
1646 priv->bt_enable_flag = basic.flags;
1647 if (priv->bt_full_concurrent)
1648 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1649 sizeof(iwlagn_concurrent_lookup));
1650 else
1651 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1652 sizeof(iwlagn_def_3w_lookup));
1653
1654 IWL_DEBUG_COEX(priv, "BT coex %s in %s mode\n",
1655 basic.flags ? "active" : "disabled",
1656 priv->bt_full_concurrent ?
1657 "full concurrency" : "3-wire");
1658
1659 if (priv->cfg->bt_params->bt_session_2) {
1660 memcpy(&bt_cmd_2000.basic, &basic,
1661 sizeof(basic));
1662 ret = trans_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1663 CMD_SYNC, sizeof(bt_cmd_2000), &bt_cmd_2000);
1664 } else {
1665 memcpy(&bt_cmd_6000.basic, &basic,
1666 sizeof(basic));
1667 ret = trans_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1668 CMD_SYNC, sizeof(bt_cmd_6000), &bt_cmd_6000);
1669 }
1670 if (ret)
1671 IWL_ERR(priv, "failed to send BT Coex Config\n");
1672
1673 }
1674
1675 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1676 {
1677 struct iwl_priv *priv =
1678 container_of(work, struct iwl_priv, bt_traffic_change_work);
1679 struct iwl_rxon_context *ctx;
1680 int smps_request = -1;
1681
1682 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1683 /* bt coex disabled */
1684 return;
1685 }
1686
1687 /*
1688 * Note: bt_traffic_load can be overridden by scan complete and
1689 * coex profile notifications. Ignore that since only bad consequence
1690 * can be not matching debug print with actual state.
1691 */
1692 IWL_DEBUG_COEX(priv, "BT traffic load changes: %d\n",
1693 priv->bt_traffic_load);
1694
1695 switch (priv->bt_traffic_load) {
1696 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1697 if (priv->bt_status)
1698 smps_request = IEEE80211_SMPS_DYNAMIC;
1699 else
1700 smps_request = IEEE80211_SMPS_AUTOMATIC;
1701 break;
1702 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1703 smps_request = IEEE80211_SMPS_DYNAMIC;
1704 break;
1705 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1706 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1707 smps_request = IEEE80211_SMPS_STATIC;
1708 break;
1709 default:
1710 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1711 priv->bt_traffic_load);
1712 break;
1713 }
1714
1715 mutex_lock(&priv->mutex);
1716
1717 /*
1718 * We can not send command to firmware while scanning. When the scan
1719 * complete we will schedule this work again. We do check with mutex
1720 * locked to prevent new scan request to arrive. We do not check
1721 * STATUS_SCANNING to avoid race when queue_work two times from
1722 * different notifications, but quit and not perform any work at all.
1723 */
1724 if (test_bit(STATUS_SCAN_HW, &priv->status))
1725 goto out;
1726
1727 if (priv->cfg->ops->lib->update_chain_flags)
1728 priv->cfg->ops->lib->update_chain_flags(priv);
1729
1730 if (smps_request != -1) {
1731 priv->current_ht_config.smps = smps_request;
1732 for_each_context(priv, ctx) {
1733 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1734 ieee80211_request_smps(ctx->vif, smps_request);
1735 }
1736 }
1737 out:
1738 mutex_unlock(&priv->mutex);
1739 }
1740
1741 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1742 struct iwl_bt_uart_msg *uart_msg)
1743 {
1744 IWL_DEBUG_COEX(priv, "Message Type = 0x%X, SSN = 0x%X, "
1745 "Update Req = 0x%X",
1746 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1747 BT_UART_MSG_FRAME1MSGTYPE_POS,
1748 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1749 BT_UART_MSG_FRAME1SSN_POS,
1750 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1751 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1752
1753 IWL_DEBUG_COEX(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1754 "Chl_SeqN = 0x%X, In band = 0x%X",
1755 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1756 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1757 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1758 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1759 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1760 BT_UART_MSG_FRAME2CHLSEQN_POS,
1761 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1762 BT_UART_MSG_FRAME2INBAND_POS);
1763
1764 IWL_DEBUG_COEX(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1765 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1766 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1767 BT_UART_MSG_FRAME3SCOESCO_POS,
1768 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1769 BT_UART_MSG_FRAME3SNIFF_POS,
1770 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1771 BT_UART_MSG_FRAME3A2DP_POS,
1772 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1773 BT_UART_MSG_FRAME3ACL_POS,
1774 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1775 BT_UART_MSG_FRAME3MASTER_POS,
1776 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1777 BT_UART_MSG_FRAME3OBEX_POS);
1778
1779 IWL_DEBUG_COEX(priv, "Idle duration = 0x%X",
1780 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1781 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1782
1783 IWL_DEBUG_COEX(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1784 "eSCO Retransmissions = 0x%X",
1785 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1786 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1787 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1788 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1789 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1790 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1791
1792 IWL_DEBUG_COEX(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1793 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1794 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1795 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1796 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1797
1798 IWL_DEBUG_COEX(priv, "Sniff Activity = 0x%X, Page = "
1799 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1800 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1801 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1802 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1803 BT_UART_MSG_FRAME7PAGE_POS,
1804 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1805 BT_UART_MSG_FRAME7INQUIRY_POS,
1806 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1807 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1808 }
1809
1810 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1811 struct iwl_bt_uart_msg *uart_msg)
1812 {
1813 u8 kill_msk;
1814 static const __le32 bt_kill_ack_msg[2] = {
1815 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1816 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1817 static const __le32 bt_kill_cts_msg[2] = {
1818 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1819 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1820
1821 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1822 ? 1 : 0;
1823 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1824 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1825 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1826 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1827 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1828 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1829
1830 /* schedule to send runtime bt_config */
1831 queue_work(priv->workqueue, &priv->bt_runtime_config);
1832 }
1833 }
1834
1835 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1836 struct iwl_rx_mem_buffer *rxb)
1837 {
1838 unsigned long flags;
1839 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1840 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1841 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1842
1843 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1844 /* bt coex disabled */
1845 return;
1846 }
1847
1848 IWL_DEBUG_COEX(priv, "BT Coex notification:\n");
1849 IWL_DEBUG_COEX(priv, " status: %d\n", coex->bt_status);
1850 IWL_DEBUG_COEX(priv, " traffic load: %d\n", coex->bt_traffic_load);
1851 IWL_DEBUG_COEX(priv, " CI compliance: %d\n",
1852 coex->bt_ci_compliance);
1853 iwlagn_print_uartmsg(priv, uart_msg);
1854
1855 priv->last_bt_traffic_load = priv->bt_traffic_load;
1856 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1857 if (priv->bt_status != coex->bt_status ||
1858 priv->last_bt_traffic_load != coex->bt_traffic_load) {
1859 if (coex->bt_status) {
1860 /* BT on */
1861 if (!priv->bt_ch_announce)
1862 priv->bt_traffic_load =
1863 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1864 else
1865 priv->bt_traffic_load =
1866 coex->bt_traffic_load;
1867 } else {
1868 /* BT off */
1869 priv->bt_traffic_load =
1870 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1871 }
1872 priv->bt_status = coex->bt_status;
1873 queue_work(priv->workqueue,
1874 &priv->bt_traffic_change_work);
1875 }
1876 }
1877
1878 iwlagn_set_kill_msk(priv, uart_msg);
1879
1880 /* FIXME: based on notification, adjust the prio_boost */
1881
1882 spin_lock_irqsave(&priv->lock, flags);
1883 priv->bt_ci_compliance = coex->bt_ci_compliance;
1884 spin_unlock_irqrestore(&priv->lock, flags);
1885 }
1886
1887 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1888 {
1889 iwlagn_rx_handler_setup(priv);
1890 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1891 iwlagn_bt_coex_profile_notif;
1892 }
1893
1894 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1895 {
1896 iwlagn_setup_deferred_work(priv);
1897
1898 INIT_WORK(&priv->bt_traffic_change_work,
1899 iwlagn_bt_traffic_change_work);
1900 }
1901
1902 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1903 {
1904 cancel_work_sync(&priv->bt_traffic_change_work);
1905 }
1906
1907 static bool is_single_rx_stream(struct iwl_priv *priv)
1908 {
1909 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1910 priv->current_ht_config.single_chain_sufficient;
1911 }
1912
1913 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
1914 #define IWL_NUM_RX_CHAINS_SINGLE 2
1915 #define IWL_NUM_IDLE_CHAINS_DUAL 2
1916 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
1917
1918 /*
1919 * Determine how many receiver/antenna chains to use.
1920 *
1921 * More provides better reception via diversity. Fewer saves power
1922 * at the expense of throughput, but only when not in powersave to
1923 * start with.
1924 *
1925 * MIMO (dual stream) requires at least 2, but works better with 3.
1926 * This does not determine *which* chains to use, just how many.
1927 */
1928 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1929 {
1930 if (priv->cfg->bt_params &&
1931 priv->cfg->bt_params->advanced_bt_coexist &&
1932 (priv->bt_full_concurrent ||
1933 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1934 /*
1935 * only use chain 'A' in bt high traffic load or
1936 * full concurrency mode
1937 */
1938 return IWL_NUM_RX_CHAINS_SINGLE;
1939 }
1940 /* # of Rx chains to use when expecting MIMO. */
1941 if (is_single_rx_stream(priv))
1942 return IWL_NUM_RX_CHAINS_SINGLE;
1943 else
1944 return IWL_NUM_RX_CHAINS_MULTIPLE;
1945 }
1946
1947 /*
1948 * When we are in power saving mode, unless device support spatial
1949 * multiplexing power save, use the active count for rx chain count.
1950 */
1951 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1952 {
1953 /* # Rx chains when idling, depending on SMPS mode */
1954 switch (priv->current_ht_config.smps) {
1955 case IEEE80211_SMPS_STATIC:
1956 case IEEE80211_SMPS_DYNAMIC:
1957 return IWL_NUM_IDLE_CHAINS_SINGLE;
1958 case IEEE80211_SMPS_OFF:
1959 return active_cnt;
1960 default:
1961 WARN(1, "invalid SMPS mode %d",
1962 priv->current_ht_config.smps);
1963 return active_cnt;
1964 }
1965 }
1966
1967 /* up to 4 chains */
1968 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1969 {
1970 u8 res;
1971 res = (chain_bitmap & BIT(0)) >> 0;
1972 res += (chain_bitmap & BIT(1)) >> 1;
1973 res += (chain_bitmap & BIT(2)) >> 2;
1974 res += (chain_bitmap & BIT(3)) >> 3;
1975 return res;
1976 }
1977
1978 /**
1979 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1980 *
1981 * Selects how many and which Rx receivers/antennas/chains to use.
1982 * This should not be used for scan command ... it puts data in wrong place.
1983 */
1984 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1985 {
1986 bool is_single = is_single_rx_stream(priv);
1987 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1988 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1989 u32 active_chains;
1990 u16 rx_chain;
1991
1992 /* Tell uCode which antennas are actually connected.
1993 * Before first association, we assume all antennas are connected.
1994 * Just after first association, iwl_chain_noise_calibration()
1995 * checks which antennas actually *are* connected. */
1996 if (priv->chain_noise_data.active_chains)
1997 active_chains = priv->chain_noise_data.active_chains;
1998 else
1999 active_chains = priv->hw_params.valid_rx_ant;
2000
2001 if (priv->cfg->bt_params &&
2002 priv->cfg->bt_params->advanced_bt_coexist &&
2003 (priv->bt_full_concurrent ||
2004 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2005 /*
2006 * only use chain 'A' in bt high traffic load or
2007 * full concurrency mode
2008 */
2009 active_chains = first_antenna(active_chains);
2010 }
2011
2012 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2013
2014 /* How many receivers should we use? */
2015 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2016 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2017
2018
2019 /* correct rx chain count according hw settings
2020 * and chain noise calibration
2021 */
2022 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2023 if (valid_rx_cnt < active_rx_cnt)
2024 active_rx_cnt = valid_rx_cnt;
2025
2026 if (valid_rx_cnt < idle_rx_cnt)
2027 idle_rx_cnt = valid_rx_cnt;
2028
2029 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2030 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2031
2032 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2033
2034 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2035 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2036 else
2037 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2038
2039 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2040 ctx->staging.rx_chain,
2041 active_rx_cnt, idle_rx_cnt);
2042
2043 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2044 active_rx_cnt < idle_rx_cnt);
2045 }
2046
2047 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2048 {
2049 int i;
2050 u8 ind = ant;
2051
2052 if (priv->band == IEEE80211_BAND_2GHZ &&
2053 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2054 return 0;
2055
2056 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2057 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2058 if (valid & BIT(ind))
2059 return ind;
2060 }
2061 return ant;
2062 }
2063
2064 static const char *get_csr_string(int cmd)
2065 {
2066 switch (cmd) {
2067 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2068 IWL_CMD(CSR_INT_COALESCING);
2069 IWL_CMD(CSR_INT);
2070 IWL_CMD(CSR_INT_MASK);
2071 IWL_CMD(CSR_FH_INT_STATUS);
2072 IWL_CMD(CSR_GPIO_IN);
2073 IWL_CMD(CSR_RESET);
2074 IWL_CMD(CSR_GP_CNTRL);
2075 IWL_CMD(CSR_HW_REV);
2076 IWL_CMD(CSR_EEPROM_REG);
2077 IWL_CMD(CSR_EEPROM_GP);
2078 IWL_CMD(CSR_OTP_GP_REG);
2079 IWL_CMD(CSR_GIO_REG);
2080 IWL_CMD(CSR_GP_UCODE_REG);
2081 IWL_CMD(CSR_GP_DRIVER_REG);
2082 IWL_CMD(CSR_UCODE_DRV_GP1);
2083 IWL_CMD(CSR_UCODE_DRV_GP2);
2084 IWL_CMD(CSR_LED_REG);
2085 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2086 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2087 IWL_CMD(CSR_ANA_PLL_CFG);
2088 IWL_CMD(CSR_HW_REV_WA_REG);
2089 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2090 default:
2091 return "UNKNOWN";
2092 }
2093 }
2094
2095 void iwl_dump_csr(struct iwl_priv *priv)
2096 {
2097 int i;
2098 static const u32 csr_tbl[] = {
2099 CSR_HW_IF_CONFIG_REG,
2100 CSR_INT_COALESCING,
2101 CSR_INT,
2102 CSR_INT_MASK,
2103 CSR_FH_INT_STATUS,
2104 CSR_GPIO_IN,
2105 CSR_RESET,
2106 CSR_GP_CNTRL,
2107 CSR_HW_REV,
2108 CSR_EEPROM_REG,
2109 CSR_EEPROM_GP,
2110 CSR_OTP_GP_REG,
2111 CSR_GIO_REG,
2112 CSR_GP_UCODE_REG,
2113 CSR_GP_DRIVER_REG,
2114 CSR_UCODE_DRV_GP1,
2115 CSR_UCODE_DRV_GP2,
2116 CSR_LED_REG,
2117 CSR_DRAM_INT_TBL_REG,
2118 CSR_GIO_CHICKEN_BITS,
2119 CSR_ANA_PLL_CFG,
2120 CSR_HW_REV_WA_REG,
2121 CSR_DBG_HPET_MEM_REG
2122 };
2123 IWL_ERR(priv, "CSR values:\n");
2124 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2125 "CSR_INT_PERIODIC_REG)\n");
2126 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2127 IWL_ERR(priv, " %25s: 0X%08x\n",
2128 get_csr_string(csr_tbl[i]),
2129 iwl_read32(priv, csr_tbl[i]));
2130 }
2131 }
2132
2133 static const char *get_fh_string(int cmd)
2134 {
2135 switch (cmd) {
2136 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2137 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2138 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2139 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2140 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2141 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2142 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2143 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2144 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2145 default:
2146 return "UNKNOWN";
2147 }
2148 }
2149
2150 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2151 {
2152 int i;
2153 #ifdef CONFIG_IWLWIFI_DEBUG
2154 int pos = 0;
2155 size_t bufsz = 0;
2156 #endif
2157 static const u32 fh_tbl[] = {
2158 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2159 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2160 FH_RSCSR_CHNL0_WPTR,
2161 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2162 FH_MEM_RSSR_SHARED_CTRL_REG,
2163 FH_MEM_RSSR_RX_STATUS_REG,
2164 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2165 FH_TSSR_TX_STATUS_REG,
2166 FH_TSSR_TX_ERROR_REG
2167 };
2168 #ifdef CONFIG_IWLWIFI_DEBUG
2169 if (display) {
2170 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2171 *buf = kmalloc(bufsz, GFP_KERNEL);
2172 if (!*buf)
2173 return -ENOMEM;
2174 pos += scnprintf(*buf + pos, bufsz - pos,
2175 "FH register values:\n");
2176 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2177 pos += scnprintf(*buf + pos, bufsz - pos,
2178 " %34s: 0X%08x\n",
2179 get_fh_string(fh_tbl[i]),
2180 iwl_read_direct32(priv, fh_tbl[i]));
2181 }
2182 return pos;
2183 }
2184 #endif
2185 IWL_ERR(priv, "FH register values:\n");
2186 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2187 IWL_ERR(priv, " %34s: 0X%08x\n",
2188 get_fh_string(fh_tbl[i]),
2189 iwl_read_direct32(priv, fh_tbl[i]));
2190 }
2191 return 0;
2192 }
2193
2194 /* notification wait support */
2195 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2196 struct iwl_notification_wait *wait_entry,
2197 u8 cmd,
2198 void (*fn)(struct iwl_priv *priv,
2199 struct iwl_rx_packet *pkt,
2200 void *data),
2201 void *fn_data)
2202 {
2203 wait_entry->fn = fn;
2204 wait_entry->fn_data = fn_data;
2205 wait_entry->cmd = cmd;
2206 wait_entry->triggered = false;
2207 wait_entry->aborted = false;
2208
2209 spin_lock_bh(&priv->_agn.notif_wait_lock);
2210 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2211 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2212 }
2213
2214 int iwlagn_wait_notification(struct iwl_priv *priv,
2215 struct iwl_notification_wait *wait_entry,
2216 unsigned long timeout)
2217 {
2218 int ret;
2219
2220 ret = wait_event_timeout(priv->_agn.notif_waitq,
2221 wait_entry->triggered || wait_entry->aborted,
2222 timeout);
2223
2224 spin_lock_bh(&priv->_agn.notif_wait_lock);
2225 list_del(&wait_entry->list);
2226 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2227
2228 if (wait_entry->aborted)
2229 return -EIO;
2230
2231 /* return value is always >= 0 */
2232 if (ret <= 0)
2233 return -ETIMEDOUT;
2234 return 0;
2235 }
2236
2237 void iwlagn_remove_notification(struct iwl_priv *priv,
2238 struct iwl_notification_wait *wait_entry)
2239 {
2240 spin_lock_bh(&priv->_agn.notif_wait_lock);
2241 list_del(&wait_entry->list);
2242 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2243 }
2244
2245 int iwlagn_start_device(struct iwl_priv *priv)
2246 {
2247 int ret;
2248
2249 if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
2250 iwl_prepare_card_hw(priv)) {
2251 IWL_WARN(priv, "Exit HW not ready\n");
2252 return -EIO;
2253 }
2254
2255 /* If platform's RF_KILL switch is NOT set to KILL */
2256 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2257 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2258 else
2259 set_bit(STATUS_RF_KILL_HW, &priv->status);
2260
2261 if (iwl_is_rfkill(priv)) {
2262 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2263 iwl_enable_interrupts(priv);
2264 return -ERFKILL;
2265 }
2266
2267 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2268
2269 ret = iwlagn_hw_nic_init(priv);
2270 if (ret) {
2271 IWL_ERR(priv, "Unable to init nic\n");
2272 return ret;
2273 }
2274
2275 /* make sure rfkill handshake bits are cleared */
2276 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2277 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2278 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2279
2280 /* clear (again), then enable host interrupts */
2281 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2282 iwl_enable_interrupts(priv);
2283
2284 /* really make sure rfkill handshake bits are cleared */
2285 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2286 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2287
2288 return 0;
2289 }
2290
2291 void iwlagn_stop_device(struct iwl_priv *priv)
2292 {
2293 unsigned long flags;
2294
2295 /* stop and reset the on-board processor */
2296 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2297
2298 /* tell the device to stop sending interrupts */
2299 spin_lock_irqsave(&priv->lock, flags);
2300 iwl_disable_interrupts(priv);
2301 spin_unlock_irqrestore(&priv->lock, flags);
2302 iwl_synchronize_irq(priv);
2303
2304 /* device going down, Stop using ICT table */
2305 iwl_disable_ict(priv);
2306
2307 /*
2308 * If a HW restart happens during firmware loading,
2309 * then the firmware loading might call this function
2310 * and later it might be called again due to the
2311 * restart. So don't process again if the device is
2312 * already dead.
2313 */
2314 if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2315 trans_tx_stop(priv);
2316 trans_rx_stop(priv);
2317
2318 /* Power-down device's busmaster DMA clocks */
2319 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2320 APMG_CLK_VAL_DMA_CLK_RQT);
2321 udelay(5);
2322 }
2323
2324 /* Make sure (redundant) we've released our request to stay awake */
2325 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2326
2327 /* Stop the device, and put it in low power state */
2328 iwl_apm_stop(priv);
2329 }
Linux kernel - Deliverables
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