1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
43 static inline u32
iwlagn_get_scd_ssn(struct iwlagn_tx_resp
*tx_resp
)
45 return le32_to_cpup((__le32
*)&tx_resp
->status
+
46 tx_resp
->frame_count
) & MAX_SN
;
49 static void iwlagn_count_tx_err_status(struct iwl_priv
*priv
, u16 status
)
51 status
&= TX_STATUS_MSK
;
54 case TX_STATUS_POSTPONE_DELAY
:
55 priv
->_agn
.reply_tx_stats
.pp_delay
++;
57 case TX_STATUS_POSTPONE_FEW_BYTES
:
58 priv
->_agn
.reply_tx_stats
.pp_few_bytes
++;
60 case TX_STATUS_POSTPONE_BT_PRIO
:
61 priv
->_agn
.reply_tx_stats
.pp_bt_prio
++;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD
:
64 priv
->_agn
.reply_tx_stats
.pp_quiet_period
++;
66 case TX_STATUS_POSTPONE_CALC_TTAK
:
67 priv
->_agn
.reply_tx_stats
.pp_calc_ttak
++;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY
:
70 priv
->_agn
.reply_tx_stats
.int_crossed_retry
++;
72 case TX_STATUS_FAIL_SHORT_LIMIT
:
73 priv
->_agn
.reply_tx_stats
.short_limit
++;
75 case TX_STATUS_FAIL_LONG_LIMIT
:
76 priv
->_agn
.reply_tx_stats
.long_limit
++;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN
:
79 priv
->_agn
.reply_tx_stats
.fifo_underrun
++;
81 case TX_STATUS_FAIL_DRAIN_FLOW
:
82 priv
->_agn
.reply_tx_stats
.drain_flow
++;
84 case TX_STATUS_FAIL_RFKILL_FLUSH
:
85 priv
->_agn
.reply_tx_stats
.rfkill_flush
++;
87 case TX_STATUS_FAIL_LIFE_EXPIRE
:
88 priv
->_agn
.reply_tx_stats
.life_expire
++;
90 case TX_STATUS_FAIL_DEST_PS
:
91 priv
->_agn
.reply_tx_stats
.dest_ps
++;
93 case TX_STATUS_FAIL_HOST_ABORTED
:
94 priv
->_agn
.reply_tx_stats
.host_abort
++;
96 case TX_STATUS_FAIL_BT_RETRY
:
97 priv
->_agn
.reply_tx_stats
.bt_retry
++;
99 case TX_STATUS_FAIL_STA_INVALID
:
100 priv
->_agn
.reply_tx_stats
.sta_invalid
++;
102 case TX_STATUS_FAIL_FRAG_DROPPED
:
103 priv
->_agn
.reply_tx_stats
.frag_drop
++;
105 case TX_STATUS_FAIL_TID_DISABLE
:
106 priv
->_agn
.reply_tx_stats
.tid_disable
++;
108 case TX_STATUS_FAIL_FIFO_FLUSHED
:
109 priv
->_agn
.reply_tx_stats
.fifo_flush
++;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL
:
112 priv
->_agn
.reply_tx_stats
.insuff_cf_poll
++;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX
:
115 priv
->_agn
.reply_tx_stats
.fail_hw_drop
++;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR
:
118 priv
->_agn
.reply_tx_stats
.sta_color_mismatch
++;
121 priv
->_agn
.reply_tx_stats
.unknown
++;
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv
*priv
, u16 status
)
128 status
&= AGG_TX_STATUS_MSK
;
131 case AGG_TX_STATE_UNDERRUN_MSK
:
132 priv
->_agn
.reply_agg_tx_stats
.underrun
++;
134 case AGG_TX_STATE_BT_PRIO_MSK
:
135 priv
->_agn
.reply_agg_tx_stats
.bt_prio
++;
137 case AGG_TX_STATE_FEW_BYTES_MSK
:
138 priv
->_agn
.reply_agg_tx_stats
.few_bytes
++;
140 case AGG_TX_STATE_ABORT_MSK
:
141 priv
->_agn
.reply_agg_tx_stats
.abort
++;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK
:
144 priv
->_agn
.reply_agg_tx_stats
.last_sent_ttl
++;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK
:
147 priv
->_agn
.reply_agg_tx_stats
.last_sent_try
++;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK
:
150 priv
->_agn
.reply_agg_tx_stats
.last_sent_bt_kill
++;
152 case AGG_TX_STATE_SCD_QUERY_MSK
:
153 priv
->_agn
.reply_agg_tx_stats
.scd_query
++;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK
:
156 priv
->_agn
.reply_agg_tx_stats
.bad_crc32
++;
158 case AGG_TX_STATE_RESPONSE_MSK
:
159 priv
->_agn
.reply_agg_tx_stats
.response
++;
161 case AGG_TX_STATE_DUMP_TX_MSK
:
162 priv
->_agn
.reply_agg_tx_stats
.dump_tx
++;
164 case AGG_TX_STATE_DELAY_TX_MSK
:
165 priv
->_agn
.reply_agg_tx_stats
.delay_tx
++;
168 priv
->_agn
.reply_agg_tx_stats
.unknown
++;
173 static void iwlagn_set_tx_status(struct iwl_priv
*priv
,
174 struct ieee80211_tx_info
*info
,
175 struct iwlagn_tx_resp
*tx_resp
,
176 int txq_id
, bool is_agg
)
178 u16 status
= le16_to_cpu(tx_resp
->status
.status
);
180 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
182 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
183 info
->flags
|= iwl_tx_status_to_mac80211(status
);
184 iwlagn_hwrate_to_tx_control(priv
, le32_to_cpu(tx_resp
->rate_n_flags
),
186 if (!iwl_is_tx_success(status
))
187 iwlagn_count_tx_err_status(priv
, status
);
189 IWL_DEBUG_TX_REPLY(priv
, "TXQ %d status %s (0x%08x) rate_n_flags "
192 iwl_get_tx_fail_reason(status
), status
,
193 le32_to_cpu(tx_resp
->rate_n_flags
),
194 tx_resp
->failure_frame
);
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
200 const char *iwl_get_agg_tx_fail_reason(u16 status
)
202 status
&= AGG_TX_STATUS_MSK
;
204 case AGG_TX_STATE_TRANSMITTED
:
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK
);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK
);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK
);
209 AGG_TX_STATE_FAIL(ABORT_MSK
);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK
);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK
);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK
);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK
);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK
);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK
);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK
);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK
);
222 #endif /* CONFIG_IWLWIFI_DEBUG */
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv
*priv
,
225 struct iwl_ht_agg
*agg
,
226 struct iwlagn_tx_resp
*tx_resp
,
227 int txq_id
, u16 start_idx
)
230 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
231 struct ieee80211_hdr
*hdr
= NULL
;
235 if (agg
->wait_for_ba
)
236 IWL_DEBUG_TX_REPLY(priv
, "got tx response w/o block-ack\n");
238 agg
->frame_count
= tx_resp
->frame_count
;
239 agg
->start_idx
= start_idx
;
240 agg
->rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
243 /* # frames attempted by Tx command */
244 if (agg
->frame_count
== 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
248 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg
->frame_count
, agg
->start_idx
, idx
);
250 iwlagn_set_tx_status(priv
,
252 priv
->txq
[txq_id
].txb
[idx
].skb
),
253 tx_resp
, txq_id
, true);
254 agg
->wait_for_ba
= 0;
256 /* Two or more frames were attempted; expect block-ack */
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
264 int start
= agg
->start_idx
;
266 /* Construct bit-map of pending frames within Tx window */
267 for (i
= 0; i
< agg
->frame_count
; i
++) {
269 status
= le16_to_cpu(frame_status
[i
].status
);
270 seq
= le16_to_cpu(frame_status
[i
].sequence
);
271 idx
= SEQ_TO_INDEX(seq
);
272 txq_id
= SEQ_TO_QUEUE(seq
);
274 if (status
& AGG_TX_STATUS_MSK
)
275 iwlagn_count_agg_tx_err_status(priv
, status
);
277 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
278 AGG_TX_STATE_ABORT_MSK
))
281 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg
->frame_count
, txq_id
, idx
);
283 IWL_DEBUG_TX_REPLY(priv
, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status
),
286 status
& AGG_TX_STATUS_MSK
,
287 status
& AGG_TX_TRY_MSK
);
289 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx
, txq_id
);
297 sc
= le16_to_cpu(hdr
->seq_ctrl
);
298 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
307 IWL_DEBUG_TX_REPLY(priv
, "AGG Frame i=%d idx %d seq=%d\n",
308 i
, idx
, SEQ_TO_SN(sc
));
311 * sh -> how many frames ahead of the starting frame is
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
328 /* Shift bitmap by start - idx, wrapped */
329 sh
= 0x100 - idx
+ start
;
330 bitmap
= bitmap
<< sh
;
331 /* Now idx is the new start so sh = 0 */
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
338 } else if (sh
<= -64) {
339 sh
= 0x100 - start
+ idx
;
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
345 /* Shift by how far start is ahead of idx */
347 bitmap
= bitmap
<< sh
;
348 /* Now idx is the new start so sh = 0 */
352 /* Sequence number start + sh was sent in this batch */
353 bitmap
|= 1ULL << sh
;
354 IWL_DEBUG_TX_REPLY(priv
, "start=%d bitmap=0x%llx\n",
355 start
, (unsigned long long)bitmap
);
359 * Store the bitmap and possibly the new start, if we wrapped
362 agg
->bitmap
= bitmap
;
363 agg
->start_idx
= start
;
364 IWL_DEBUG_TX_REPLY(priv
, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg
->frame_count
, agg
->start_idx
,
366 (unsigned long long)agg
->bitmap
);
369 agg
->wait_for_ba
= 1;
374 void iwl_check_abort_status(struct iwl_priv
*priv
,
375 u8 frame_count
, u32 status
)
377 if (frame_count
== 1 && status
== TX_STATUS_FAIL_RFKILL_FLUSH
) {
378 IWL_ERR(priv
, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
380 queue_work(priv
->workqueue
, &priv
->tx_flush
);
384 static void iwlagn_rx_reply_tx(struct iwl_priv
*priv
,
385 struct iwl_rx_mem_buffer
*rxb
)
387 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
388 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
389 int txq_id
= SEQ_TO_QUEUE(sequence
);
390 int index
= SEQ_TO_INDEX(sequence
);
391 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
392 struct ieee80211_tx_info
*info
;
393 struct iwlagn_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
394 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
400 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
401 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id
,
403 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
408 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
);
409 memset(&info
->status
, 0, sizeof(info
->status
));
411 tid
= (tx_resp
->ra_tid
& IWLAGN_TX_RES_TID_MSK
) >>
412 IWLAGN_TX_RES_TID_POS
;
413 sta_id
= (tx_resp
->ra_tid
& IWLAGN_TX_RES_RA_MSK
) >>
414 IWLAGN_TX_RES_RA_POS
;
416 spin_lock_irqsave(&priv
->sta_lock
, flags
);
417 if (txq
->sched_retry
) {
418 const u32 scd_ssn
= iwlagn_get_scd_ssn(tx_resp
);
419 struct iwl_ht_agg
*agg
;
421 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
423 * If the BT kill count is non-zero, we'll get this
424 * notification again.
426 if (tx_resp
->bt_kill_count
&& tx_resp
->frame_count
== 1 &&
427 priv
->cfg
->bt_params
&&
428 priv
->cfg
->bt_params
->advanced_bt_coexist
) {
429 IWL_WARN(priv
, "receive reply tx with bt_kill\n");
431 iwlagn_tx_status_reply_tx(priv
, agg
, tx_resp
, txq_id
, index
);
433 /* check if BAR is needed */
434 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
))
435 info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
437 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
438 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
439 IWL_DEBUG_TX_REPLY(priv
, "Retry scheduler reclaim "
440 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
441 scd_ssn
, index
, txq_id
, txq
->swq_id
);
443 freed
= iwlagn_tx_queue_reclaim(priv
, txq_id
, index
);
444 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
446 if (priv
->mac80211_registered
&&
447 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
448 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
449 iwl_wake_queue(priv
, txq
);
452 BUG_ON(txq_id
!= txq
->swq_id
);
453 iwlagn_set_tx_status(priv
, info
, tx_resp
, txq_id
, false);
454 freed
= iwlagn_tx_queue_reclaim(priv
, txq_id
, index
);
455 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
457 if (priv
->mac80211_registered
&&
458 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
))
459 iwl_wake_queue(priv
, txq
);
462 iwlagn_txq_check_empty(priv
, sta_id
, tid
, txq_id
);
464 iwl_check_abort_status(priv
, tx_resp
->frame_count
, status
);
465 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
468 void iwlagn_rx_handler_setup(struct iwl_priv
*priv
)
470 /* init calibration handlers */
471 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
472 iwlagn_rx_calib_result
;
473 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
474 iwlagn_rx_calib_complete
;
475 priv
->rx_handlers
[REPLY_TX
] = iwlagn_rx_reply_tx
;
478 void iwlagn_setup_deferred_work(struct iwl_priv
*priv
)
480 /* in agn, the tx power calibration is done in uCode */
481 priv
->disable_tx_power_cal
= 1;
484 int iwlagn_hw_valid_rtc_data_addr(u32 addr
)
486 return (addr
>= IWLAGN_RTC_DATA_LOWER_BOUND
) &&
487 (addr
< IWLAGN_RTC_DATA_UPPER_BOUND
);
490 int iwlagn_send_tx_power(struct iwl_priv
*priv
)
492 struct iwlagn_tx_power_dbm_cmd tx_power_cmd
;
495 if (WARN_ONCE(test_bit(STATUS_SCAN_HW
, &priv
->status
),
496 "TX Power requested while scanning!\n"))
499 /* half dBm need to multiply */
500 tx_power_cmd
.global_lmt
= (s8
)(2 * priv
->tx_power_user_lmt
);
502 if (priv
->tx_power_lmt_in_half_dbm
&&
503 priv
->tx_power_lmt_in_half_dbm
< tx_power_cmd
.global_lmt
) {
505 * For the newer devices which using enhanced/extend tx power
506 * table in EEPROM, the format is in half dBm. driver need to
507 * convert to dBm format before report to mac80211.
508 * By doing so, there is a possibility of 1/2 dBm resolution
509 * lost. driver will perform "round-up" operation before
510 * reporting, but it will cause 1/2 dBm tx power over the
511 * regulatory limit. Perform the checking here, if the
512 * "tx_power_user_lmt" is higher than EEPROM value (in
513 * half-dBm format), lower the tx power based on EEPROM
515 tx_power_cmd
.global_lmt
= priv
->tx_power_lmt_in_half_dbm
;
517 tx_power_cmd
.flags
= IWLAGN_TX_POWER_NO_CLOSED
;
518 tx_power_cmd
.srv_chan_lmt
= IWLAGN_TX_POWER_AUTO
;
520 if (IWL_UCODE_API(priv
->ucode_ver
) == 1)
521 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD_V1
;
523 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD
;
525 return iwl_send_cmd_pdu(priv
, tx_ant_cfg_cmd
, sizeof(tx_power_cmd
),
529 void iwlagn_temperature(struct iwl_priv
*priv
)
531 /* store temperature from statistics (in Celsius) */
533 le32_to_cpu(priv
->_agn
.statistics
.general
.common
.temperature
);
534 iwl_tt_handler(priv
);
537 u16
iwlagn_eeprom_calib_version(struct iwl_priv
*priv
)
539 struct iwl_eeprom_calib_hdr
{
545 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
554 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
558 if ((address
& INDIRECT_ADDRESS
) == 0)
561 switch (address
& INDIRECT_TYPE_MSK
) {
563 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_HOST
);
565 case INDIRECT_GENERAL
:
566 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_GENERAL
);
568 case INDIRECT_REGULATORY
:
569 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_REGULATORY
);
571 case INDIRECT_CALIBRATION
:
572 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_CALIBRATION
);
574 case INDIRECT_PROCESS_ADJST
:
575 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_PROCESS_ADJST
);
577 case INDIRECT_OTHERS
:
578 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_OTHERS
);
581 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
582 address
& INDIRECT_TYPE_MSK
);
586 /* translate the offset from words to byte */
587 return (address
& ADDRESS_MSK
) + (offset
<< 1);
590 const u8
*iwlagn_eeprom_query_addr(const struct iwl_priv
*priv
,
593 u32 address
= eeprom_indirect_address(priv
, offset
);
594 BUG_ON(address
>= priv
->cfg
->base_params
->eeprom_size
);
595 return &priv
->eeprom
[address
];
598 struct iwl_mod_params iwlagn_mod_params
= {
601 /* the rest are 0 by default */
604 void iwlagn_rx_queue_reset(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
608 spin_lock_irqsave(&rxq
->lock
, flags
);
609 INIT_LIST_HEAD(&rxq
->rx_free
);
610 INIT_LIST_HEAD(&rxq
->rx_used
);
611 /* Fill the rx_used queue with _all_ of the Rx buffers */
612 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
613 /* In the reset function, these buffers may have been allocated
614 * to an SKB, so we need to unmap and free potential storage */
615 if (rxq
->pool
[i
].page
!= NULL
) {
616 pci_unmap_page(priv
->pci_dev
, rxq
->pool
[i
].page_dma
,
617 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
619 __iwl_free_pages(priv
, rxq
->pool
[i
].page
);
620 rxq
->pool
[i
].page
= NULL
;
622 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
625 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
626 rxq
->queue
[i
] = NULL
;
628 /* Set us so that we have processed and used all buffers, but have
629 * not restocked the Rx queue with fresh buffers */
630 rxq
->read
= rxq
->write
= 0;
631 rxq
->write_actual
= 0;
633 spin_unlock_irqrestore(&rxq
->lock
, flags
);
636 int iwlagn_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
639 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
640 u32 rb_timeout
= 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
642 if (!priv
->cfg
->base_params
->use_isr_legacy
)
643 rb_timeout
= RX_RB_TIMEOUT
;
645 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
646 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
648 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
651 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
653 /* Reset driver's Rx queue write index */
654 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
656 /* Tell device where to find RBD circular buffer in DRAM */
657 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
658 (u32
)(rxq
->bd_dma
>> 8));
660 /* Tell device where in DRAM to update its Rx status */
661 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
662 rxq
->rb_stts_dma
>> 4);
665 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
666 * the credit mechanism in 5000 HW RX FIFO
667 * Direct rx interrupts to hosts
668 * Rx buffer size 4 or 8k
672 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
673 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
674 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
675 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
676 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
678 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
679 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
681 /* Set interrupt coalescing timer to default (2048 usecs) */
682 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
687 static void iwlagn_set_pwr_vmain(struct iwl_priv
*priv
)
690 * (for documentation purposes)
691 * to set power to V_AUX, do:
693 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
694 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
695 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
696 ~APMG_PS_CTRL_MSK_PWR_SRC);
699 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
700 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
701 ~APMG_PS_CTRL_MSK_PWR_SRC
);
704 int iwlagn_hw_nic_init(struct iwl_priv
*priv
)
707 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
711 spin_lock_irqsave(&priv
->lock
, flags
);
712 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
714 /* Set interrupt coalescing calibration timer to default (512 usecs) */
715 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
717 spin_unlock_irqrestore(&priv
->lock
, flags
);
719 iwlagn_set_pwr_vmain(priv
);
721 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
723 /* Allocate the RX queue, or reset if it is already allocated */
725 ret
= iwl_rx_queue_alloc(priv
);
727 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
731 iwlagn_rx_queue_reset(priv
, rxq
);
733 iwlagn_rx_replenish(priv
);
735 iwlagn_rx_init(priv
, rxq
);
737 spin_lock_irqsave(&priv
->lock
, flags
);
739 rxq
->need_update
= 1;
740 iwl_rx_queue_update_write_ptr(priv
, rxq
);
742 spin_unlock_irqrestore(&priv
->lock
, flags
);
744 /* Allocate or reset and init all Tx and Command queues */
746 ret
= iwlagn_txq_ctx_alloc(priv
);
750 iwlagn_txq_ctx_reset(priv
);
752 if (priv
->cfg
->base_params
->shadow_reg_enable
) {
753 /* enable shadow regs in HW */
754 iwl_set_bit(priv
, CSR_MAC_SHADOW_REG_CTRL
,
758 set_bit(STATUS_INIT
, &priv
->status
);
764 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
766 static inline __le32
iwlagn_dma_addr2rbd_ptr(struct iwl_priv
*priv
,
769 return cpu_to_le32((u32
)(dma_addr
>> 8));
773 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
775 * If there are slots in the RX queue that need to be restocked,
776 * and we have free pre-allocated buffers, fill the ranks as much
777 * as we can, pulling from rx_free.
779 * This moves the 'write' index forward to catch up with 'processed', and
780 * also updates the memory address in the firmware to reference the new
783 void iwlagn_rx_queue_restock(struct iwl_priv
*priv
)
785 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
786 struct list_head
*element
;
787 struct iwl_rx_mem_buffer
*rxb
;
790 spin_lock_irqsave(&rxq
->lock
, flags
);
791 while ((iwl_rx_queue_space(rxq
) > 0) && (rxq
->free_count
)) {
792 /* The overwritten rxb must be a used one */
793 rxb
= rxq
->queue
[rxq
->write
];
794 BUG_ON(rxb
&& rxb
->page
);
796 /* Get next free Rx buffer, remove from free list */
797 element
= rxq
->rx_free
.next
;
798 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
801 /* Point to Rx buffer via next RBD in circular buffer */
802 rxq
->bd
[rxq
->write
] = iwlagn_dma_addr2rbd_ptr(priv
,
804 rxq
->queue
[rxq
->write
] = rxb
;
805 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
808 spin_unlock_irqrestore(&rxq
->lock
, flags
);
809 /* If the pre-allocated buffer pool is dropping low, schedule to
811 if (rxq
->free_count
<= RX_LOW_WATERMARK
)
812 queue_work(priv
->workqueue
, &priv
->rx_replenish
);
815 /* If we've added more space for the firmware to place data, tell it.
816 * Increment device's write pointer in multiples of 8. */
817 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
818 spin_lock_irqsave(&rxq
->lock
, flags
);
819 rxq
->need_update
= 1;
820 spin_unlock_irqrestore(&rxq
->lock
, flags
);
821 iwl_rx_queue_update_write_ptr(priv
, rxq
);
826 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
828 * When moving to rx_free an SKB is allocated for the slot.
830 * Also restock the Rx queue via iwl_rx_queue_restock.
831 * This is called as a scheduled work item (except for during initialization)
833 void iwlagn_rx_allocate(struct iwl_priv
*priv
, gfp_t priority
)
835 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
836 struct list_head
*element
;
837 struct iwl_rx_mem_buffer
*rxb
;
840 gfp_t gfp_mask
= priority
;
843 spin_lock_irqsave(&rxq
->lock
, flags
);
844 if (list_empty(&rxq
->rx_used
)) {
845 spin_unlock_irqrestore(&rxq
->lock
, flags
);
848 spin_unlock_irqrestore(&rxq
->lock
, flags
);
850 if (rxq
->free_count
> RX_LOW_WATERMARK
)
851 gfp_mask
|= __GFP_NOWARN
;
853 if (priv
->hw_params
.rx_page_order
> 0)
854 gfp_mask
|= __GFP_COMP
;
856 /* Alloc a new receive buffer */
857 page
= alloc_pages(gfp_mask
, priv
->hw_params
.rx_page_order
);
860 IWL_DEBUG_INFO(priv
, "alloc_pages failed, "
862 priv
->hw_params
.rx_page_order
);
864 if ((rxq
->free_count
<= RX_LOW_WATERMARK
) &&
866 IWL_CRIT(priv
, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
867 priority
== GFP_ATOMIC
? "GFP_ATOMIC" : "GFP_KERNEL",
869 /* We don't reschedule replenish work here -- we will
870 * call the restock method and if it still needs
871 * more buffers it will schedule replenish */
875 spin_lock_irqsave(&rxq
->lock
, flags
);
877 if (list_empty(&rxq
->rx_used
)) {
878 spin_unlock_irqrestore(&rxq
->lock
, flags
);
879 __free_pages(page
, priv
->hw_params
.rx_page_order
);
882 element
= rxq
->rx_used
.next
;
883 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
886 spin_unlock_irqrestore(&rxq
->lock
, flags
);
890 /* Get physical address of the RB */
891 rxb
->page_dma
= pci_map_page(priv
->pci_dev
, page
, 0,
892 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
894 /* dma address must be no more than 36 bits */
895 BUG_ON(rxb
->page_dma
& ~DMA_BIT_MASK(36));
896 /* and also 256 byte aligned! */
897 BUG_ON(rxb
->page_dma
& DMA_BIT_MASK(8));
899 spin_lock_irqsave(&rxq
->lock
, flags
);
901 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
903 priv
->alloc_rxb_page
++;
905 spin_unlock_irqrestore(&rxq
->lock
, flags
);
909 void iwlagn_rx_replenish(struct iwl_priv
*priv
)
913 iwlagn_rx_allocate(priv
, GFP_KERNEL
);
915 spin_lock_irqsave(&priv
->lock
, flags
);
916 iwlagn_rx_queue_restock(priv
);
917 spin_unlock_irqrestore(&priv
->lock
, flags
);
920 void iwlagn_rx_replenish_now(struct iwl_priv
*priv
)
922 iwlagn_rx_allocate(priv
, GFP_ATOMIC
);
924 iwlagn_rx_queue_restock(priv
);
927 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
928 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
929 * This free routine walks the list of POOL entries and if SKB is set to
930 * non NULL it is unmapped and freed
932 void iwlagn_rx_queue_free(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
935 for (i
= 0; i
< RX_QUEUE_SIZE
+ RX_FREE_BUFFERS
; i
++) {
936 if (rxq
->pool
[i
].page
!= NULL
) {
937 pci_unmap_page(priv
->pci_dev
, rxq
->pool
[i
].page_dma
,
938 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
940 __iwl_free_pages(priv
, rxq
->pool
[i
].page
);
941 rxq
->pool
[i
].page
= NULL
;
945 dma_free_coherent(&priv
->pci_dev
->dev
, 4 * RX_QUEUE_SIZE
, rxq
->bd
,
947 dma_free_coherent(&priv
->pci_dev
->dev
, sizeof(struct iwl_rb_status
),
948 rxq
->rb_stts
, rxq
->rb_stts_dma
);
953 int iwlagn_rxq_stop(struct iwl_priv
*priv
)
957 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
958 iwl_poll_direct_bit(priv
, FH_MEM_RSSR_RX_STATUS_REG
,
959 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
964 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags
, enum ieee80211_band band
)
969 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
970 if (rate_n_flags
& RATE_MCS_HT_MSK
) {
971 idx
= (rate_n_flags
& 0xff);
973 /* Legacy rate format, search for match in table */
975 if (band
== IEEE80211_BAND_5GHZ
)
976 band_offset
= IWL_FIRST_OFDM_RATE
;
977 for (idx
= band_offset
; idx
< IWL_RATE_COUNT_LEGACY
; idx
++)
978 if (iwl_rates
[idx
].plcp
== (rate_n_flags
& 0xFF))
979 return idx
- band_offset
;
985 /* Calc max signal level (dBm) among 3 possible receivers */
986 static inline int iwlagn_calc_rssi(struct iwl_priv
*priv
,
987 struct iwl_rx_phy_res
*rx_resp
)
989 return priv
->cfg
->ops
->utils
->calc_rssi(priv
, rx_resp
);
992 static u32
iwlagn_translate_rx_status(struct iwl_priv
*priv
, u32 decrypt_in
)
996 if ((decrypt_in
& RX_RES_STATUS_STATION_FOUND
) ==
997 RX_RES_STATUS_STATION_FOUND
)
998 decrypt_out
|= (RX_RES_STATUS_STATION_FOUND
|
999 RX_RES_STATUS_NO_STATION_INFO_MISMATCH
);
1001 decrypt_out
|= (decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
);
1003 /* packet was not encrypted */
1004 if ((decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) ==
1005 RX_RES_STATUS_SEC_TYPE_NONE
)
1008 /* packet was encrypted with unknown alg */
1009 if ((decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) ==
1010 RX_RES_STATUS_SEC_TYPE_ERR
)
1013 /* decryption was not done in HW */
1014 if ((decrypt_in
& RX_MPDU_RES_STATUS_DEC_DONE_MSK
) !=
1015 RX_MPDU_RES_STATUS_DEC_DONE_MSK
)
1018 switch (decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) {
1020 case RX_RES_STATUS_SEC_TYPE_CCMP
:
1021 /* alg is CCM: check MIC only */
1022 if (!(decrypt_in
& RX_MPDU_RES_STATUS_MIC_OK
))
1024 decrypt_out
|= RX_RES_STATUS_BAD_ICV_MIC
;
1026 decrypt_out
|= RX_RES_STATUS_DECRYPT_OK
;
1030 case RX_RES_STATUS_SEC_TYPE_TKIP
:
1031 if (!(decrypt_in
& RX_MPDU_RES_STATUS_TTAK_OK
)) {
1033 decrypt_out
|= RX_RES_STATUS_BAD_KEY_TTAK
;
1036 /* fall through if TTAK OK */
1038 if (!(decrypt_in
& RX_MPDU_RES_STATUS_ICV_OK
))
1039 decrypt_out
|= RX_RES_STATUS_BAD_ICV_MIC
;
1041 decrypt_out
|= RX_RES_STATUS_DECRYPT_OK
;
1045 IWL_DEBUG_RX(priv
, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1046 decrypt_in
, decrypt_out
);
1051 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv
*priv
,
1052 struct ieee80211_hdr
*hdr
,
1055 struct iwl_rx_mem_buffer
*rxb
,
1056 struct ieee80211_rx_status
*stats
)
1058 struct sk_buff
*skb
;
1059 __le16 fc
= hdr
->frame_control
;
1061 /* We only process data packets if the interface is open */
1062 if (unlikely(!priv
->is_open
)) {
1063 IWL_DEBUG_DROP_LIMIT(priv
,
1064 "Dropping packet while interface is not open.\n");
1068 /* In case of HW accelerated crypto and bad decryption, drop */
1069 if (!priv
->cfg
->mod_params
->sw_crypto
&&
1070 iwl_set_decrypted_flag(priv
, hdr
, ampdu_status
, stats
))
1073 skb
= dev_alloc_skb(128);
1075 IWL_ERR(priv
, "dev_alloc_skb failed\n");
1079 skb_add_rx_frag(skb
, 0, rxb
->page
, (void *)hdr
- rxb_addr(rxb
), len
);
1081 iwl_update_stats(priv
, false, fc
, len
);
1082 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
1084 ieee80211_rx(priv
->hw
, skb
);
1085 priv
->alloc_rxb_page
--;
1089 /* Called for REPLY_RX (legacy ABG frames), or
1090 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1091 void iwlagn_rx_reply_rx(struct iwl_priv
*priv
,
1092 struct iwl_rx_mem_buffer
*rxb
)
1094 struct ieee80211_hdr
*header
;
1095 struct ieee80211_rx_status rx_status
;
1096 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1097 struct iwl_rx_phy_res
*phy_res
;
1098 __le32 rx_pkt_status
;
1099 struct iwl_rx_mpdu_res_start
*amsdu
;
1105 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1106 * REPLY_RX: physical layer info is in this buffer
1107 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1108 * command and cached in priv->last_phy_res
1110 * Here we set up local variables depending on which command is
1113 if (pkt
->hdr
.cmd
== REPLY_RX
) {
1114 phy_res
= (struct iwl_rx_phy_res
*)pkt
->u
.raw
;
1115 header
= (struct ieee80211_hdr
*)(pkt
->u
.raw
+ sizeof(*phy_res
)
1116 + phy_res
->cfg_phy_cnt
);
1118 len
= le16_to_cpu(phy_res
->byte_count
);
1119 rx_pkt_status
= *(__le32
*)(pkt
->u
.raw
+ sizeof(*phy_res
) +
1120 phy_res
->cfg_phy_cnt
+ len
);
1121 ampdu_status
= le32_to_cpu(rx_pkt_status
);
1123 if (!priv
->_agn
.last_phy_res_valid
) {
1124 IWL_ERR(priv
, "MPDU frame without cached PHY data\n");
1127 phy_res
= &priv
->_agn
.last_phy_res
;
1128 amsdu
= (struct iwl_rx_mpdu_res_start
*)pkt
->u
.raw
;
1129 header
= (struct ieee80211_hdr
*)(pkt
->u
.raw
+ sizeof(*amsdu
));
1130 len
= le16_to_cpu(amsdu
->byte_count
);
1131 rx_pkt_status
= *(__le32
*)(pkt
->u
.raw
+ sizeof(*amsdu
) + len
);
1132 ampdu_status
= iwlagn_translate_rx_status(priv
,
1133 le32_to_cpu(rx_pkt_status
));
1136 if ((unlikely(phy_res
->cfg_phy_cnt
> 20))) {
1137 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
1138 phy_res
->cfg_phy_cnt
);
1142 if (!(rx_pkt_status
& RX_RES_STATUS_NO_CRC32_ERROR
) ||
1143 !(rx_pkt_status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
1144 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n",
1145 le32_to_cpu(rx_pkt_status
));
1149 /* This will be used in several places later */
1150 rate_n_flags
= le32_to_cpu(phy_res
->rate_n_flags
);
1152 /* rx_status carries information about the packet to mac80211 */
1153 rx_status
.mactime
= le64_to_cpu(phy_res
->timestamp
);
1155 ieee80211_channel_to_frequency(le16_to_cpu(phy_res
->channel
));
1156 rx_status
.band
= (phy_res
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
1157 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
1158 rx_status
.rate_idx
=
1159 iwlagn_hwrate_to_mac80211_idx(rate_n_flags
, rx_status
.band
);
1162 /* TSF isn't reliable. In order to allow smooth user experience,
1163 * this W/A doesn't propagate it to the mac80211 */
1164 /*rx_status.flag |= RX_FLAG_TSFT;*/
1166 priv
->ucode_beacon_time
= le32_to_cpu(phy_res
->beacon_time_stamp
);
1168 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1169 rx_status
.signal
= iwlagn_calc_rssi(priv
, phy_res
);
1171 iwl_dbg_log_rx_data_frame(priv
, len
, header
);
1172 IWL_DEBUG_STATS_LIMIT(priv
, "Rssi %d, TSF %llu\n",
1173 rx_status
.signal
, (unsigned long long)rx_status
.mactime
);
1178 * It seems that the antenna field in the phy flags value
1179 * is actually a bit field. This is undefined by radiotap,
1180 * it wants an actual antenna number but I always get "7"
1181 * for most legacy frames I receive indicating that the
1182 * same frame was received on all three RX chains.
1184 * I think this field should be removed in favor of a
1185 * new 802.11n radiotap field "RX chains" that is defined
1189 (le16_to_cpu(phy_res
->phy_flags
) & RX_RES_PHY_FLAGS_ANTENNA_MSK
)
1190 >> RX_RES_PHY_FLAGS_ANTENNA_POS
;
1192 /* set the preamble flag if appropriate */
1193 if (phy_res
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
1194 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
1196 /* Set up the HT phy flags */
1197 if (rate_n_flags
& RATE_MCS_HT_MSK
)
1198 rx_status
.flag
|= RX_FLAG_HT
;
1199 if (rate_n_flags
& RATE_MCS_HT40_MSK
)
1200 rx_status
.flag
|= RX_FLAG_40MHZ
;
1201 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
1202 rx_status
.flag
|= RX_FLAG_SHORT_GI
;
1204 iwlagn_pass_packet_to_mac80211(priv
, header
, len
, ampdu_status
,
1208 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1209 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1210 void iwlagn_rx_reply_rx_phy(struct iwl_priv
*priv
,
1211 struct iwl_rx_mem_buffer
*rxb
)
1213 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1214 priv
->_agn
.last_phy_res_valid
= true;
1215 memcpy(&priv
->_agn
.last_phy_res
, pkt
->u
.raw
,
1216 sizeof(struct iwl_rx_phy_res
));
1219 static int iwl_get_single_channel_for_scan(struct iwl_priv
*priv
,
1220 struct ieee80211_vif
*vif
,
1221 enum ieee80211_band band
,
1222 struct iwl_scan_channel
*scan_ch
)
1224 const struct ieee80211_supported_band
*sband
;
1225 u16 passive_dwell
= 0;
1226 u16 active_dwell
= 0;
1230 sband
= iwl_get_hw_mode(priv
, band
);
1232 IWL_ERR(priv
, "invalid band\n");
1236 active_dwell
= iwl_get_active_dwell_time(priv
, band
, 0);
1237 passive_dwell
= iwl_get_passive_dwell_time(priv
, band
, vif
);
1239 if (passive_dwell
<= active_dwell
)
1240 passive_dwell
= active_dwell
+ 1;
1242 channel
= iwl_get_single_channel_number(priv
, band
);
1244 scan_ch
->channel
= cpu_to_le16(channel
);
1245 scan_ch
->type
= SCAN_CHANNEL_TYPE_PASSIVE
;
1246 scan_ch
->active_dwell
= cpu_to_le16(active_dwell
);
1247 scan_ch
->passive_dwell
= cpu_to_le16(passive_dwell
);
1248 /* Set txpower levels to defaults */
1249 scan_ch
->dsp_atten
= 110;
1250 if (band
== IEEE80211_BAND_5GHZ
)
1251 scan_ch
->tx_gain
= ((1 << 5) | (3 << 3)) | 3;
1253 scan_ch
->tx_gain
= ((1 << 5) | (5 << 3));
1256 IWL_ERR(priv
, "no valid channel found\n");
1260 static int iwl_get_channels_for_scan(struct iwl_priv
*priv
,
1261 struct ieee80211_vif
*vif
,
1262 enum ieee80211_band band
,
1263 u8 is_active
, u8 n_probes
,
1264 struct iwl_scan_channel
*scan_ch
)
1266 struct ieee80211_channel
*chan
;
1267 const struct ieee80211_supported_band
*sband
;
1268 const struct iwl_channel_info
*ch_info
;
1269 u16 passive_dwell
= 0;
1270 u16 active_dwell
= 0;
1274 sband
= iwl_get_hw_mode(priv
, band
);
1278 active_dwell
= iwl_get_active_dwell_time(priv
, band
, n_probes
);
1279 passive_dwell
= iwl_get_passive_dwell_time(priv
, band
, vif
);
1281 if (passive_dwell
<= active_dwell
)
1282 passive_dwell
= active_dwell
+ 1;
1284 for (i
= 0, added
= 0; i
< priv
->scan_request
->n_channels
; i
++) {
1285 chan
= priv
->scan_request
->channels
[i
];
1287 if (chan
->band
!= band
)
1290 channel
= chan
->hw_value
;
1291 scan_ch
->channel
= cpu_to_le16(channel
);
1293 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
1294 if (!is_channel_valid(ch_info
)) {
1295 IWL_DEBUG_SCAN(priv
, "Channel %d is INVALID for this band.\n",
1300 if (!is_active
|| is_channel_passive(ch_info
) ||
1301 (chan
->flags
& IEEE80211_CHAN_PASSIVE_SCAN
))
1302 scan_ch
->type
= SCAN_CHANNEL_TYPE_PASSIVE
;
1304 scan_ch
->type
= SCAN_CHANNEL_TYPE_ACTIVE
;
1307 scan_ch
->type
|= IWL_SCAN_PROBE_MASK(n_probes
);
1309 scan_ch
->active_dwell
= cpu_to_le16(active_dwell
);
1310 scan_ch
->passive_dwell
= cpu_to_le16(passive_dwell
);
1312 /* Set txpower levels to defaults */
1313 scan_ch
->dsp_atten
= 110;
1315 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1317 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1319 if (band
== IEEE80211_BAND_5GHZ
)
1320 scan_ch
->tx_gain
= ((1 << 5) | (3 << 3)) | 3;
1322 scan_ch
->tx_gain
= ((1 << 5) | (5 << 3));
1324 IWL_DEBUG_SCAN(priv
, "Scanning ch=%d prob=0x%X [%s %d]\n",
1325 channel
, le32_to_cpu(scan_ch
->type
),
1326 (scan_ch
->type
& SCAN_CHANNEL_TYPE_ACTIVE
) ?
1327 "ACTIVE" : "PASSIVE",
1328 (scan_ch
->type
& SCAN_CHANNEL_TYPE_ACTIVE
) ?
1329 active_dwell
: passive_dwell
);
1335 IWL_DEBUG_SCAN(priv
, "total channels to scan %d\n", added
);
1339 int iwlagn_request_scan(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
)
1341 struct iwl_host_cmd cmd
= {
1342 .id
= REPLY_SCAN_CMD
,
1343 .len
= sizeof(struct iwl_scan_cmd
),
1344 .flags
= CMD_SIZE_HUGE
,
1346 struct iwl_scan_cmd
*scan
;
1347 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
1351 enum ieee80211_band band
;
1353 u8 rx_ant
= priv
->hw_params
.valid_rx_ant
;
1355 bool is_active
= false;
1358 u8 scan_tx_antennas
= priv
->hw_params
.valid_tx_ant
;
1361 lockdep_assert_held(&priv
->mutex
);
1364 ctx
= iwl_rxon_ctx_from_vif(vif
);
1366 if (!priv
->scan_cmd
) {
1367 priv
->scan_cmd
= kmalloc(sizeof(struct iwl_scan_cmd
) +
1368 IWL_MAX_SCAN_SIZE
, GFP_KERNEL
);
1369 if (!priv
->scan_cmd
) {
1370 IWL_DEBUG_SCAN(priv
,
1371 "fail to allocate memory for scan\n");
1375 scan
= priv
->scan_cmd
;
1376 memset(scan
, 0, sizeof(struct iwl_scan_cmd
) + IWL_MAX_SCAN_SIZE
);
1378 scan
->quiet_plcp_th
= IWL_PLCP_QUIET_THRESH
;
1379 scan
->quiet_time
= IWL_ACTIVE_QUIET_TIME
;
1381 if (iwl_is_any_associated(priv
)) {
1384 u32 suspend_time
= 100;
1385 u32 scan_suspend_time
= 100;
1386 unsigned long flags
;
1388 IWL_DEBUG_INFO(priv
, "Scanning while associated...\n");
1389 spin_lock_irqsave(&priv
->lock
, flags
);
1390 if (priv
->is_internal_short_scan
)
1393 interval
= vif
->bss_conf
.beacon_int
;
1394 spin_unlock_irqrestore(&priv
->lock
, flags
);
1396 scan
->suspend_time
= 0;
1397 scan
->max_out_time
= cpu_to_le32(200 * 1024);
1399 interval
= suspend_time
;
1401 extra
= (suspend_time
/ interval
) << 22;
1402 scan_suspend_time
= (extra
|
1403 ((suspend_time
% interval
) * 1024));
1404 scan
->suspend_time
= cpu_to_le32(scan_suspend_time
);
1405 IWL_DEBUG_SCAN(priv
, "suspend_time 0x%X beacon interval %d\n",
1406 scan_suspend_time
, interval
);
1409 if (priv
->is_internal_short_scan
) {
1410 IWL_DEBUG_SCAN(priv
, "Start internal passive scan.\n");
1411 } else if (priv
->scan_request
->n_ssids
) {
1413 IWL_DEBUG_SCAN(priv
, "Kicking off active scan\n");
1414 for (i
= 0; i
< priv
->scan_request
->n_ssids
; i
++) {
1415 /* always does wildcard anyway */
1416 if (!priv
->scan_request
->ssids
[i
].ssid_len
)
1418 scan
->direct_scan
[p
].id
= WLAN_EID_SSID
;
1419 scan
->direct_scan
[p
].len
=
1420 priv
->scan_request
->ssids
[i
].ssid_len
;
1421 memcpy(scan
->direct_scan
[p
].ssid
,
1422 priv
->scan_request
->ssids
[i
].ssid
,
1423 priv
->scan_request
->ssids
[i
].ssid_len
);
1429 IWL_DEBUG_SCAN(priv
, "Start passive scan.\n");
1431 scan
->tx_cmd
.tx_flags
= TX_CMD_FLG_SEQ_CTL_MSK
;
1432 scan
->tx_cmd
.sta_id
= ctx
->bcast_sta_id
;
1433 scan
->tx_cmd
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
1435 switch (priv
->scan_band
) {
1436 case IEEE80211_BAND_2GHZ
:
1437 scan
->flags
= RXON_FLG_BAND_24G_MSK
| RXON_FLG_AUTO_DETECT_MSK
;
1438 chan_mod
= le32_to_cpu(
1439 priv
->contexts
[IWL_RXON_CTX_BSS
].active
.flags
&
1440 RXON_FLG_CHANNEL_MODE_MSK
)
1441 >> RXON_FLG_CHANNEL_MODE_POS
;
1442 if (chan_mod
== CHANNEL_MODE_PURE_40
) {
1443 rate
= IWL_RATE_6M_PLCP
;
1445 rate
= IWL_RATE_1M_PLCP
;
1446 rate_flags
= RATE_MCS_CCK_MSK
;
1449 * Internal scans are passive, so we can indiscriminately set
1450 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1452 if (priv
->cfg
->bt_params
&&
1453 priv
->cfg
->bt_params
->advanced_bt_coexist
)
1454 scan
->tx_cmd
.tx_flags
|= TX_CMD_FLG_IGNORE_BT
;
1456 case IEEE80211_BAND_5GHZ
:
1457 rate
= IWL_RATE_6M_PLCP
;
1460 IWL_WARN(priv
, "Invalid scan band\n");
1465 * If active scanning is requested but a certain channel is
1466 * marked passive, we can do active scanning if we detect
1469 * There is an issue with some firmware versions that triggers
1470 * a sysassert on a "good CRC threshold" of zero (== disabled),
1471 * on a radar channel even though this means that we should NOT
1474 * The "good CRC threshold" is the number of frames that we
1475 * need to receive during our dwell time on a channel before
1476 * sending out probes -- setting this to a huge value will
1477 * mean we never reach it, but at the same time work around
1478 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1479 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1481 scan
->good_CRC_th
= is_active
? IWL_GOOD_CRC_TH_DEFAULT
:
1482 IWL_GOOD_CRC_TH_NEVER
;
1484 band
= priv
->scan_band
;
1486 if (priv
->cfg
->scan_rx_antennas
[band
])
1487 rx_ant
= priv
->cfg
->scan_rx_antennas
[band
];
1489 if (priv
->cfg
->scan_tx_antennas
[band
])
1490 scan_tx_antennas
= priv
->cfg
->scan_tx_antennas
[band
];
1492 if (priv
->cfg
->bt_params
&&
1493 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
1494 priv
->bt_full_concurrent
) {
1495 /* operated as 1x1 in full concurrency mode */
1496 scan_tx_antennas
= first_antenna(
1497 priv
->cfg
->scan_tx_antennas
[band
]);
1500 priv
->scan_tx_ant
[band
] = iwl_toggle_tx_ant(priv
, priv
->scan_tx_ant
[band
],
1502 rate_flags
|= iwl_ant_idx_to_flags(priv
->scan_tx_ant
[band
]);
1503 scan
->tx_cmd
.rate_n_flags
= iwl_hw_set_rate_n_flags(rate
, rate_flags
);
1505 /* In power save mode use one chain, otherwise use all chains */
1506 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
1507 /* rx_ant has been set to all valid chains previously */
1508 active_chains
= rx_ant
&
1509 ((u8
)(priv
->chain_noise_data
.active_chains
));
1511 active_chains
= rx_ant
;
1513 IWL_DEBUG_SCAN(priv
, "chain_noise_data.active_chains: %u\n",
1514 priv
->chain_noise_data
.active_chains
);
1516 rx_ant
= first_antenna(active_chains
);
1518 if (priv
->cfg
->bt_params
&&
1519 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
1520 priv
->bt_full_concurrent
) {
1521 /* operated as 1x1 in full concurrency mode */
1522 rx_ant
= first_antenna(rx_ant
);
1525 /* MIMO is not used here, but value is required */
1526 rx_chain
|= priv
->hw_params
.valid_rx_ant
<< RXON_RX_CHAIN_VALID_POS
;
1527 rx_chain
|= rx_ant
<< RXON_RX_CHAIN_FORCE_MIMO_SEL_POS
;
1528 rx_chain
|= rx_ant
<< RXON_RX_CHAIN_FORCE_SEL_POS
;
1529 rx_chain
|= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS
;
1530 scan
->rx_chain
= cpu_to_le16(rx_chain
);
1531 if (!priv
->is_internal_short_scan
) {
1532 cmd_len
= iwl_fill_probe_req(priv
,
1533 (struct ieee80211_mgmt
*)scan
->data
,
1535 priv
->scan_request
->ie
,
1536 priv
->scan_request
->ie_len
,
1537 IWL_MAX_SCAN_SIZE
- sizeof(*scan
));
1539 /* use bcast addr, will not be transmitted but must be valid */
1540 cmd_len
= iwl_fill_probe_req(priv
,
1541 (struct ieee80211_mgmt
*)scan
->data
,
1542 iwl_bcast_addr
, NULL
, 0,
1543 IWL_MAX_SCAN_SIZE
- sizeof(*scan
));
1546 scan
->tx_cmd
.len
= cpu_to_le16(cmd_len
);
1548 scan
->filter_flags
|= (RXON_FILTER_ACCEPT_GRP_MSK
|
1549 RXON_FILTER_BCON_AWARE_MSK
);
1551 if (priv
->is_internal_short_scan
) {
1552 scan
->channel_count
=
1553 iwl_get_single_channel_for_scan(priv
, vif
, band
,
1554 (void *)&scan
->data
[le16_to_cpu(
1555 scan
->tx_cmd
.len
)]);
1557 scan
->channel_count
=
1558 iwl_get_channels_for_scan(priv
, vif
, band
,
1559 is_active
, n_probes
,
1560 (void *)&scan
->data
[le16_to_cpu(
1561 scan
->tx_cmd
.len
)]);
1563 if (scan
->channel_count
== 0) {
1564 IWL_DEBUG_SCAN(priv
, "channel count %d\n", scan
->channel_count
);
1568 cmd
.len
+= le16_to_cpu(scan
->tx_cmd
.len
) +
1569 scan
->channel_count
* sizeof(struct iwl_scan_channel
);
1571 scan
->len
= cpu_to_le16(cmd
.len
);
1573 /* set scan bit here for PAN params */
1574 set_bit(STATUS_SCAN_HW
, &priv
->status
);
1576 if (priv
->cfg
->ops
->hcmd
->set_pan_params
) {
1577 ret
= priv
->cfg
->ops
->hcmd
->set_pan_params(priv
);
1582 ret
= iwl_send_cmd_sync(priv
, &cmd
);
1584 clear_bit(STATUS_SCAN_HW
, &priv
->status
);
1585 if (priv
->cfg
->ops
->hcmd
->set_pan_params
)
1586 priv
->cfg
->ops
->hcmd
->set_pan_params(priv
);
1592 int iwlagn_manage_ibss_station(struct iwl_priv
*priv
,
1593 struct ieee80211_vif
*vif
, bool add
)
1595 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
1598 return iwlagn_add_bssid_station(priv
, vif_priv
->ctx
,
1599 vif
->bss_conf
.bssid
,
1600 &vif_priv
->ibss_bssid_sta_id
);
1601 return iwl_remove_station(priv
, vif_priv
->ibss_bssid_sta_id
,
1602 vif
->bss_conf
.bssid
);
1605 void iwl_free_tfds_in_queue(struct iwl_priv
*priv
,
1606 int sta_id
, int tid
, int freed
)
1608 lockdep_assert_held(&priv
->sta_lock
);
1610 if (priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
>= freed
)
1611 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1613 IWL_DEBUG_TX(priv
, "free more than tfds_in_queue (%u:%d)\n",
1614 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
,
1616 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
= 0;
1620 #define IWL_FLUSH_WAIT_MS 2000
1622 int iwlagn_wait_tx_queue_empty(struct iwl_priv
*priv
)
1624 struct iwl_tx_queue
*txq
;
1625 struct iwl_queue
*q
;
1627 unsigned long now
= jiffies
;
1630 /* waiting for all the tx frames complete might take a while */
1631 for (cnt
= 0; cnt
< priv
->hw_params
.max_txq_num
; cnt
++) {
1632 if (cnt
== priv
->cmd_queue
)
1634 txq
= &priv
->txq
[cnt
];
1636 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1637 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1640 if (q
->read_ptr
!= q
->write_ptr
) {
1641 IWL_ERR(priv
, "fail to flush all tx fifo queues\n");
1649 #define IWL_TX_QUEUE_MSK 0xfffff
1652 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1655 * 1. acquire mutex before calling
1656 * 2. make sure rf is on and not in exit state
1658 int iwlagn_txfifo_flush(struct iwl_priv
*priv
, u16 flush_control
)
1660 struct iwl_txfifo_flush_cmd flush_cmd
;
1661 struct iwl_host_cmd cmd
= {
1662 .id
= REPLY_TXFIFO_FLUSH
,
1663 .len
= sizeof(struct iwl_txfifo_flush_cmd
),
1670 memset(&flush_cmd
, 0, sizeof(flush_cmd
));
1671 flush_cmd
.fifo_control
= IWL_TX_FIFO_VO_MSK
| IWL_TX_FIFO_VI_MSK
|
1672 IWL_TX_FIFO_BE_MSK
| IWL_TX_FIFO_BK_MSK
;
1673 if (priv
->cfg
->sku
& IWL_SKU_N
)
1674 flush_cmd
.fifo_control
|= IWL_AGG_TX_QUEUE_MSK
;
1676 IWL_DEBUG_INFO(priv
, "fifo queue control: 0X%x\n",
1677 flush_cmd
.fifo_control
);
1678 flush_cmd
.flush_control
= cpu_to_le16(flush_control
);
1680 return iwl_send_cmd(priv
, &cmd
);
1683 void iwlagn_dev_txfifo_flush(struct iwl_priv
*priv
, u16 flush_control
)
1685 mutex_lock(&priv
->mutex
);
1686 ieee80211_stop_queues(priv
->hw
);
1687 if (priv
->cfg
->ops
->lib
->txfifo_flush(priv
, IWL_DROP_ALL
)) {
1688 IWL_ERR(priv
, "flush request fail\n");
1691 IWL_DEBUG_INFO(priv
, "wait transmit/flush all frames\n");
1692 iwlagn_wait_tx_queue_empty(priv
);
1694 ieee80211_wake_queues(priv
->hw
);
1695 mutex_unlock(&priv
->mutex
);
1702 * Macros to access the lookup table.
1704 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1705 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1707 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1709 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1710 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1711 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1713 * These macros encode that format.
1715 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1716 wifi_txrx, wifi_sh_ant_req) \
1717 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1718 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1720 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1721 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1722 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1723 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1724 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1725 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1727 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1728 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1729 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1730 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1732 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1733 wifi_req, wifi_prio, wifi_txrx, \
1735 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1736 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1739 #define LUT_WLAN_KILL_OP(lut, op, val) \
1740 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1741 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1742 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1743 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1744 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1745 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1746 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1747 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1748 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1749 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1750 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1751 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1752 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1754 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1755 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1756 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1757 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1758 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1759 wifi_req, wifi_prio, wifi_txrx, \
1761 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1762 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1763 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1764 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1765 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1766 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1767 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1768 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1770 static const __le32 iwlagn_def_3w_lookup
[12] = {
1771 cpu_to_le32(0xaaaaaaaa),
1772 cpu_to_le32(0xaaaaaaaa),
1773 cpu_to_le32(0xaeaaaaaa),
1774 cpu_to_le32(0xaaaaaaaa),
1775 cpu_to_le32(0xcc00ff28),
1776 cpu_to_le32(0x0000aaaa),
1777 cpu_to_le32(0xcc00aaaa),
1778 cpu_to_le32(0x0000aaaa),
1779 cpu_to_le32(0xc0004000),
1780 cpu_to_le32(0x00004000),
1781 cpu_to_le32(0xf0005000),
1782 cpu_to_le32(0xf0004000),
1785 static const __le32 iwlagn_concurrent_lookup
[12] = {
1786 cpu_to_le32(0xaaaaaaaa),
1787 cpu_to_le32(0xaaaaaaaa),
1788 cpu_to_le32(0xaaaaaaaa),
1789 cpu_to_le32(0xaaaaaaaa),
1790 cpu_to_le32(0xaaaaaaaa),
1791 cpu_to_le32(0xaaaaaaaa),
1792 cpu_to_le32(0xaaaaaaaa),
1793 cpu_to_le32(0xaaaaaaaa),
1794 cpu_to_le32(0x00000000),
1795 cpu_to_le32(0x00000000),
1796 cpu_to_le32(0x00000000),
1797 cpu_to_le32(0x00000000),
1800 void iwlagn_send_advance_bt_config(struct iwl_priv
*priv
)
1802 struct iwlagn_bt_cmd bt_cmd
= {
1803 .max_kill
= IWLAGN_BT_MAX_KILL_DEFAULT
,
1804 .bt3_timer_t7_value
= IWLAGN_BT3_T7_DEFAULT
,
1805 .bt3_prio_sample_time
= IWLAGN_BT3_PRIO_SAMPLE_DEFAULT
,
1806 .bt3_timer_t2_value
= IWLAGN_BT3_T2_DEFAULT
,
1809 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup
) !=
1810 sizeof(bt_cmd
.bt3_lookup_table
));
1812 if (priv
->cfg
->bt_params
)
1813 bt_cmd
.prio_boost
= priv
->cfg
->bt_params
->bt_prio_boost
;
1815 bt_cmd
.prio_boost
= 0;
1816 bt_cmd
.kill_ack_mask
= priv
->kill_ack_mask
;
1817 bt_cmd
.kill_cts_mask
= priv
->kill_cts_mask
;
1818 bt_cmd
.valid
= priv
->bt_valid
;
1819 bt_cmd
.tx_prio_boost
= 0;
1820 bt_cmd
.rx_prio_boost
= 0;
1823 * Configure BT coex mode to "no coexistence" when the
1824 * user disabled BT coexistence, we have no interface
1825 * (might be in monitor mode), or the interface is in
1826 * IBSS mode (no proper uCode support for coex then).
1828 if (!bt_coex_active
|| priv
->iw_mode
== NL80211_IFTYPE_ADHOC
) {
1831 bt_cmd
.flags
= IWLAGN_BT_FLAG_COEX_MODE_3W
<<
1832 IWLAGN_BT_FLAG_COEX_MODE_SHIFT
;
1833 if (priv
->bt_ch_announce
)
1834 bt_cmd
.flags
|= IWLAGN_BT_FLAG_CHANNEL_INHIBITION
;
1835 IWL_DEBUG_INFO(priv
, "BT coex flag: 0X%x\n", bt_cmd
.flags
);
1837 if (priv
->bt_full_concurrent
)
1838 memcpy(bt_cmd
.bt3_lookup_table
, iwlagn_concurrent_lookup
,
1839 sizeof(iwlagn_concurrent_lookup
));
1841 memcpy(bt_cmd
.bt3_lookup_table
, iwlagn_def_3w_lookup
,
1842 sizeof(iwlagn_def_3w_lookup
));
1844 IWL_DEBUG_INFO(priv
, "BT coex %s in %s mode\n",
1845 bt_cmd
.flags
? "active" : "disabled",
1846 priv
->bt_full_concurrent
?
1847 "full concurrency" : "3-wire");
1849 if (iwl_send_cmd_pdu(priv
, REPLY_BT_CONFIG
, sizeof(bt_cmd
), &bt_cmd
))
1850 IWL_ERR(priv
, "failed to send BT Coex Config\n");
1853 * When we are doing a restart, need to also reconfigure BT
1854 * SCO to the device. If not doing a restart, bt_sco_active
1855 * will always be false, so there's no need to have an extra
1856 * variable to check for it.
1858 if (priv
->bt_sco_active
) {
1859 struct iwlagn_bt_sco_cmd sco_cmd
= { .flags
= 0 };
1861 if (priv
->bt_sco_active
)
1862 sco_cmd
.flags
|= IWLAGN_BT_SCO_ACTIVE
;
1863 if (iwl_send_cmd_pdu(priv
, REPLY_BT_COEX_SCO
,
1864 sizeof(sco_cmd
), &sco_cmd
))
1865 IWL_ERR(priv
, "failed to send BT SCO command\n");
1869 static void iwlagn_bt_traffic_change_work(struct work_struct
*work
)
1871 struct iwl_priv
*priv
=
1872 container_of(work
, struct iwl_priv
, bt_traffic_change_work
);
1873 struct iwl_rxon_context
*ctx
;
1874 int smps_request
= -1;
1877 * Note: bt_traffic_load can be overridden by scan complete and
1878 * coex profile notifications. Ignore that since only bad consequence
1879 * can be not matching debug print with actual state.
1881 IWL_DEBUG_INFO(priv
, "BT traffic load changes: %d\n",
1882 priv
->bt_traffic_load
);
1884 switch (priv
->bt_traffic_load
) {
1885 case IWL_BT_COEX_TRAFFIC_LOAD_NONE
:
1886 if (priv
->bt_status
)
1887 smps_request
= IEEE80211_SMPS_DYNAMIC
;
1889 smps_request
= IEEE80211_SMPS_AUTOMATIC
;
1891 case IWL_BT_COEX_TRAFFIC_LOAD_LOW
:
1892 smps_request
= IEEE80211_SMPS_DYNAMIC
;
1894 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH
:
1895 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS
:
1896 smps_request
= IEEE80211_SMPS_STATIC
;
1899 IWL_ERR(priv
, "Invalid BT traffic load: %d\n",
1900 priv
->bt_traffic_load
);
1904 mutex_lock(&priv
->mutex
);
1907 * We can not send command to firmware while scanning. When the scan
1908 * complete we will schedule this work again. We do check with mutex
1909 * locked to prevent new scan request to arrive. We do not check
1910 * STATUS_SCANNING to avoid race when queue_work two times from
1911 * different notifications, but quit and not perform any work at all.
1913 if (test_bit(STATUS_SCAN_HW
, &priv
->status
))
1916 if (priv
->cfg
->ops
->lib
->update_chain_flags
)
1917 priv
->cfg
->ops
->lib
->update_chain_flags(priv
);
1919 if (smps_request
!= -1) {
1920 for_each_context(priv
, ctx
) {
1921 if (ctx
->vif
&& ctx
->vif
->type
== NL80211_IFTYPE_STATION
)
1922 ieee80211_request_smps(ctx
->vif
, smps_request
);
1926 mutex_unlock(&priv
->mutex
);
1929 static void iwlagn_print_uartmsg(struct iwl_priv
*priv
,
1930 struct iwl_bt_uart_msg
*uart_msg
)
1932 IWL_DEBUG_NOTIF(priv
, "Message Type = 0x%X, SSN = 0x%X, "
1933 "Update Req = 0x%X",
1934 (BT_UART_MSG_FRAME1MSGTYPE_MSK
& uart_msg
->frame1
) >>
1935 BT_UART_MSG_FRAME1MSGTYPE_POS
,
1936 (BT_UART_MSG_FRAME1SSN_MSK
& uart_msg
->frame1
) >>
1937 BT_UART_MSG_FRAME1SSN_POS
,
1938 (BT_UART_MSG_FRAME1UPDATEREQ_MSK
& uart_msg
->frame1
) >>
1939 BT_UART_MSG_FRAME1UPDATEREQ_POS
);
1941 IWL_DEBUG_NOTIF(priv
, "Open connections = 0x%X, Traffic load = 0x%X, "
1942 "Chl_SeqN = 0x%X, In band = 0x%X",
1943 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK
& uart_msg
->frame2
) >>
1944 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS
,
1945 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK
& uart_msg
->frame2
) >>
1946 BT_UART_MSG_FRAME2TRAFFICLOAD_POS
,
1947 (BT_UART_MSG_FRAME2CHLSEQN_MSK
& uart_msg
->frame2
) >>
1948 BT_UART_MSG_FRAME2CHLSEQN_POS
,
1949 (BT_UART_MSG_FRAME2INBAND_MSK
& uart_msg
->frame2
) >>
1950 BT_UART_MSG_FRAME2INBAND_POS
);
1952 IWL_DEBUG_NOTIF(priv
, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1953 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1954 (BT_UART_MSG_FRAME3SCOESCO_MSK
& uart_msg
->frame3
) >>
1955 BT_UART_MSG_FRAME3SCOESCO_POS
,
1956 (BT_UART_MSG_FRAME3SNIFF_MSK
& uart_msg
->frame3
) >>
1957 BT_UART_MSG_FRAME3SNIFF_POS
,
1958 (BT_UART_MSG_FRAME3A2DP_MSK
& uart_msg
->frame3
) >>
1959 BT_UART_MSG_FRAME3A2DP_POS
,
1960 (BT_UART_MSG_FRAME3ACL_MSK
& uart_msg
->frame3
) >>
1961 BT_UART_MSG_FRAME3ACL_POS
,
1962 (BT_UART_MSG_FRAME3MASTER_MSK
& uart_msg
->frame3
) >>
1963 BT_UART_MSG_FRAME3MASTER_POS
,
1964 (BT_UART_MSG_FRAME3OBEX_MSK
& uart_msg
->frame3
) >>
1965 BT_UART_MSG_FRAME3OBEX_POS
);
1967 IWL_DEBUG_NOTIF(priv
, "Idle duration = 0x%X",
1968 (BT_UART_MSG_FRAME4IDLEDURATION_MSK
& uart_msg
->frame4
) >>
1969 BT_UART_MSG_FRAME4IDLEDURATION_POS
);
1971 IWL_DEBUG_NOTIF(priv
, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1972 "eSCO Retransmissions = 0x%X",
1973 (BT_UART_MSG_FRAME5TXACTIVITY_MSK
& uart_msg
->frame5
) >>
1974 BT_UART_MSG_FRAME5TXACTIVITY_POS
,
1975 (BT_UART_MSG_FRAME5RXACTIVITY_MSK
& uart_msg
->frame5
) >>
1976 BT_UART_MSG_FRAME5RXACTIVITY_POS
,
1977 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK
& uart_msg
->frame5
) >>
1978 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS
);
1980 IWL_DEBUG_NOTIF(priv
, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1981 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK
& uart_msg
->frame6
) >>
1982 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS
,
1983 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK
& uart_msg
->frame6
) >>
1984 BT_UART_MSG_FRAME6DISCOVERABLE_POS
);
1986 IWL_DEBUG_NOTIF(priv
, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1987 "0x%X, Connectable = 0x%X",
1988 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK
& uart_msg
->frame7
) >>
1989 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS
,
1990 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK
& uart_msg
->frame7
) >>
1991 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS
,
1992 (BT_UART_MSG_FRAME7CONNECTABLE_MSK
& uart_msg
->frame7
) >>
1993 BT_UART_MSG_FRAME7CONNECTABLE_POS
);
1996 static void iwlagn_set_kill_ack_msk(struct iwl_priv
*priv
,
1997 struct iwl_bt_uart_msg
*uart_msg
)
2000 __le32 bt_kill_ack_msg
[2] = {
2001 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
2003 kill_ack_msk
= (((BT_UART_MSG_FRAME3A2DP_MSK
|
2004 BT_UART_MSG_FRAME3SNIFF_MSK
|
2005 BT_UART_MSG_FRAME3SCOESCO_MSK
) &
2006 uart_msg
->frame3
) == 0) ? 1 : 0;
2007 if (priv
->kill_ack_mask
!= bt_kill_ack_msg
[kill_ack_msk
]) {
2008 priv
->bt_valid
|= IWLAGN_BT_VALID_KILL_ACK_MASK
;
2009 priv
->kill_ack_mask
= bt_kill_ack_msg
[kill_ack_msk
];
2010 /* schedule to send runtime bt_config */
2011 queue_work(priv
->workqueue
, &priv
->bt_runtime_config
);
2016 void iwlagn_bt_coex_profile_notif(struct iwl_priv
*priv
,
2017 struct iwl_rx_mem_buffer
*rxb
)
2019 unsigned long flags
;
2020 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
2021 struct iwl_bt_coex_profile_notif
*coex
= &pkt
->u
.bt_coex_profile_notif
;
2022 struct iwlagn_bt_sco_cmd sco_cmd
= { .flags
= 0 };
2023 struct iwl_bt_uart_msg
*uart_msg
= &coex
->last_bt_uart_msg
;
2025 IWL_DEBUG_NOTIF(priv
, "BT Coex notification:\n");
2026 IWL_DEBUG_NOTIF(priv
, " status: %d\n", coex
->bt_status
);
2027 IWL_DEBUG_NOTIF(priv
, " traffic load: %d\n", coex
->bt_traffic_load
);
2028 IWL_DEBUG_NOTIF(priv
, " CI compliance: %d\n",
2029 coex
->bt_ci_compliance
);
2030 iwlagn_print_uartmsg(priv
, uart_msg
);
2032 priv
->last_bt_traffic_load
= priv
->bt_traffic_load
;
2033 if (priv
->iw_mode
!= NL80211_IFTYPE_ADHOC
) {
2034 if (priv
->bt_status
!= coex
->bt_status
||
2035 priv
->last_bt_traffic_load
!= coex
->bt_traffic_load
) {
2036 if (coex
->bt_status
) {
2038 if (!priv
->bt_ch_announce
)
2039 priv
->bt_traffic_load
=
2040 IWL_BT_COEX_TRAFFIC_LOAD_HIGH
;
2042 priv
->bt_traffic_load
=
2043 coex
->bt_traffic_load
;
2046 priv
->bt_traffic_load
=
2047 IWL_BT_COEX_TRAFFIC_LOAD_NONE
;
2049 priv
->bt_status
= coex
->bt_status
;
2050 queue_work(priv
->workqueue
,
2051 &priv
->bt_traffic_change_work
);
2053 if (priv
->bt_sco_active
!=
2054 (uart_msg
->frame3
& BT_UART_MSG_FRAME3SCOESCO_MSK
)) {
2055 priv
->bt_sco_active
= uart_msg
->frame3
&
2056 BT_UART_MSG_FRAME3SCOESCO_MSK
;
2057 if (priv
->bt_sco_active
)
2058 sco_cmd
.flags
|= IWLAGN_BT_SCO_ACTIVE
;
2059 iwl_send_cmd_pdu_async(priv
, REPLY_BT_COEX_SCO
,
2060 sizeof(sco_cmd
), &sco_cmd
, NULL
);
2064 iwlagn_set_kill_ack_msk(priv
, uart_msg
);
2066 /* FIXME: based on notification, adjust the prio_boost */
2068 spin_lock_irqsave(&priv
->lock
, flags
);
2069 priv
->bt_ci_compliance
= coex
->bt_ci_compliance
;
2070 spin_unlock_irqrestore(&priv
->lock
, flags
);
2073 void iwlagn_bt_rx_handler_setup(struct iwl_priv
*priv
)
2075 iwlagn_rx_handler_setup(priv
);
2076 priv
->rx_handlers
[REPLY_BT_COEX_PROFILE_NOTIF
] =
2077 iwlagn_bt_coex_profile_notif
;
2080 void iwlagn_bt_setup_deferred_work(struct iwl_priv
*priv
)
2082 iwlagn_setup_deferred_work(priv
);
2084 INIT_WORK(&priv
->bt_traffic_change_work
,
2085 iwlagn_bt_traffic_change_work
);
2088 void iwlagn_bt_cancel_deferred_work(struct iwl_priv
*priv
)
2090 cancel_work_sync(&priv
->bt_traffic_change_work
);
2093 static bool is_single_rx_stream(struct iwl_priv
*priv
)
2095 return priv
->current_ht_config
.smps
== IEEE80211_SMPS_STATIC
||
2096 priv
->current_ht_config
.single_chain_sufficient
;
2099 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
2100 #define IWL_NUM_RX_CHAINS_SINGLE 2
2101 #define IWL_NUM_IDLE_CHAINS_DUAL 2
2102 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
2105 * Determine how many receiver/antenna chains to use.
2107 * More provides better reception via diversity. Fewer saves power
2108 * at the expense of throughput, but only when not in powersave to
2111 * MIMO (dual stream) requires at least 2, but works better with 3.
2112 * This does not determine *which* chains to use, just how many.
2114 static int iwl_get_active_rx_chain_count(struct iwl_priv
*priv
)
2116 if (priv
->cfg
->bt_params
&&
2117 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
2118 (priv
->bt_full_concurrent
||
2119 priv
->bt_traffic_load
>= IWL_BT_COEX_TRAFFIC_LOAD_HIGH
)) {
2121 * only use chain 'A' in bt high traffic load or
2122 * full concurrency mode
2124 return IWL_NUM_RX_CHAINS_SINGLE
;
2126 /* # of Rx chains to use when expecting MIMO. */
2127 if (is_single_rx_stream(priv
))
2128 return IWL_NUM_RX_CHAINS_SINGLE
;
2130 return IWL_NUM_RX_CHAINS_MULTIPLE
;
2134 * When we are in power saving mode, unless device support spatial
2135 * multiplexing power save, use the active count for rx chain count.
2137 static int iwl_get_idle_rx_chain_count(struct iwl_priv
*priv
, int active_cnt
)
2139 /* # Rx chains when idling, depending on SMPS mode */
2140 switch (priv
->current_ht_config
.smps
) {
2141 case IEEE80211_SMPS_STATIC
:
2142 case IEEE80211_SMPS_DYNAMIC
:
2143 return IWL_NUM_IDLE_CHAINS_SINGLE
;
2144 case IEEE80211_SMPS_OFF
:
2147 WARN(1, "invalid SMPS mode %d",
2148 priv
->current_ht_config
.smps
);
2153 /* up to 4 chains */
2154 static u8
iwl_count_chain_bitmap(u32 chain_bitmap
)
2157 res
= (chain_bitmap
& BIT(0)) >> 0;
2158 res
+= (chain_bitmap
& BIT(1)) >> 1;
2159 res
+= (chain_bitmap
& BIT(2)) >> 2;
2160 res
+= (chain_bitmap
& BIT(3)) >> 3;
2165 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2167 * Selects how many and which Rx receivers/antennas/chains to use.
2168 * This should not be used for scan command ... it puts data in wrong place.
2170 void iwlagn_set_rxon_chain(struct iwl_priv
*priv
, struct iwl_rxon_context
*ctx
)
2172 bool is_single
= is_single_rx_stream(priv
);
2173 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
2174 u8 idle_rx_cnt
, active_rx_cnt
, valid_rx_cnt
;
2178 /* Tell uCode which antennas are actually connected.
2179 * Before first association, we assume all antennas are connected.
2180 * Just after first association, iwl_chain_noise_calibration()
2181 * checks which antennas actually *are* connected. */
2182 if (priv
->chain_noise_data
.active_chains
)
2183 active_chains
= priv
->chain_noise_data
.active_chains
;
2185 active_chains
= priv
->hw_params
.valid_rx_ant
;
2187 if (priv
->cfg
->bt_params
&&
2188 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
2189 (priv
->bt_full_concurrent
||
2190 priv
->bt_traffic_load
>= IWL_BT_COEX_TRAFFIC_LOAD_HIGH
)) {
2192 * only use chain 'A' in bt high traffic load or
2193 * full concurrency mode
2195 active_chains
= first_antenna(active_chains
);
2198 rx_chain
= active_chains
<< RXON_RX_CHAIN_VALID_POS
;
2200 /* How many receivers should we use? */
2201 active_rx_cnt
= iwl_get_active_rx_chain_count(priv
);
2202 idle_rx_cnt
= iwl_get_idle_rx_chain_count(priv
, active_rx_cnt
);
2205 /* correct rx chain count according hw settings
2206 * and chain noise calibration
2208 valid_rx_cnt
= iwl_count_chain_bitmap(active_chains
);
2209 if (valid_rx_cnt
< active_rx_cnt
)
2210 active_rx_cnt
= valid_rx_cnt
;
2212 if (valid_rx_cnt
< idle_rx_cnt
)
2213 idle_rx_cnt
= valid_rx_cnt
;
2215 rx_chain
|= active_rx_cnt
<< RXON_RX_CHAIN_MIMO_CNT_POS
;
2216 rx_chain
|= idle_rx_cnt
<< RXON_RX_CHAIN_CNT_POS
;
2218 ctx
->staging
.rx_chain
= cpu_to_le16(rx_chain
);
2220 if (!is_single
&& (active_rx_cnt
>= IWL_NUM_RX_CHAINS_SINGLE
) && is_cam
)
2221 ctx
->staging
.rx_chain
|= RXON_RX_CHAIN_MIMO_FORCE_MSK
;
2223 ctx
->staging
.rx_chain
&= ~RXON_RX_CHAIN_MIMO_FORCE_MSK
;
2225 IWL_DEBUG_ASSOC(priv
, "rx_chain=0x%X active=%d idle=%d\n",
2226 ctx
->staging
.rx_chain
,
2227 active_rx_cnt
, idle_rx_cnt
);
2229 WARN_ON(active_rx_cnt
== 0 || idle_rx_cnt
== 0 ||
2230 active_rx_cnt
< idle_rx_cnt
);
2233 u8
iwl_toggle_tx_ant(struct iwl_priv
*priv
, u8 ant
, u8 valid
)
2238 if (priv
->band
== IEEE80211_BAND_2GHZ
&&
2239 priv
->bt_traffic_load
>= IWL_BT_COEX_TRAFFIC_LOAD_HIGH
)
2242 for (i
= 0; i
< RATE_ANT_NUM
- 1; i
++) {
2243 ind
= (ind
+ 1) < RATE_ANT_NUM
? ind
+ 1 : 0;
2244 if (valid
& BIT(ind
))
2250 static const char *get_csr_string(int cmd
)
2253 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
2254 IWL_CMD(CSR_INT_COALESCING
);
2256 IWL_CMD(CSR_INT_MASK
);
2257 IWL_CMD(CSR_FH_INT_STATUS
);
2258 IWL_CMD(CSR_GPIO_IN
);
2260 IWL_CMD(CSR_GP_CNTRL
);
2261 IWL_CMD(CSR_HW_REV
);
2262 IWL_CMD(CSR_EEPROM_REG
);
2263 IWL_CMD(CSR_EEPROM_GP
);
2264 IWL_CMD(CSR_OTP_GP_REG
);
2265 IWL_CMD(CSR_GIO_REG
);
2266 IWL_CMD(CSR_GP_UCODE_REG
);
2267 IWL_CMD(CSR_GP_DRIVER_REG
);
2268 IWL_CMD(CSR_UCODE_DRV_GP1
);
2269 IWL_CMD(CSR_UCODE_DRV_GP2
);
2270 IWL_CMD(CSR_LED_REG
);
2271 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
2272 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
2273 IWL_CMD(CSR_ANA_PLL_CFG
);
2274 IWL_CMD(CSR_HW_REV_WA_REG
);
2275 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
2281 void iwl_dump_csr(struct iwl_priv
*priv
)
2285 CSR_HW_IF_CONFIG_REG
,
2303 CSR_DRAM_INT_TBL_REG
,
2304 CSR_GIO_CHICKEN_BITS
,
2307 CSR_DBG_HPET_MEM_REG
2309 IWL_ERR(priv
, "CSR values:\n");
2310 IWL_ERR(priv
, "(2nd byte of CSR_INT_COALESCING is "
2311 "CSR_INT_PERIODIC_REG)\n");
2312 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
2313 IWL_ERR(priv
, " %25s: 0X%08x\n",
2314 get_csr_string(csr_tbl
[i
]),
2315 iwl_read32(priv
, csr_tbl
[i
]));
2319 static const char *get_fh_string(int cmd
)
2322 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
2323 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
2324 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
2325 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
2326 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
2327 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
2328 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
2329 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
2330 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
2336 int iwl_dump_fh(struct iwl_priv
*priv
, char **buf
, bool display
)
2339 #ifdef CONFIG_IWLWIFI_DEBUG
2344 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
2345 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
2346 FH_RSCSR_CHNL0_WPTR
,
2347 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
2348 FH_MEM_RSSR_SHARED_CTRL_REG
,
2349 FH_MEM_RSSR_RX_STATUS_REG
,
2350 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
2351 FH_TSSR_TX_STATUS_REG
,
2352 FH_TSSR_TX_ERROR_REG
2354 #ifdef CONFIG_IWLWIFI_DEBUG
2356 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
2357 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
2360 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2361 "FH register values:\n");
2362 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
2363 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2365 get_fh_string(fh_tbl
[i
]),
2366 iwl_read_direct32(priv
, fh_tbl
[i
]));
2371 IWL_ERR(priv
, "FH register values:\n");
2372 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
2373 IWL_ERR(priv
, " %34s: 0X%08x\n",
2374 get_fh_string(fh_tbl
[i
]),
2375 iwl_read_direct32(priv
, fh_tbl
[i
]));