1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
43 static inline u32
iwlagn_get_scd_ssn(struct iwl5000_tx_resp
*tx_resp
)
45 return le32_to_cpup((__le32
*)&tx_resp
->status
+
46 tx_resp
->frame_count
) & MAX_SN
;
49 static void iwlagn_count_tx_err_status(struct iwl_priv
*priv
, u16 status
)
51 status
&= TX_STATUS_MSK
;
54 case TX_STATUS_POSTPONE_DELAY
:
55 priv
->_agn
.reply_tx_stats
.pp_delay
++;
57 case TX_STATUS_POSTPONE_FEW_BYTES
:
58 priv
->_agn
.reply_tx_stats
.pp_few_bytes
++;
60 case TX_STATUS_POSTPONE_BT_PRIO
:
61 priv
->_agn
.reply_tx_stats
.pp_bt_prio
++;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD
:
64 priv
->_agn
.reply_tx_stats
.pp_quiet_period
++;
66 case TX_STATUS_POSTPONE_CALC_TTAK
:
67 priv
->_agn
.reply_tx_stats
.pp_calc_ttak
++;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY
:
70 priv
->_agn
.reply_tx_stats
.int_crossed_retry
++;
72 case TX_STATUS_FAIL_SHORT_LIMIT
:
73 priv
->_agn
.reply_tx_stats
.short_limit
++;
75 case TX_STATUS_FAIL_LONG_LIMIT
:
76 priv
->_agn
.reply_tx_stats
.long_limit
++;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN
:
79 priv
->_agn
.reply_tx_stats
.fifo_underrun
++;
81 case TX_STATUS_FAIL_DRAIN_FLOW
:
82 priv
->_agn
.reply_tx_stats
.drain_flow
++;
84 case TX_STATUS_FAIL_RFKILL_FLUSH
:
85 priv
->_agn
.reply_tx_stats
.rfkill_flush
++;
87 case TX_STATUS_FAIL_LIFE_EXPIRE
:
88 priv
->_agn
.reply_tx_stats
.life_expire
++;
90 case TX_STATUS_FAIL_DEST_PS
:
91 priv
->_agn
.reply_tx_stats
.dest_ps
++;
93 case TX_STATUS_FAIL_HOST_ABORTED
:
94 priv
->_agn
.reply_tx_stats
.host_abort
++;
96 case TX_STATUS_FAIL_BT_RETRY
:
97 priv
->_agn
.reply_tx_stats
.bt_retry
++;
99 case TX_STATUS_FAIL_STA_INVALID
:
100 priv
->_agn
.reply_tx_stats
.sta_invalid
++;
102 case TX_STATUS_FAIL_FRAG_DROPPED
:
103 priv
->_agn
.reply_tx_stats
.frag_drop
++;
105 case TX_STATUS_FAIL_TID_DISABLE
:
106 priv
->_agn
.reply_tx_stats
.tid_disable
++;
108 case TX_STATUS_FAIL_FIFO_FLUSHED
:
109 priv
->_agn
.reply_tx_stats
.fifo_flush
++;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL
:
112 priv
->_agn
.reply_tx_stats
.insuff_cf_poll
++;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX
:
115 priv
->_agn
.reply_tx_stats
.fail_hw_drop
++;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR
:
118 priv
->_agn
.reply_tx_stats
.sta_color_mismatch
++;
121 priv
->_agn
.reply_tx_stats
.unknown
++;
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv
*priv
, u16 status
)
128 status
&= AGG_TX_STATUS_MSK
;
131 case AGG_TX_STATE_UNDERRUN_MSK
:
132 priv
->_agn
.reply_agg_tx_stats
.underrun
++;
134 case AGG_TX_STATE_BT_PRIO_MSK
:
135 priv
->_agn
.reply_agg_tx_stats
.bt_prio
++;
137 case AGG_TX_STATE_FEW_BYTES_MSK
:
138 priv
->_agn
.reply_agg_tx_stats
.few_bytes
++;
140 case AGG_TX_STATE_ABORT_MSK
:
141 priv
->_agn
.reply_agg_tx_stats
.abort
++;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK
:
144 priv
->_agn
.reply_agg_tx_stats
.last_sent_ttl
++;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK
:
147 priv
->_agn
.reply_agg_tx_stats
.last_sent_try
++;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK
:
150 priv
->_agn
.reply_agg_tx_stats
.last_sent_bt_kill
++;
152 case AGG_TX_STATE_SCD_QUERY_MSK
:
153 priv
->_agn
.reply_agg_tx_stats
.scd_query
++;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK
:
156 priv
->_agn
.reply_agg_tx_stats
.bad_crc32
++;
158 case AGG_TX_STATE_RESPONSE_MSK
:
159 priv
->_agn
.reply_agg_tx_stats
.response
++;
161 case AGG_TX_STATE_DUMP_TX_MSK
:
162 priv
->_agn
.reply_agg_tx_stats
.dump_tx
++;
164 case AGG_TX_STATE_DELAY_TX_MSK
:
165 priv
->_agn
.reply_agg_tx_stats
.delay_tx
++;
168 priv
->_agn
.reply_agg_tx_stats
.unknown
++;
173 static void iwlagn_set_tx_status(struct iwl_priv
*priv
,
174 struct ieee80211_tx_info
*info
,
175 struct iwl5000_tx_resp
*tx_resp
,
176 int txq_id
, bool is_agg
)
178 u16 status
= le16_to_cpu(tx_resp
->status
.status
);
180 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
182 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
183 info
->flags
|= iwl_tx_status_to_mac80211(status
);
184 iwlagn_hwrate_to_tx_control(priv
, le32_to_cpu(tx_resp
->rate_n_flags
),
186 if (!iwl_is_tx_success(status
))
187 iwlagn_count_tx_err_status(priv
, status
);
189 IWL_DEBUG_TX_REPLY(priv
, "TXQ %d status %s (0x%08x) rate_n_flags "
192 iwl_get_tx_fail_reason(status
), status
,
193 le32_to_cpu(tx_resp
->rate_n_flags
),
194 tx_resp
->failure_frame
);
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
200 const char *iwl_get_agg_tx_fail_reason(u16 status
)
202 status
&= AGG_TX_STATUS_MSK
;
204 case AGG_TX_STATE_TRANSMITTED
:
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK
);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK
);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK
);
209 AGG_TX_STATE_FAIL(ABORT_MSK
);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK
);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK
);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK
);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK
);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK
);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK
);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK
);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK
);
222 #endif /* CONFIG_IWLWIFI_DEBUG */
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv
*priv
,
225 struct iwl_ht_agg
*agg
,
226 struct iwl5000_tx_resp
*tx_resp
,
227 int txq_id
, u16 start_idx
)
230 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
231 struct ieee80211_hdr
*hdr
= NULL
;
235 if (agg
->wait_for_ba
)
236 IWL_DEBUG_TX_REPLY(priv
, "got tx response w/o block-ack\n");
238 agg
->frame_count
= tx_resp
->frame_count
;
239 agg
->start_idx
= start_idx
;
240 agg
->rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
243 /* # frames attempted by Tx command */
244 if (agg
->frame_count
== 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
248 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg
->frame_count
, agg
->start_idx
, idx
);
250 iwlagn_set_tx_status(priv
,
252 priv
->txq
[txq_id
].txb
[idx
].skb
),
253 tx_resp
, txq_id
, true);
254 agg
->wait_for_ba
= 0;
256 /* Two or more frames were attempted; expect block-ack */
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
264 int start
= agg
->start_idx
;
266 /* Construct bit-map of pending frames within Tx window */
267 for (i
= 0; i
< agg
->frame_count
; i
++) {
269 status
= le16_to_cpu(frame_status
[i
].status
);
270 seq
= le16_to_cpu(frame_status
[i
].sequence
);
271 idx
= SEQ_TO_INDEX(seq
);
272 txq_id
= SEQ_TO_QUEUE(seq
);
274 if (status
& AGG_TX_STATUS_MSK
)
275 iwlagn_count_agg_tx_err_status(priv
, status
);
277 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
278 AGG_TX_STATE_ABORT_MSK
))
281 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg
->frame_count
, txq_id
, idx
);
283 IWL_DEBUG_TX_REPLY(priv
, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status
),
286 status
& AGG_TX_STATUS_MSK
,
287 status
& AGG_TX_TRY_MSK
);
289 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx
, txq_id
);
297 sc
= le16_to_cpu(hdr
->seq_ctrl
);
298 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
307 IWL_DEBUG_TX_REPLY(priv
, "AGG Frame i=%d idx %d seq=%d\n",
308 i
, idx
, SEQ_TO_SN(sc
));
311 * sh -> how many frames ahead of the starting frame is
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
328 /* Shift bitmap by start - idx, wrapped */
329 sh
= 0x100 - idx
+ start
;
330 bitmap
= bitmap
<< sh
;
331 /* Now idx is the new start so sh = 0 */
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
338 } else if (sh
<= -64) {
339 sh
= 0x100 - start
+ idx
;
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
345 /* Shift by how far start is ahead of idx */
347 bitmap
= bitmap
<< sh
;
348 /* Now idx is the new start so sh = 0 */
352 /* Sequence number start + sh was sent in this batch */
353 bitmap
|= 1ULL << sh
;
354 IWL_DEBUG_TX_REPLY(priv
, "start=%d bitmap=0x%llx\n",
355 start
, (unsigned long long)bitmap
);
359 * Store the bitmap and possibly the new start, if we wrapped
362 agg
->bitmap
= bitmap
;
363 agg
->start_idx
= start
;
364 IWL_DEBUG_TX_REPLY(priv
, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg
->frame_count
, agg
->start_idx
,
366 (unsigned long long)agg
->bitmap
);
369 agg
->wait_for_ba
= 1;
374 void iwl_check_abort_status(struct iwl_priv
*priv
,
375 u8 frame_count
, u32 status
)
377 if (frame_count
== 1 && status
== TX_STATUS_FAIL_RFKILL_FLUSH
) {
378 IWL_ERR(priv
, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
380 queue_work(priv
->workqueue
, &priv
->tx_flush
);
384 static void iwlagn_rx_reply_tx(struct iwl_priv
*priv
,
385 struct iwl_rx_mem_buffer
*rxb
)
387 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
388 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
389 int txq_id
= SEQ_TO_QUEUE(sequence
);
390 int index
= SEQ_TO_INDEX(sequence
);
391 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
392 struct ieee80211_tx_info
*info
;
393 struct iwl5000_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
394 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
400 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
401 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id
,
403 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
408 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
);
409 memset(&info
->status
, 0, sizeof(info
->status
));
411 tid
= (tx_resp
->ra_tid
& IWL50_TX_RES_TID_MSK
) >> IWL50_TX_RES_TID_POS
;
412 sta_id
= (tx_resp
->ra_tid
& IWL50_TX_RES_RA_MSK
) >> IWL50_TX_RES_RA_POS
;
414 spin_lock_irqsave(&priv
->sta_lock
, flags
);
415 if (txq
->sched_retry
) {
416 const u32 scd_ssn
= iwlagn_get_scd_ssn(tx_resp
);
417 struct iwl_ht_agg
*agg
;
419 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
421 * If the BT kill count is non-zero, we'll get this
422 * notification again.
424 if (tx_resp
->bt_kill_count
&& tx_resp
->frame_count
== 1 &&
425 priv
->cfg
->advanced_bt_coexist
) {
426 IWL_WARN(priv
, "receive reply tx with bt_kill\n");
428 iwlagn_tx_status_reply_tx(priv
, agg
, tx_resp
, txq_id
, index
);
430 /* check if BAR is needed */
431 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
))
432 info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
434 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
435 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
436 IWL_DEBUG_TX_REPLY(priv
, "Retry scheduler reclaim "
437 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
438 scd_ssn
, index
, txq_id
, txq
->swq_id
);
440 freed
= iwlagn_tx_queue_reclaim(priv
, txq_id
, index
);
441 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
443 if (priv
->mac80211_registered
&&
444 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
445 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
)) {
446 if (agg
->state
== IWL_AGG_OFF
)
447 iwl_wake_queue(priv
, txq_id
);
449 iwl_wake_queue(priv
, txq
->swq_id
);
453 BUG_ON(txq_id
!= txq
->swq_id
);
454 iwlagn_set_tx_status(priv
, info
, tx_resp
, txq_id
, false);
455 freed
= iwlagn_tx_queue_reclaim(priv
, txq_id
, index
);
456 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
458 if (priv
->mac80211_registered
&&
459 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
))
460 iwl_wake_queue(priv
, txq_id
);
463 iwlagn_txq_check_empty(priv
, sta_id
, tid
, txq_id
);
465 iwl_check_abort_status(priv
, tx_resp
->frame_count
, status
);
466 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
469 void iwlagn_rx_handler_setup(struct iwl_priv
*priv
)
471 /* init calibration handlers */
472 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
473 iwlagn_rx_calib_result
;
474 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
475 iwlagn_rx_calib_complete
;
476 priv
->rx_handlers
[REPLY_TX
] = iwlagn_rx_reply_tx
;
479 void iwlagn_setup_deferred_work(struct iwl_priv
*priv
)
481 /* in agn, the tx power calibration is done in uCode */
482 priv
->disable_tx_power_cal
= 1;
485 int iwlagn_hw_valid_rtc_data_addr(u32 addr
)
487 return (addr
>= IWLAGN_RTC_DATA_LOWER_BOUND
) &&
488 (addr
< IWLAGN_RTC_DATA_UPPER_BOUND
);
491 int iwlagn_send_tx_power(struct iwl_priv
*priv
)
493 struct iwl5000_tx_power_dbm_cmd tx_power_cmd
;
496 /* half dBm need to multiply */
497 tx_power_cmd
.global_lmt
= (s8
)(2 * priv
->tx_power_user_lmt
);
499 if (priv
->tx_power_lmt_in_half_dbm
&&
500 priv
->tx_power_lmt_in_half_dbm
< tx_power_cmd
.global_lmt
) {
502 * For the newer devices which using enhanced/extend tx power
503 * table in EEPROM, the format is in half dBm. driver need to
504 * convert to dBm format before report to mac80211.
505 * By doing so, there is a possibility of 1/2 dBm resolution
506 * lost. driver will perform "round-up" operation before
507 * reporting, but it will cause 1/2 dBm tx power over the
508 * regulatory limit. Perform the checking here, if the
509 * "tx_power_user_lmt" is higher than EEPROM value (in
510 * half-dBm format), lower the tx power based on EEPROM
512 tx_power_cmd
.global_lmt
= priv
->tx_power_lmt_in_half_dbm
;
514 tx_power_cmd
.flags
= IWL50_TX_POWER_NO_CLOSED
;
515 tx_power_cmd
.srv_chan_lmt
= IWL50_TX_POWER_AUTO
;
517 if (IWL_UCODE_API(priv
->ucode_ver
) == 1)
518 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD_V1
;
520 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD
;
522 return iwl_send_cmd_pdu_async(priv
, tx_ant_cfg_cmd
,
523 sizeof(tx_power_cmd
), &tx_power_cmd
,
527 void iwlagn_temperature(struct iwl_priv
*priv
)
529 /* store temperature from statistics (in Celsius) */
531 le32_to_cpu(priv
->_agn
.statistics
.general
.common
.temperature
);
532 iwl_tt_handler(priv
);
535 u16
iwlagn_eeprom_calib_version(struct iwl_priv
*priv
)
537 struct iwl_eeprom_calib_hdr
{
543 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
552 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
556 if ((address
& INDIRECT_ADDRESS
) == 0)
559 switch (address
& INDIRECT_TYPE_MSK
) {
561 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_HOST
);
563 case INDIRECT_GENERAL
:
564 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_GENERAL
);
566 case INDIRECT_REGULATORY
:
567 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_REGULATORY
);
569 case INDIRECT_CALIBRATION
:
570 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_CALIBRATION
);
572 case INDIRECT_PROCESS_ADJST
:
573 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_PROCESS_ADJST
);
575 case INDIRECT_OTHERS
:
576 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_OTHERS
);
579 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
580 address
& INDIRECT_TYPE_MSK
);
584 /* translate the offset from words to byte */
585 return (address
& ADDRESS_MSK
) + (offset
<< 1);
588 const u8
*iwlagn_eeprom_query_addr(const struct iwl_priv
*priv
,
591 u32 address
= eeprom_indirect_address(priv
, offset
);
592 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
593 return &priv
->eeprom
[address
];
596 struct iwl_mod_params iwlagn_mod_params
= {
599 /* the rest are 0 by default */
602 void iwlagn_rx_queue_reset(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
606 spin_lock_irqsave(&rxq
->lock
, flags
);
607 INIT_LIST_HEAD(&rxq
->rx_free
);
608 INIT_LIST_HEAD(&rxq
->rx_used
);
609 /* Fill the rx_used queue with _all_ of the Rx buffers */
610 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
611 /* In the reset function, these buffers may have been allocated
612 * to an SKB, so we need to unmap and free potential storage */
613 if (rxq
->pool
[i
].page
!= NULL
) {
614 pci_unmap_page(priv
->pci_dev
, rxq
->pool
[i
].page_dma
,
615 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
617 __iwl_free_pages(priv
, rxq
->pool
[i
].page
);
618 rxq
->pool
[i
].page
= NULL
;
620 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
623 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
624 rxq
->queue
[i
] = NULL
;
626 /* Set us so that we have processed and used all buffers, but have
627 * not restocked the Rx queue with fresh buffers */
628 rxq
->read
= rxq
->write
= 0;
629 rxq
->write_actual
= 0;
631 spin_unlock_irqrestore(&rxq
->lock
, flags
);
634 int iwlagn_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
637 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
638 u32 rb_timeout
= 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
640 if (!priv
->cfg
->use_isr_legacy
)
641 rb_timeout
= RX_RB_TIMEOUT
;
643 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
644 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
646 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
649 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
651 /* Reset driver's Rx queue write index */
652 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
654 /* Tell device where to find RBD circular buffer in DRAM */
655 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
656 (u32
)(rxq
->bd_dma
>> 8));
658 /* Tell device where in DRAM to update its Rx status */
659 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
660 rxq
->rb_stts_dma
>> 4);
663 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
664 * the credit mechanism in 5000 HW RX FIFO
665 * Direct rx interrupts to hosts
666 * Rx buffer size 4 or 8k
670 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
671 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
672 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
673 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
674 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
676 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
677 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
679 /* Set interrupt coalescing timer to default (2048 usecs) */
680 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
685 int iwlagn_hw_nic_init(struct iwl_priv
*priv
)
688 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
692 spin_lock_irqsave(&priv
->lock
, flags
);
693 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
695 /* Set interrupt coalescing calibration timer to default (512 usecs) */
696 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
698 spin_unlock_irqrestore(&priv
->lock
, flags
);
700 ret
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
702 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
704 /* Allocate the RX queue, or reset if it is already allocated */
706 ret
= iwl_rx_queue_alloc(priv
);
708 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
712 iwlagn_rx_queue_reset(priv
, rxq
);
714 iwlagn_rx_replenish(priv
);
716 iwlagn_rx_init(priv
, rxq
);
718 spin_lock_irqsave(&priv
->lock
, flags
);
720 rxq
->need_update
= 1;
721 iwl_rx_queue_update_write_ptr(priv
, rxq
);
723 spin_unlock_irqrestore(&priv
->lock
, flags
);
725 /* Allocate or reset and init all Tx and Command queues */
727 ret
= iwlagn_txq_ctx_alloc(priv
);
731 iwlagn_txq_ctx_reset(priv
);
733 set_bit(STATUS_INIT
, &priv
->status
);
739 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
741 static inline __le32
iwlagn_dma_addr2rbd_ptr(struct iwl_priv
*priv
,
744 return cpu_to_le32((u32
)(dma_addr
>> 8));
748 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
750 * If there are slots in the RX queue that need to be restocked,
751 * and we have free pre-allocated buffers, fill the ranks as much
752 * as we can, pulling from rx_free.
754 * This moves the 'write' index forward to catch up with 'processed', and
755 * also updates the memory address in the firmware to reference the new
758 void iwlagn_rx_queue_restock(struct iwl_priv
*priv
)
760 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
761 struct list_head
*element
;
762 struct iwl_rx_mem_buffer
*rxb
;
765 spin_lock_irqsave(&rxq
->lock
, flags
);
766 while ((iwl_rx_queue_space(rxq
) > 0) && (rxq
->free_count
)) {
767 /* The overwritten rxb must be a used one */
768 rxb
= rxq
->queue
[rxq
->write
];
769 BUG_ON(rxb
&& rxb
->page
);
771 /* Get next free Rx buffer, remove from free list */
772 element
= rxq
->rx_free
.next
;
773 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
776 /* Point to Rx buffer via next RBD in circular buffer */
777 rxq
->bd
[rxq
->write
] = iwlagn_dma_addr2rbd_ptr(priv
,
779 rxq
->queue
[rxq
->write
] = rxb
;
780 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
783 spin_unlock_irqrestore(&rxq
->lock
, flags
);
784 /* If the pre-allocated buffer pool is dropping low, schedule to
786 if (rxq
->free_count
<= RX_LOW_WATERMARK
)
787 queue_work(priv
->workqueue
, &priv
->rx_replenish
);
790 /* If we've added more space for the firmware to place data, tell it.
791 * Increment device's write pointer in multiples of 8. */
792 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
793 spin_lock_irqsave(&rxq
->lock
, flags
);
794 rxq
->need_update
= 1;
795 spin_unlock_irqrestore(&rxq
->lock
, flags
);
796 iwl_rx_queue_update_write_ptr(priv
, rxq
);
801 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
803 * When moving to rx_free an SKB is allocated for the slot.
805 * Also restock the Rx queue via iwl_rx_queue_restock.
806 * This is called as a scheduled work item (except for during initialization)
808 void iwlagn_rx_allocate(struct iwl_priv
*priv
, gfp_t priority
)
810 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
811 struct list_head
*element
;
812 struct iwl_rx_mem_buffer
*rxb
;
815 gfp_t gfp_mask
= priority
;
818 spin_lock_irqsave(&rxq
->lock
, flags
);
819 if (list_empty(&rxq
->rx_used
)) {
820 spin_unlock_irqrestore(&rxq
->lock
, flags
);
823 spin_unlock_irqrestore(&rxq
->lock
, flags
);
825 if (rxq
->free_count
> RX_LOW_WATERMARK
)
826 gfp_mask
|= __GFP_NOWARN
;
828 if (priv
->hw_params
.rx_page_order
> 0)
829 gfp_mask
|= __GFP_COMP
;
831 /* Alloc a new receive buffer */
832 page
= alloc_pages(gfp_mask
, priv
->hw_params
.rx_page_order
);
835 IWL_DEBUG_INFO(priv
, "alloc_pages failed, "
837 priv
->hw_params
.rx_page_order
);
839 if ((rxq
->free_count
<= RX_LOW_WATERMARK
) &&
841 IWL_CRIT(priv
, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
842 priority
== GFP_ATOMIC
? "GFP_ATOMIC" : "GFP_KERNEL",
844 /* We don't reschedule replenish work here -- we will
845 * call the restock method and if it still needs
846 * more buffers it will schedule replenish */
850 spin_lock_irqsave(&rxq
->lock
, flags
);
852 if (list_empty(&rxq
->rx_used
)) {
853 spin_unlock_irqrestore(&rxq
->lock
, flags
);
854 __free_pages(page
, priv
->hw_params
.rx_page_order
);
857 element
= rxq
->rx_used
.next
;
858 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
861 spin_unlock_irqrestore(&rxq
->lock
, flags
);
865 /* Get physical address of the RB */
866 rxb
->page_dma
= pci_map_page(priv
->pci_dev
, page
, 0,
867 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
869 /* dma address must be no more than 36 bits */
870 BUG_ON(rxb
->page_dma
& ~DMA_BIT_MASK(36));
871 /* and also 256 byte aligned! */
872 BUG_ON(rxb
->page_dma
& DMA_BIT_MASK(8));
874 spin_lock_irqsave(&rxq
->lock
, flags
);
876 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
878 priv
->alloc_rxb_page
++;
880 spin_unlock_irqrestore(&rxq
->lock
, flags
);
884 void iwlagn_rx_replenish(struct iwl_priv
*priv
)
888 iwlagn_rx_allocate(priv
, GFP_KERNEL
);
890 spin_lock_irqsave(&priv
->lock
, flags
);
891 iwlagn_rx_queue_restock(priv
);
892 spin_unlock_irqrestore(&priv
->lock
, flags
);
895 void iwlagn_rx_replenish_now(struct iwl_priv
*priv
)
897 iwlagn_rx_allocate(priv
, GFP_ATOMIC
);
899 iwlagn_rx_queue_restock(priv
);
902 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
903 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
904 * This free routine walks the list of POOL entries and if SKB is set to
905 * non NULL it is unmapped and freed
907 void iwlagn_rx_queue_free(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
910 for (i
= 0; i
< RX_QUEUE_SIZE
+ RX_FREE_BUFFERS
; i
++) {
911 if (rxq
->pool
[i
].page
!= NULL
) {
912 pci_unmap_page(priv
->pci_dev
, rxq
->pool
[i
].page_dma
,
913 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
915 __iwl_free_pages(priv
, rxq
->pool
[i
].page
);
916 rxq
->pool
[i
].page
= NULL
;
920 dma_free_coherent(&priv
->pci_dev
->dev
, 4 * RX_QUEUE_SIZE
, rxq
->bd
,
922 dma_free_coherent(&priv
->pci_dev
->dev
, sizeof(struct iwl_rb_status
),
923 rxq
->rb_stts
, rxq
->rb_stts_dma
);
928 int iwlagn_rxq_stop(struct iwl_priv
*priv
)
932 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
933 iwl_poll_direct_bit(priv
, FH_MEM_RSSR_RX_STATUS_REG
,
934 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
939 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags
, enum ieee80211_band band
)
944 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
945 if (rate_n_flags
& RATE_MCS_HT_MSK
) {
946 idx
= (rate_n_flags
& 0xff);
948 /* Legacy rate format, search for match in table */
950 if (band
== IEEE80211_BAND_5GHZ
)
951 band_offset
= IWL_FIRST_OFDM_RATE
;
952 for (idx
= band_offset
; idx
< IWL_RATE_COUNT_LEGACY
; idx
++)
953 if (iwl_rates
[idx
].plcp
== (rate_n_flags
& 0xFF))
954 return idx
- band_offset
;
960 /* Calc max signal level (dBm) among 3 possible receivers */
961 static inline int iwlagn_calc_rssi(struct iwl_priv
*priv
,
962 struct iwl_rx_phy_res
*rx_resp
)
964 return priv
->cfg
->ops
->utils
->calc_rssi(priv
, rx_resp
);
967 static u32
iwlagn_translate_rx_status(struct iwl_priv
*priv
, u32 decrypt_in
)
971 if ((decrypt_in
& RX_RES_STATUS_STATION_FOUND
) ==
972 RX_RES_STATUS_STATION_FOUND
)
973 decrypt_out
|= (RX_RES_STATUS_STATION_FOUND
|
974 RX_RES_STATUS_NO_STATION_INFO_MISMATCH
);
976 decrypt_out
|= (decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
);
978 /* packet was not encrypted */
979 if ((decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) ==
980 RX_RES_STATUS_SEC_TYPE_NONE
)
983 /* packet was encrypted with unknown alg */
984 if ((decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) ==
985 RX_RES_STATUS_SEC_TYPE_ERR
)
988 /* decryption was not done in HW */
989 if ((decrypt_in
& RX_MPDU_RES_STATUS_DEC_DONE_MSK
) !=
990 RX_MPDU_RES_STATUS_DEC_DONE_MSK
)
993 switch (decrypt_in
& RX_RES_STATUS_SEC_TYPE_MSK
) {
995 case RX_RES_STATUS_SEC_TYPE_CCMP
:
996 /* alg is CCM: check MIC only */
997 if (!(decrypt_in
& RX_MPDU_RES_STATUS_MIC_OK
))
999 decrypt_out
|= RX_RES_STATUS_BAD_ICV_MIC
;
1001 decrypt_out
|= RX_RES_STATUS_DECRYPT_OK
;
1005 case RX_RES_STATUS_SEC_TYPE_TKIP
:
1006 if (!(decrypt_in
& RX_MPDU_RES_STATUS_TTAK_OK
)) {
1008 decrypt_out
|= RX_RES_STATUS_BAD_KEY_TTAK
;
1011 /* fall through if TTAK OK */
1013 if (!(decrypt_in
& RX_MPDU_RES_STATUS_ICV_OK
))
1014 decrypt_out
|= RX_RES_STATUS_BAD_ICV_MIC
;
1016 decrypt_out
|= RX_RES_STATUS_DECRYPT_OK
;
1020 IWL_DEBUG_RX(priv
, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1021 decrypt_in
, decrypt_out
);
1026 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv
*priv
,
1027 struct ieee80211_hdr
*hdr
,
1030 struct iwl_rx_mem_buffer
*rxb
,
1031 struct ieee80211_rx_status
*stats
)
1033 struct sk_buff
*skb
;
1034 __le16 fc
= hdr
->frame_control
;
1036 /* We only process data packets if the interface is open */
1037 if (unlikely(!priv
->is_open
)) {
1038 IWL_DEBUG_DROP_LIMIT(priv
,
1039 "Dropping packet while interface is not open.\n");
1043 /* In case of HW accelerated crypto and bad decryption, drop */
1044 if (!priv
->cfg
->mod_params
->sw_crypto
&&
1045 iwl_set_decrypted_flag(priv
, hdr
, ampdu_status
, stats
))
1048 skb
= dev_alloc_skb(128);
1050 IWL_ERR(priv
, "dev_alloc_skb failed\n");
1054 skb_add_rx_frag(skb
, 0, rxb
->page
, (void *)hdr
- rxb_addr(rxb
), len
);
1056 iwl_update_stats(priv
, false, fc
, len
);
1057 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
1059 ieee80211_rx(priv
->hw
, skb
);
1060 priv
->alloc_rxb_page
--;
1064 /* Called for REPLY_RX (legacy ABG frames), or
1065 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1066 void iwlagn_rx_reply_rx(struct iwl_priv
*priv
,
1067 struct iwl_rx_mem_buffer
*rxb
)
1069 struct ieee80211_hdr
*header
;
1070 struct ieee80211_rx_status rx_status
;
1071 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1072 struct iwl_rx_phy_res
*phy_res
;
1073 __le32 rx_pkt_status
;
1074 struct iwl_rx_mpdu_res_start
*amsdu
;
1080 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1081 * REPLY_RX: physical layer info is in this buffer
1082 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1083 * command and cached in priv->last_phy_res
1085 * Here we set up local variables depending on which command is
1088 if (pkt
->hdr
.cmd
== REPLY_RX
) {
1089 phy_res
= (struct iwl_rx_phy_res
*)pkt
->u
.raw
;
1090 header
= (struct ieee80211_hdr
*)(pkt
->u
.raw
+ sizeof(*phy_res
)
1091 + phy_res
->cfg_phy_cnt
);
1093 len
= le16_to_cpu(phy_res
->byte_count
);
1094 rx_pkt_status
= *(__le32
*)(pkt
->u
.raw
+ sizeof(*phy_res
) +
1095 phy_res
->cfg_phy_cnt
+ len
);
1096 ampdu_status
= le32_to_cpu(rx_pkt_status
);
1098 if (!priv
->_agn
.last_phy_res_valid
) {
1099 IWL_ERR(priv
, "MPDU frame without cached PHY data\n");
1102 phy_res
= &priv
->_agn
.last_phy_res
;
1103 amsdu
= (struct iwl_rx_mpdu_res_start
*)pkt
->u
.raw
;
1104 header
= (struct ieee80211_hdr
*)(pkt
->u
.raw
+ sizeof(*amsdu
));
1105 len
= le16_to_cpu(amsdu
->byte_count
);
1106 rx_pkt_status
= *(__le32
*)(pkt
->u
.raw
+ sizeof(*amsdu
) + len
);
1107 ampdu_status
= iwlagn_translate_rx_status(priv
,
1108 le32_to_cpu(rx_pkt_status
));
1111 if ((unlikely(phy_res
->cfg_phy_cnt
> 20))) {
1112 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
1113 phy_res
->cfg_phy_cnt
);
1117 if (!(rx_pkt_status
& RX_RES_STATUS_NO_CRC32_ERROR
) ||
1118 !(rx_pkt_status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
1119 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n",
1120 le32_to_cpu(rx_pkt_status
));
1124 /* This will be used in several places later */
1125 rate_n_flags
= le32_to_cpu(phy_res
->rate_n_flags
);
1127 /* rx_status carries information about the packet to mac80211 */
1128 rx_status
.mactime
= le64_to_cpu(phy_res
->timestamp
);
1130 ieee80211_channel_to_frequency(le16_to_cpu(phy_res
->channel
));
1131 rx_status
.band
= (phy_res
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
1132 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
1133 rx_status
.rate_idx
=
1134 iwlagn_hwrate_to_mac80211_idx(rate_n_flags
, rx_status
.band
);
1137 /* TSF isn't reliable. In order to allow smooth user experience,
1138 * this W/A doesn't propagate it to the mac80211 */
1139 /*rx_status.flag |= RX_FLAG_TSFT;*/
1141 priv
->ucode_beacon_time
= le32_to_cpu(phy_res
->beacon_time_stamp
);
1143 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1144 rx_status
.signal
= iwlagn_calc_rssi(priv
, phy_res
);
1146 iwl_dbg_log_rx_data_frame(priv
, len
, header
);
1147 IWL_DEBUG_STATS_LIMIT(priv
, "Rssi %d, TSF %llu\n",
1148 rx_status
.signal
, (unsigned long long)rx_status
.mactime
);
1153 * It seems that the antenna field in the phy flags value
1154 * is actually a bit field. This is undefined by radiotap,
1155 * it wants an actual antenna number but I always get "7"
1156 * for most legacy frames I receive indicating that the
1157 * same frame was received on all three RX chains.
1159 * I think this field should be removed in favor of a
1160 * new 802.11n radiotap field "RX chains" that is defined
1164 (le16_to_cpu(phy_res
->phy_flags
) & RX_RES_PHY_FLAGS_ANTENNA_MSK
)
1165 >> RX_RES_PHY_FLAGS_ANTENNA_POS
;
1167 /* set the preamble flag if appropriate */
1168 if (phy_res
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
1169 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
1171 /* Set up the HT phy flags */
1172 if (rate_n_flags
& RATE_MCS_HT_MSK
)
1173 rx_status
.flag
|= RX_FLAG_HT
;
1174 if (rate_n_flags
& RATE_MCS_HT40_MSK
)
1175 rx_status
.flag
|= RX_FLAG_40MHZ
;
1176 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
1177 rx_status
.flag
|= RX_FLAG_SHORT_GI
;
1179 iwlagn_pass_packet_to_mac80211(priv
, header
, len
, ampdu_status
,
1183 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1184 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1185 void iwlagn_rx_reply_rx_phy(struct iwl_priv
*priv
,
1186 struct iwl_rx_mem_buffer
*rxb
)
1188 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1189 priv
->_agn
.last_phy_res_valid
= true;
1190 memcpy(&priv
->_agn
.last_phy_res
, pkt
->u
.raw
,
1191 sizeof(struct iwl_rx_phy_res
));
1194 static int iwl_get_single_channel_for_scan(struct iwl_priv
*priv
,
1195 struct ieee80211_vif
*vif
,
1196 enum ieee80211_band band
,
1197 struct iwl_scan_channel
*scan_ch
)
1199 const struct ieee80211_supported_band
*sband
;
1200 u16 passive_dwell
= 0;
1201 u16 active_dwell
= 0;
1205 sband
= iwl_get_hw_mode(priv
, band
);
1207 IWL_ERR(priv
, "invalid band\n");
1211 active_dwell
= iwl_get_active_dwell_time(priv
, band
, 0);
1212 passive_dwell
= iwl_get_passive_dwell_time(priv
, band
, vif
);
1214 if (passive_dwell
<= active_dwell
)
1215 passive_dwell
= active_dwell
+ 1;
1217 channel
= iwl_get_single_channel_number(priv
, band
);
1219 scan_ch
->channel
= cpu_to_le16(channel
);
1220 scan_ch
->type
= SCAN_CHANNEL_TYPE_PASSIVE
;
1221 scan_ch
->active_dwell
= cpu_to_le16(active_dwell
);
1222 scan_ch
->passive_dwell
= cpu_to_le16(passive_dwell
);
1223 /* Set txpower levels to defaults */
1224 scan_ch
->dsp_atten
= 110;
1225 if (band
== IEEE80211_BAND_5GHZ
)
1226 scan_ch
->tx_gain
= ((1 << 5) | (3 << 3)) | 3;
1228 scan_ch
->tx_gain
= ((1 << 5) | (5 << 3));
1231 IWL_ERR(priv
, "no valid channel found\n");
1235 static int iwl_get_channels_for_scan(struct iwl_priv
*priv
,
1236 struct ieee80211_vif
*vif
,
1237 enum ieee80211_band band
,
1238 u8 is_active
, u8 n_probes
,
1239 struct iwl_scan_channel
*scan_ch
)
1241 struct ieee80211_channel
*chan
;
1242 const struct ieee80211_supported_band
*sband
;
1243 const struct iwl_channel_info
*ch_info
;
1244 u16 passive_dwell
= 0;
1245 u16 active_dwell
= 0;
1249 sband
= iwl_get_hw_mode(priv
, band
);
1253 active_dwell
= iwl_get_active_dwell_time(priv
, band
, n_probes
);
1254 passive_dwell
= iwl_get_passive_dwell_time(priv
, band
, vif
);
1256 if (passive_dwell
<= active_dwell
)
1257 passive_dwell
= active_dwell
+ 1;
1259 for (i
= 0, added
= 0; i
< priv
->scan_request
->n_channels
; i
++) {
1260 chan
= priv
->scan_request
->channels
[i
];
1262 if (chan
->band
!= band
)
1265 channel
= chan
->hw_value
;
1266 scan_ch
->channel
= cpu_to_le16(channel
);
1268 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
1269 if (!is_channel_valid(ch_info
)) {
1270 IWL_DEBUG_SCAN(priv
, "Channel %d is INVALID for this band.\n",
1275 if (!is_active
|| is_channel_passive(ch_info
) ||
1276 (chan
->flags
& IEEE80211_CHAN_PASSIVE_SCAN
))
1277 scan_ch
->type
= SCAN_CHANNEL_TYPE_PASSIVE
;
1279 scan_ch
->type
= SCAN_CHANNEL_TYPE_ACTIVE
;
1282 scan_ch
->type
|= IWL_SCAN_PROBE_MASK(n_probes
);
1284 scan_ch
->active_dwell
= cpu_to_le16(active_dwell
);
1285 scan_ch
->passive_dwell
= cpu_to_le16(passive_dwell
);
1287 /* Set txpower levels to defaults */
1288 scan_ch
->dsp_atten
= 110;
1290 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1292 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1294 if (band
== IEEE80211_BAND_5GHZ
)
1295 scan_ch
->tx_gain
= ((1 << 5) | (3 << 3)) | 3;
1297 scan_ch
->tx_gain
= ((1 << 5) | (5 << 3));
1299 IWL_DEBUG_SCAN(priv
, "Scanning ch=%d prob=0x%X [%s %d]\n",
1300 channel
, le32_to_cpu(scan_ch
->type
),
1301 (scan_ch
->type
& SCAN_CHANNEL_TYPE_ACTIVE
) ?
1302 "ACTIVE" : "PASSIVE",
1303 (scan_ch
->type
& SCAN_CHANNEL_TYPE_ACTIVE
) ?
1304 active_dwell
: passive_dwell
);
1310 IWL_DEBUG_SCAN(priv
, "total channels to scan %d\n", added
);
1314 int iwlagn_request_scan(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
)
1316 struct iwl_host_cmd cmd
= {
1317 .id
= REPLY_SCAN_CMD
,
1318 .len
= sizeof(struct iwl_scan_cmd
),
1319 .flags
= CMD_SIZE_HUGE
,
1321 struct iwl_scan_cmd
*scan
;
1322 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
1326 enum ieee80211_band band
;
1328 u8 rx_ant
= priv
->hw_params
.valid_rx_ant
;
1330 bool is_active
= false;
1333 u8 scan_tx_antennas
= priv
->hw_params
.valid_tx_ant
;
1336 lockdep_assert_held(&priv
->mutex
);
1339 ctx
= iwl_rxon_ctx_from_vif(vif
);
1341 if (!priv
->scan_cmd
) {
1342 priv
->scan_cmd
= kmalloc(sizeof(struct iwl_scan_cmd
) +
1343 IWL_MAX_SCAN_SIZE
, GFP_KERNEL
);
1344 if (!priv
->scan_cmd
) {
1345 IWL_DEBUG_SCAN(priv
,
1346 "fail to allocate memory for scan\n");
1350 scan
= priv
->scan_cmd
;
1351 memset(scan
, 0, sizeof(struct iwl_scan_cmd
) + IWL_MAX_SCAN_SIZE
);
1353 scan
->quiet_plcp_th
= IWL_PLCP_QUIET_THRESH
;
1354 scan
->quiet_time
= IWL_ACTIVE_QUIET_TIME
;
1356 if (iwl_is_any_associated(priv
)) {
1359 u32 suspend_time
= 100;
1360 u32 scan_suspend_time
= 100;
1361 unsigned long flags
;
1363 IWL_DEBUG_INFO(priv
, "Scanning while associated...\n");
1364 spin_lock_irqsave(&priv
->lock
, flags
);
1365 if (priv
->is_internal_short_scan
)
1368 interval
= vif
->bss_conf
.beacon_int
;
1369 spin_unlock_irqrestore(&priv
->lock
, flags
);
1371 scan
->suspend_time
= 0;
1372 scan
->max_out_time
= cpu_to_le32(200 * 1024);
1374 interval
= suspend_time
;
1376 extra
= (suspend_time
/ interval
) << 22;
1377 scan_suspend_time
= (extra
|
1378 ((suspend_time
% interval
) * 1024));
1379 scan
->suspend_time
= cpu_to_le32(scan_suspend_time
);
1380 IWL_DEBUG_SCAN(priv
, "suspend_time 0x%X beacon interval %d\n",
1381 scan_suspend_time
, interval
);
1384 if (priv
->is_internal_short_scan
) {
1385 IWL_DEBUG_SCAN(priv
, "Start internal passive scan.\n");
1386 } else if (priv
->scan_request
->n_ssids
) {
1388 IWL_DEBUG_SCAN(priv
, "Kicking off active scan\n");
1389 for (i
= 0; i
< priv
->scan_request
->n_ssids
; i
++) {
1390 /* always does wildcard anyway */
1391 if (!priv
->scan_request
->ssids
[i
].ssid_len
)
1393 scan
->direct_scan
[p
].id
= WLAN_EID_SSID
;
1394 scan
->direct_scan
[p
].len
=
1395 priv
->scan_request
->ssids
[i
].ssid_len
;
1396 memcpy(scan
->direct_scan
[p
].ssid
,
1397 priv
->scan_request
->ssids
[i
].ssid
,
1398 priv
->scan_request
->ssids
[i
].ssid_len
);
1404 IWL_DEBUG_SCAN(priv
, "Start passive scan.\n");
1406 scan
->tx_cmd
.tx_flags
= TX_CMD_FLG_SEQ_CTL_MSK
;
1407 scan
->tx_cmd
.sta_id
= ctx
->bcast_sta_id
;
1408 scan
->tx_cmd
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
1410 switch (priv
->scan_band
) {
1411 case IEEE80211_BAND_2GHZ
:
1412 scan
->flags
= RXON_FLG_BAND_24G_MSK
| RXON_FLG_AUTO_DETECT_MSK
;
1413 chan_mod
= le32_to_cpu(
1414 priv
->contexts
[IWL_RXON_CTX_BSS
].active
.flags
&
1415 RXON_FLG_CHANNEL_MODE_MSK
)
1416 >> RXON_FLG_CHANNEL_MODE_POS
;
1417 if (chan_mod
== CHANNEL_MODE_PURE_40
) {
1418 rate
= IWL_RATE_6M_PLCP
;
1420 rate
= IWL_RATE_1M_PLCP
;
1421 rate_flags
= RATE_MCS_CCK_MSK
;
1424 * Internal scans are passive, so we can indiscriminately set
1425 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1427 if (priv
->cfg
->advanced_bt_coexist
)
1428 scan
->tx_cmd
.tx_flags
|= TX_CMD_FLG_IGNORE_BT
;
1429 scan
->good_CRC_th
= IWL_GOOD_CRC_TH_DISABLED
;
1431 case IEEE80211_BAND_5GHZ
:
1432 rate
= IWL_RATE_6M_PLCP
;
1434 * If active scanning is requested but a certain channel is
1435 * marked passive, we can do active scanning if we detect
1438 * There is an issue with some firmware versions that triggers
1439 * a sysassert on a "good CRC threshold" of zero (== disabled),
1440 * on a radar channel even though this means that we should NOT
1443 * The "good CRC threshold" is the number of frames that we
1444 * need to receive during our dwell time on a channel before
1445 * sending out probes -- setting this to a huge value will
1446 * mean we never reach it, but at the same time work around
1447 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1448 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1450 scan
->good_CRC_th
= is_active
? IWL_GOOD_CRC_TH_DEFAULT
:
1451 IWL_GOOD_CRC_TH_NEVER
;
1454 IWL_WARN(priv
, "Invalid scan band\n");
1458 band
= priv
->scan_band
;
1460 if (priv
->cfg
->scan_rx_antennas
[band
])
1461 rx_ant
= priv
->cfg
->scan_rx_antennas
[band
];
1463 if (priv
->cfg
->scan_tx_antennas
[band
])
1464 scan_tx_antennas
= priv
->cfg
->scan_tx_antennas
[band
];
1466 if (priv
->cfg
->advanced_bt_coexist
&& priv
->bt_full_concurrent
) {
1467 /* operated as 1x1 in full concurrency mode */
1469 first_antenna(priv
->cfg
->scan_tx_antennas
[band
]);
1472 priv
->scan_tx_ant
[band
] = iwl_toggle_tx_ant(priv
, priv
->scan_tx_ant
[band
],
1474 rate_flags
|= iwl_ant_idx_to_flags(priv
->scan_tx_ant
[band
]);
1475 scan
->tx_cmd
.rate_n_flags
= iwl_hw_set_rate_n_flags(rate
, rate_flags
);
1477 /* In power save mode use one chain, otherwise use all chains */
1478 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
1479 /* rx_ant has been set to all valid chains previously */
1480 active_chains
= rx_ant
&
1481 ((u8
)(priv
->chain_noise_data
.active_chains
));
1483 active_chains
= rx_ant
;
1485 IWL_DEBUG_SCAN(priv
, "chain_noise_data.active_chains: %u\n",
1486 priv
->chain_noise_data
.active_chains
);
1488 rx_ant
= first_antenna(active_chains
);
1490 if (priv
->cfg
->advanced_bt_coexist
&& priv
->bt_full_concurrent
) {
1491 /* operated as 1x1 in full concurrency mode */
1492 rx_ant
= first_antenna(rx_ant
);
1495 /* MIMO is not used here, but value is required */
1496 rx_chain
|= priv
->hw_params
.valid_rx_ant
<< RXON_RX_CHAIN_VALID_POS
;
1497 rx_chain
|= rx_ant
<< RXON_RX_CHAIN_FORCE_MIMO_SEL_POS
;
1498 rx_chain
|= rx_ant
<< RXON_RX_CHAIN_FORCE_SEL_POS
;
1499 rx_chain
|= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS
;
1500 scan
->rx_chain
= cpu_to_le16(rx_chain
);
1501 if (!priv
->is_internal_short_scan
) {
1502 cmd_len
= iwl_fill_probe_req(priv
,
1503 (struct ieee80211_mgmt
*)scan
->data
,
1505 priv
->scan_request
->ie
,
1506 priv
->scan_request
->ie_len
,
1507 IWL_MAX_SCAN_SIZE
- sizeof(*scan
));
1509 /* use bcast addr, will not be transmitted but must be valid */
1510 cmd_len
= iwl_fill_probe_req(priv
,
1511 (struct ieee80211_mgmt
*)scan
->data
,
1512 iwl_bcast_addr
, NULL
, 0,
1513 IWL_MAX_SCAN_SIZE
- sizeof(*scan
));
1516 scan
->tx_cmd
.len
= cpu_to_le16(cmd_len
);
1518 scan
->filter_flags
|= (RXON_FILTER_ACCEPT_GRP_MSK
|
1519 RXON_FILTER_BCON_AWARE_MSK
);
1521 if (priv
->is_internal_short_scan
) {
1522 scan
->channel_count
=
1523 iwl_get_single_channel_for_scan(priv
, vif
, band
,
1524 (void *)&scan
->data
[le16_to_cpu(
1525 scan
->tx_cmd
.len
)]);
1527 scan
->channel_count
=
1528 iwl_get_channels_for_scan(priv
, vif
, band
,
1529 is_active
, n_probes
,
1530 (void *)&scan
->data
[le16_to_cpu(
1531 scan
->tx_cmd
.len
)]);
1533 if (scan
->channel_count
== 0) {
1534 IWL_DEBUG_SCAN(priv
, "channel count %d\n", scan
->channel_count
);
1538 cmd
.len
+= le16_to_cpu(scan
->tx_cmd
.len
) +
1539 scan
->channel_count
* sizeof(struct iwl_scan_channel
);
1541 scan
->len
= cpu_to_le16(cmd
.len
);
1543 if (priv
->cfg
->ops
->hcmd
->set_pan_params
) {
1544 ret
= priv
->cfg
->ops
->hcmd
->set_pan_params(priv
);
1549 set_bit(STATUS_SCAN_HW
, &priv
->status
);
1550 ret
= iwl_send_cmd_sync(priv
, &cmd
);
1552 clear_bit(STATUS_SCAN_HW
, &priv
->status
);
1553 if (priv
->cfg
->ops
->hcmd
->set_pan_params
)
1554 priv
->cfg
->ops
->hcmd
->set_pan_params(priv
);
1560 int iwlagn_manage_ibss_station(struct iwl_priv
*priv
,
1561 struct ieee80211_vif
*vif
, bool add
)
1563 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
1566 return iwl_add_bssid_station(priv
, vif_priv
->ctx
,
1567 vif
->bss_conf
.bssid
, true,
1568 &vif_priv
->ibss_bssid_sta_id
);
1569 return iwl_remove_station(priv
, vif_priv
->ibss_bssid_sta_id
,
1570 vif
->bss_conf
.bssid
);
1573 void iwl_free_tfds_in_queue(struct iwl_priv
*priv
,
1574 int sta_id
, int tid
, int freed
)
1576 lockdep_assert_held(&priv
->sta_lock
);
1578 if (priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
>= freed
)
1579 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1581 IWL_DEBUG_TX(priv
, "free more than tfds_in_queue (%u:%d)\n",
1582 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
,
1584 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
= 0;
1588 #define IWL_FLUSH_WAIT_MS 2000
1590 int iwlagn_wait_tx_queue_empty(struct iwl_priv
*priv
)
1592 struct iwl_tx_queue
*txq
;
1593 struct iwl_queue
*q
;
1595 unsigned long now
= jiffies
;
1598 /* waiting for all the tx frames complete might take a while */
1599 for (cnt
= 0; cnt
< priv
->hw_params
.max_txq_num
; cnt
++) {
1600 if (cnt
== priv
->cmd_queue
)
1602 txq
= &priv
->txq
[cnt
];
1604 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1605 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1608 if (q
->read_ptr
!= q
->write_ptr
) {
1609 IWL_ERR(priv
, "fail to flush all tx fifo queues\n");
1617 #define IWL_TX_QUEUE_MSK 0xfffff
1620 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1623 * 1. acquire mutex before calling
1624 * 2. make sure rf is on and not in exit state
1626 int iwlagn_txfifo_flush(struct iwl_priv
*priv
, u16 flush_control
)
1628 struct iwl_txfifo_flush_cmd flush_cmd
;
1629 struct iwl_host_cmd cmd
= {
1630 .id
= REPLY_TXFIFO_FLUSH
,
1631 .len
= sizeof(struct iwl_txfifo_flush_cmd
),
1638 memset(&flush_cmd
, 0, sizeof(flush_cmd
));
1639 flush_cmd
.fifo_control
= IWL_TX_FIFO_VO_MSK
| IWL_TX_FIFO_VI_MSK
|
1640 IWL_TX_FIFO_BE_MSK
| IWL_TX_FIFO_BK_MSK
;
1641 if (priv
->cfg
->sku
& IWL_SKU_N
)
1642 flush_cmd
.fifo_control
|= IWL_AGG_TX_QUEUE_MSK
;
1644 IWL_DEBUG_INFO(priv
, "fifo queue control: 0X%x\n",
1645 flush_cmd
.fifo_control
);
1646 flush_cmd
.flush_control
= cpu_to_le16(flush_control
);
1648 return iwl_send_cmd(priv
, &cmd
);
1651 void iwlagn_dev_txfifo_flush(struct iwl_priv
*priv
, u16 flush_control
)
1653 mutex_lock(&priv
->mutex
);
1654 ieee80211_stop_queues(priv
->hw
);
1655 if (priv
->cfg
->ops
->lib
->txfifo_flush(priv
, IWL_DROP_ALL
)) {
1656 IWL_ERR(priv
, "flush request fail\n");
1659 IWL_DEBUG_INFO(priv
, "wait transmit/flush all frames\n");
1660 iwlagn_wait_tx_queue_empty(priv
);
1662 ieee80211_wake_queues(priv
->hw
);
1663 mutex_unlock(&priv
->mutex
);
1670 * Macros to access the lookup table.
1672 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1673 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1675 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1677 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1678 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1679 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1681 * These macros encode that format.
1683 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1684 wifi_txrx, wifi_sh_ant_req) \
1685 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1686 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1688 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1689 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1690 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1691 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1692 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1693 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1695 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1696 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1697 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1698 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1700 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1701 wifi_req, wifi_prio, wifi_txrx, \
1703 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1704 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1707 #define LUT_WLAN_KILL_OP(lut, op, val) \
1708 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1709 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1710 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1711 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1712 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1713 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1714 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1715 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1716 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1717 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1718 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1719 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1720 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1722 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1723 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1724 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1725 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1726 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1727 wifi_req, wifi_prio, wifi_txrx, \
1729 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1730 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1731 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1732 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1733 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1734 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1735 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1736 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1738 static const __le32 iwlagn_def_3w_lookup
[12] = {
1739 cpu_to_le32(0xaaaaaaaa),
1740 cpu_to_le32(0xaaaaaaaa),
1741 cpu_to_le32(0xaeaaaaaa),
1742 cpu_to_le32(0xaaaaaaaa),
1743 cpu_to_le32(0xcc00ff28),
1744 cpu_to_le32(0x0000aaaa),
1745 cpu_to_le32(0xcc00aaaa),
1746 cpu_to_le32(0x0000aaaa),
1747 cpu_to_le32(0xc0004000),
1748 cpu_to_le32(0x00004000),
1749 cpu_to_le32(0xf0005000),
1750 cpu_to_le32(0xf0004000),
1753 static const __le32 iwlagn_concurrent_lookup
[12] = {
1754 cpu_to_le32(0xaaaaaaaa),
1755 cpu_to_le32(0xaaaaaaaa),
1756 cpu_to_le32(0xaaaaaaaa),
1757 cpu_to_le32(0xaaaaaaaa),
1758 cpu_to_le32(0xaaaaaaaa),
1759 cpu_to_le32(0xaaaaaaaa),
1760 cpu_to_le32(0xaaaaaaaa),
1761 cpu_to_le32(0xaaaaaaaa),
1762 cpu_to_le32(0x00000000),
1763 cpu_to_le32(0x00000000),
1764 cpu_to_le32(0x00000000),
1765 cpu_to_le32(0x00000000),
1768 void iwlagn_send_advance_bt_config(struct iwl_priv
*priv
)
1770 struct iwlagn_bt_cmd bt_cmd
= {
1771 .max_kill
= IWLAGN_BT_MAX_KILL_DEFAULT
,
1772 .bt3_timer_t7_value
= IWLAGN_BT3_T7_DEFAULT
,
1773 .bt3_prio_sample_time
= IWLAGN_BT3_PRIO_SAMPLE_DEFAULT
,
1774 .bt3_timer_t2_value
= IWLAGN_BT3_T2_DEFAULT
,
1777 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup
) !=
1778 sizeof(bt_cmd
.bt3_lookup_table
));
1780 bt_cmd
.prio_boost
= priv
->cfg
->bt_prio_boost
;
1781 bt_cmd
.kill_ack_mask
= priv
->kill_ack_mask
;
1782 bt_cmd
.kill_cts_mask
= priv
->kill_cts_mask
;
1783 bt_cmd
.valid
= priv
->bt_valid
;
1786 * Configure BT coex mode to "no coexistence" when the
1787 * user disabled BT coexistence, we have no interface
1788 * (might be in monitor mode), or the interface is in
1789 * IBSS mode (no proper uCode support for coex then).
1791 if (!bt_coex_active
|| priv
->iw_mode
== NL80211_IFTYPE_ADHOC
) {
1794 bt_cmd
.flags
= IWLAGN_BT_FLAG_COEX_MODE_3W
<<
1795 IWLAGN_BT_FLAG_COEX_MODE_SHIFT
;
1796 if (priv
->bt_ch_announce
)
1797 bt_cmd
.flags
|= IWLAGN_BT_FLAG_CHANNEL_INHIBITION
;
1798 IWL_DEBUG_INFO(priv
, "BT coex flag: 0X%x\n", bt_cmd
.flags
);
1800 if (priv
->bt_full_concurrent
)
1801 memcpy(bt_cmd
.bt3_lookup_table
, iwlagn_concurrent_lookup
,
1802 sizeof(iwlagn_concurrent_lookup
));
1804 memcpy(bt_cmd
.bt3_lookup_table
, iwlagn_def_3w_lookup
,
1805 sizeof(iwlagn_def_3w_lookup
));
1807 IWL_DEBUG_INFO(priv
, "BT coex %s in %s mode\n",
1808 bt_cmd
.flags
? "active" : "disabled",
1809 priv
->bt_full_concurrent
?
1810 "full concurrency" : "3-wire");
1812 if (iwl_send_cmd_pdu(priv
, REPLY_BT_CONFIG
, sizeof(bt_cmd
), &bt_cmd
))
1813 IWL_ERR(priv
, "failed to send BT Coex Config\n");
1816 * When we are doing a restart, need to also reconfigure BT
1817 * SCO to the device. If not doing a restart, bt_sco_active
1818 * will always be false, so there's no need to have an extra
1819 * variable to check for it.
1821 if (priv
->bt_sco_active
) {
1822 struct iwlagn_bt_sco_cmd sco_cmd
= { .flags
= 0 };
1824 if (priv
->bt_sco_active
)
1825 sco_cmd
.flags
|= IWLAGN_BT_SCO_ACTIVE
;
1826 if (iwl_send_cmd_pdu(priv
, REPLY_BT_COEX_SCO
,
1827 sizeof(sco_cmd
), &sco_cmd
))
1828 IWL_ERR(priv
, "failed to send BT SCO command\n");
1832 static void iwlagn_bt_traffic_change_work(struct work_struct
*work
)
1834 struct iwl_priv
*priv
=
1835 container_of(work
, struct iwl_priv
, bt_traffic_change_work
);
1836 struct iwl_rxon_context
*ctx
;
1837 int smps_request
= -1;
1839 IWL_DEBUG_INFO(priv
, "BT traffic load changes: %d\n",
1840 priv
->bt_traffic_load
);
1842 switch (priv
->bt_traffic_load
) {
1843 case IWL_BT_COEX_TRAFFIC_LOAD_NONE
:
1844 smps_request
= IEEE80211_SMPS_AUTOMATIC
;
1846 case IWL_BT_COEX_TRAFFIC_LOAD_LOW
:
1847 smps_request
= IEEE80211_SMPS_DYNAMIC
;
1849 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH
:
1850 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS
:
1851 smps_request
= IEEE80211_SMPS_STATIC
;
1854 IWL_ERR(priv
, "Invalid BT traffic load: %d\n",
1855 priv
->bt_traffic_load
);
1859 mutex_lock(&priv
->mutex
);
1861 if (priv
->cfg
->ops
->lib
->update_chain_flags
)
1862 priv
->cfg
->ops
->lib
->update_chain_flags(priv
);
1864 if (smps_request
!= -1) {
1865 for_each_context(priv
, ctx
) {
1866 if (ctx
->vif
&& ctx
->vif
->type
== NL80211_IFTYPE_STATION
)
1867 ieee80211_request_smps(ctx
->vif
, smps_request
);
1871 mutex_unlock(&priv
->mutex
);
1874 static void iwlagn_print_uartmsg(struct iwl_priv
*priv
,
1875 struct iwl_bt_uart_msg
*uart_msg
)
1877 IWL_DEBUG_NOTIF(priv
, "Message Type = 0x%X, SSN = 0x%X, "
1878 "Update Req = 0x%X",
1879 (BT_UART_MSG_FRAME1MSGTYPE_MSK
& uart_msg
->frame1
) >>
1880 BT_UART_MSG_FRAME1MSGTYPE_POS
,
1881 (BT_UART_MSG_FRAME1SSN_MSK
& uart_msg
->frame1
) >>
1882 BT_UART_MSG_FRAME1SSN_POS
,
1883 (BT_UART_MSG_FRAME1UPDATEREQ_MSK
& uart_msg
->frame1
) >>
1884 BT_UART_MSG_FRAME1UPDATEREQ_POS
);
1886 IWL_DEBUG_NOTIF(priv
, "Open connections = 0x%X, Traffic load = 0x%X, "
1887 "Chl_SeqN = 0x%X, In band = 0x%X",
1888 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK
& uart_msg
->frame2
) >>
1889 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS
,
1890 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK
& uart_msg
->frame2
) >>
1891 BT_UART_MSG_FRAME2TRAFFICLOAD_POS
,
1892 (BT_UART_MSG_FRAME2CHLSEQN_MSK
& uart_msg
->frame2
) >>
1893 BT_UART_MSG_FRAME2CHLSEQN_POS
,
1894 (BT_UART_MSG_FRAME2INBAND_MSK
& uart_msg
->frame2
) >>
1895 BT_UART_MSG_FRAME2INBAND_POS
);
1897 IWL_DEBUG_NOTIF(priv
, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1898 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1899 (BT_UART_MSG_FRAME3SCOESCO_MSK
& uart_msg
->frame3
) >>
1900 BT_UART_MSG_FRAME3SCOESCO_POS
,
1901 (BT_UART_MSG_FRAME3SNIFF_MSK
& uart_msg
->frame3
) >>
1902 BT_UART_MSG_FRAME3SNIFF_POS
,
1903 (BT_UART_MSG_FRAME3A2DP_MSK
& uart_msg
->frame3
) >>
1904 BT_UART_MSG_FRAME3A2DP_POS
,
1905 (BT_UART_MSG_FRAME3ACL_MSK
& uart_msg
->frame3
) >>
1906 BT_UART_MSG_FRAME3ACL_POS
,
1907 (BT_UART_MSG_FRAME3MASTER_MSK
& uart_msg
->frame3
) >>
1908 BT_UART_MSG_FRAME3MASTER_POS
,
1909 (BT_UART_MSG_FRAME3OBEX_MSK
& uart_msg
->frame3
) >>
1910 BT_UART_MSG_FRAME3OBEX_POS
);
1912 IWL_DEBUG_NOTIF(priv
, "Idle duration = 0x%X",
1913 (BT_UART_MSG_FRAME4IDLEDURATION_MSK
& uart_msg
->frame4
) >>
1914 BT_UART_MSG_FRAME4IDLEDURATION_POS
);
1916 IWL_DEBUG_NOTIF(priv
, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1917 "eSCO Retransmissions = 0x%X",
1918 (BT_UART_MSG_FRAME5TXACTIVITY_MSK
& uart_msg
->frame5
) >>
1919 BT_UART_MSG_FRAME5TXACTIVITY_POS
,
1920 (BT_UART_MSG_FRAME5RXACTIVITY_MSK
& uart_msg
->frame5
) >>
1921 BT_UART_MSG_FRAME5RXACTIVITY_POS
,
1922 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK
& uart_msg
->frame5
) >>
1923 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS
);
1925 IWL_DEBUG_NOTIF(priv
, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1926 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK
& uart_msg
->frame6
) >>
1927 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS
,
1928 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK
& uart_msg
->frame6
) >>
1929 BT_UART_MSG_FRAME6DISCOVERABLE_POS
);
1931 IWL_DEBUG_NOTIF(priv
, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1932 "0x%X, Connectable = 0x%X",
1933 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK
& uart_msg
->frame7
) >>
1934 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS
,
1935 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK
& uart_msg
->frame7
) >>
1936 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS
,
1937 (BT_UART_MSG_FRAME7CONNECTABLE_MSK
& uart_msg
->frame7
) >>
1938 BT_UART_MSG_FRAME7CONNECTABLE_POS
);
1941 static void iwlagn_set_kill_ack_msk(struct iwl_priv
*priv
,
1942 struct iwl_bt_uart_msg
*uart_msg
)
1945 __le32 bt_kill_ack_msg
[2] = {
1946 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1948 kill_ack_msk
= (((BT_UART_MSG_FRAME3A2DP_MSK
|
1949 BT_UART_MSG_FRAME3SNIFF_MSK
|
1950 BT_UART_MSG_FRAME3SCOESCO_MSK
) &
1951 uart_msg
->frame3
) == 0) ? 1 : 0;
1952 if (priv
->kill_ack_mask
!= bt_kill_ack_msg
[kill_ack_msk
]) {
1953 priv
->bt_valid
|= IWLAGN_BT_VALID_KILL_ACK_MASK
;
1954 priv
->kill_ack_mask
= bt_kill_ack_msg
[kill_ack_msk
];
1955 /* schedule to send runtime bt_config */
1956 queue_work(priv
->workqueue
, &priv
->bt_runtime_config
);
1961 void iwlagn_bt_coex_profile_notif(struct iwl_priv
*priv
,
1962 struct iwl_rx_mem_buffer
*rxb
)
1964 unsigned long flags
;
1965 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1966 struct iwl_bt_coex_profile_notif
*coex
= &pkt
->u
.bt_coex_profile_notif
;
1967 struct iwlagn_bt_sco_cmd sco_cmd
= { .flags
= 0 };
1968 struct iwl_bt_uart_msg
*uart_msg
= &coex
->last_bt_uart_msg
;
1969 u8 last_traffic_load
;
1971 IWL_DEBUG_NOTIF(priv
, "BT Coex notification:\n");
1972 IWL_DEBUG_NOTIF(priv
, " status: %d\n", coex
->bt_status
);
1973 IWL_DEBUG_NOTIF(priv
, " traffic load: %d\n", coex
->bt_traffic_load
);
1974 IWL_DEBUG_NOTIF(priv
, " CI compliance: %d\n",
1975 coex
->bt_ci_compliance
);
1976 iwlagn_print_uartmsg(priv
, uart_msg
);
1978 last_traffic_load
= priv
->notif_bt_traffic_load
;
1979 priv
->notif_bt_traffic_load
= coex
->bt_traffic_load
;
1980 if (priv
->iw_mode
!= NL80211_IFTYPE_ADHOC
) {
1981 if (priv
->bt_status
!= coex
->bt_status
||
1982 last_traffic_load
!= coex
->bt_traffic_load
) {
1983 if (coex
->bt_status
) {
1985 if (!priv
->bt_ch_announce
)
1986 priv
->bt_traffic_load
=
1987 IWL_BT_COEX_TRAFFIC_LOAD_HIGH
;
1989 priv
->bt_traffic_load
=
1990 coex
->bt_traffic_load
;
1993 priv
->bt_traffic_load
=
1994 IWL_BT_COEX_TRAFFIC_LOAD_NONE
;
1996 priv
->bt_status
= coex
->bt_status
;
1997 queue_work(priv
->workqueue
,
1998 &priv
->bt_traffic_change_work
);
2000 if (priv
->bt_sco_active
!=
2001 (uart_msg
->frame3
& BT_UART_MSG_FRAME3SCOESCO_MSK
)) {
2002 priv
->bt_sco_active
= uart_msg
->frame3
&
2003 BT_UART_MSG_FRAME3SCOESCO_MSK
;
2004 if (priv
->bt_sco_active
)
2005 sco_cmd
.flags
|= IWLAGN_BT_SCO_ACTIVE
;
2006 iwl_send_cmd_pdu_async(priv
, REPLY_BT_COEX_SCO
,
2007 sizeof(sco_cmd
), &sco_cmd
, NULL
);
2011 iwlagn_set_kill_ack_msk(priv
, uart_msg
);
2013 /* FIXME: based on notification, adjust the prio_boost */
2015 spin_lock_irqsave(&priv
->lock
, flags
);
2016 priv
->bt_ci_compliance
= coex
->bt_ci_compliance
;
2017 spin_unlock_irqrestore(&priv
->lock
, flags
);
2020 void iwlagn_bt_rx_handler_setup(struct iwl_priv
*priv
)
2022 iwlagn_rx_handler_setup(priv
);
2023 priv
->rx_handlers
[REPLY_BT_COEX_PROFILE_NOTIF
] =
2024 iwlagn_bt_coex_profile_notif
;
2027 void iwlagn_bt_setup_deferred_work(struct iwl_priv
*priv
)
2029 iwlagn_setup_deferred_work(priv
);
2031 INIT_WORK(&priv
->bt_traffic_change_work
,
2032 iwlagn_bt_traffic_change_work
);
2035 void iwlagn_bt_cancel_deferred_work(struct iwl_priv
*priv
)
2037 cancel_work_sync(&priv
->bt_traffic_change_work
);