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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
50 struct iwl_ht_agg *agg,
51 struct iwl5000_tx_resp *tx_resp,
52 int txq_id, u16 start_idx)
53 {
54 u16 status;
55 struct agg_tx_status *frame_status = &tx_resp->status;
56 struct ieee80211_tx_info *info = NULL;
57 struct ieee80211_hdr *hdr = NULL;
58 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
59 int i, sh, idx;
60 u16 seq;
61
62 if (agg->wait_for_ba)
63 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
64
65 agg->frame_count = tx_resp->frame_count;
66 agg->start_idx = start_idx;
67 agg->rate_n_flags = rate_n_flags;
68 agg->bitmap = 0;
69
70 /* # frames attempted by Tx command */
71 if (agg->frame_count == 1) {
72 /* Only one frame was attempted; no block-ack will arrive */
73 status = le16_to_cpu(frame_status[0].status);
74 idx = start_idx;
75
76 /* FIXME: code repetition */
77 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
78 agg->frame_count, agg->start_idx, idx);
79
80 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb);
81 info->status.rates[0].count = tx_resp->failure_frame + 1;
82 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
83 info->flags |= iwl_tx_status_to_mac80211(status);
84 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
85
86 /* FIXME: code repetition end */
87
88 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
89 status & 0xff, tx_resp->failure_frame);
90 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
91
92 agg->wait_for_ba = 0;
93 } else {
94 /* Two or more frames were attempted; expect block-ack */
95 u64 bitmap = 0;
96
97 /*
98 * Start is the lowest frame sent. It may not be the first
99 * frame in the batch; we figure this out dynamically during
100 * the following loop.
101 */
102 int start = agg->start_idx;
103
104 /* Construct bit-map of pending frames within Tx window */
105 for (i = 0; i < agg->frame_count; i++) {
106 u16 sc;
107 status = le16_to_cpu(frame_status[i].status);
108 seq = le16_to_cpu(frame_status[i].sequence);
109 idx = SEQ_TO_INDEX(seq);
110 txq_id = SEQ_TO_QUEUE(seq);
111
112 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
113 AGG_TX_STATE_ABORT_MSK))
114 continue;
115
116 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
117 agg->frame_count, txq_id, idx);
118
119 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
120 if (!hdr) {
121 IWL_ERR(priv,
122 "BUG_ON idx doesn't point to valid skb"
123 " idx=%d, txq_id=%d\n", idx, txq_id);
124 return -1;
125 }
126
127 sc = le16_to_cpu(hdr->seq_ctrl);
128 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
129 IWL_ERR(priv,
130 "BUG_ON idx doesn't match seq control"
131 " idx=%d, seq_idx=%d, seq=%d\n",
132 idx, SEQ_TO_SN(sc),
133 hdr->seq_ctrl);
134 return -1;
135 }
136
137 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
138 i, idx, SEQ_TO_SN(sc));
139
140 /*
141 * sh -> how many frames ahead of the starting frame is
142 * the current one?
143 *
144 * Note that all frames sent in the batch must be in a
145 * 64-frame window, so this number should be in [0,63].
146 * If outside of this window, then we've found a new
147 * "first" frame in the batch and need to change start.
148 */
149 sh = idx - start;
150
151 /*
152 * If >= 64, out of window. start must be at the front
153 * of the circular buffer, idx must be near the end of
154 * the buffer, and idx is the new "first" frame. Shift
155 * the indices around.
156 */
157 if (sh >= 64) {
158 /* Shift bitmap by start - idx, wrapped */
159 sh = 0x100 - idx + start;
160 bitmap = bitmap << sh;
161 /* Now idx is the new start so sh = 0 */
162 sh = 0;
163 start = idx;
164 /*
165 * If <= -64 then wraps the 256-pkt circular buffer
166 * (e.g., start = 255 and idx = 0, sh should be 1)
167 */
168 } else if (sh <= -64) {
169 sh = 0x100 - start + idx;
170 /*
171 * If < 0 but > -64, out of window. idx is before start
172 * but not wrapped. Shift the indices around.
173 */
174 } else if (sh < 0) {
175 /* Shift by how far start is ahead of idx */
176 sh = start - idx;
177 bitmap = bitmap << sh;
178 /* Now idx is the new start so sh = 0 */
179 start = idx;
180 sh = 0;
181 }
182 /* Sequence number start + sh was sent in this batch */
183 bitmap |= 1ULL << sh;
184 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
185 start, (unsigned long long)bitmap);
186 }
187
188 /*
189 * Store the bitmap and possibly the new start, if we wrapped
190 * the buffer above
191 */
192 agg->bitmap = bitmap;
193 agg->start_idx = start;
194 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
195 agg->frame_count, agg->start_idx,
196 (unsigned long long)agg->bitmap);
197
198 if (bitmap)
199 agg->wait_for_ba = 1;
200 }
201 return 0;
202 }
203
204 void iwl_check_abort_status(struct iwl_priv *priv,
205 u8 frame_count, u32 status)
206 {
207 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
208 IWL_ERR(priv, "TODO: Implement Tx flush command!!!\n");
209 }
210 }
211
212 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
213 struct iwl_rx_mem_buffer *rxb)
214 {
215 struct iwl_rx_packet *pkt = rxb_addr(rxb);
216 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
217 int txq_id = SEQ_TO_QUEUE(sequence);
218 int index = SEQ_TO_INDEX(sequence);
219 struct iwl_tx_queue *txq = &priv->txq[txq_id];
220 struct ieee80211_tx_info *info;
221 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
222 u32 status = le16_to_cpu(tx_resp->status.status);
223 int tid;
224 int sta_id;
225 int freed;
226 unsigned long flags;
227
228 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
229 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
230 "is out of range [0-%d] %d %d\n", txq_id,
231 index, txq->q.n_bd, txq->q.write_ptr,
232 txq->q.read_ptr);
233 return;
234 }
235
236 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
237 memset(&info->status, 0, sizeof(info->status));
238
239 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
240 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
241
242 spin_lock_irqsave(&priv->sta_lock, flags);
243 if (txq->sched_retry) {
244 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
245 struct iwl_ht_agg *agg;
246
247 agg = &priv->stations[sta_id].tid[tid].agg;
248
249 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
250
251 /* check if BAR is needed */
252 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
253 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
254
255 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
256 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
257 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
258 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
259 scd_ssn , index, txq_id, txq->swq_id);
260
261 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
262 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
263
264 if (priv->mac80211_registered &&
265 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
266 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
267 if (agg->state == IWL_AGG_OFF)
268 iwl_wake_queue(priv, txq_id);
269 else
270 iwl_wake_queue(priv, txq->swq_id);
271 }
272 }
273 } else {
274 BUG_ON(txq_id != txq->swq_id);
275
276 info->status.rates[0].count = tx_resp->failure_frame + 1;
277 info->flags |= iwl_tx_status_to_mac80211(status);
278 iwlagn_hwrate_to_tx_control(priv,
279 le32_to_cpu(tx_resp->rate_n_flags),
280 info);
281
282 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
283 "0x%x retries %d\n",
284 txq_id,
285 iwl_get_tx_fail_reason(status), status,
286 le32_to_cpu(tx_resp->rate_n_flags),
287 tx_resp->failure_frame);
288
289 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
290 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
291
292 if (priv->mac80211_registered &&
293 (iwl_queue_space(&txq->q) > txq->q.low_mark))
294 iwl_wake_queue(priv, txq_id);
295 }
296
297 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
298
299 iwl_check_abort_status(priv, tx_resp->frame_count, status);
300 spin_unlock_irqrestore(&priv->sta_lock, flags);
301 }
302
303 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
304 {
305 /* init calibration handlers */
306 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
307 iwlagn_rx_calib_result;
308 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
309 iwlagn_rx_calib_complete;
310 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
311 }
312
313 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
314 {
315 /* in agn, the tx power calibration is done in uCode */
316 priv->disable_tx_power_cal = 1;
317 }
318
319 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
320 {
321 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
322 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
323 }
324
325 int iwlagn_send_tx_power(struct iwl_priv *priv)
326 {
327 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
328 u8 tx_ant_cfg_cmd;
329
330 /* half dBm need to multiply */
331 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
332
333 if (priv->tx_power_lmt_in_half_dbm &&
334 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
335 /*
336 * For the newer devices which using enhanced/extend tx power
337 * table in EEPROM, the format is in half dBm. driver need to
338 * convert to dBm format before report to mac80211.
339 * By doing so, there is a possibility of 1/2 dBm resolution
340 * lost. driver will perform "round-up" operation before
341 * reporting, but it will cause 1/2 dBm tx power over the
342 * regulatory limit. Perform the checking here, if the
343 * "tx_power_user_lmt" is higher than EEPROM value (in
344 * half-dBm format), lower the tx power based on EEPROM
345 */
346 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
347 }
348 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
349 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
350
351 if (IWL_UCODE_API(priv->ucode_ver) == 1)
352 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
353 else
354 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
355
356 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
357 sizeof(tx_power_cmd), &tx_power_cmd,
358 NULL);
359 }
360
361 void iwlagn_temperature(struct iwl_priv *priv)
362 {
363 /* store temperature from statistics (in Celsius) */
364 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
365 iwl_tt_handler(priv);
366 }
367
368 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
369 {
370 struct iwl_eeprom_calib_hdr {
371 u8 version;
372 u8 pa_type;
373 u16 voltage;
374 } *hdr;
375
376 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
377 EEPROM_CALIB_ALL);
378 return hdr->version;
379
380 }
381
382 /*
383 * EEPROM
384 */
385 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
386 {
387 u16 offset = 0;
388
389 if ((address & INDIRECT_ADDRESS) == 0)
390 return address;
391
392 switch (address & INDIRECT_TYPE_MSK) {
393 case INDIRECT_HOST:
394 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
395 break;
396 case INDIRECT_GENERAL:
397 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
398 break;
399 case INDIRECT_REGULATORY:
400 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
401 break;
402 case INDIRECT_CALIBRATION:
403 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
404 break;
405 case INDIRECT_PROCESS_ADJST:
406 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
407 break;
408 case INDIRECT_OTHERS:
409 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
410 break;
411 default:
412 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
413 address & INDIRECT_TYPE_MSK);
414 break;
415 }
416
417 /* translate the offset from words to byte */
418 return (address & ADDRESS_MSK) + (offset << 1);
419 }
420
421 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
422 size_t offset)
423 {
424 u32 address = eeprom_indirect_address(priv, offset);
425 BUG_ON(address >= priv->cfg->eeprom_size);
426 return &priv->eeprom[address];
427 }
428
429 struct iwl_mod_params iwlagn_mod_params = {
430 .amsdu_size_8K = 1,
431 .restart_fw = 1,
432 /* the rest are 0 by default */
433 };
434
435 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
436 {
437 unsigned long flags;
438 int i;
439 spin_lock_irqsave(&rxq->lock, flags);
440 INIT_LIST_HEAD(&rxq->rx_free);
441 INIT_LIST_HEAD(&rxq->rx_used);
442 /* Fill the rx_used queue with _all_ of the Rx buffers */
443 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
444 /* In the reset function, these buffers may have been allocated
445 * to an SKB, so we need to unmap and free potential storage */
446 if (rxq->pool[i].page != NULL) {
447 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
448 PAGE_SIZE << priv->hw_params.rx_page_order,
449 PCI_DMA_FROMDEVICE);
450 __iwl_free_pages(priv, rxq->pool[i].page);
451 rxq->pool[i].page = NULL;
452 }
453 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
454 }
455
456 for (i = 0; i < RX_QUEUE_SIZE; i++)
457 rxq->queue[i] = NULL;
458
459 /* Set us so that we have processed and used all buffers, but have
460 * not restocked the Rx queue with fresh buffers */
461 rxq->read = rxq->write = 0;
462 rxq->write_actual = 0;
463 rxq->free_count = 0;
464 spin_unlock_irqrestore(&rxq->lock, flags);
465 }
466
467 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
468 {
469 u32 rb_size;
470 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
471 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
472
473 if (!priv->cfg->use_isr_legacy)
474 rb_timeout = RX_RB_TIMEOUT;
475
476 if (priv->cfg->mod_params->amsdu_size_8K)
477 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
478 else
479 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
480
481 /* Stop Rx DMA */
482 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
483
484 /* Reset driver's Rx queue write index */
485 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
486
487 /* Tell device where to find RBD circular buffer in DRAM */
488 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
489 (u32)(rxq->bd_dma >> 8));
490
491 /* Tell device where in DRAM to update its Rx status */
492 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
493 rxq->rb_stts_dma >> 4);
494
495 /* Enable Rx DMA
496 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
497 * the credit mechanism in 5000 HW RX FIFO
498 * Direct rx interrupts to hosts
499 * Rx buffer size 4 or 8k
500 * RB timeout 0x10
501 * 256 RBDs
502 */
503 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
504 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
505 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
506 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
507 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
508 rb_size|
509 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
510 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
511
512 /* Set interrupt coalescing timer to default (2048 usecs) */
513 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
514
515 return 0;
516 }
517
518 int iwlagn_hw_nic_init(struct iwl_priv *priv)
519 {
520 unsigned long flags;
521 struct iwl_rx_queue *rxq = &priv->rxq;
522 int ret;
523
524 /* nic_init */
525 spin_lock_irqsave(&priv->lock, flags);
526 priv->cfg->ops->lib->apm_ops.init(priv);
527
528 /* Set interrupt coalescing calibration timer to default (512 usecs) */
529 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
530
531 spin_unlock_irqrestore(&priv->lock, flags);
532
533 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
534
535 priv->cfg->ops->lib->apm_ops.config(priv);
536
537 /* Allocate the RX queue, or reset if it is already allocated */
538 if (!rxq->bd) {
539 ret = iwl_rx_queue_alloc(priv);
540 if (ret) {
541 IWL_ERR(priv, "Unable to initialize Rx queue\n");
542 return -ENOMEM;
543 }
544 } else
545 iwlagn_rx_queue_reset(priv, rxq);
546
547 iwlagn_rx_replenish(priv);
548
549 iwlagn_rx_init(priv, rxq);
550
551 spin_lock_irqsave(&priv->lock, flags);
552
553 rxq->need_update = 1;
554 iwl_rx_queue_update_write_ptr(priv, rxq);
555
556 spin_unlock_irqrestore(&priv->lock, flags);
557
558 /* Allocate or reset and init all Tx and Command queues */
559 if (!priv->txq) {
560 ret = iwlagn_txq_ctx_alloc(priv);
561 if (ret)
562 return ret;
563 } else
564 iwlagn_txq_ctx_reset(priv);
565
566 set_bit(STATUS_INIT, &priv->status);
567
568 return 0;
569 }
570
571 /**
572 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
573 */
574 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
575 dma_addr_t dma_addr)
576 {
577 return cpu_to_le32((u32)(dma_addr >> 8));
578 }
579
580 /**
581 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
582 *
583 * If there are slots in the RX queue that need to be restocked,
584 * and we have free pre-allocated buffers, fill the ranks as much
585 * as we can, pulling from rx_free.
586 *
587 * This moves the 'write' index forward to catch up with 'processed', and
588 * also updates the memory address in the firmware to reference the new
589 * target buffer.
590 */
591 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
592 {
593 struct iwl_rx_queue *rxq = &priv->rxq;
594 struct list_head *element;
595 struct iwl_rx_mem_buffer *rxb;
596 unsigned long flags;
597
598 spin_lock_irqsave(&rxq->lock, flags);
599 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
600 /* The overwritten rxb must be a used one */
601 rxb = rxq->queue[rxq->write];
602 BUG_ON(rxb && rxb->page);
603
604 /* Get next free Rx buffer, remove from free list */
605 element = rxq->rx_free.next;
606 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
607 list_del(element);
608
609 /* Point to Rx buffer via next RBD in circular buffer */
610 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
611 rxb->page_dma);
612 rxq->queue[rxq->write] = rxb;
613 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
614 rxq->free_count--;
615 }
616 spin_unlock_irqrestore(&rxq->lock, flags);
617 /* If the pre-allocated buffer pool is dropping low, schedule to
618 * refill it */
619 if (rxq->free_count <= RX_LOW_WATERMARK)
620 queue_work(priv->workqueue, &priv->rx_replenish);
621
622
623 /* If we've added more space for the firmware to place data, tell it.
624 * Increment device's write pointer in multiples of 8. */
625 if (rxq->write_actual != (rxq->write & ~0x7)) {
626 spin_lock_irqsave(&rxq->lock, flags);
627 rxq->need_update = 1;
628 spin_unlock_irqrestore(&rxq->lock, flags);
629 iwl_rx_queue_update_write_ptr(priv, rxq);
630 }
631 }
632
633 /**
634 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
635 *
636 * When moving to rx_free an SKB is allocated for the slot.
637 *
638 * Also restock the Rx queue via iwl_rx_queue_restock.
639 * This is called as a scheduled work item (except for during initialization)
640 */
641 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
642 {
643 struct iwl_rx_queue *rxq = &priv->rxq;
644 struct list_head *element;
645 struct iwl_rx_mem_buffer *rxb;
646 struct page *page;
647 unsigned long flags;
648 gfp_t gfp_mask = priority;
649
650 while (1) {
651 spin_lock_irqsave(&rxq->lock, flags);
652 if (list_empty(&rxq->rx_used)) {
653 spin_unlock_irqrestore(&rxq->lock, flags);
654 return;
655 }
656 spin_unlock_irqrestore(&rxq->lock, flags);
657
658 if (rxq->free_count > RX_LOW_WATERMARK)
659 gfp_mask |= __GFP_NOWARN;
660
661 if (priv->hw_params.rx_page_order > 0)
662 gfp_mask |= __GFP_COMP;
663
664 /* Alloc a new receive buffer */
665 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
666 if (!page) {
667 if (net_ratelimit())
668 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
669 "order: %d\n",
670 priv->hw_params.rx_page_order);
671
672 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
673 net_ratelimit())
674 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
675 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
676 rxq->free_count);
677 /* We don't reschedule replenish work here -- we will
678 * call the restock method and if it still needs
679 * more buffers it will schedule replenish */
680 return;
681 }
682
683 spin_lock_irqsave(&rxq->lock, flags);
684
685 if (list_empty(&rxq->rx_used)) {
686 spin_unlock_irqrestore(&rxq->lock, flags);
687 __free_pages(page, priv->hw_params.rx_page_order);
688 return;
689 }
690 element = rxq->rx_used.next;
691 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
692 list_del(element);
693
694 spin_unlock_irqrestore(&rxq->lock, flags);
695
696 BUG_ON(rxb->page);
697 rxb->page = page;
698 /* Get physical address of the RB */
699 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
700 PAGE_SIZE << priv->hw_params.rx_page_order,
701 PCI_DMA_FROMDEVICE);
702 /* dma address must be no more than 36 bits */
703 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
704 /* and also 256 byte aligned! */
705 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
706
707 spin_lock_irqsave(&rxq->lock, flags);
708
709 list_add_tail(&rxb->list, &rxq->rx_free);
710 rxq->free_count++;
711 priv->alloc_rxb_page++;
712
713 spin_unlock_irqrestore(&rxq->lock, flags);
714 }
715 }
716
717 void iwlagn_rx_replenish(struct iwl_priv *priv)
718 {
719 unsigned long flags;
720
721 iwlagn_rx_allocate(priv, GFP_KERNEL);
722
723 spin_lock_irqsave(&priv->lock, flags);
724 iwlagn_rx_queue_restock(priv);
725 spin_unlock_irqrestore(&priv->lock, flags);
726 }
727
728 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
729 {
730 iwlagn_rx_allocate(priv, GFP_ATOMIC);
731
732 iwlagn_rx_queue_restock(priv);
733 }
734
735 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
736 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
737 * This free routine walks the list of POOL entries and if SKB is set to
738 * non NULL it is unmapped and freed
739 */
740 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
741 {
742 int i;
743 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
744 if (rxq->pool[i].page != NULL) {
745 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
746 PAGE_SIZE << priv->hw_params.rx_page_order,
747 PCI_DMA_FROMDEVICE);
748 __iwl_free_pages(priv, rxq->pool[i].page);
749 rxq->pool[i].page = NULL;
750 }
751 }
752
753 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
754 rxq->bd_dma);
755 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
756 rxq->rb_stts, rxq->rb_stts_dma);
757 rxq->bd = NULL;
758 rxq->rb_stts = NULL;
759 }
760
761 int iwlagn_rxq_stop(struct iwl_priv *priv)
762 {
763
764 /* stop Rx DMA */
765 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
766 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
767 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
768
769 return 0;
770 }
771
772 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
773 {
774 int idx = 0;
775 int band_offset = 0;
776
777 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
778 if (rate_n_flags & RATE_MCS_HT_MSK) {
779 idx = (rate_n_flags & 0xff);
780 return idx;
781 /* Legacy rate format, search for match in table */
782 } else {
783 if (band == IEEE80211_BAND_5GHZ)
784 band_offset = IWL_FIRST_OFDM_RATE;
785 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
786 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
787 return idx - band_offset;
788 }
789
790 return -1;
791 }
792
793 /* Calc max signal level (dBm) among 3 possible receivers */
794 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
795 struct iwl_rx_phy_res *rx_resp)
796 {
797 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
798 }
799
800 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
801 {
802 u32 decrypt_out = 0;
803
804 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
805 RX_RES_STATUS_STATION_FOUND)
806 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
807 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
808
809 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
810
811 /* packet was not encrypted */
812 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
813 RX_RES_STATUS_SEC_TYPE_NONE)
814 return decrypt_out;
815
816 /* packet was encrypted with unknown alg */
817 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
818 RX_RES_STATUS_SEC_TYPE_ERR)
819 return decrypt_out;
820
821 /* decryption was not done in HW */
822 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
823 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
824 return decrypt_out;
825
826 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
827
828 case RX_RES_STATUS_SEC_TYPE_CCMP:
829 /* alg is CCM: check MIC only */
830 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
831 /* Bad MIC */
832 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
833 else
834 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
835
836 break;
837
838 case RX_RES_STATUS_SEC_TYPE_TKIP:
839 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
840 /* Bad TTAK */
841 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
842 break;
843 }
844 /* fall through if TTAK OK */
845 default:
846 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
847 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
848 else
849 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
850 break;
851 }
852
853 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
854 decrypt_in, decrypt_out);
855
856 return decrypt_out;
857 }
858
859 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
860 struct ieee80211_hdr *hdr,
861 u16 len,
862 u32 ampdu_status,
863 struct iwl_rx_mem_buffer *rxb,
864 struct ieee80211_rx_status *stats)
865 {
866 struct sk_buff *skb;
867 __le16 fc = hdr->frame_control;
868
869 /* We only process data packets if the interface is open */
870 if (unlikely(!priv->is_open)) {
871 IWL_DEBUG_DROP_LIMIT(priv,
872 "Dropping packet while interface is not open.\n");
873 return;
874 }
875
876 /* In case of HW accelerated crypto and bad decryption, drop */
877 if (!priv->cfg->mod_params->sw_crypto &&
878 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
879 return;
880
881 skb = dev_alloc_skb(128);
882 if (!skb) {
883 IWL_ERR(priv, "dev_alloc_skb failed\n");
884 return;
885 }
886
887 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
888
889 iwl_update_stats(priv, false, fc, len);
890 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
891
892 ieee80211_rx(priv->hw, skb);
893 priv->alloc_rxb_page--;
894 rxb->page = NULL;
895 }
896
897 /* Called for REPLY_RX (legacy ABG frames), or
898 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
899 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
900 struct iwl_rx_mem_buffer *rxb)
901 {
902 struct ieee80211_hdr *header;
903 struct ieee80211_rx_status rx_status;
904 struct iwl_rx_packet *pkt = rxb_addr(rxb);
905 struct iwl_rx_phy_res *phy_res;
906 __le32 rx_pkt_status;
907 struct iwl_rx_mpdu_res_start *amsdu;
908 u32 len;
909 u32 ampdu_status;
910 u32 rate_n_flags;
911
912 /**
913 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
914 * REPLY_RX: physical layer info is in this buffer
915 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
916 * command and cached in priv->last_phy_res
917 *
918 * Here we set up local variables depending on which command is
919 * received.
920 */
921 if (pkt->hdr.cmd == REPLY_RX) {
922 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
923 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
924 + phy_res->cfg_phy_cnt);
925
926 len = le16_to_cpu(phy_res->byte_count);
927 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
928 phy_res->cfg_phy_cnt + len);
929 ampdu_status = le32_to_cpu(rx_pkt_status);
930 } else {
931 if (!priv->_agn.last_phy_res_valid) {
932 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
933 return;
934 }
935 phy_res = &priv->_agn.last_phy_res;
936 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
937 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
938 len = le16_to_cpu(amsdu->byte_count);
939 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
940 ampdu_status = iwlagn_translate_rx_status(priv,
941 le32_to_cpu(rx_pkt_status));
942 }
943
944 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
945 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
946 phy_res->cfg_phy_cnt);
947 return;
948 }
949
950 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
951 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
952 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
953 le32_to_cpu(rx_pkt_status));
954 return;
955 }
956
957 /* This will be used in several places later */
958 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
959
960 /* rx_status carries information about the packet to mac80211 */
961 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
962 rx_status.freq =
963 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
964 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
965 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
966 rx_status.rate_idx =
967 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
968 rx_status.flag = 0;
969
970 /* TSF isn't reliable. In order to allow smooth user experience,
971 * this W/A doesn't propagate it to the mac80211 */
972 /*rx_status.flag |= RX_FLAG_TSFT;*/
973
974 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
975
976 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
977 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
978
979 iwl_dbg_log_rx_data_frame(priv, len, header);
980 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
981 rx_status.signal, (unsigned long long)rx_status.mactime);
982
983 /*
984 * "antenna number"
985 *
986 * It seems that the antenna field in the phy flags value
987 * is actually a bit field. This is undefined by radiotap,
988 * it wants an actual antenna number but I always get "7"
989 * for most legacy frames I receive indicating that the
990 * same frame was received on all three RX chains.
991 *
992 * I think this field should be removed in favor of a
993 * new 802.11n radiotap field "RX chains" that is defined
994 * as a bitmask.
995 */
996 rx_status.antenna =
997 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
998 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
999
1000 /* set the preamble flag if appropriate */
1001 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1002 rx_status.flag |= RX_FLAG_SHORTPRE;
1003
1004 /* Set up the HT phy flags */
1005 if (rate_n_flags & RATE_MCS_HT_MSK)
1006 rx_status.flag |= RX_FLAG_HT;
1007 if (rate_n_flags & RATE_MCS_HT40_MSK)
1008 rx_status.flag |= RX_FLAG_40MHZ;
1009 if (rate_n_flags & RATE_MCS_SGI_MSK)
1010 rx_status.flag |= RX_FLAG_SHORT_GI;
1011
1012 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1013 rxb, &rx_status);
1014 }
1015
1016 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1017 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1018 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1019 struct iwl_rx_mem_buffer *rxb)
1020 {
1021 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1022 priv->_agn.last_phy_res_valid = true;
1023 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1024 sizeof(struct iwl_rx_phy_res));
1025 }
1026
1027 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1028 struct ieee80211_vif *vif,
1029 enum ieee80211_band band,
1030 struct iwl_scan_channel *scan_ch)
1031 {
1032 const struct ieee80211_supported_band *sband;
1033 u16 passive_dwell = 0;
1034 u16 active_dwell = 0;
1035 int added = 0;
1036 u16 channel = 0;
1037
1038 sband = iwl_get_hw_mode(priv, band);
1039 if (!sband) {
1040 IWL_ERR(priv, "invalid band\n");
1041 return added;
1042 }
1043
1044 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1045 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1046
1047 if (passive_dwell <= active_dwell)
1048 passive_dwell = active_dwell + 1;
1049
1050 channel = iwl_get_single_channel_number(priv, band);
1051 if (channel) {
1052 scan_ch->channel = cpu_to_le16(channel);
1053 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1054 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1055 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1056 /* Set txpower levels to defaults */
1057 scan_ch->dsp_atten = 110;
1058 if (band == IEEE80211_BAND_5GHZ)
1059 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1060 else
1061 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1062 added++;
1063 } else
1064 IWL_ERR(priv, "no valid channel found\n");
1065 return added;
1066 }
1067
1068 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1069 struct ieee80211_vif *vif,
1070 enum ieee80211_band band,
1071 u8 is_active, u8 n_probes,
1072 struct iwl_scan_channel *scan_ch)
1073 {
1074 struct ieee80211_channel *chan;
1075 const struct ieee80211_supported_band *sband;
1076 const struct iwl_channel_info *ch_info;
1077 u16 passive_dwell = 0;
1078 u16 active_dwell = 0;
1079 int added, i;
1080 u16 channel;
1081
1082 sband = iwl_get_hw_mode(priv, band);
1083 if (!sband)
1084 return 0;
1085
1086 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1087 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1088
1089 if (passive_dwell <= active_dwell)
1090 passive_dwell = active_dwell + 1;
1091
1092 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1093 chan = priv->scan_request->channels[i];
1094
1095 if (chan->band != band)
1096 continue;
1097
1098 channel = ieee80211_frequency_to_channel(chan->center_freq);
1099 scan_ch->channel = cpu_to_le16(channel);
1100
1101 ch_info = iwl_get_channel_info(priv, band, channel);
1102 if (!is_channel_valid(ch_info)) {
1103 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1104 channel);
1105 continue;
1106 }
1107
1108 if (!is_active || is_channel_passive(ch_info) ||
1109 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1110 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1111 else
1112 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1113
1114 if (n_probes)
1115 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1116
1117 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1118 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1119
1120 /* Set txpower levels to defaults */
1121 scan_ch->dsp_atten = 110;
1122
1123 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1124 * power level:
1125 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1126 */
1127 if (band == IEEE80211_BAND_5GHZ)
1128 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1129 else
1130 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1131
1132 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1133 channel, le32_to_cpu(scan_ch->type),
1134 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1135 "ACTIVE" : "PASSIVE",
1136 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1137 active_dwell : passive_dwell);
1138
1139 scan_ch++;
1140 added++;
1141 }
1142
1143 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1144 return added;
1145 }
1146
1147 void iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1148 {
1149 struct iwl_host_cmd cmd = {
1150 .id = REPLY_SCAN_CMD,
1151 .len = sizeof(struct iwl_scan_cmd),
1152 .flags = CMD_SIZE_HUGE,
1153 };
1154 struct iwl_scan_cmd *scan;
1155 struct ieee80211_conf *conf = NULL;
1156 u32 rate_flags = 0;
1157 u16 cmd_len;
1158 u16 rx_chain = 0;
1159 enum ieee80211_band band;
1160 u8 n_probes = 0;
1161 u8 rx_ant = priv->hw_params.valid_rx_ant;
1162 u8 rate;
1163 bool is_active = false;
1164 int chan_mod;
1165 u8 active_chains;
1166 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1167
1168 conf = ieee80211_get_hw_conf(priv->hw);
1169
1170 cancel_delayed_work(&priv->scan_check);
1171
1172 if (!iwl_is_ready(priv)) {
1173 IWL_WARN(priv, "request scan called when driver not ready.\n");
1174 goto done;
1175 }
1176
1177 /* Make sure the scan wasn't canceled before this queued work
1178 * was given the chance to run... */
1179 if (!test_bit(STATUS_SCANNING, &priv->status))
1180 goto done;
1181
1182 /* This should never be called or scheduled if there is currently
1183 * a scan active in the hardware. */
1184 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
1185 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests in parallel. "
1186 "Ignoring second request.\n");
1187 goto done;
1188 }
1189
1190 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1191 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
1192 goto done;
1193 }
1194
1195 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1196 IWL_DEBUG_HC(priv, "Scan request while abort pending. Queuing.\n");
1197 goto done;
1198 }
1199
1200 if (iwl_is_rfkill(priv)) {
1201 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
1202 goto done;
1203 }
1204
1205 if (!test_bit(STATUS_READY, &priv->status)) {
1206 IWL_DEBUG_HC(priv, "Scan request while uninitialized. Queuing.\n");
1207 goto done;
1208 }
1209
1210 if (!priv->scan_cmd) {
1211 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1212 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1213 if (!priv->scan_cmd) {
1214 IWL_DEBUG_SCAN(priv,
1215 "fail to allocate memory for scan\n");
1216 goto done;
1217 }
1218 }
1219 scan = priv->scan_cmd;
1220 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1221
1222 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1223 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1224
1225 if (iwl_is_associated(priv)) {
1226 u16 interval = 0;
1227 u32 extra;
1228 u32 suspend_time = 100;
1229 u32 scan_suspend_time = 100;
1230 unsigned long flags;
1231
1232 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1233 spin_lock_irqsave(&priv->lock, flags);
1234 interval = vif ? vif->bss_conf.beacon_int : 0;
1235 spin_unlock_irqrestore(&priv->lock, flags);
1236
1237 scan->suspend_time = 0;
1238 scan->max_out_time = cpu_to_le32(200 * 1024);
1239 if (!interval)
1240 interval = suspend_time;
1241
1242 extra = (suspend_time / interval) << 22;
1243 scan_suspend_time = (extra |
1244 ((suspend_time % interval) * 1024));
1245 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1246 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1247 scan_suspend_time, interval);
1248 }
1249
1250 if (priv->is_internal_short_scan) {
1251 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1252 } else if (priv->scan_request->n_ssids) {
1253 int i, p = 0;
1254 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1255 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1256 /* always does wildcard anyway */
1257 if (!priv->scan_request->ssids[i].ssid_len)
1258 continue;
1259 scan->direct_scan[p].id = WLAN_EID_SSID;
1260 scan->direct_scan[p].len =
1261 priv->scan_request->ssids[i].ssid_len;
1262 memcpy(scan->direct_scan[p].ssid,
1263 priv->scan_request->ssids[i].ssid,
1264 priv->scan_request->ssids[i].ssid_len);
1265 n_probes++;
1266 p++;
1267 }
1268 is_active = true;
1269 } else
1270 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1271
1272 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1273 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
1274 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1275
1276 switch (priv->scan_band) {
1277 case IEEE80211_BAND_2GHZ:
1278 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1279 chan_mod = le32_to_cpu(priv->active_rxon.flags & RXON_FLG_CHANNEL_MODE_MSK)
1280 >> RXON_FLG_CHANNEL_MODE_POS;
1281 if (chan_mod == CHANNEL_MODE_PURE_40) {
1282 rate = IWL_RATE_6M_PLCP;
1283 } else {
1284 rate = IWL_RATE_1M_PLCP;
1285 rate_flags = RATE_MCS_CCK_MSK;
1286 }
1287 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
1288 break;
1289 case IEEE80211_BAND_5GHZ:
1290 rate = IWL_RATE_6M_PLCP;
1291 /*
1292 * If active scanning is requested but a certain channel is
1293 * marked passive, we can do active scanning if we detect
1294 * transmissions.
1295 *
1296 * There is an issue with some firmware versions that triggers
1297 * a sysassert on a "good CRC threshold" of zero (== disabled),
1298 * on a radar channel even though this means that we should NOT
1299 * send probes.
1300 *
1301 * The "good CRC threshold" is the number of frames that we
1302 * need to receive during our dwell time on a channel before
1303 * sending out probes -- setting this to a huge value will
1304 * mean we never reach it, but at the same time work around
1305 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1306 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1307 */
1308 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1309 IWL_GOOD_CRC_TH_NEVER;
1310 break;
1311 default:
1312 IWL_WARN(priv, "Invalid scan band count\n");
1313 goto done;
1314 }
1315
1316 band = priv->scan_band;
1317
1318 if (priv->cfg->scan_rx_antennas[band])
1319 rx_ant = priv->cfg->scan_rx_antennas[band];
1320
1321 if (priv->cfg->scan_tx_antennas[band])
1322 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1323
1324 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1325 scan_tx_antennas);
1326 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1327 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1328
1329 /* In power save mode use one chain, otherwise use all chains */
1330 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1331 /* rx_ant has been set to all valid chains previously */
1332 active_chains = rx_ant &
1333 ((u8)(priv->chain_noise_data.active_chains));
1334 if (!active_chains)
1335 active_chains = rx_ant;
1336
1337 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1338 priv->chain_noise_data.active_chains);
1339
1340 rx_ant = first_antenna(active_chains);
1341 }
1342 /* MIMO is not used here, but value is required */
1343 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1344 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1345 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1346 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1347 scan->rx_chain = cpu_to_le16(rx_chain);
1348 if (!priv->is_internal_short_scan) {
1349 cmd_len = iwl_fill_probe_req(priv,
1350 (struct ieee80211_mgmt *)scan->data,
1351 vif->addr,
1352 priv->scan_request->ie,
1353 priv->scan_request->ie_len,
1354 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1355 } else {
1356 /* use bcast addr, will not be transmitted but must be valid */
1357 cmd_len = iwl_fill_probe_req(priv,
1358 (struct ieee80211_mgmt *)scan->data,
1359 iwl_bcast_addr, NULL, 0,
1360 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1361
1362 }
1363 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1364
1365 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1366 RXON_FILTER_BCON_AWARE_MSK);
1367
1368 if (priv->is_internal_short_scan) {
1369 scan->channel_count =
1370 iwl_get_single_channel_for_scan(priv, vif, band,
1371 (void *)&scan->data[le16_to_cpu(
1372 scan->tx_cmd.len)]);
1373 } else {
1374 scan->channel_count =
1375 iwl_get_channels_for_scan(priv, vif, band,
1376 is_active, n_probes,
1377 (void *)&scan->data[le16_to_cpu(
1378 scan->tx_cmd.len)]);
1379 }
1380 if (scan->channel_count == 0) {
1381 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1382 goto done;
1383 }
1384
1385 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1386 scan->channel_count * sizeof(struct iwl_scan_channel);
1387 cmd.data = scan;
1388 scan->len = cpu_to_le16(cmd.len);
1389
1390 set_bit(STATUS_SCAN_HW, &priv->status);
1391 if (iwl_send_cmd_sync(priv, &cmd))
1392 goto done;
1393
1394 queue_delayed_work(priv->workqueue, &priv->scan_check,
1395 IWL_SCAN_CHECK_WATCHDOG);
1396
1397 return;
1398
1399 done:
1400 /* Cannot perform scan. Make sure we clear scanning
1401 * bits from status so next scan request can be performed.
1402 * If we don't clear scanning status bit here all next scan
1403 * will fail
1404 */
1405 clear_bit(STATUS_SCAN_HW, &priv->status);
1406 clear_bit(STATUS_SCANNING, &priv->status);
1407 /* inform mac80211 scan aborted */
1408 queue_work(priv->workqueue, &priv->scan_completed);
1409 }
1410
1411 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1412 struct ieee80211_vif *vif, bool add)
1413 {
1414 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1415
1416 if (add)
1417 return iwl_add_bssid_station(priv, vif->bss_conf.bssid, true,
1418 &vif_priv->ibss_bssid_sta_id);
1419 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1420 vif->bss_conf.bssid);
1421 }
1422
1423 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1424 int sta_id, int tid, int freed)
1425 {
1426 WARN_ON(!spin_is_locked(&priv->sta_lock));
1427
1428 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1429 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1430 else {
1431 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1432 priv->stations[sta_id].tid[tid].tfds_in_queue,
1433 freed);
1434 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1435 }
1436 }
Linux kernel - Deliverables
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