1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
44 * mac80211 queues, ACs, hardware queues, FIFOs.
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
69 static const u8 tid_to_ac
[] = {
70 /* this matches the mac80211 numbers */
71 2, 3, 3, 2, 1, 1, 0, 0
74 static inline int get_ac_from_tid(u16 tid
)
76 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
77 return tid_to_ac
[tid
];
79 /* no support for TIDs 8-15 yet */
83 static inline int get_fifo_from_tid(struct iwl_rxon_context
*ctx
, u16 tid
)
85 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
86 return ctx
->ac_to_fifo
[tid_to_ac
[tid
]];
88 /* no support for TIDs 8-15 yet */
93 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
95 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
96 struct iwl_tx_queue
*txq
,
99 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
100 int write_ptr
= txq
->q
.write_ptr
;
101 int txq_id
= txq
->q
.id
;
104 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
107 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
109 if (txq_id
!= priv
->cmd_queue
) {
110 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
111 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
113 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
117 case TX_CMD_SEC_TKIP
:
121 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
126 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
128 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
130 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
132 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
135 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
136 struct iwl_tx_queue
*txq
)
138 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
139 int txq_id
= txq
->q
.id
;
140 int read_ptr
= txq
->q
.read_ptr
;
144 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
146 if (txq_id
!= priv
->cmd_queue
)
147 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
149 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
150 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
152 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
154 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
157 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv
*priv
, u16 ra_tid
,
164 scd_q2ratid
= ra_tid
& IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
166 tbl_dw_addr
= priv
->scd_base_addr
+
167 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id
);
169 tbl_dw
= iwl_read_targ_mem(priv
, tbl_dw_addr
);
172 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
174 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
176 iwl_write_targ_mem(priv
, tbl_dw_addr
, tbl_dw
);
181 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv
*priv
, u16 txq_id
)
183 /* Simply stop the queue, but don't change any configuration;
184 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
186 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id
),
187 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
188 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
191 void iwlagn_set_wr_ptrs(struct iwl_priv
*priv
,
192 int txq_id
, u32 index
)
194 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
195 (index
& 0xff) | (txq_id
<< 8));
196 iwl_write_prph(priv
, IWLAGN_SCD_QUEUE_RDPTR(txq_id
), index
);
199 void iwlagn_tx_queue_set_status(struct iwl_priv
*priv
,
200 struct iwl_tx_queue
*txq
,
201 int tx_fifo_id
, int scd_retry
)
203 int txq_id
= txq
->q
.id
;
204 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
) ? 1 : 0;
206 iwl_write_prph(priv
, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id
),
207 (active
<< IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
208 (tx_fifo_id
<< IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF
) |
209 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL
) |
210 IWLAGN_SCD_QUEUE_STTS_REG_MSK
);
212 txq
->sched_retry
= scd_retry
;
214 IWL_DEBUG_INFO(priv
, "%s %s Queue %d on FIFO %d\n",
215 active
? "Activate" : "Deactivate",
216 scd_retry
? "BA" : "AC/CMD", txq_id
, tx_fifo_id
);
219 int iwlagn_txq_agg_enable(struct iwl_priv
*priv
, int txq_id
,
220 int tx_fifo
, int sta_id
, int tid
, u16 ssn_idx
)
226 if ((IWLAGN_FIRST_AMPDU_QUEUE
> txq_id
) ||
227 (IWLAGN_FIRST_AMPDU_QUEUE
+
228 priv
->cfg
->base_params
->num_of_ampdu_queues
<= txq_id
)) {
230 "queue number out of range: %d, must be %d to %d\n",
231 txq_id
, IWLAGN_FIRST_AMPDU_QUEUE
,
232 IWLAGN_FIRST_AMPDU_QUEUE
+
233 priv
->cfg
->base_params
->num_of_ampdu_queues
- 1);
237 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
239 /* Modify device's station table to Tx this TID */
240 ret
= iwl_sta_tx_modify_enable_tid(priv
, sta_id
, tid
);
244 spin_lock_irqsave(&priv
->lock
, flags
);
246 /* Stop this Tx queue before configuring it */
247 iwlagn_tx_queue_stop_scheduler(priv
, txq_id
);
249 /* Map receiver-address / traffic-ID to this queue */
250 iwlagn_tx_queue_set_q2ratid(priv
, ra_tid
, txq_id
);
252 /* Set this queue as a chain-building queue */
253 iwl_set_bits_prph(priv
, IWLAGN_SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
255 /* enable aggregations for the queue */
256 iwl_set_bits_prph(priv
, IWLAGN_SCD_AGGR_SEL
, (1<<txq_id
));
258 /* Place first TFD at index corresponding to start sequence number.
259 * Assumes that ssn_idx is valid (!= 0xFFF) */
260 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
261 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
262 iwlagn_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
264 /* Set up Tx window size and frame limit for this queue */
265 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
266 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
269 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
270 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
272 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
273 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
275 iwl_set_bits_prph(priv
, IWLAGN_SCD_INTERRUPT_MASK
, (1 << txq_id
));
277 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
278 iwlagn_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 1);
280 spin_unlock_irqrestore(&priv
->lock
, flags
);
285 int iwlagn_txq_agg_disable(struct iwl_priv
*priv
, u16 txq_id
,
286 u16 ssn_idx
, u8 tx_fifo
)
288 if ((IWLAGN_FIRST_AMPDU_QUEUE
> txq_id
) ||
289 (IWLAGN_FIRST_AMPDU_QUEUE
+
290 priv
->cfg
->base_params
->num_of_ampdu_queues
<= txq_id
)) {
292 "queue number out of range: %d, must be %d to %d\n",
293 txq_id
, IWLAGN_FIRST_AMPDU_QUEUE
,
294 IWLAGN_FIRST_AMPDU_QUEUE
+
295 priv
->cfg
->base_params
->num_of_ampdu_queues
- 1);
299 iwlagn_tx_queue_stop_scheduler(priv
, txq_id
);
301 iwl_clear_bits_prph(priv
, IWLAGN_SCD_AGGR_SEL
, (1 << txq_id
));
303 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
304 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
305 /* supposes that ssn_idx is valid (!= 0xFFF) */
306 iwlagn_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
308 iwl_clear_bits_prph(priv
, IWLAGN_SCD_INTERRUPT_MASK
, (1 << txq_id
));
309 iwl_txq_ctx_deactivate(priv
, txq_id
);
310 iwlagn_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 0);
316 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
317 * must be called under priv->lock and mac access
319 void iwlagn_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
321 iwl_write_prph(priv
, IWLAGN_SCD_TXFACT
, mask
);
325 * handle build REPLY_TX command notification.
327 static void iwlagn_tx_cmd_build_basic(struct iwl_priv
*priv
,
329 struct iwl_tx_cmd
*tx_cmd
,
330 struct ieee80211_tx_info
*info
,
331 struct ieee80211_hdr
*hdr
,
334 __le16 fc
= hdr
->frame_control
;
335 __le32 tx_flags
= tx_cmd
->tx_flags
;
337 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
338 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
339 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
340 if (ieee80211_is_mgmt(fc
))
341 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
342 if (ieee80211_is_probe_resp(fc
) &&
343 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
344 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
346 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
347 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
350 if (ieee80211_is_back_req(fc
))
351 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
352 else if (info
->band
== IEEE80211_BAND_2GHZ
&&
353 priv
->cfg
->bt_params
&&
354 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
355 (ieee80211_is_auth(fc
) || ieee80211_is_assoc_req(fc
) ||
356 ieee80211_is_reassoc_req(fc
) ||
357 skb
->protocol
== cpu_to_be16(ETH_P_PAE
)))
358 tx_flags
|= TX_CMD_FLG_IGNORE_BT
;
361 tx_cmd
->sta_id
= std_id
;
362 if (ieee80211_has_morefrags(fc
))
363 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
365 if (ieee80211_is_data_qos(fc
)) {
366 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
367 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
368 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
370 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
373 priv
->cfg
->ops
->utils
->tx_cmd_protection(priv
, info
, fc
, &tx_flags
);
375 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
376 if (ieee80211_is_mgmt(fc
)) {
377 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
378 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
380 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
382 tx_cmd
->timeout
.pm_frame_timeout
= 0;
385 tx_cmd
->driver_txop
= 0;
386 tx_cmd
->tx_flags
= tx_flags
;
387 tx_cmd
->next_frame_len
= 0;
390 #define RTS_DFAULT_RETRY_LIMIT 60
392 static void iwlagn_tx_cmd_build_rate(struct iwl_priv
*priv
,
393 struct iwl_tx_cmd
*tx_cmd
,
394 struct ieee80211_tx_info
*info
,
403 /* Set retry limit on DATA packets and Probe Responses*/
404 if (ieee80211_is_probe_resp(fc
))
405 data_retry_limit
= 3;
407 data_retry_limit
= IWLAGN_DEFAULT_TX_RETRY
;
408 tx_cmd
->data_retry_limit
= data_retry_limit
;
410 /* Set retry limit on RTS packets */
411 rts_retry_limit
= RTS_DFAULT_RETRY_LIMIT
;
412 if (data_retry_limit
< rts_retry_limit
)
413 rts_retry_limit
= data_retry_limit
;
414 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
416 /* DATA packets will use the uCode station table for rate/antenna
418 if (ieee80211_is_data(fc
)) {
419 tx_cmd
->initial_rate_index
= 0;
420 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
425 * If the current TX rate stored in mac80211 has the MCS bit set, it's
426 * not really a TX rate. Thus, we use the lowest supported rate for
427 * this band. Also use the lowest supported rate if the stored rate
430 rate_idx
= info
->control
.rates
[0].idx
;
431 if (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_MCS
||
432 (rate_idx
< 0) || (rate_idx
> IWL_RATE_COUNT_LEGACY
))
433 rate_idx
= rate_lowest_index(&priv
->bands
[info
->band
],
435 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
436 if (info
->band
== IEEE80211_BAND_5GHZ
)
437 rate_idx
+= IWL_FIRST_OFDM_RATE
;
438 /* Get PLCP rate for tx_cmd->rate_n_flags */
439 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
440 /* Zero out flags for this packet */
443 /* Set CCK flag as needed */
444 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
445 rate_flags
|= RATE_MCS_CCK_MSK
;
447 /* Set up antennas */
448 if (priv
->cfg
->bt_params
&&
449 priv
->cfg
->bt_params
->advanced_bt_coexist
&&
450 priv
->bt_full_concurrent
) {
451 /* operated as 1x1 in full concurrency mode */
452 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
,
453 first_antenna(priv
->hw_params
.valid_tx_ant
));
455 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
,
456 priv
->hw_params
.valid_tx_ant
);
457 rate_flags
|= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
459 /* Set the rate in the TX cmd */
460 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
463 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
464 struct ieee80211_tx_info
*info
,
465 struct iwl_tx_cmd
*tx_cmd
,
466 struct sk_buff
*skb_frag
,
469 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
471 switch (keyconf
->cipher
) {
472 case WLAN_CIPHER_SUITE_CCMP
:
473 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
474 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
475 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
476 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
477 IWL_DEBUG_TX(priv
, "tx_cmd with AES hwcrypto\n");
480 case WLAN_CIPHER_SUITE_TKIP
:
481 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
482 ieee80211_get_tkip_key(keyconf
, skb_frag
,
483 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
484 IWL_DEBUG_TX(priv
, "tx_cmd with tkip hwcrypto\n");
487 case WLAN_CIPHER_SUITE_WEP104
:
488 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
490 case WLAN_CIPHER_SUITE_WEP40
:
491 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
492 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
494 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
496 IWL_DEBUG_TX(priv
, "Configuring packet for WEP encryption "
497 "with key %d\n", keyconf
->keyidx
);
501 IWL_ERR(priv
, "Unknown encode cipher %x\n", keyconf
->cipher
);
507 * start REPLY_TX command process
509 int iwlagn_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
511 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
512 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
513 struct ieee80211_sta
*sta
= info
->control
.sta
;
514 struct iwl_station_priv
*sta_priv
= NULL
;
515 struct iwl_tx_queue
*txq
;
517 struct iwl_device_cmd
*out_cmd
;
518 struct iwl_cmd_meta
*out_meta
;
519 struct iwl_tx_cmd
*tx_cmd
;
520 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
522 dma_addr_t phys_addr
;
523 dma_addr_t txcmd_phys
;
524 dma_addr_t scratch_phys
;
525 u16 len
, len_org
, firstlen
, secondlen
;
530 u8 wait_write_ptr
= 0;
535 if (info
->control
.vif
)
536 ctx
= iwl_rxon_ctx_from_vif(info
->control
.vif
);
538 spin_lock_irqsave(&priv
->lock
, flags
);
539 if (iwl_is_rfkill(priv
)) {
540 IWL_DEBUG_DROP(priv
, "Dropping - RF KILL\n");
544 fc
= hdr
->frame_control
;
546 #ifdef CONFIG_IWLWIFI_DEBUG
547 if (ieee80211_is_auth(fc
))
548 IWL_DEBUG_TX(priv
, "Sending AUTH frame\n");
549 else if (ieee80211_is_assoc_req(fc
))
550 IWL_DEBUG_TX(priv
, "Sending ASSOC frame\n");
551 else if (ieee80211_is_reassoc_req(fc
))
552 IWL_DEBUG_TX(priv
, "Sending REASSOC frame\n");
555 hdr_len
= ieee80211_hdrlen(fc
);
557 /* Find index into station table for destination station */
558 sta_id
= iwl_sta_id_or_broadcast(priv
, ctx
, info
->control
.sta
);
559 if (sta_id
== IWL_INVALID_STATION
) {
560 IWL_DEBUG_DROP(priv
, "Dropping - INVALID STATION: %pM\n",
565 IWL_DEBUG_TX(priv
, "station Id %d\n", sta_id
);
568 sta_priv
= (void *)sta
->drv_priv
;
570 if (sta_priv
&& sta_priv
->asleep
) {
571 WARN_ON(!(info
->flags
& IEEE80211_TX_CTL_PSPOLL_RESPONSE
));
573 * This sends an asynchronous command to the device,
574 * but we can rely on it being processed before the
575 * next frame is processed -- and the next frame to
576 * this station is the one that will consume this
578 * For now set the counter to just 1 since we do not
581 iwl_sta_modify_sleep_tx_count(priv
, sta_id
, 1);
585 * Send this frame after DTIM -- there's a special queue
586 * reserved for this for contexts that support AP mode.
588 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
589 txq_id
= ctx
->mcast_queue
;
591 * The microcode will clear the more data
592 * bit in the last frame it transmits.
594 hdr
->frame_control
|=
595 cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
597 txq_id
= ctx
->ac_to_queue
[skb_get_queue_mapping(skb
)];
599 /* irqs already disabled/saved above when locking priv->lock */
600 spin_lock(&priv
->sta_lock
);
602 if (ieee80211_is_data_qos(fc
)) {
603 qc
= ieee80211_get_qos_ctl(hdr
);
604 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
605 if (WARN_ON_ONCE(tid
>= MAX_TID_COUNT
)) {
606 spin_unlock(&priv
->sta_lock
);
609 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
610 seq_number
&= IEEE80211_SCTL_SEQ
;
611 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
612 cpu_to_le16(IEEE80211_SCTL_FRAG
);
613 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
615 /* aggregation is on for this <sta,tid> */
616 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
&&
617 priv
->stations
[sta_id
].tid
[tid
].agg
.state
== IWL_AGG_ON
) {
618 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
622 txq
= &priv
->txq
[txq_id
];
623 swq_id
= txq
->swq_id
;
626 if (unlikely(iwl_queue_space(q
) < q
->high_mark
)) {
627 spin_unlock(&priv
->sta_lock
);
631 if (ieee80211_is_data_qos(fc
)) {
632 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
633 if (!ieee80211_has_morefrags(fc
))
634 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
637 spin_unlock(&priv
->sta_lock
);
639 /* Set up driver data for this TFD */
640 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
641 txq
->txb
[q
->write_ptr
].skb
= skb
;
642 txq
->txb
[q
->write_ptr
].ctx
= ctx
;
644 /* Set up first empty entry in queue's array of Tx/cmd buffers */
645 out_cmd
= txq
->cmd
[q
->write_ptr
];
646 out_meta
= &txq
->meta
[q
->write_ptr
];
647 tx_cmd
= &out_cmd
->cmd
.tx
;
648 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
649 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
652 * Set up the Tx-command (not MAC!) header.
653 * Store the chosen Tx queue and TFD index within the sequence field;
654 * after Tx, uCode's Tx response will return this value so driver can
655 * locate the frame within the tx queue and do post-tx processing.
657 out_cmd
->hdr
.cmd
= REPLY_TX
;
658 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
659 INDEX_TO_SEQ(q
->write_ptr
)));
661 /* Copy MAC header from skb into command buffer */
662 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
665 /* Total # bytes to be transmitted */
667 tx_cmd
->len
= cpu_to_le16(len
);
669 if (info
->control
.hw_key
)
670 iwlagn_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
672 /* TODO need this for burst mode later on */
673 iwlagn_tx_cmd_build_basic(priv
, skb
, tx_cmd
, info
, hdr
, sta_id
);
674 iwl_dbg_log_tx_data_frame(priv
, len
, hdr
);
676 iwlagn_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
);
678 iwl_update_stats(priv
, true, fc
, len
);
680 * Use the first empty entry in this queue's command buffer array
681 * to contain the Tx command and MAC header concatenated together
682 * (payload data will be in another buffer).
683 * Size of this varies, due to varying MAC header length.
684 * If end is not dword aligned, we'll have 2 extra bytes at the end
685 * of the MAC header (device reads on dword boundaries).
686 * We'll tell device about this padding later.
688 len
= sizeof(struct iwl_tx_cmd
) +
689 sizeof(struct iwl_cmd_header
) + hdr_len
;
692 firstlen
= len
= (len
+ 3) & ~3;
699 /* Tell NIC about any 2-byte padding after MAC header */
701 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
703 /* Physical address of this Tx command's header (not MAC header!),
704 * within command buffer array. */
705 txcmd_phys
= pci_map_single(priv
->pci_dev
,
707 PCI_DMA_BIDIRECTIONAL
);
708 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
709 dma_unmap_len_set(out_meta
, len
, len
);
710 /* Add buffer containing Tx command and MAC(!) header to TFD's
712 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
713 txcmd_phys
, len
, 1, 0);
715 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
716 txq
->need_update
= 1;
719 txq
->need_update
= 0;
722 /* Set up TFD's 2nd entry to point directly to remainder of skb,
723 * if any (802.11 null frames have no payload). */
724 secondlen
= len
= skb
->len
- hdr_len
;
726 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
727 len
, PCI_DMA_TODEVICE
);
728 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
733 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
734 offsetof(struct iwl_tx_cmd
, scratch
);
736 len
= sizeof(struct iwl_tx_cmd
) +
737 sizeof(struct iwl_cmd_header
) + hdr_len
;
738 /* take back ownership of DMA buffer to enable update */
739 pci_dma_sync_single_for_cpu(priv
->pci_dev
, txcmd_phys
,
740 len
, PCI_DMA_BIDIRECTIONAL
);
741 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
742 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
744 IWL_DEBUG_TX(priv
, "sequence nr = 0X%x\n",
745 le16_to_cpu(out_cmd
->hdr
.sequence
));
746 IWL_DEBUG_TX(priv
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
747 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
748 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
750 /* Set up entry for this TFD in Tx byte-count array */
751 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
752 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
,
753 le16_to_cpu(tx_cmd
->len
));
755 pci_dma_sync_single_for_device(priv
->pci_dev
, txcmd_phys
,
756 len
, PCI_DMA_BIDIRECTIONAL
);
758 trace_iwlwifi_dev_tx(priv
,
759 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
760 sizeof(struct iwl_tfd
),
761 &out_cmd
->hdr
, firstlen
,
762 skb
->data
+ hdr_len
, secondlen
);
764 /* Tell device the write index *just past* this latest filled TFD */
765 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
766 iwl_txq_update_write_ptr(priv
, txq
);
767 spin_unlock_irqrestore(&priv
->lock
, flags
);
770 * At this point the frame is "transmitted" successfully
771 * and we will get a TX status notification eventually,
772 * regardless of the value of ret. "ret" only indicates
773 * whether or not we should update the write pointer.
776 /* avoid atomic ops if it isn't an associated client */
777 if (sta_priv
&& sta_priv
->client
)
778 atomic_inc(&sta_priv
->pending_frames
);
780 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
781 if (wait_write_ptr
) {
782 spin_lock_irqsave(&priv
->lock
, flags
);
783 txq
->need_update
= 1;
784 iwl_txq_update_write_ptr(priv
, txq
);
785 spin_unlock_irqrestore(&priv
->lock
, flags
);
787 iwl_stop_queue(priv
, txq
->swq_id
);
794 spin_unlock_irqrestore(&priv
->lock
, flags
);
798 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv
*priv
,
799 struct iwl_dma_ptr
*ptr
, size_t size
)
801 ptr
->addr
= dma_alloc_coherent(&priv
->pci_dev
->dev
, size
, &ptr
->dma
,
809 static inline void iwlagn_free_dma_ptr(struct iwl_priv
*priv
,
810 struct iwl_dma_ptr
*ptr
)
812 if (unlikely(!ptr
->addr
))
815 dma_free_coherent(&priv
->pci_dev
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
816 memset(ptr
, 0, sizeof(*ptr
));
820 * iwlagn_hw_txq_ctx_free - Free TXQ Context
822 * Destroy all TX DMA queues and structures
824 void iwlagn_hw_txq_ctx_free(struct iwl_priv
*priv
)
830 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
831 if (txq_id
== priv
->cmd_queue
)
832 iwl_cmd_queue_free(priv
);
834 iwl_tx_queue_free(priv
, txq_id
);
836 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
838 iwlagn_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
840 /* free tx queue structure */
841 iwl_free_txq_mem(priv
);
845 * iwlagn_txq_ctx_alloc - allocate TX queue context
846 * Allocate all Tx DMA structures and initialize them
851 int iwlagn_txq_ctx_alloc(struct iwl_priv
*priv
)
854 int txq_id
, slots_num
;
857 /* Free all tx/cmd queues and keep-warm buffer */
858 iwlagn_hw_txq_ctx_free(priv
);
860 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
861 priv
->hw_params
.scd_bc_tbls_size
);
863 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
866 /* Alloc keep-warm buffer */
867 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
869 IWL_ERR(priv
, "Keep Warm allocation failed\n");
873 /* allocate tx queue structure */
874 ret
= iwl_alloc_txq_mem(priv
);
878 spin_lock_irqsave(&priv
->lock
, flags
);
880 /* Turn off all Tx DMA fifos */
881 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
883 /* Tell NIC where to find the "keep warm" buffer */
884 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
886 spin_unlock_irqrestore(&priv
->lock
, flags
);
888 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
889 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
890 slots_num
= (txq_id
== priv
->cmd_queue
) ?
891 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
892 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
895 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
903 iwlagn_hw_txq_ctx_free(priv
);
904 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
906 iwlagn_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
911 void iwlagn_txq_ctx_reset(struct iwl_priv
*priv
)
913 int txq_id
, slots_num
;
916 spin_lock_irqsave(&priv
->lock
, flags
);
918 /* Turn off all Tx DMA fifos */
919 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
921 /* Tell NIC where to find the "keep warm" buffer */
922 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
924 spin_unlock_irqrestore(&priv
->lock
, flags
);
926 /* Alloc and init all Tx queues, including the command queue (#4) */
927 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
928 slots_num
= txq_id
== priv
->cmd_queue
?
929 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
930 iwl_tx_queue_reset(priv
, &priv
->txq
[txq_id
], slots_num
, txq_id
);
935 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
937 void iwlagn_txq_ctx_stop(struct iwl_priv
*priv
)
942 /* Turn off all Tx DMA fifos */
943 spin_lock_irqsave(&priv
->lock
, flags
);
945 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
947 /* Stop each Tx DMA channel, and wait for it to be idle */
948 for (ch
= 0; ch
< priv
->hw_params
.dma_chnl_num
; ch
++) {
949 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
950 if (iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
951 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
953 IWL_ERR(priv
, "Failing on timeout while stopping"
954 " DMA channel %d [0x%08x]", ch
,
955 iwl_read_direct32(priv
, FH_TSSR_TX_STATUS_REG
));
957 spin_unlock_irqrestore(&priv
->lock
, flags
);
961 * Find first available (lowest unused) Tx Queue, mark it "active".
962 * Called only when finding queue for aggregation.
963 * Should never return anything < 7, because they should already
964 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
966 static int iwlagn_txq_ctx_activate_free(struct iwl_priv
*priv
)
970 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
971 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
976 int iwlagn_tx_agg_start(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
,
977 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
)
984 struct iwl_tid_data
*tid_data
;
986 tx_fifo
= get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif
), tid
);
987 if (unlikely(tx_fifo
< 0))
990 IWL_WARN(priv
, "%s on ra = %pM tid = %d\n",
991 __func__
, sta
->addr
, tid
);
993 sta_id
= iwl_sta_id(sta
);
994 if (sta_id
== IWL_INVALID_STATION
) {
995 IWL_ERR(priv
, "Start AGG on invalid station\n");
998 if (unlikely(tid
>= MAX_TID_COUNT
))
1001 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
1002 IWL_ERR(priv
, "Start AGG when state is not IWL_AGG_OFF !\n");
1006 txq_id
= iwlagn_txq_ctx_activate_free(priv
);
1008 IWL_ERR(priv
, "No free aggregation queue available\n");
1012 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1013 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1014 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1015 tid_data
->agg
.txq_id
= txq_id
;
1016 priv
->txq
[txq_id
].swq_id
= iwl_virtual_agg_queue_num(get_ac_from_tid(tid
), txq_id
);
1017 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1019 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1024 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1025 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1026 if (tid_data
->tfds_in_queue
== 0) {
1027 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1028 tid_data
->agg
.state
= IWL_AGG_ON
;
1029 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
1031 IWL_DEBUG_HT(priv
, "HW queue is NOT empty: %d packets in HW queue\n",
1032 tid_data
->tfds_in_queue
);
1033 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1035 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1039 int iwlagn_tx_agg_stop(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
,
1040 struct ieee80211_sta
*sta
, u16 tid
)
1042 int tx_fifo_id
, txq_id
, sta_id
, ssn
;
1043 struct iwl_tid_data
*tid_data
;
1044 int write_ptr
, read_ptr
;
1045 unsigned long flags
;
1047 tx_fifo_id
= get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif
), tid
);
1048 if (unlikely(tx_fifo_id
< 0))
1051 sta_id
= iwl_sta_id(sta
);
1053 if (sta_id
== IWL_INVALID_STATION
) {
1054 IWL_ERR(priv
, "Invalid station for AGG tid %d\n", tid
);
1058 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1060 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1061 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1062 txq_id
= tid_data
->agg
.txq_id
;
1064 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1065 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1067 * This can happen if the peer stops aggregation
1068 * again before we've had a chance to drain the
1069 * queue we selected previously, i.e. before the
1070 * session was really started completely.
1072 IWL_DEBUG_HT(priv
, "AGG stop before setup done\n");
1077 IWL_WARN(priv
, "Stopping AGG while state not ON or starting\n");
1080 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1081 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1083 /* The queue is not empty */
1084 if (write_ptr
!= read_ptr
) {
1085 IWL_DEBUG_HT(priv
, "Stopping a non empty AGG HW QUEUE\n");
1086 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1087 IWL_EMPTYING_HW_QUEUE_DELBA
;
1088 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1092 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1094 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1096 /* do not restore/save irqs */
1097 spin_unlock(&priv
->sta_lock
);
1098 spin_lock(&priv
->lock
);
1101 * the only reason this call can fail is queue number out of range,
1102 * which can happen if uCode is reloaded and all the station
1103 * information are lost. if it is outside the range, there is no need
1104 * to deactivate the uCode queue, just return "success" to allow
1105 * mac80211 to clean up it own data.
1107 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1109 spin_unlock_irqrestore(&priv
->lock
, flags
);
1111 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
1116 int iwlagn_txq_check_empty(struct iwl_priv
*priv
,
1117 int sta_id
, u8 tid
, int txq_id
)
1119 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1120 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1121 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1122 struct iwl_rxon_context
*ctx
;
1124 ctx
= &priv
->contexts
[priv
->stations
[sta_id
].ctxid
];
1126 lockdep_assert_held(&priv
->sta_lock
);
1128 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1129 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1130 /* We are reclaiming the last packet of the */
1131 /* aggregated HW queue */
1132 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1133 (q
->read_ptr
== q
->write_ptr
)) {
1134 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1135 int tx_fifo
= get_fifo_from_tid(ctx
, tid
);
1136 IWL_DEBUG_HT(priv
, "HW queue empty: continue DELBA flow\n");
1137 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1139 tid_data
->agg
.state
= IWL_AGG_OFF
;
1140 ieee80211_stop_tx_ba_cb_irqsafe(ctx
->vif
, addr
, tid
);
1143 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1144 /* We are reclaiming the last packet of the queue */
1145 if (tid_data
->tfds_in_queue
== 0) {
1146 IWL_DEBUG_HT(priv
, "HW queue empty: continue ADDBA flow\n");
1147 tid_data
->agg
.state
= IWL_AGG_ON
;
1148 ieee80211_start_tx_ba_cb_irqsafe(ctx
->vif
, addr
, tid
);
1156 static void iwlagn_tx_status(struct iwl_priv
*priv
, struct iwl_tx_info
*tx_info
)
1158 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) tx_info
->skb
->data
;
1159 struct ieee80211_sta
*sta
;
1160 struct iwl_station_priv
*sta_priv
;
1163 sta
= ieee80211_find_sta(tx_info
->ctx
->vif
, hdr
->addr1
);
1165 sta_priv
= (void *)sta
->drv_priv
;
1166 /* avoid atomic ops if this isn't a client */
1167 if (sta_priv
->client
&&
1168 atomic_dec_return(&sta_priv
->pending_frames
) == 0)
1169 ieee80211_sta_block_awake(priv
->hw
, sta
, false);
1173 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
);
1176 int iwlagn_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1178 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1179 struct iwl_queue
*q
= &txq
->q
;
1180 struct iwl_tx_info
*tx_info
;
1182 struct ieee80211_hdr
*hdr
;
1184 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1185 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1186 "is out of range [0-%d] %d %d.\n", txq_id
,
1187 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1191 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
);
1192 q
->read_ptr
!= index
;
1193 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1195 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1196 iwlagn_tx_status(priv
, tx_info
);
1198 hdr
= (struct ieee80211_hdr
*)tx_info
->skb
->data
;
1199 if (hdr
&& ieee80211_is_data_qos(hdr
->frame_control
))
1201 tx_info
->skb
= NULL
;
1203 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1204 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1206 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
1212 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1214 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1215 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1217 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1218 struct iwl_ht_agg
*agg
,
1219 struct iwl_compressed_ba_resp
*ba_resp
)
1223 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1224 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1225 u64 bitmap
, sent_bitmap
;
1227 struct ieee80211_tx_info
*info
;
1229 if (unlikely(!agg
->wait_for_ba
)) {
1230 IWL_ERR(priv
, "Received BA when not expected\n");
1234 /* Mark that the expected block-ack response arrived */
1235 agg
->wait_for_ba
= 0;
1236 IWL_DEBUG_TX_REPLY(priv
, "BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1238 /* Calculate shift to align block-ack bits with our Tx window bits */
1239 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>> 4);
1240 if (sh
< 0) /* tbw something is wrong with indices */
1243 /* don't use 64-bit values for now */
1244 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1246 if (agg
->frame_count
> (64 - sh
)) {
1247 IWL_DEBUG_TX_REPLY(priv
, "more frames than bitmap size");
1251 /* check for success or failure according to the
1252 * transmitted bitmap and block-ack bitmap */
1253 sent_bitmap
= bitmap
& agg
->bitmap
;
1255 /* For each frame attempted in aggregation,
1256 * update driver's record of tx frame's status. */
1258 while (sent_bitmap
) {
1259 ack
= sent_bitmap
& 1ULL;
1261 IWL_DEBUG_TX_REPLY(priv
, "%s ON i=%d idx=%d raw=%d\n",
1262 ack
? "ACK" : "NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1263 agg
->start_idx
+ i
);
1268 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
);
1269 memset(&info
->status
, 0, sizeof(info
->status
));
1270 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1271 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1272 info
->status
.ampdu_ack_len
= successes
;
1273 info
->status
.ampdu_len
= agg
->frame_count
;
1274 iwlagn_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1276 IWL_DEBUG_TX_REPLY(priv
, "Bitmap %llx\n", (unsigned long long)bitmap
);
1282 * translate ucode response to mac80211 tx status control values
1284 void iwlagn_hwrate_to_tx_control(struct iwl_priv
*priv
, u32 rate_n_flags
,
1285 struct ieee80211_tx_info
*info
)
1287 struct ieee80211_tx_rate
*r
= &info
->control
.rates
[0];
1289 info
->antenna_sel_tx
=
1290 ((rate_n_flags
& RATE_MCS_ANT_ABC_MSK
) >> RATE_MCS_ANT_POS
);
1291 if (rate_n_flags
& RATE_MCS_HT_MSK
)
1292 r
->flags
|= IEEE80211_TX_RC_MCS
;
1293 if (rate_n_flags
& RATE_MCS_GF_MSK
)
1294 r
->flags
|= IEEE80211_TX_RC_GREEN_FIELD
;
1295 if (rate_n_flags
& RATE_MCS_HT40_MSK
)
1296 r
->flags
|= IEEE80211_TX_RC_40_MHZ_WIDTH
;
1297 if (rate_n_flags
& RATE_MCS_DUP_MSK
)
1298 r
->flags
|= IEEE80211_TX_RC_DUP_DATA
;
1299 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
1300 r
->flags
|= IEEE80211_TX_RC_SHORT_GI
;
1301 r
->idx
= iwlagn_hwrate_to_mac80211_idx(rate_n_flags
, info
->band
);
1305 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1307 * Handles block-acknowledge notification from device, which reports success
1308 * of frames sent via aggregation.
1310 void iwlagn_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1311 struct iwl_rx_mem_buffer
*rxb
)
1313 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1314 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1315 struct iwl_tx_queue
*txq
= NULL
;
1316 struct iwl_ht_agg
*agg
;
1320 unsigned long flags
;
1322 /* "flow" corresponds to Tx queue */
1323 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1325 /* "ssn" is start of block-ack Tx window, corresponds to index
1326 * (in Tx queue's circular buffer) of first TFD/frame in window */
1327 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1329 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1331 "BUG_ON scd_flow is bigger than number of queues\n");
1335 txq
= &priv
->txq
[scd_flow
];
1336 sta_id
= ba_resp
->sta_id
;
1338 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1339 if (unlikely(agg
->txq_id
!= scd_flow
)) {
1341 * FIXME: this is a uCode bug which need to be addressed,
1342 * log the information and return for now!
1343 * since it is possible happen very often and in order
1344 * not to fill the syslog, don't enable the logging by default
1346 IWL_DEBUG_TX_REPLY(priv
,
1347 "BA scd_flow %d does not match txq_id %d\n",
1348 scd_flow
, agg
->txq_id
);
1352 /* Find index just before block-ack window */
1353 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1355 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1357 IWL_DEBUG_TX_REPLY(priv
, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1360 (u8
*) &ba_resp
->sta_addr_lo32
,
1362 IWL_DEBUG_TX_REPLY(priv
, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1363 "%d, scd_ssn = %d\n",
1366 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1369 IWL_DEBUG_TX_REPLY(priv
, "DAT start_idx = %d, bitmap = 0x%llx\n",
1371 (unsigned long long)agg
->bitmap
);
1373 /* Update driver's record of ACK vs. not for each frame in window */
1374 iwlagn_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1376 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1377 * block-ack window (we assume that they've been successfully
1378 * transmitted ... if not, it's too late anyway). */
1379 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1380 /* calculate mac80211 ampdu sw queue to wake */
1381 int freed
= iwlagn_tx_queue_reclaim(priv
, scd_flow
, index
);
1382 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
1384 if ((iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1385 priv
->mac80211_registered
&&
1386 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
1387 iwl_wake_queue(priv
, txq
->swq_id
);
1389 iwlagn_txq_check_empty(priv
, sta_id
, tid
, scd_flow
);
1392 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);