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Merge branch 'slab/next' into for-linus
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-tx.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-sta.h"
38 #include "iwl-io.h"
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
41 #include "iwl-agn.h"
42
43 /*
44 * mac80211 queues, ACs, hardware queues, FIFOs.
45 *
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
47 *
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
50 *
51 * VO 0
52 * VI 1
53 * BE 2
54 * BK 3
55 *
56 *
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
63 *
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 * mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80 static inline int get_ac_from_tid(u16 tid)
81 {
82 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
83 return tid_to_ac[tid];
84
85 /* no support for TIDs 8-15 yet */
86 return -EINVAL;
87 }
88
89 static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
90 {
91 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
92 return ctx->ac_to_fifo[tid_to_ac[tid]];
93
94 /* no support for TIDs 8-15 yet */
95 return -EINVAL;
96 }
97
98 /**
99 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
100 */
101 static void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
102 struct iwl_tx_queue *txq,
103 u16 byte_cnt)
104 {
105 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
106 int write_ptr = txq->q.write_ptr;
107 int txq_id = txq->q.id;
108 u8 sec_ctl = 0;
109 u8 sta_id = 0;
110 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
111 __le16 bc_ent;
112
113 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
114
115 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
116 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
117
118 switch (sec_ctl & TX_CMD_SEC_MSK) {
119 case TX_CMD_SEC_CCM:
120 len += CCMP_MIC_LEN;
121 break;
122 case TX_CMD_SEC_TKIP:
123 len += TKIP_ICV_LEN;
124 break;
125 case TX_CMD_SEC_WEP:
126 len += WEP_IV_LEN + WEP_ICV_LEN;
127 break;
128 }
129
130 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
131
132 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
133
134 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
135 scd_bc_tbl[txq_id].
136 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
137 }
138
139 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
140 struct iwl_tx_queue *txq)
141 {
142 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
143 int txq_id = txq->q.id;
144 int read_ptr = txq->q.read_ptr;
145 u8 sta_id = 0;
146 __le16 bc_ent;
147
148 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
149
150 if (txq_id != priv->cmd_queue)
151 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
152
153 bc_ent = cpu_to_le16(1 | (sta_id << 12));
154 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
155
156 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
157 scd_bc_tbl[txq_id].
158 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
159 }
160
161 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
162 u16 txq_id)
163 {
164 u32 tbl_dw_addr;
165 u32 tbl_dw;
166 u16 scd_q2ratid;
167
168 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
169
170 tbl_dw_addr = priv->scd_base_addr +
171 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
172
173 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
174
175 if (txq_id & 0x1)
176 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
177 else
178 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
179
180 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
181
182 return 0;
183 }
184
185 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
186 {
187 /* Simply stop the queue, but don't change any configuration;
188 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
189 iwl_write_prph(priv,
190 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
191 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
192 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
193 }
194
195 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
196 int txq_id, u32 index)
197 {
198 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
199 (index & 0xff) | (txq_id << 8));
200 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
201 }
202
203 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
204 struct iwl_tx_queue *txq,
205 int tx_fifo_id, int scd_retry)
206 {
207 int txq_id = txq->q.id;
208 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
209
210 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
211 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
212 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
213 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
214 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
215
216 txq->sched_retry = scd_retry;
217
218 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
219 active ? "Activate" : "Deactivate",
220 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
221 }
222
223 static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid)
224 {
225 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
226 (IWLAGN_FIRST_AMPDU_QUEUE +
227 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
228 IWL_WARN(priv,
229 "queue number out of range: %d, must be %d to %d\n",
230 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
231 IWLAGN_FIRST_AMPDU_QUEUE +
232 priv->cfg->base_params->num_of_ampdu_queues - 1);
233 return -EINVAL;
234 }
235
236 /* Modify device's station table to Tx this TID */
237 return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
238 }
239
240 void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
241 struct ieee80211_sta *sta,
242 int tid, int frame_limit)
243 {
244 int sta_id, tx_fifo, txq_id, ssn_idx;
245 u16 ra_tid;
246 unsigned long flags;
247 struct iwl_tid_data *tid_data;
248
249 sta_id = iwl_sta_id(sta);
250 if (WARN_ON(sta_id == IWL_INVALID_STATION))
251 return;
252 if (WARN_ON(tid >= MAX_TID_COUNT))
253 return;
254
255 spin_lock_irqsave(&priv->sta_lock, flags);
256 tid_data = &priv->stations[sta_id].tid[tid];
257 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
258 txq_id = tid_data->agg.txq_id;
259 tx_fifo = tid_data->agg.tx_fifo;
260 spin_unlock_irqrestore(&priv->sta_lock, flags);
261
262 ra_tid = BUILD_RAxTID(sta_id, tid);
263
264 spin_lock_irqsave(&priv->lock, flags);
265
266 /* Stop this Tx queue before configuring it */
267 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
268
269 /* Map receiver-address / traffic-ID to this queue */
270 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
271
272 /* Set this queue as a chain-building queue */
273 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
274
275 /* enable aggregations for the queue */
276 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
277
278 /* Place first TFD at index corresponding to start sequence number.
279 * Assumes that ssn_idx is valid (!= 0xFFF) */
280 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
281 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
282 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
283
284 /* Set up Tx window size and frame limit for this queue */
285 iwl_write_targ_mem(priv, priv->scd_base_addr +
286 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
287 sizeof(u32),
288 ((frame_limit <<
289 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
290 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
291 ((frame_limit <<
292 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
293 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
294
295 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
296
297 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
298 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
299
300 spin_unlock_irqrestore(&priv->lock, flags);
301 }
302
303 static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
304 u16 ssn_idx, u8 tx_fifo)
305 {
306 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
307 (IWLAGN_FIRST_AMPDU_QUEUE +
308 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
309 IWL_ERR(priv,
310 "queue number out of range: %d, must be %d to %d\n",
311 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
312 IWLAGN_FIRST_AMPDU_QUEUE +
313 priv->cfg->base_params->num_of_ampdu_queues - 1);
314 return -EINVAL;
315 }
316
317 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
318
319 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
320
321 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
322 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
323 /* supposes that ssn_idx is valid (!= 0xFFF) */
324 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
325
326 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
327 iwl_txq_ctx_deactivate(priv, txq_id);
328 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
329
330 return 0;
331 }
332
333 /*
334 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
335 * must be called under priv->lock and mac access
336 */
337 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
338 {
339 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
340 }
341
342 /*
343 * handle build REPLY_TX command notification.
344 */
345 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
346 struct sk_buff *skb,
347 struct iwl_tx_cmd *tx_cmd,
348 struct ieee80211_tx_info *info,
349 struct ieee80211_hdr *hdr,
350 u8 std_id)
351 {
352 __le16 fc = hdr->frame_control;
353 __le32 tx_flags = tx_cmd->tx_flags;
354
355 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
356 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
357 tx_flags |= TX_CMD_FLG_ACK_MSK;
358 if (ieee80211_is_mgmt(fc))
359 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
360 if (ieee80211_is_probe_resp(fc) &&
361 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
362 tx_flags |= TX_CMD_FLG_TSF_MSK;
363 } else {
364 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
365 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
366 }
367
368 if (ieee80211_is_back_req(fc))
369 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
370 else if (info->band == IEEE80211_BAND_2GHZ &&
371 priv->cfg->bt_params &&
372 priv->cfg->bt_params->advanced_bt_coexist &&
373 (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) ||
374 ieee80211_is_reassoc_req(fc) ||
375 skb->protocol == cpu_to_be16(ETH_P_PAE)))
376 tx_flags |= TX_CMD_FLG_IGNORE_BT;
377
378
379 tx_cmd->sta_id = std_id;
380 if (ieee80211_has_morefrags(fc))
381 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
382
383 if (ieee80211_is_data_qos(fc)) {
384 u8 *qc = ieee80211_get_qos_ctl(hdr);
385 tx_cmd->tid_tspec = qc[0] & 0xf;
386 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
387 } else {
388 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
389 }
390
391 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
392
393 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
394 if (ieee80211_is_mgmt(fc)) {
395 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
396 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
397 else
398 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
399 } else {
400 tx_cmd->timeout.pm_frame_timeout = 0;
401 }
402
403 tx_cmd->driver_txop = 0;
404 tx_cmd->tx_flags = tx_flags;
405 tx_cmd->next_frame_len = 0;
406 }
407
408 #define RTS_DFAULT_RETRY_LIMIT 60
409
410 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
411 struct iwl_tx_cmd *tx_cmd,
412 struct ieee80211_tx_info *info,
413 __le16 fc)
414 {
415 u32 rate_flags;
416 int rate_idx;
417 u8 rts_retry_limit;
418 u8 data_retry_limit;
419 u8 rate_plcp;
420
421 /* Set retry limit on DATA packets and Probe Responses*/
422 if (ieee80211_is_probe_resp(fc))
423 data_retry_limit = 3;
424 else
425 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
426 tx_cmd->data_retry_limit = data_retry_limit;
427
428 /* Set retry limit on RTS packets */
429 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
430 if (data_retry_limit < rts_retry_limit)
431 rts_retry_limit = data_retry_limit;
432 tx_cmd->rts_retry_limit = rts_retry_limit;
433
434 /* DATA packets will use the uCode station table for rate/antenna
435 * selection */
436 if (ieee80211_is_data(fc)) {
437 tx_cmd->initial_rate_index = 0;
438 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
439 return;
440 }
441
442 /**
443 * If the current TX rate stored in mac80211 has the MCS bit set, it's
444 * not really a TX rate. Thus, we use the lowest supported rate for
445 * this band. Also use the lowest supported rate if the stored rate
446 * index is invalid.
447 */
448 rate_idx = info->control.rates[0].idx;
449 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
450 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
451 rate_idx = rate_lowest_index(&priv->bands[info->band],
452 info->control.sta);
453 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
454 if (info->band == IEEE80211_BAND_5GHZ)
455 rate_idx += IWL_FIRST_OFDM_RATE;
456 /* Get PLCP rate for tx_cmd->rate_n_flags */
457 rate_plcp = iwl_rates[rate_idx].plcp;
458 /* Zero out flags for this packet */
459 rate_flags = 0;
460
461 /* Set CCK flag as needed */
462 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
463 rate_flags |= RATE_MCS_CCK_MSK;
464
465 /* Set up antennas */
466 if (priv->cfg->bt_params &&
467 priv->cfg->bt_params->advanced_bt_coexist &&
468 priv->bt_full_concurrent) {
469 /* operated as 1x1 in full concurrency mode */
470 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
471 first_antenna(priv->hw_params.valid_tx_ant));
472 } else
473 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
474 priv->hw_params.valid_tx_ant);
475 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
476
477 /* Set the rate in the TX cmd */
478 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
479 }
480
481 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
482 struct ieee80211_tx_info *info,
483 struct iwl_tx_cmd *tx_cmd,
484 struct sk_buff *skb_frag,
485 int sta_id)
486 {
487 struct ieee80211_key_conf *keyconf = info->control.hw_key;
488
489 switch (keyconf->cipher) {
490 case WLAN_CIPHER_SUITE_CCMP:
491 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
492 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
493 if (info->flags & IEEE80211_TX_CTL_AMPDU)
494 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
495 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
496 break;
497
498 case WLAN_CIPHER_SUITE_TKIP:
499 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
500 ieee80211_get_tkip_key(keyconf, skb_frag,
501 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
502 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
503 break;
504
505 case WLAN_CIPHER_SUITE_WEP104:
506 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
507 /* fall through */
508 case WLAN_CIPHER_SUITE_WEP40:
509 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
510 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
511
512 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
513
514 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
515 "with key %d\n", keyconf->keyidx);
516 break;
517
518 default:
519 IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher);
520 break;
521 }
522 }
523
524 /*
525 * start REPLY_TX command process
526 */
527 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
528 {
529 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
530 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
531 struct ieee80211_sta *sta = info->control.sta;
532 struct iwl_station_priv *sta_priv = NULL;
533 struct iwl_tx_queue *txq;
534 struct iwl_queue *q;
535 struct iwl_device_cmd *out_cmd;
536 struct iwl_cmd_meta *out_meta;
537 struct iwl_tx_cmd *tx_cmd;
538 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
539 int txq_id;
540 dma_addr_t phys_addr = 0;
541 dma_addr_t txcmd_phys;
542 dma_addr_t scratch_phys;
543 u16 len, firstlen, secondlen;
544 u16 seq_number = 0;
545 __le16 fc;
546 u8 hdr_len;
547 u8 sta_id;
548 u8 wait_write_ptr = 0;
549 u8 tid = 0;
550 u8 *qc = NULL;
551 unsigned long flags;
552 bool is_agg = false;
553
554 /*
555 * If the frame needs to go out off-channel, then
556 * we'll have put the PAN context to that channel,
557 * so make the frame go out there.
558 */
559 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
560 ctx = &priv->contexts[IWL_RXON_CTX_PAN];
561 else if (info->control.vif)
562 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
563
564 spin_lock_irqsave(&priv->lock, flags);
565 if (iwl_is_rfkill(priv)) {
566 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
567 goto drop_unlock_priv;
568 }
569
570 fc = hdr->frame_control;
571
572 #ifdef CONFIG_IWLWIFI_DEBUG
573 if (ieee80211_is_auth(fc))
574 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
575 else if (ieee80211_is_assoc_req(fc))
576 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
577 else if (ieee80211_is_reassoc_req(fc))
578 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
579 #endif
580
581 hdr_len = ieee80211_hdrlen(fc);
582
583 /* For management frames use broadcast id to do not break aggregation */
584 if (!ieee80211_is_data(fc))
585 sta_id = ctx->bcast_sta_id;
586 else {
587 /* Find index into station table for destination station */
588 sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta);
589 if (sta_id == IWL_INVALID_STATION) {
590 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
591 hdr->addr1);
592 goto drop_unlock_priv;
593 }
594 }
595
596 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
597
598 if (sta)
599 sta_priv = (void *)sta->drv_priv;
600
601 if (sta_priv && sta_priv->asleep &&
602 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
603 /*
604 * This sends an asynchronous command to the device,
605 * but we can rely on it being processed before the
606 * next frame is processed -- and the next frame to
607 * this station is the one that will consume this
608 * counter.
609 * For now set the counter to just 1 since we do not
610 * support uAPSD yet.
611 */
612 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
613 }
614
615 /*
616 * Send this frame after DTIM -- there's a special queue
617 * reserved for this for contexts that support AP mode.
618 */
619 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
620 txq_id = ctx->mcast_queue;
621 /*
622 * The microcode will clear the more data
623 * bit in the last frame it transmits.
624 */
625 hdr->frame_control |=
626 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
627 } else
628 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
629
630 /* irqs already disabled/saved above when locking priv->lock */
631 spin_lock(&priv->sta_lock);
632
633 if (ieee80211_is_data_qos(fc)) {
634 qc = ieee80211_get_qos_ctl(hdr);
635 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
636
637 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT))
638 goto drop_unlock_sta;
639
640 seq_number = priv->stations[sta_id].tid[tid].seq_number;
641 seq_number &= IEEE80211_SCTL_SEQ;
642 hdr->seq_ctrl = hdr->seq_ctrl &
643 cpu_to_le16(IEEE80211_SCTL_FRAG);
644 hdr->seq_ctrl |= cpu_to_le16(seq_number);
645 seq_number += 0x10;
646 /* aggregation is on for this <sta,tid> */
647 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
648 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
649 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
650 is_agg = true;
651 }
652 }
653
654 txq = &priv->txq[txq_id];
655 q = &txq->q;
656
657 if (unlikely(iwl_queue_space(q) < q->high_mark))
658 goto drop_unlock_sta;
659
660 /* Set up driver data for this TFD */
661 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
662 txq->txb[q->write_ptr].skb = skb;
663 txq->txb[q->write_ptr].ctx = ctx;
664
665 /* Set up first empty entry in queue's array of Tx/cmd buffers */
666 out_cmd = txq->cmd[q->write_ptr];
667 out_meta = &txq->meta[q->write_ptr];
668 tx_cmd = &out_cmd->cmd.tx;
669 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
670 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
671
672 /*
673 * Set up the Tx-command (not MAC!) header.
674 * Store the chosen Tx queue and TFD index within the sequence field;
675 * after Tx, uCode's Tx response will return this value so driver can
676 * locate the frame within the tx queue and do post-tx processing.
677 */
678 out_cmd->hdr.cmd = REPLY_TX;
679 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
680 INDEX_TO_SEQ(q->write_ptr)));
681
682 /* Copy MAC header from skb into command buffer */
683 memcpy(tx_cmd->hdr, hdr, hdr_len);
684
685
686 /* Total # bytes to be transmitted */
687 len = (u16)skb->len;
688 tx_cmd->len = cpu_to_le16(len);
689
690 if (info->control.hw_key)
691 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
692
693 /* TODO need this for burst mode later on */
694 iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id);
695 iwl_dbg_log_tx_data_frame(priv, len, hdr);
696
697 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
698
699 iwl_update_stats(priv, true, fc, len);
700 /*
701 * Use the first empty entry in this queue's command buffer array
702 * to contain the Tx command and MAC header concatenated together
703 * (payload data will be in another buffer).
704 * Size of this varies, due to varying MAC header length.
705 * If end is not dword aligned, we'll have 2 extra bytes at the end
706 * of the MAC header (device reads on dword boundaries).
707 * We'll tell device about this padding later.
708 */
709 len = sizeof(struct iwl_tx_cmd) +
710 sizeof(struct iwl_cmd_header) + hdr_len;
711 firstlen = (len + 3) & ~3;
712
713 /* Tell NIC about any 2-byte padding after MAC header */
714 if (firstlen != len)
715 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
716
717 /* Physical address of this Tx command's header (not MAC header!),
718 * within command buffer array. */
719 txcmd_phys = pci_map_single(priv->pci_dev,
720 &out_cmd->hdr, firstlen,
721 PCI_DMA_BIDIRECTIONAL);
722 if (unlikely(pci_dma_mapping_error(priv->pci_dev, txcmd_phys)))
723 goto drop_unlock_sta;
724 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
725 dma_unmap_len_set(out_meta, len, firstlen);
726
727 if (!ieee80211_has_morefrags(hdr->frame_control)) {
728 txq->need_update = 1;
729 } else {
730 wait_write_ptr = 1;
731 txq->need_update = 0;
732 }
733
734 /* Set up TFD's 2nd entry to point directly to remainder of skb,
735 * if any (802.11 null frames have no payload). */
736 secondlen = skb->len - hdr_len;
737 if (secondlen > 0) {
738 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
739 secondlen, PCI_DMA_TODEVICE);
740 if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
741 pci_unmap_single(priv->pci_dev,
742 dma_unmap_addr(out_meta, mapping),
743 dma_unmap_len(out_meta, len),
744 PCI_DMA_BIDIRECTIONAL);
745 goto drop_unlock_sta;
746 }
747 }
748
749 if (ieee80211_is_data_qos(fc)) {
750 priv->stations[sta_id].tid[tid].tfds_in_queue++;
751 if (!ieee80211_has_morefrags(fc))
752 priv->stations[sta_id].tid[tid].seq_number = seq_number;
753 }
754
755 spin_unlock(&priv->sta_lock);
756
757 /* Attach buffers to TFD */
758 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
759 txcmd_phys, firstlen, 1, 0);
760 if (secondlen > 0)
761 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
762 phys_addr, secondlen,
763 0, 0);
764
765 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
766 offsetof(struct iwl_tx_cmd, scratch);
767
768 /* take back ownership of DMA buffer to enable update */
769 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
770 firstlen, PCI_DMA_BIDIRECTIONAL);
771 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
772 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
773
774 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
775 le16_to_cpu(out_cmd->hdr.sequence));
776 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
777 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
778 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
779
780 /* Set up entry for this TFD in Tx byte-count array */
781 if (info->flags & IEEE80211_TX_CTL_AMPDU)
782 iwlagn_txq_update_byte_cnt_tbl(priv, txq,
783 le16_to_cpu(tx_cmd->len));
784
785 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
786 firstlen, PCI_DMA_BIDIRECTIONAL);
787
788 trace_iwlwifi_dev_tx(priv,
789 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
790 sizeof(struct iwl_tfd),
791 &out_cmd->hdr, firstlen,
792 skb->data + hdr_len, secondlen);
793
794 /* Tell device the write index *just past* this latest filled TFD */
795 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
796 iwl_txq_update_write_ptr(priv, txq);
797 spin_unlock_irqrestore(&priv->lock, flags);
798
799 /*
800 * At this point the frame is "transmitted" successfully
801 * and we will get a TX status notification eventually,
802 * regardless of the value of ret. "ret" only indicates
803 * whether or not we should update the write pointer.
804 */
805
806 /*
807 * Avoid atomic ops if it isn't an associated client.
808 * Also, if this is a packet for aggregation, don't
809 * increase the counter because the ucode will stop
810 * aggregation queues when their respective station
811 * goes to sleep.
812 */
813 if (sta_priv && sta_priv->client && !is_agg)
814 atomic_inc(&sta_priv->pending_frames);
815
816 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
817 if (wait_write_ptr) {
818 spin_lock_irqsave(&priv->lock, flags);
819 txq->need_update = 1;
820 iwl_txq_update_write_ptr(priv, txq);
821 spin_unlock_irqrestore(&priv->lock, flags);
822 } else {
823 iwl_stop_queue(priv, txq);
824 }
825 }
826
827 return 0;
828
829 drop_unlock_sta:
830 spin_unlock(&priv->sta_lock);
831 drop_unlock_priv:
832 spin_unlock_irqrestore(&priv->lock, flags);
833 return -1;
834 }
835
836 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
837 struct iwl_dma_ptr *ptr, size_t size)
838 {
839 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
840 GFP_KERNEL);
841 if (!ptr->addr)
842 return -ENOMEM;
843 ptr->size = size;
844 return 0;
845 }
846
847 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
848 struct iwl_dma_ptr *ptr)
849 {
850 if (unlikely(!ptr->addr))
851 return;
852
853 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
854 memset(ptr, 0, sizeof(*ptr));
855 }
856
857 /**
858 * iwlagn_hw_txq_ctx_free - Free TXQ Context
859 *
860 * Destroy all TX DMA queues and structures
861 */
862 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
863 {
864 int txq_id;
865
866 /* Tx queues */
867 if (priv->txq) {
868 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
869 if (txq_id == priv->cmd_queue)
870 iwl_cmd_queue_free(priv);
871 else
872 iwl_tx_queue_free(priv, txq_id);
873 }
874 iwlagn_free_dma_ptr(priv, &priv->kw);
875
876 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
877
878 /* free tx queue structure */
879 iwl_free_txq_mem(priv);
880 }
881
882 /**
883 * iwlagn_txq_ctx_alloc - allocate TX queue context
884 * Allocate all Tx DMA structures and initialize them
885 *
886 * @param priv
887 * @return error code
888 */
889 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
890 {
891 int ret;
892 int txq_id, slots_num;
893 unsigned long flags;
894
895 /* Free all tx/cmd queues and keep-warm buffer */
896 iwlagn_hw_txq_ctx_free(priv);
897
898 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
899 priv->hw_params.scd_bc_tbls_size);
900 if (ret) {
901 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
902 goto error_bc_tbls;
903 }
904 /* Alloc keep-warm buffer */
905 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
906 if (ret) {
907 IWL_ERR(priv, "Keep Warm allocation failed\n");
908 goto error_kw;
909 }
910
911 /* allocate tx queue structure */
912 ret = iwl_alloc_txq_mem(priv);
913 if (ret)
914 goto error;
915
916 spin_lock_irqsave(&priv->lock, flags);
917
918 /* Turn off all Tx DMA fifos */
919 priv->cfg->ops->lib->txq_set_sched(priv, 0);
920
921 /* Tell NIC where to find the "keep warm" buffer */
922 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
923
924 spin_unlock_irqrestore(&priv->lock, flags);
925
926 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
927 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
928 slots_num = (txq_id == priv->cmd_queue) ?
929 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
930 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
931 txq_id);
932 if (ret) {
933 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
934 goto error;
935 }
936 }
937
938 return ret;
939
940 error:
941 iwlagn_hw_txq_ctx_free(priv);
942 iwlagn_free_dma_ptr(priv, &priv->kw);
943 error_kw:
944 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
945 error_bc_tbls:
946 return ret;
947 }
948
949 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
950 {
951 int txq_id, slots_num;
952 unsigned long flags;
953
954 spin_lock_irqsave(&priv->lock, flags);
955
956 /* Turn off all Tx DMA fifos */
957 priv->cfg->ops->lib->txq_set_sched(priv, 0);
958
959 /* Tell NIC where to find the "keep warm" buffer */
960 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
961
962 spin_unlock_irqrestore(&priv->lock, flags);
963
964 /* Alloc and init all Tx queues, including the command queue (#4) */
965 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
966 slots_num = txq_id == priv->cmd_queue ?
967 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
968 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
969 }
970 }
971
972 /**
973 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
974 */
975 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
976 {
977 int ch, txq_id;
978 unsigned long flags;
979
980 /* Turn off all Tx DMA fifos */
981 spin_lock_irqsave(&priv->lock, flags);
982
983 priv->cfg->ops->lib->txq_set_sched(priv, 0);
984
985 /* Stop each Tx DMA channel, and wait for it to be idle */
986 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
987 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
988 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
989 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
990 1000))
991 IWL_ERR(priv, "Failing on timeout while stopping"
992 " DMA channel %d [0x%08x]", ch,
993 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
994 }
995 spin_unlock_irqrestore(&priv->lock, flags);
996
997 if (!priv->txq)
998 return;
999
1000 /* Unmap DMA from host system and free skb's */
1001 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1002 if (txq_id == priv->cmd_queue)
1003 iwl_cmd_queue_unmap(priv);
1004 else
1005 iwl_tx_queue_unmap(priv, txq_id);
1006 }
1007
1008 /*
1009 * Find first available (lowest unused) Tx Queue, mark it "active".
1010 * Called only when finding queue for aggregation.
1011 * Should never return anything < 7, because they should already
1012 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
1013 */
1014 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
1015 {
1016 int txq_id;
1017
1018 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1019 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1020 return txq_id;
1021 return -1;
1022 }
1023
1024 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
1025 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1026 {
1027 int sta_id;
1028 int tx_fifo;
1029 int txq_id;
1030 int ret;
1031 unsigned long flags;
1032 struct iwl_tid_data *tid_data;
1033
1034 tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1035 if (unlikely(tx_fifo < 0))
1036 return tx_fifo;
1037
1038 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1039 __func__, sta->addr, tid);
1040
1041 sta_id = iwl_sta_id(sta);
1042 if (sta_id == IWL_INVALID_STATION) {
1043 IWL_ERR(priv, "Start AGG on invalid station\n");
1044 return -ENXIO;
1045 }
1046 if (unlikely(tid >= MAX_TID_COUNT))
1047 return -EINVAL;
1048
1049 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1050 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1051 return -ENXIO;
1052 }
1053
1054 txq_id = iwlagn_txq_ctx_activate_free(priv);
1055 if (txq_id == -1) {
1056 IWL_ERR(priv, "No free aggregation queue available\n");
1057 return -ENXIO;
1058 }
1059
1060 spin_lock_irqsave(&priv->sta_lock, flags);
1061 tid_data = &priv->stations[sta_id].tid[tid];
1062 *ssn = SEQ_TO_SN(tid_data->seq_number);
1063 tid_data->agg.txq_id = txq_id;
1064 tid_data->agg.tx_fifo = tx_fifo;
1065 iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
1066 spin_unlock_irqrestore(&priv->sta_lock, flags);
1067
1068 ret = iwlagn_txq_agg_enable(priv, txq_id, sta_id, tid);
1069 if (ret)
1070 return ret;
1071
1072 spin_lock_irqsave(&priv->sta_lock, flags);
1073 tid_data = &priv->stations[sta_id].tid[tid];
1074 if (tid_data->tfds_in_queue == 0) {
1075 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1076 tid_data->agg.state = IWL_AGG_ON;
1077 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1078 } else {
1079 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1080 tid_data->tfds_in_queue);
1081 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1082 }
1083 spin_unlock_irqrestore(&priv->sta_lock, flags);
1084 return ret;
1085 }
1086
1087 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1088 struct ieee80211_sta *sta, u16 tid)
1089 {
1090 int tx_fifo_id, txq_id, sta_id, ssn;
1091 struct iwl_tid_data *tid_data;
1092 int write_ptr, read_ptr;
1093 unsigned long flags;
1094
1095 tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1096 if (unlikely(tx_fifo_id < 0))
1097 return tx_fifo_id;
1098
1099 sta_id = iwl_sta_id(sta);
1100
1101 if (sta_id == IWL_INVALID_STATION) {
1102 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1103 return -ENXIO;
1104 }
1105
1106 spin_lock_irqsave(&priv->sta_lock, flags);
1107
1108 tid_data = &priv->stations[sta_id].tid[tid];
1109 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1110 txq_id = tid_data->agg.txq_id;
1111
1112 switch (priv->stations[sta_id].tid[tid].agg.state) {
1113 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1114 /*
1115 * This can happen if the peer stops aggregation
1116 * again before we've had a chance to drain the
1117 * queue we selected previously, i.e. before the
1118 * session was really started completely.
1119 */
1120 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1121 goto turn_off;
1122 case IWL_AGG_ON:
1123 break;
1124 default:
1125 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1126 }
1127
1128 write_ptr = priv->txq[txq_id].q.write_ptr;
1129 read_ptr = priv->txq[txq_id].q.read_ptr;
1130
1131 /* The queue is not empty */
1132 if (write_ptr != read_ptr) {
1133 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1134 priv->stations[sta_id].tid[tid].agg.state =
1135 IWL_EMPTYING_HW_QUEUE_DELBA;
1136 spin_unlock_irqrestore(&priv->sta_lock, flags);
1137 return 0;
1138 }
1139
1140 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1141 turn_off:
1142 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1143
1144 /* do not restore/save irqs */
1145 spin_unlock(&priv->sta_lock);
1146 spin_lock(&priv->lock);
1147
1148 /*
1149 * the only reason this call can fail is queue number out of range,
1150 * which can happen if uCode is reloaded and all the station
1151 * information are lost. if it is outside the range, there is no need
1152 * to deactivate the uCode queue, just return "success" to allow
1153 * mac80211 to clean up it own data.
1154 */
1155 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id);
1156 spin_unlock_irqrestore(&priv->lock, flags);
1157
1158 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1159
1160 return 0;
1161 }
1162
1163 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1164 int sta_id, u8 tid, int txq_id)
1165 {
1166 struct iwl_queue *q = &priv->txq[txq_id].q;
1167 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1168 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1169 struct iwl_rxon_context *ctx;
1170
1171 ctx = &priv->contexts[priv->stations[sta_id].ctxid];
1172
1173 lockdep_assert_held(&priv->sta_lock);
1174
1175 switch (priv->stations[sta_id].tid[tid].agg.state) {
1176 case IWL_EMPTYING_HW_QUEUE_DELBA:
1177 /* We are reclaiming the last packet of the */
1178 /* aggregated HW queue */
1179 if ((txq_id == tid_data->agg.txq_id) &&
1180 (q->read_ptr == q->write_ptr)) {
1181 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1182 int tx_fifo = get_fifo_from_tid(ctx, tid);
1183 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1184 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo);
1185 tid_data->agg.state = IWL_AGG_OFF;
1186 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1187 }
1188 break;
1189 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1190 /* We are reclaiming the last packet of the queue */
1191 if (tid_data->tfds_in_queue == 0) {
1192 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1193 tid_data->agg.state = IWL_AGG_ON;
1194 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1195 }
1196 break;
1197 }
1198
1199 return 0;
1200 }
1201
1202 static void iwlagn_non_agg_tx_status(struct iwl_priv *priv,
1203 struct iwl_rxon_context *ctx,
1204 const u8 *addr1)
1205 {
1206 struct ieee80211_sta *sta;
1207 struct iwl_station_priv *sta_priv;
1208
1209 rcu_read_lock();
1210 sta = ieee80211_find_sta(ctx->vif, addr1);
1211 if (sta) {
1212 sta_priv = (void *)sta->drv_priv;
1213 /* avoid atomic ops if this isn't a client */
1214 if (sta_priv->client &&
1215 atomic_dec_return(&sta_priv->pending_frames) == 0)
1216 ieee80211_sta_block_awake(priv->hw, sta, false);
1217 }
1218 rcu_read_unlock();
1219 }
1220
1221 static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info,
1222 bool is_agg)
1223 {
1224 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1225
1226 if (!is_agg)
1227 iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1);
1228
1229 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
1230 }
1231
1232 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1233 {
1234 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1235 struct iwl_queue *q = &txq->q;
1236 struct iwl_tx_info *tx_info;
1237 int nfreed = 0;
1238 struct ieee80211_hdr *hdr;
1239
1240 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1241 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1242 "is out of range [0-%d] %d %d.\n", txq_id,
1243 index, q->n_bd, q->write_ptr, q->read_ptr);
1244 return 0;
1245 }
1246
1247 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1248 q->read_ptr != index;
1249 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1250
1251 tx_info = &txq->txb[txq->q.read_ptr];
1252
1253 if (WARN_ON_ONCE(tx_info->skb == NULL))
1254 continue;
1255
1256 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1257 if (ieee80211_is_data_qos(hdr->frame_control))
1258 nfreed++;
1259
1260 iwlagn_tx_status(priv, tx_info,
1261 txq_id >= IWLAGN_FIRST_AMPDU_QUEUE);
1262 tx_info->skb = NULL;
1263
1264 iwlagn_txq_inval_byte_cnt_tbl(priv, txq);
1265
1266 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1267 }
1268 return nfreed;
1269 }
1270
1271 /**
1272 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1273 *
1274 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1275 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1276 */
1277 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1278 struct iwl_ht_agg *agg,
1279 struct iwl_compressed_ba_resp *ba_resp)
1280
1281 {
1282 int sh;
1283 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1284 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1285 struct ieee80211_tx_info *info;
1286 u64 bitmap, sent_bitmap;
1287
1288 if (unlikely(!agg->wait_for_ba)) {
1289 if (unlikely(ba_resp->bitmap))
1290 IWL_ERR(priv, "Received BA when not expected\n");
1291 return -EINVAL;
1292 }
1293
1294 /* Mark that the expected block-ack response arrived */
1295 agg->wait_for_ba = 0;
1296 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1297
1298 /* Calculate shift to align block-ack bits with our Tx window bits */
1299 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1300 if (sh < 0)
1301 sh += 0x100;
1302
1303 /*
1304 * Check for success or failure according to the
1305 * transmitted bitmap and block-ack bitmap
1306 */
1307 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1308 sent_bitmap = bitmap & agg->bitmap;
1309
1310 /* Sanity check values reported by uCode */
1311 if (ba_resp->txed_2_done > ba_resp->txed) {
1312 IWL_DEBUG_TX_REPLY(priv,
1313 "bogus sent(%d) and ack(%d) count\n",
1314 ba_resp->txed, ba_resp->txed_2_done);
1315 /*
1316 * set txed_2_done = txed,
1317 * so it won't impact rate scale
1318 */
1319 ba_resp->txed = ba_resp->txed_2_done;
1320 }
1321 IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
1322 ba_resp->txed, ba_resp->txed_2_done);
1323
1324 /* Find the first ACKed frame to store the TX status */
1325 while (sent_bitmap && !(sent_bitmap & 1)) {
1326 agg->start_idx = (agg->start_idx + 1) & 0xff;
1327 sent_bitmap >>= 1;
1328 }
1329
1330 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1331 memset(&info->status, 0, sizeof(info->status));
1332 info->flags |= IEEE80211_TX_STAT_ACK;
1333 info->flags |= IEEE80211_TX_STAT_AMPDU;
1334 info->status.ampdu_ack_len = ba_resp->txed_2_done;
1335 info->status.ampdu_len = ba_resp->txed;
1336 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1337
1338 return 0;
1339 }
1340
1341 /**
1342 * translate ucode response to mac80211 tx status control values
1343 */
1344 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1345 struct ieee80211_tx_info *info)
1346 {
1347 struct ieee80211_tx_rate *r = &info->control.rates[0];
1348
1349 info->antenna_sel_tx =
1350 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1351 if (rate_n_flags & RATE_MCS_HT_MSK)
1352 r->flags |= IEEE80211_TX_RC_MCS;
1353 if (rate_n_flags & RATE_MCS_GF_MSK)
1354 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1355 if (rate_n_flags & RATE_MCS_HT40_MSK)
1356 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1357 if (rate_n_flags & RATE_MCS_DUP_MSK)
1358 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1359 if (rate_n_flags & RATE_MCS_SGI_MSK)
1360 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1361 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1362 }
1363
1364 /**
1365 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1366 *
1367 * Handles block-acknowledge notification from device, which reports success
1368 * of frames sent via aggregation.
1369 */
1370 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1371 struct iwl_rx_mem_buffer *rxb)
1372 {
1373 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1374 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1375 struct iwl_tx_queue *txq = NULL;
1376 struct iwl_ht_agg *agg;
1377 int index;
1378 int sta_id;
1379 int tid;
1380 unsigned long flags;
1381
1382 /* "flow" corresponds to Tx queue */
1383 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1384
1385 /* "ssn" is start of block-ack Tx window, corresponds to index
1386 * (in Tx queue's circular buffer) of first TFD/frame in window */
1387 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1388
1389 if (scd_flow >= priv->hw_params.max_txq_num) {
1390 IWL_ERR(priv,
1391 "BUG_ON scd_flow is bigger than number of queues\n");
1392 return;
1393 }
1394
1395 txq = &priv->txq[scd_flow];
1396 sta_id = ba_resp->sta_id;
1397 tid = ba_resp->tid;
1398 agg = &priv->stations[sta_id].tid[tid].agg;
1399 if (unlikely(agg->txq_id != scd_flow)) {
1400 /*
1401 * FIXME: this is a uCode bug which need to be addressed,
1402 * log the information and return for now!
1403 * since it is possible happen very often and in order
1404 * not to fill the syslog, don't enable the logging by default
1405 */
1406 IWL_DEBUG_TX_REPLY(priv,
1407 "BA scd_flow %d does not match txq_id %d\n",
1408 scd_flow, agg->txq_id);
1409 return;
1410 }
1411
1412 /* Find index just before block-ack window */
1413 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1414
1415 spin_lock_irqsave(&priv->sta_lock, flags);
1416
1417 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1418 "sta_id = %d\n",
1419 agg->wait_for_ba,
1420 (u8 *) &ba_resp->sta_addr_lo32,
1421 ba_resp->sta_id);
1422 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1423 "%d, scd_ssn = %d\n",
1424 ba_resp->tid,
1425 ba_resp->seq_ctl,
1426 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1427 ba_resp->scd_flow,
1428 ba_resp->scd_ssn);
1429 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1430 agg->start_idx,
1431 (unsigned long long)agg->bitmap);
1432
1433 /* Update driver's record of ACK vs. not for each frame in window */
1434 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1435
1436 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1437 * block-ack window (we assume that they've been successfully
1438 * transmitted ... if not, it's too late anyway). */
1439 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1440 /* calculate mac80211 ampdu sw queue to wake */
1441 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1442 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1443
1444 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1445 priv->mac80211_registered &&
1446 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1447 iwl_wake_queue(priv, txq);
1448
1449 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1450 }
1451
1452 spin_unlock_irqrestore(&priv->sta_lock, flags);
1453 }
1454
1455 #ifdef CONFIG_IWLWIFI_DEBUG
1456 const char *iwl_get_tx_fail_reason(u32 status)
1457 {
1458 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
1459 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
1460
1461 switch (status & TX_STATUS_MSK) {
1462 case TX_STATUS_SUCCESS:
1463 return "SUCCESS";
1464 TX_STATUS_POSTPONE(DELAY);
1465 TX_STATUS_POSTPONE(FEW_BYTES);
1466 TX_STATUS_POSTPONE(BT_PRIO);
1467 TX_STATUS_POSTPONE(QUIET_PERIOD);
1468 TX_STATUS_POSTPONE(CALC_TTAK);
1469 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
1470 TX_STATUS_FAIL(SHORT_LIMIT);
1471 TX_STATUS_FAIL(LONG_LIMIT);
1472 TX_STATUS_FAIL(FIFO_UNDERRUN);
1473 TX_STATUS_FAIL(DRAIN_FLOW);
1474 TX_STATUS_FAIL(RFKILL_FLUSH);
1475 TX_STATUS_FAIL(LIFE_EXPIRE);
1476 TX_STATUS_FAIL(DEST_PS);
1477 TX_STATUS_FAIL(HOST_ABORTED);
1478 TX_STATUS_FAIL(BT_RETRY);
1479 TX_STATUS_FAIL(STA_INVALID);
1480 TX_STATUS_FAIL(FRAG_DROPPED);
1481 TX_STATUS_FAIL(TID_DISABLE);
1482 TX_STATUS_FAIL(FIFO_FLUSHED);
1483 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
1484 TX_STATUS_FAIL(PASSIVE_NO_RX);
1485 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
1486 }
1487
1488 return "UNKNOWN";
1489
1490 #undef TX_STATUS_FAIL
1491 #undef TX_STATUS_POSTPONE
1492 }
1493 #endif /* CONFIG_IWLWIFI_DEBUG */
Linux kernel - Deliverables
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