1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
42 static const s8 iwlagn_default_queue_to_tx_fifo
[] = {
55 static const s8 iwlagn_ipan_queue_to_tx_fifo
[] = {
68 static struct iwl_wimax_coex_event_entry cu_priorities
[COEX_NUM_OF_EVENTS
] = {
69 {COEX_CU_UNASSOC_IDLE_RP
, COEX_CU_UNASSOC_IDLE_WP
,
70 0, COEX_UNASSOC_IDLE_FLAGS
},
71 {COEX_CU_UNASSOC_MANUAL_SCAN_RP
, COEX_CU_UNASSOC_MANUAL_SCAN_WP
,
72 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS
},
73 {COEX_CU_UNASSOC_AUTO_SCAN_RP
, COEX_CU_UNASSOC_AUTO_SCAN_WP
,
74 0, COEX_UNASSOC_AUTO_SCAN_FLAGS
},
75 {COEX_CU_CALIBRATION_RP
, COEX_CU_CALIBRATION_WP
,
76 0, COEX_CALIBRATION_FLAGS
},
77 {COEX_CU_PERIODIC_CALIBRATION_RP
, COEX_CU_PERIODIC_CALIBRATION_WP
,
78 0, COEX_PERIODIC_CALIBRATION_FLAGS
},
79 {COEX_CU_CONNECTION_ESTAB_RP
, COEX_CU_CONNECTION_ESTAB_WP
,
80 0, COEX_CONNECTION_ESTAB_FLAGS
},
81 {COEX_CU_ASSOCIATED_IDLE_RP
, COEX_CU_ASSOCIATED_IDLE_WP
,
82 0, COEX_ASSOCIATED_IDLE_FLAGS
},
83 {COEX_CU_ASSOC_MANUAL_SCAN_RP
, COEX_CU_ASSOC_MANUAL_SCAN_WP
,
84 0, COEX_ASSOC_MANUAL_SCAN_FLAGS
},
85 {COEX_CU_ASSOC_AUTO_SCAN_RP
, COEX_CU_ASSOC_AUTO_SCAN_WP
,
86 0, COEX_ASSOC_AUTO_SCAN_FLAGS
},
87 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP
, COEX_CU_ASSOC_ACTIVE_LEVEL_WP
,
88 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS
},
89 {COEX_CU_RF_ON_RP
, COEX_CU_RF_ON_WP
, 0, COEX_CU_RF_ON_FLAGS
},
90 {COEX_CU_RF_OFF_RP
, COEX_CU_RF_OFF_WP
, 0, COEX_RF_OFF_FLAGS
},
91 {COEX_CU_STAND_ALONE_DEBUG_RP
, COEX_CU_STAND_ALONE_DEBUG_WP
,
92 0, COEX_STAND_ALONE_DEBUG_FLAGS
},
93 {COEX_CU_IPAN_ASSOC_LEVEL_RP
, COEX_CU_IPAN_ASSOC_LEVEL_WP
,
94 0, COEX_IPAN_ASSOC_LEVEL_FLAGS
},
95 {COEX_CU_RSRVD1_RP
, COEX_CU_RSRVD1_WP
, 0, COEX_RSRVD1_FLAGS
},
96 {COEX_CU_RSRVD2_RP
, COEX_CU_RSRVD2_WP
, 0, COEX_RSRVD2_FLAGS
}
102 static int iwlagn_load_section(struct iwl_priv
*priv
, const char *name
,
103 struct fw_desc
*image
, u32 dst_addr
)
105 dma_addr_t phy_addr
= image
->p_addr
;
106 u32 byte_cnt
= image
->len
;
109 priv
->ucode_write_complete
= 0;
111 iwl_write_direct32(priv
,
112 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
113 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
115 iwl_write_direct32(priv
,
116 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
118 iwl_write_direct32(priv
,
119 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
120 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
122 iwl_write_direct32(priv
,
123 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
124 (iwl_get_dma_hi_addr(phy_addr
)
125 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
127 iwl_write_direct32(priv
,
128 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
129 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
130 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
131 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
133 iwl_write_direct32(priv
,
134 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
135 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
136 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
137 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
139 IWL_DEBUG_INFO(priv
, "%s uCode section being loaded...\n", name
);
140 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
141 priv
->ucode_write_complete
, 5 * HZ
);
142 if (ret
== -ERESTARTSYS
) {
143 IWL_ERR(priv
, "Could not load the %s uCode section due "
144 "to interrupt\n", name
);
148 IWL_ERR(priv
, "Could not load the %s uCode section\n",
156 static int iwlagn_load_given_ucode(struct iwl_priv
*priv
,
157 struct fw_desc
*inst_image
,
158 struct fw_desc
*data_image
)
162 ret
= iwlagn_load_section(priv
, "INST", inst_image
,
163 IWLAGN_RTC_INST_LOWER_BOUND
);
167 return iwlagn_load_section(priv
, "DATA", data_image
,
168 IWLAGN_RTC_DATA_LOWER_BOUND
);
171 int iwlagn_load_ucode(struct iwl_priv
*priv
)
175 /* check whether init ucode should be loaded, or rather runtime ucode */
176 if (priv
->ucode_init
.len
&& (priv
->ucode_type
== UCODE_NONE
)) {
177 IWL_DEBUG_INFO(priv
, "Init ucode found. Loading init ucode...\n");
178 ret
= iwlagn_load_given_ucode(priv
,
179 &priv
->ucode_init
, &priv
->ucode_init_data
);
181 IWL_DEBUG_INFO(priv
, "Init ucode load complete.\n");
182 priv
->ucode_type
= UCODE_INIT
;
185 IWL_DEBUG_INFO(priv
, "Init ucode not found, or already loaded. "
186 "Loading runtime ucode...\n");
187 ret
= iwlagn_load_given_ucode(priv
,
188 &priv
->ucode_code
, &priv
->ucode_data
);
190 IWL_DEBUG_INFO(priv
, "Runtime ucode load complete.\n");
191 priv
->ucode_type
= UCODE_RT
;
201 static int iwlagn_set_Xtal_calib(struct iwl_priv
*priv
)
203 struct iwl_calib_xtal_freq_cmd cmd
;
205 (__le16
*)iwl_eeprom_query_addr(priv
, EEPROM_XTAL
);
207 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
;
208 cmd
.hdr
.first_group
= 0;
209 cmd
.hdr
.groups_num
= 1;
210 cmd
.hdr
.data_valid
= 1;
211 cmd
.cap_pin1
= le16_to_cpu(xtal_calib
[0]);
212 cmd
.cap_pin2
= le16_to_cpu(xtal_calib
[1]);
213 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_XTAL
],
214 (u8
*)&cmd
, sizeof(cmd
));
217 static int iwlagn_send_calib_cfg(struct iwl_priv
*priv
)
219 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
220 struct iwl_host_cmd cmd
= {
221 .id
= CALIBRATION_CFG_CMD
,
222 .len
= sizeof(struct iwl_calib_cfg_cmd
),
223 .data
= &calib_cfg_cmd
,
226 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
227 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
228 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
229 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
230 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
232 return iwl_send_cmd(priv
, &cmd
);
235 void iwlagn_rx_calib_result(struct iwl_priv
*priv
,
236 struct iwl_rx_mem_buffer
*rxb
)
238 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
239 struct iwl_calib_hdr
*hdr
= (struct iwl_calib_hdr
*)pkt
->u
.raw
;
240 int len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
243 /* reduce the size of the length field itself */
246 /* Define the order in which the results will be sent to the runtime
247 * uCode. iwl_send_calib_results sends them in a row according to
248 * their index. We sort them here
250 switch (hdr
->op_code
) {
251 case IWL_PHY_CALIBRATE_DC_CMD
:
252 index
= IWL_CALIB_DC
;
254 case IWL_PHY_CALIBRATE_LO_CMD
:
255 index
= IWL_CALIB_LO
;
257 case IWL_PHY_CALIBRATE_TX_IQ_CMD
:
258 index
= IWL_CALIB_TX_IQ
;
260 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
261 index
= IWL_CALIB_TX_IQ_PERD
;
263 case IWL_PHY_CALIBRATE_BASE_BAND_CMD
:
264 index
= IWL_CALIB_BASE_BAND
;
267 IWL_ERR(priv
, "Unknown calibration notification %d\n",
271 iwl_calib_set(&priv
->calib_results
[index
], pkt
->u
.raw
, len
);
274 void iwlagn_rx_calib_complete(struct iwl_priv
*priv
,
275 struct iwl_rx_mem_buffer
*rxb
)
277 IWL_DEBUG_INFO(priv
, "Init. calibration is completed, restarting fw.\n");
278 queue_work(priv
->workqueue
, &priv
->restart
);
281 void iwlagn_init_alive_start(struct iwl_priv
*priv
)
285 /* Check alive response for "valid" sign from uCode */
286 if (priv
->card_alive_init
.is_valid
!= UCODE_VALID_OK
) {
287 /* We had an error bringing up the hardware, so take it
288 * all the way back down so we can try again */
289 IWL_DEBUG_INFO(priv
, "Initialize Alive failed.\n");
293 /* initialize uCode was loaded... verify inst image.
294 * This is a paranoid check, because we would not have gotten the
295 * "initialize" alive if code weren't properly loaded. */
296 if (iwl_verify_ucode(priv
)) {
297 /* Runtime instruction load was bad;
298 * take it all the way back down so we can try again */
299 IWL_DEBUG_INFO(priv
, "Bad \"initialize\" uCode load.\n");
303 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
306 "Could not complete ALIVE transition: %d\n", ret
);
310 if (priv
->cfg
->advanced_bt_coexist
) {
312 * Tell uCode we are ready to perform calibration
313 * need to perform this before any calibration
314 * no need to close the envlope since we are going
315 * to load the runtime uCode later.
317 iwlagn_send_bt_env(priv
, IWL_BT_COEX_ENV_OPEN
,
318 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2
);
321 iwlagn_send_calib_cfg(priv
);
325 /* real restart (first load init_ucode) */
326 queue_work(priv
->workqueue
, &priv
->restart
);
329 static int iwlagn_send_wimax_coex(struct iwl_priv
*priv
)
331 struct iwl_wimax_coex_cmd coex_cmd
;
333 if (priv
->cfg
->support_wimax_coexist
) {
334 /* UnMask wake up src at associated sleep */
335 coex_cmd
.flags
= COEX_FLAGS_ASSOC_WA_UNMASK_MSK
;
337 /* UnMask wake up src at unassociated sleep */
338 coex_cmd
.flags
|= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK
;
339 memcpy(coex_cmd
.sta_prio
, cu_priorities
,
340 sizeof(struct iwl_wimax_coex_event_entry
) *
343 /* enabling the coexistence feature */
344 coex_cmd
.flags
|= COEX_FLAGS_COEX_ENABLE_MSK
;
346 /* enabling the priorities tables */
347 coex_cmd
.flags
|= COEX_FLAGS_STA_TABLE_VALID_MSK
;
349 /* coexistence is disabled */
350 memset(&coex_cmd
, 0, sizeof(coex_cmd
));
352 return iwl_send_cmd_pdu(priv
, COEX_PRIORITY_TABLE_CMD
,
353 sizeof(coex_cmd
), &coex_cmd
);
356 static const u8 iwlagn_bt_prio_tbl
[BT_COEX_PRIO_TBL_EVT_MAX
] = {
357 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
358 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
359 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
360 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
361 ((BT_COEX_PRIO_TBL_PRIO_LOW
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
362 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
363 ((BT_COEX_PRIO_TBL_PRIO_LOW
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
364 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
365 ((BT_COEX_PRIO_TBL_PRIO_HIGH
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
366 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
367 ((BT_COEX_PRIO_TBL_PRIO_HIGH
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
368 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
369 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
370 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
371 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
372 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
373 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
374 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
378 void iwlagn_send_prio_tbl(struct iwl_priv
*priv
)
380 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd
;
382 memcpy(prio_tbl_cmd
.prio_tbl
, iwlagn_bt_prio_tbl
,
383 sizeof(iwlagn_bt_prio_tbl
));
384 if (iwl_send_cmd_pdu(priv
, REPLY_BT_COEX_PRIO_TABLE
,
385 sizeof(prio_tbl_cmd
), &prio_tbl_cmd
))
386 IWL_ERR(priv
, "failed to send BT prio tbl command\n");
389 void iwlagn_send_bt_env(struct iwl_priv
*priv
, u8 action
, u8 type
)
391 struct iwl_bt_coex_prot_env_cmd env_cmd
;
393 env_cmd
.action
= action
;
395 if (iwl_send_cmd_pdu(priv
, REPLY_BT_COEX_PROT_ENV
,
396 sizeof(env_cmd
), &env_cmd
))
397 IWL_ERR(priv
, "failed to send BT env command\n");
401 int iwlagn_alive_notify(struct iwl_priv
*priv
)
409 spin_lock_irqsave(&priv
->lock
, flags
);
411 priv
->scd_base_addr
= iwl_read_prph(priv
, IWLAGN_SCD_SRAM_BASE_ADDR
);
412 a
= priv
->scd_base_addr
+ IWLAGN_SCD_CONTEXT_DATA_OFFSET
;
413 for (; a
< priv
->scd_base_addr
+ IWLAGN_SCD_TX_STTS_BITMAP_OFFSET
;
415 iwl_write_targ_mem(priv
, a
, 0);
416 for (; a
< priv
->scd_base_addr
+ IWLAGN_SCD_TRANSLATE_TBL_OFFSET
;
418 iwl_write_targ_mem(priv
, a
, 0);
419 for (; a
< priv
->scd_base_addr
+
420 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv
->hw_params
.max_txq_num
); a
+= 4)
421 iwl_write_targ_mem(priv
, a
, 0);
423 iwl_write_prph(priv
, IWLAGN_SCD_DRAM_BASE_ADDR
,
424 priv
->scd_bc_tbls
.dma
>> 10);
426 /* Enable DMA channel */
427 for (chan
= 0; chan
< FH50_TCSR_CHNL_NUM
; chan
++)
428 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
429 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
430 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
432 /* Update FH chicken bits */
433 reg_val
= iwl_read_direct32(priv
, FH_TX_CHICKEN_BITS_REG
);
434 iwl_write_direct32(priv
, FH_TX_CHICKEN_BITS_REG
,
435 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
437 iwl_write_prph(priv
, IWLAGN_SCD_QUEUECHAIN_SEL
,
438 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv
));
439 iwl_write_prph(priv
, IWLAGN_SCD_AGGR_SEL
, 0);
441 /* initiate the queues */
442 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++) {
443 iwl_write_prph(priv
, IWLAGN_SCD_QUEUE_RDPTR(i
), 0);
444 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
445 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
446 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
447 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
448 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i
) +
451 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
452 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
454 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
455 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
458 iwl_write_prph(priv
, IWLAGN_SCD_INTERRUPT_MASK
,
459 IWL_MASK(0, priv
->hw_params
.max_txq_num
));
461 /* Activate all Tx DMA/FIFO channels */
462 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, IWL_MASK(0, 7));
464 /* map queues to FIFOs */
465 if (priv
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
466 queues
= iwlagn_ipan_queue_to_tx_fifo
;
468 queues
= iwlagn_default_queue_to_tx_fifo
;
470 iwlagn_set_wr_ptrs(priv
, priv
->cmd_queue
, 0);
472 /* make sure all queue are not stopped */
473 memset(&priv
->queue_stopped
[0], 0, sizeof(priv
->queue_stopped
));
474 for (i
= 0; i
< 4; i
++)
475 atomic_set(&priv
->queue_stop_count
[i
], 0);
477 /* reset to 0 to enable all the queue first */
478 priv
->txq_ctx_active_msk
= 0;
480 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) != 10);
481 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) != 10);
483 for (i
= 0; i
< 10; i
++) {
486 iwl_txq_ctx_activate(priv
, i
);
488 if (ac
== IWL_TX_FIFO_UNUSED
)
491 iwlagn_tx_queue_set_status(priv
, &priv
->txq
[i
], ac
, 0);
494 spin_unlock_irqrestore(&priv
->lock
, flags
);
496 iwlagn_send_wimax_coex(priv
);
498 iwlagn_set_Xtal_calib(priv
);
499 iwl_send_calib_results(priv
);
506 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
507 * using sample data 100 bytes apart. If these sample points are good,
508 * it's a pretty good bet that everything between them is good, too.
510 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
, __le32
*image
, u32 len
)
517 IWL_DEBUG_INFO(priv
, "ucode inst image size is %u\n", len
);
519 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
520 /* read data comes through single port, auto-incr addr */
521 /* NOTE: Use the debugless read so we don't flood kernel log
522 * if IWL_DL_IO is set */
523 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
524 i
+ IWLAGN_RTC_INST_LOWER_BOUND
);
525 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
526 if (val
!= le32_to_cpu(*image
)) {
538 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
539 * looking at all data.
541 static int iwl_verify_inst_full(struct iwl_priv
*priv
, __le32
*image
,
549 IWL_DEBUG_INFO(priv
, "ucode inst image size is %u\n", len
);
551 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
552 IWLAGN_RTC_INST_LOWER_BOUND
);
555 for (; len
> 0; len
-= sizeof(u32
), image
++) {
556 /* read data comes through single port, auto-incr addr */
557 /* NOTE: Use the debugless read so we don't flood kernel log
558 * if IWL_DL_IO is set */
559 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
560 if (val
!= le32_to_cpu(*image
)) {
561 IWL_ERR(priv
, "uCode INST section is invalid at "
562 "offset 0x%x, is 0x%x, s/b 0x%x\n",
563 save_len
- len
, val
, le32_to_cpu(*image
));
573 "ucode image in INSTRUCTION memory is good\n");
579 * iwl_verify_ucode - determine which instruction image is in SRAM,
580 * and verify its contents
582 int iwl_verify_ucode(struct iwl_priv
*priv
)
589 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
590 len
= priv
->ucode_boot
.len
;
591 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
593 IWL_DEBUG_INFO(priv
, "Bootstrap uCode is good in inst SRAM\n");
598 image
= (__le32
*)priv
->ucode_init
.v_addr
;
599 len
= priv
->ucode_init
.len
;
600 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
602 IWL_DEBUG_INFO(priv
, "Initialize uCode is good in inst SRAM\n");
606 /* Try runtime/protocol */
607 image
= (__le32
*)priv
->ucode_code
.v_addr
;
608 len
= priv
->ucode_code
.len
;
609 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
611 IWL_DEBUG_INFO(priv
, "Runtime uCode is good in inst SRAM\n");
615 IWL_ERR(priv
, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
617 /* Since nothing seems to match, show first several data entries in
618 * instruction SRAM, so maybe visual inspection will give a clue.
619 * Selection of bootstrap image (vs. other images) is arbitrary. */
620 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
621 len
= priv
->ucode_boot
.len
;
622 ret
= iwl_verify_inst_full(priv
, image
, len
);