1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
41 #include "iwl-agn-calib.h"
42 #include "iwl-trans.h"
44 static struct iwl_wimax_coex_event_entry cu_priorities
[COEX_NUM_OF_EVENTS
] = {
45 {COEX_CU_UNASSOC_IDLE_RP
, COEX_CU_UNASSOC_IDLE_WP
,
46 0, COEX_UNASSOC_IDLE_FLAGS
},
47 {COEX_CU_UNASSOC_MANUAL_SCAN_RP
, COEX_CU_UNASSOC_MANUAL_SCAN_WP
,
48 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS
},
49 {COEX_CU_UNASSOC_AUTO_SCAN_RP
, COEX_CU_UNASSOC_AUTO_SCAN_WP
,
50 0, COEX_UNASSOC_AUTO_SCAN_FLAGS
},
51 {COEX_CU_CALIBRATION_RP
, COEX_CU_CALIBRATION_WP
,
52 0, COEX_CALIBRATION_FLAGS
},
53 {COEX_CU_PERIODIC_CALIBRATION_RP
, COEX_CU_PERIODIC_CALIBRATION_WP
,
54 0, COEX_PERIODIC_CALIBRATION_FLAGS
},
55 {COEX_CU_CONNECTION_ESTAB_RP
, COEX_CU_CONNECTION_ESTAB_WP
,
56 0, COEX_CONNECTION_ESTAB_FLAGS
},
57 {COEX_CU_ASSOCIATED_IDLE_RP
, COEX_CU_ASSOCIATED_IDLE_WP
,
58 0, COEX_ASSOCIATED_IDLE_FLAGS
},
59 {COEX_CU_ASSOC_MANUAL_SCAN_RP
, COEX_CU_ASSOC_MANUAL_SCAN_WP
,
60 0, COEX_ASSOC_MANUAL_SCAN_FLAGS
},
61 {COEX_CU_ASSOC_AUTO_SCAN_RP
, COEX_CU_ASSOC_AUTO_SCAN_WP
,
62 0, COEX_ASSOC_AUTO_SCAN_FLAGS
},
63 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP
, COEX_CU_ASSOC_ACTIVE_LEVEL_WP
,
64 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS
},
65 {COEX_CU_RF_ON_RP
, COEX_CU_RF_ON_WP
, 0, COEX_CU_RF_ON_FLAGS
},
66 {COEX_CU_RF_OFF_RP
, COEX_CU_RF_OFF_WP
, 0, COEX_RF_OFF_FLAGS
},
67 {COEX_CU_STAND_ALONE_DEBUG_RP
, COEX_CU_STAND_ALONE_DEBUG_WP
,
68 0, COEX_STAND_ALONE_DEBUG_FLAGS
},
69 {COEX_CU_IPAN_ASSOC_LEVEL_RP
, COEX_CU_IPAN_ASSOC_LEVEL_WP
,
70 0, COEX_IPAN_ASSOC_LEVEL_FLAGS
},
71 {COEX_CU_RSRVD1_RP
, COEX_CU_RSRVD1_WP
, 0, COEX_RSRVD1_FLAGS
},
72 {COEX_CU_RSRVD2_RP
, COEX_CU_RSRVD2_WP
, 0, COEX_RSRVD2_FLAGS
}
78 static int iwlagn_load_section(struct iwl_priv
*priv
, const char *name
,
79 struct fw_desc
*image
, u32 dst_addr
)
81 dma_addr_t phy_addr
= image
->p_addr
;
82 u32 byte_cnt
= image
->len
;
85 priv
->ucode_write_complete
= 0;
87 iwl_write_direct32(priv
,
88 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
89 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
91 iwl_write_direct32(priv
,
92 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
94 iwl_write_direct32(priv
,
95 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
96 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
98 iwl_write_direct32(priv
,
99 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
100 (iwl_get_dma_hi_addr(phy_addr
)
101 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
103 iwl_write_direct32(priv
,
104 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
105 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
106 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
107 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
109 iwl_write_direct32(priv
,
110 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
111 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
113 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
115 IWL_DEBUG_FW(priv
, "%s uCode section being loaded...\n", name
);
116 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
117 priv
->ucode_write_complete
, 5 * HZ
);
118 if (ret
== -ERESTARTSYS
) {
119 IWL_ERR(priv
, "Could not load the %s uCode section due "
120 "to interrupt\n", name
);
124 IWL_ERR(priv
, "Could not load the %s uCode section\n",
132 static int iwlagn_load_given_ucode(struct iwl_priv
*priv
,
133 struct fw_img
*image
)
137 ret
= iwlagn_load_section(priv
, "INST", &image
->code
,
138 IWLAGN_RTC_INST_LOWER_BOUND
);
142 return iwlagn_load_section(priv
, "DATA", &image
->data
,
143 IWLAGN_RTC_DATA_LOWER_BOUND
);
149 static int iwlagn_set_Xtal_calib(struct iwl_priv
*priv
)
151 struct iwl_calib_xtal_freq_cmd cmd
;
153 (__le16
*)iwl_eeprom_query_addr(priv
, EEPROM_XTAL
);
155 iwl_set_calib_hdr(&cmd
.hdr
, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
);
156 cmd
.cap_pin1
= le16_to_cpu(xtal_calib
[0]);
157 cmd
.cap_pin2
= le16_to_cpu(xtal_calib
[1]);
158 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_XTAL
],
159 (u8
*)&cmd
, sizeof(cmd
));
162 static int iwlagn_set_temperature_offset_calib(struct iwl_priv
*priv
)
164 struct iwl_calib_temperature_offset_cmd cmd
;
165 __le16
*offset_calib
=
166 (__le16
*)iwl_eeprom_query_addr(priv
, EEPROM_TEMPERATURE
);
168 memset(&cmd
, 0, sizeof(cmd
));
169 iwl_set_calib_hdr(&cmd
.hdr
, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD
);
170 cmd
.radio_sensor_offset
= le16_to_cpu(offset_calib
[1]);
171 if (!(cmd
.radio_sensor_offset
))
172 cmd
.radio_sensor_offset
= DEFAULT_RADIO_SENSOR_OFFSET
;
174 IWL_DEBUG_CALIB(priv
, "Radio sensor offset: %d\n",
175 cmd
.radio_sensor_offset
);
176 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_TEMP_OFFSET
],
177 (u8
*)&cmd
, sizeof(cmd
));
180 static int iwlagn_send_calib_cfg(struct iwl_priv
*priv
)
182 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
183 struct iwl_host_cmd cmd
= {
184 .id
= CALIBRATION_CFG_CMD
,
185 .len
= { sizeof(struct iwl_calib_cfg_cmd
), },
186 .data
= { &calib_cfg_cmd
, },
189 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
190 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
191 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
192 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
193 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
195 return trans_send_cmd(priv
, &cmd
);
198 void iwlagn_rx_calib_result(struct iwl_priv
*priv
,
199 struct iwl_rx_mem_buffer
*rxb
)
201 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
202 struct iwl_calib_hdr
*hdr
= (struct iwl_calib_hdr
*)pkt
->u
.raw
;
203 int len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
206 /* reduce the size of the length field itself */
209 /* Define the order in which the results will be sent to the runtime
210 * uCode. iwl_send_calib_results sends them in a row according to
211 * their index. We sort them here
213 switch (hdr
->op_code
) {
214 case IWL_PHY_CALIBRATE_DC_CMD
:
215 index
= IWL_CALIB_DC
;
217 case IWL_PHY_CALIBRATE_LO_CMD
:
218 index
= IWL_CALIB_LO
;
220 case IWL_PHY_CALIBRATE_TX_IQ_CMD
:
221 index
= IWL_CALIB_TX_IQ
;
223 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
224 index
= IWL_CALIB_TX_IQ_PERD
;
226 case IWL_PHY_CALIBRATE_BASE_BAND_CMD
:
227 index
= IWL_CALIB_BASE_BAND
;
230 IWL_ERR(priv
, "Unknown calibration notification %d\n",
234 iwl_calib_set(&priv
->calib_results
[index
], pkt
->u
.raw
, len
);
237 int iwlagn_init_alive_start(struct iwl_priv
*priv
)
241 if (priv
->cfg
->bt_params
&&
242 priv
->cfg
->bt_params
->advanced_bt_coexist
) {
244 * Tell uCode we are ready to perform calibration
245 * need to perform this before any calibration
246 * no need to close the envlope since we are going
247 * to load the runtime uCode later.
249 ret
= iwlagn_send_bt_env(priv
, IWL_BT_COEX_ENV_OPEN
,
250 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2
);
256 ret
= iwlagn_send_calib_cfg(priv
);
261 * temperature offset calibration is only needed for runtime ucode,
262 * so prepare the value now.
264 if (priv
->cfg
->need_temp_offset_calib
)
265 return iwlagn_set_temperature_offset_calib(priv
);
270 static int iwlagn_send_wimax_coex(struct iwl_priv
*priv
)
272 struct iwl_wimax_coex_cmd coex_cmd
;
274 if (priv
->cfg
->base_params
->support_wimax_coexist
) {
275 /* UnMask wake up src at associated sleep */
276 coex_cmd
.flags
= COEX_FLAGS_ASSOC_WA_UNMASK_MSK
;
278 /* UnMask wake up src at unassociated sleep */
279 coex_cmd
.flags
|= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK
;
280 memcpy(coex_cmd
.sta_prio
, cu_priorities
,
281 sizeof(struct iwl_wimax_coex_event_entry
) *
284 /* enabling the coexistence feature */
285 coex_cmd
.flags
|= COEX_FLAGS_COEX_ENABLE_MSK
;
287 /* enabling the priorities tables */
288 coex_cmd
.flags
|= COEX_FLAGS_STA_TABLE_VALID_MSK
;
290 /* coexistence is disabled */
291 memset(&coex_cmd
, 0, sizeof(coex_cmd
));
293 return trans_send_cmd_pdu(priv
,
294 COEX_PRIORITY_TABLE_CMD
, CMD_SYNC
,
295 sizeof(coex_cmd
), &coex_cmd
);
298 static const u8 iwlagn_bt_prio_tbl
[BT_COEX_PRIO_TBL_EVT_MAX
] = {
299 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
300 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
301 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
302 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
303 ((BT_COEX_PRIO_TBL_PRIO_LOW
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
304 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
305 ((BT_COEX_PRIO_TBL_PRIO_LOW
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
306 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
307 ((BT_COEX_PRIO_TBL_PRIO_HIGH
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
308 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
309 ((BT_COEX_PRIO_TBL_PRIO_HIGH
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
310 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
311 ((BT_COEX_PRIO_TBL_PRIO_BYPASS
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
312 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
313 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
314 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
315 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON
<< IWL_BT_COEX_PRIO_TBL_PRIO_POS
) |
316 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
)),
320 void iwlagn_send_prio_tbl(struct iwl_priv
*priv
)
322 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd
;
324 memcpy(prio_tbl_cmd
.prio_tbl
, iwlagn_bt_prio_tbl
,
325 sizeof(iwlagn_bt_prio_tbl
));
326 if (trans_send_cmd_pdu(priv
,
327 REPLY_BT_COEX_PRIO_TABLE
, CMD_SYNC
,
328 sizeof(prio_tbl_cmd
), &prio_tbl_cmd
))
329 IWL_ERR(priv
, "failed to send BT prio tbl command\n");
332 int iwlagn_send_bt_env(struct iwl_priv
*priv
, u8 action
, u8 type
)
334 struct iwl_bt_coex_prot_env_cmd env_cmd
;
337 env_cmd
.action
= action
;
339 ret
= trans_send_cmd_pdu(priv
,
340 REPLY_BT_COEX_PROT_ENV
, CMD_SYNC
,
341 sizeof(env_cmd
), &env_cmd
);
343 IWL_ERR(priv
, "failed to send BT env command\n");
348 static int iwlagn_alive_notify(struct iwl_priv
*priv
)
352 trans_tx_start(priv
);
354 ret
= iwlagn_send_wimax_coex(priv
);
358 ret
= iwlagn_set_Xtal_calib(priv
);
362 return iwl_send_calib_results(priv
);
367 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
368 * using sample data 100 bytes apart. If these sample points are good,
369 * it's a pretty good bet that everything between them is good, too.
371 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
,
372 struct fw_desc
*fw_desc
)
374 __le32
*image
= (__le32
*)fw_desc
->v_addr
;
375 u32 len
= fw_desc
->len
;
379 IWL_DEBUG_FW(priv
, "ucode inst image size is %u\n", len
);
381 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
382 /* read data comes through single port, auto-incr addr */
383 /* NOTE: Use the debugless read so we don't flood kernel log
384 * if IWL_DL_IO is set */
385 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
386 i
+ IWLAGN_RTC_INST_LOWER_BOUND
);
387 val
= iwl_read32(priv
, HBUS_TARG_MEM_RDAT
);
388 if (val
!= le32_to_cpu(*image
))
395 static void iwl_print_mismatch_inst(struct iwl_priv
*priv
,
396 struct fw_desc
*fw_desc
)
398 __le32
*image
= (__le32
*)fw_desc
->v_addr
;
399 u32 len
= fw_desc
->len
;
404 IWL_DEBUG_FW(priv
, "ucode inst image size is %u\n", len
);
406 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
407 IWLAGN_RTC_INST_LOWER_BOUND
);
410 offs
< len
&& errors
< 20;
411 offs
+= sizeof(u32
), image
++) {
412 /* read data comes through single port, auto-incr addr */
413 val
= iwl_read32(priv
, HBUS_TARG_MEM_RDAT
);
414 if (val
!= le32_to_cpu(*image
)) {
415 IWL_ERR(priv
, "uCode INST section at "
416 "offset 0x%x, is 0x%x, s/b 0x%x\n",
417 offs
, val
, le32_to_cpu(*image
));
424 * iwl_verify_ucode - determine which instruction image is in SRAM,
425 * and verify its contents
427 static int iwl_verify_ucode(struct iwl_priv
*priv
, struct fw_img
*img
)
429 if (!iwlcore_verify_inst_sparse(priv
, &img
->code
)) {
430 IWL_DEBUG_FW(priv
, "uCode is good in inst SRAM\n");
434 IWL_ERR(priv
, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
436 iwl_print_mismatch_inst(priv
, &img
->code
);
440 struct iwlagn_alive_data
{
445 static void iwlagn_alive_fn(struct iwl_priv
*priv
,
446 struct iwl_rx_packet
*pkt
,
449 struct iwlagn_alive_data
*alive_data
= data
;
450 struct iwl_alive_resp
*palive
;
452 palive
= &pkt
->u
.alive_frame
;
454 IWL_DEBUG_FW(priv
, "Alive ucode status 0x%08X revision "
456 palive
->is_valid
, palive
->ver_type
,
457 palive
->ver_subtype
);
459 priv
->device_pointers
.error_event_table
=
460 le32_to_cpu(palive
->error_event_table_ptr
);
461 priv
->device_pointers
.log_event_table
=
462 le32_to_cpu(palive
->log_event_table_ptr
);
464 alive_data
->subtype
= palive
->ver_subtype
;
465 alive_data
->valid
= palive
->is_valid
== UCODE_VALID_OK
;
468 #define UCODE_ALIVE_TIMEOUT HZ
469 #define UCODE_CALIB_TIMEOUT (2*HZ)
471 int iwlagn_load_ucode_wait_alive(struct iwl_priv
*priv
,
472 struct fw_img
*image
,
473 enum iwlagn_ucode_type ucode_type
)
475 struct iwl_notification_wait alive_wait
;
476 struct iwlagn_alive_data alive_data
;
478 enum iwlagn_ucode_type old_type
;
480 ret
= iwlagn_start_device(priv
);
484 iwlagn_init_notification_wait(priv
, &alive_wait
, REPLY_ALIVE
,
485 iwlagn_alive_fn
, &alive_data
);
487 old_type
= priv
->ucode_type
;
488 priv
->ucode_type
= ucode_type
;
490 ret
= iwlagn_load_given_ucode(priv
, image
);
492 priv
->ucode_type
= old_type
;
493 iwlagn_remove_notification(priv
, &alive_wait
);
497 /* Remove all resets to allow NIC to operate */
498 iwl_write32(priv
, CSR_RESET
, 0);
501 * Some things may run in the background now, but we
502 * just wait for the ALIVE notification here.
504 ret
= iwlagn_wait_notification(priv
, &alive_wait
, UCODE_ALIVE_TIMEOUT
);
506 priv
->ucode_type
= old_type
;
510 if (!alive_data
.valid
) {
511 IWL_ERR(priv
, "Loaded ucode is not valid!\n");
512 priv
->ucode_type
= old_type
;
516 ret
= iwl_verify_ucode(priv
, image
);
518 priv
->ucode_type
= old_type
;
522 /* delay a bit to give rfkill time to run */
525 ret
= iwlagn_alive_notify(priv
);
528 "Could not complete ALIVE transition: %d\n", ret
);
529 priv
->ucode_type
= old_type
;
536 int iwlagn_run_init_ucode(struct iwl_priv
*priv
)
538 struct iwl_notification_wait calib_wait
;
541 lockdep_assert_held(&priv
->mutex
);
543 /* No init ucode required? Curious, but maybe ok */
544 if (!priv
->ucode_init
.code
.len
)
547 if (priv
->ucode_type
!= IWL_UCODE_NONE
)
550 iwlagn_init_notification_wait(priv
, &calib_wait
,
551 CALIBRATION_COMPLETE_NOTIFICATION
,
554 /* Will also start the device */
555 ret
= iwlagn_load_ucode_wait_alive(priv
, &priv
->ucode_init
,
560 ret
= iwlagn_init_alive_start(priv
);
565 * Some things may run in the background now, but we
566 * just wait for the calibration complete notification.
568 ret
= iwlagn_wait_notification(priv
, &calib_wait
, UCODE_CALIB_TIMEOUT
);
573 iwlagn_remove_notification(priv
, &calib_wait
);
575 /* Whatever happened, stop the device */
576 trans_stop_device(priv
);