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iwlagn: prepare for new firmware file format
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h>
37 #include <linux/skbuff.h>
38 #include <linux/netdevice.h>
39 #include <linux/wireless.h>
40 #include <linux/firmware.h>
41 #include <linux/etherdevice.h>
42 #include <linux/if_arp.h>
43
44 #include <net/mac80211.h>
45
46 #include <asm/div64.h>
47
48 #define DRV_NAME "iwlagn"
49
50 #include "iwl-eeprom.h"
51 #include "iwl-dev.h"
52 #include "iwl-core.h"
53 #include "iwl-io.h"
54 #include "iwl-helpers.h"
55 #include "iwl-sta.h"
56 #include "iwl-calib.h"
57 #include "iwl-agn.h"
58
59
60 /******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66 /*
67 * module name, copyright, version, etc.
68 */
69 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
70
71 #ifdef CONFIG_IWLWIFI_DEBUG
72 #define VD "d"
73 #else
74 #define VD
75 #endif
76
77 #define DRV_VERSION IWLWIFI_VERSION VD
78
79
80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
81 MODULE_VERSION(DRV_VERSION);
82 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
83 MODULE_LICENSE("GPL");
84 MODULE_ALIAS("iwl4965");
85
86 /**
87 * iwl_commit_rxon - commit staging_rxon to hardware
88 *
89 * The RXON command in staging_rxon is committed to the hardware and
90 * the active_rxon structure is updated with the new data. This
91 * function correctly transitions out of the RXON_ASSOC_MSK state if
92 * a HW tune is required based on the RXON structure changes.
93 */
94 int iwl_commit_rxon(struct iwl_priv *priv)
95 {
96 /* cast away the const for active_rxon in this function */
97 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
98 int ret;
99 bool new_assoc =
100 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
101
102 if (!iwl_is_alive(priv))
103 return -EBUSY;
104
105 /* always get timestamp with Rx frame */
106 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
107
108 ret = iwl_check_rxon_cmd(priv);
109 if (ret) {
110 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
111 return -EINVAL;
112 }
113
114 /*
115 * receive commit_rxon request
116 * abort any previous channel switch if still in process
117 */
118 if (priv->switch_rxon.switch_in_progress &&
119 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
120 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
121 le16_to_cpu(priv->switch_rxon.channel));
122 priv->switch_rxon.switch_in_progress = false;
123 }
124
125 /* If we don't need to send a full RXON, we can use
126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
127 * and other flags for the current radio configuration. */
128 if (!iwl_full_rxon_required(priv)) {
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
132 return ret;
133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
136 iwl_print_rx_config_cmd(priv);
137 return 0;
138 }
139
140 /* If we are currently associated and the new config requires
141 * an RXON_ASSOC and the new config wants the associated mask enabled,
142 * we must clear the associated from the active configuration
143 * before we apply the new config */
144 if (iwl_is_associated(priv) && new_assoc) {
145 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
146 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
147
148 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
149 sizeof(struct iwl_rxon_cmd),
150 &priv->active_rxon);
151
152 /* If the mask clearing failed then we set
153 * active_rxon back to what it was previously */
154 if (ret) {
155 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
156 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
157 return ret;
158 }
159 iwl_clear_ucode_stations(priv, false);
160 iwl_restore_stations(priv);
161 ret = iwl_restore_default_wep_keys(priv);
162 if (ret) {
163 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
164 return ret;
165 }
166 }
167
168 IWL_DEBUG_INFO(priv, "Sending RXON\n"
169 "* with%s RXON_FILTER_ASSOC_MSK\n"
170 "* channel = %d\n"
171 "* bssid = %pM\n",
172 (new_assoc ? "" : "out"),
173 le16_to_cpu(priv->staging_rxon.channel),
174 priv->staging_rxon.bssid_addr);
175
176 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
177
178 /* Apply the new configuration
179 * RXON unassoc clears the station table in uCode so restoration of
180 * stations is needed after it (the RXON command) completes
181 */
182 if (!new_assoc) {
183 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
184 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
185 if (ret) {
186 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
187 return ret;
188 }
189 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
190 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
191 iwl_clear_ucode_stations(priv, false);
192 iwl_restore_stations(priv);
193 ret = iwl_restore_default_wep_keys(priv);
194 if (ret) {
195 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
196 return ret;
197 }
198 }
199
200 priv->start_calib = 0;
201 if (new_assoc) {
202 /*
203 * allow CTS-to-self if possible for new association.
204 * this is relevant only for 5000 series and up,
205 * but will not damage 4965
206 */
207 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
208
209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
219 }
220 iwl_print_rx_config_cmd(priv);
221
222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
229 return ret;
230 }
231
232 return 0;
233 }
234
235 void iwl_update_chain_flags(struct iwl_priv *priv)
236 {
237
238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
240 iwlcore_commit_rxon(priv);
241 }
242
243 static void iwl_clear_free_frames(struct iwl_priv *priv)
244 {
245 struct list_head *element;
246
247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
253 kfree(list_entry(element, struct iwl_frame, list));
254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262 }
263
264 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
265 {
266 struct iwl_frame *frame;
267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
271 IWL_ERR(priv, "Could not allocate frame!\n");
272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
281 return list_entry(element, struct iwl_frame, list);
282 }
283
284 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
285 {
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288 }
289
290 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
291 struct ieee80211_hdr *hdr,
292 int left)
293 {
294 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
295 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
296 (priv->iw_mode != NL80211_IFTYPE_AP)))
297 return 0;
298
299 if (priv->ibss_beacon->len > left)
300 return 0;
301
302 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
303
304 return priv->ibss_beacon->len;
305 }
306
307 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
308 static void iwl_set_beacon_tim(struct iwl_priv *priv,
309 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
310 u8 *beacon, u32 frame_size)
311 {
312 u16 tim_idx;
313 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
314
315 /*
316 * The index is relative to frame start but we start looking at the
317 * variable-length part of the beacon.
318 */
319 tim_idx = mgmt->u.beacon.variable - beacon;
320
321 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
322 while ((tim_idx < (frame_size - 2)) &&
323 (beacon[tim_idx] != WLAN_EID_TIM))
324 tim_idx += beacon[tim_idx+1] + 2;
325
326 /* If TIM field was found, set variables */
327 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
328 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
329 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
330 } else
331 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
332 }
333
334 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
335 struct iwl_frame *frame)
336 {
337 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
338 u32 frame_size;
339 u32 rate_flags;
340 u32 rate;
341 /*
342 * We have to set up the TX command, the TX Beacon command, and the
343 * beacon contents.
344 */
345
346 /* Initialize memory */
347 tx_beacon_cmd = &frame->u.beacon;
348 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
349
350 /* Set up TX beacon contents */
351 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
352 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
353 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
354 return 0;
355
356 /* Set up TX command fields */
357 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
358 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
359 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
360 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
361 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
362
363 /* Set up TX beacon command fields */
364 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
365 frame_size);
366
367 /* Set up packet rate and flags */
368 rate = iwl_rate_get_lowest_plcp(priv);
369 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
370 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
371 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
372 rate_flags |= RATE_MCS_CCK_MSK;
373 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
374 rate_flags);
375
376 return sizeof(*tx_beacon_cmd) + frame_size;
377 }
378 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
379 {
380 struct iwl_frame *frame;
381 unsigned int frame_size;
382 int rc;
383
384 frame = iwl_get_free_frame(priv);
385 if (!frame) {
386 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
387 "command.\n");
388 return -ENOMEM;
389 }
390
391 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
392 if (!frame_size) {
393 IWL_ERR(priv, "Error configuring the beacon command\n");
394 iwl_free_frame(priv, frame);
395 return -EINVAL;
396 }
397
398 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
399 &frame->u.cmd[0]);
400
401 iwl_free_frame(priv, frame);
402
403 return rc;
404 }
405
406 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
407 {
408 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
409
410 dma_addr_t addr = get_unaligned_le32(&tb->lo);
411 if (sizeof(dma_addr_t) > sizeof(u32))
412 addr |=
413 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
414
415 return addr;
416 }
417
418 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
419 {
420 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
421
422 return le16_to_cpu(tb->hi_n_len) >> 4;
423 }
424
425 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
426 dma_addr_t addr, u16 len)
427 {
428 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
429 u16 hi_n_len = len << 4;
430
431 put_unaligned_le32(addr, &tb->lo);
432 if (sizeof(dma_addr_t) > sizeof(u32))
433 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
434
435 tb->hi_n_len = cpu_to_le16(hi_n_len);
436
437 tfd->num_tbs = idx + 1;
438 }
439
440 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
441 {
442 return tfd->num_tbs & 0x1f;
443 }
444
445 /**
446 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
447 * @priv - driver private data
448 * @txq - tx queue
449 *
450 * Does NOT advance any TFD circular buffer read/write indexes
451 * Does NOT free the TFD itself (which is within circular buffer)
452 */
453 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
454 {
455 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
456 struct iwl_tfd *tfd;
457 struct pci_dev *dev = priv->pci_dev;
458 int index = txq->q.read_ptr;
459 int i;
460 int num_tbs;
461
462 tfd = &tfd_tmp[index];
463
464 /* Sanity check on number of chunks */
465 num_tbs = iwl_tfd_get_num_tbs(tfd);
466
467 if (num_tbs >= IWL_NUM_OF_TBS) {
468 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
469 /* @todo issue fatal error, it is quite serious situation */
470 return;
471 }
472
473 /* Unmap tx_cmd */
474 if (num_tbs)
475 pci_unmap_single(dev,
476 pci_unmap_addr(&txq->meta[index], mapping),
477 pci_unmap_len(&txq->meta[index], len),
478 PCI_DMA_BIDIRECTIONAL);
479
480 /* Unmap chunks, if any. */
481 for (i = 1; i < num_tbs; i++) {
482 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
483 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
484
485 if (txq->txb) {
486 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
487 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
488 }
489 }
490 }
491
492 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
493 struct iwl_tx_queue *txq,
494 dma_addr_t addr, u16 len,
495 u8 reset, u8 pad)
496 {
497 struct iwl_queue *q;
498 struct iwl_tfd *tfd, *tfd_tmp;
499 u32 num_tbs;
500
501 q = &txq->q;
502 tfd_tmp = (struct iwl_tfd *)txq->tfds;
503 tfd = &tfd_tmp[q->write_ptr];
504
505 if (reset)
506 memset(tfd, 0, sizeof(*tfd));
507
508 num_tbs = iwl_tfd_get_num_tbs(tfd);
509
510 /* Each TFD can point to a maximum 20 Tx buffers */
511 if (num_tbs >= IWL_NUM_OF_TBS) {
512 IWL_ERR(priv, "Error can not send more than %d chunks\n",
513 IWL_NUM_OF_TBS);
514 return -EINVAL;
515 }
516
517 BUG_ON(addr & ~DMA_BIT_MASK(36));
518 if (unlikely(addr & ~IWL_TX_DMA_MASK))
519 IWL_ERR(priv, "Unaligned address = %llx\n",
520 (unsigned long long)addr);
521
522 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
523
524 return 0;
525 }
526
527 /*
528 * Tell nic where to find circular buffer of Tx Frame Descriptors for
529 * given Tx queue, and enable the DMA channel used for that queue.
530 *
531 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
532 * channels supported in hardware.
533 */
534 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
535 struct iwl_tx_queue *txq)
536 {
537 int txq_id = txq->q.id;
538
539 /* Circular buffer (TFD queue in DRAM) physical base address */
540 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
541 txq->q.dma_addr >> 8);
542
543 return 0;
544 }
545
546 /******************************************************************************
547 *
548 * Generic RX handler implementations
549 *
550 ******************************************************************************/
551 static void iwl_rx_reply_alive(struct iwl_priv *priv,
552 struct iwl_rx_mem_buffer *rxb)
553 {
554 struct iwl_rx_packet *pkt = rxb_addr(rxb);
555 struct iwl_alive_resp *palive;
556 struct delayed_work *pwork;
557
558 palive = &pkt->u.alive_frame;
559
560 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
561 "0x%01X 0x%01X\n",
562 palive->is_valid, palive->ver_type,
563 palive->ver_subtype);
564
565 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
566 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
567 memcpy(&priv->card_alive_init,
568 &pkt->u.alive_frame,
569 sizeof(struct iwl_init_alive_resp));
570 pwork = &priv->init_alive_start;
571 } else {
572 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
573 memcpy(&priv->card_alive, &pkt->u.alive_frame,
574 sizeof(struct iwl_alive_resp));
575 pwork = &priv->alive_start;
576 }
577
578 /* We delay the ALIVE response by 5ms to
579 * give the HW RF Kill time to activate... */
580 if (palive->is_valid == UCODE_VALID_OK)
581 queue_delayed_work(priv->workqueue, pwork,
582 msecs_to_jiffies(5));
583 else
584 IWL_WARN(priv, "uCode did not respond OK.\n");
585 }
586
587 static void iwl_bg_beacon_update(struct work_struct *work)
588 {
589 struct iwl_priv *priv =
590 container_of(work, struct iwl_priv, beacon_update);
591 struct sk_buff *beacon;
592
593 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
594 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
595
596 if (!beacon) {
597 IWL_ERR(priv, "update beacon failed\n");
598 return;
599 }
600
601 mutex_lock(&priv->mutex);
602 /* new beacon skb is allocated every time; dispose previous.*/
603 if (priv->ibss_beacon)
604 dev_kfree_skb(priv->ibss_beacon);
605
606 priv->ibss_beacon = beacon;
607 mutex_unlock(&priv->mutex);
608
609 iwl_send_beacon_cmd(priv);
610 }
611
612 /**
613 * iwl_bg_statistics_periodic - Timer callback to queue statistics
614 *
615 * This callback is provided in order to send a statistics request.
616 *
617 * This timer function is continually reset to execute within
618 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
619 * was received. We need to ensure we receive the statistics in order
620 * to update the temperature used for calibrating the TXPOWER.
621 */
622 static void iwl_bg_statistics_periodic(unsigned long data)
623 {
624 struct iwl_priv *priv = (struct iwl_priv *)data;
625
626 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
627 return;
628
629 /* dont send host command if rf-kill is on */
630 if (!iwl_is_ready_rf(priv))
631 return;
632
633 iwl_send_statistics_request(priv, CMD_ASYNC, false);
634 }
635
636
637 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
638 u32 start_idx, u32 num_events,
639 u32 mode)
640 {
641 u32 i;
642 u32 ptr; /* SRAM byte address of log data */
643 u32 ev, time, data; /* event log data */
644 unsigned long reg_flags;
645
646 if (mode == 0)
647 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
648 else
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
650
651 /* Make sure device is powered up for SRAM reads */
652 spin_lock_irqsave(&priv->reg_lock, reg_flags);
653 if (iwl_grab_nic_access(priv)) {
654 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
655 return;
656 }
657
658 /* Set starting address; reads will auto-increment */
659 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
660 rmb();
661
662 /*
663 * "time" is actually "data" for mode 0 (no timestamp).
664 * place event id # at far right for easier visual parsing.
665 */
666 for (i = 0; i < num_events; i++) {
667 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
668 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 if (mode == 0) {
670 trace_iwlwifi_dev_ucode_cont_event(priv,
671 0, time, ev);
672 } else {
673 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
674 trace_iwlwifi_dev_ucode_cont_event(priv,
675 time, data, ev);
676 }
677 }
678 /* Allow device to power down */
679 iwl_release_nic_access(priv);
680 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
681 }
682
683 static void iwl_continuous_event_trace(struct iwl_priv *priv)
684 {
685 u32 capacity; /* event log capacity in # entries */
686 u32 base; /* SRAM byte address of event log header */
687 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
688 u32 num_wraps; /* # times uCode wrapped to top of log */
689 u32 next_entry; /* index of next entry to be written by uCode */
690
691 if (priv->ucode_type == UCODE_INIT)
692 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
693 else
694 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
695 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
696 capacity = iwl_read_targ_mem(priv, base);
697 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
698 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
699 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
700 } else
701 return;
702
703 if (num_wraps == priv->event_log.num_wraps) {
704 iwl_print_cont_event_trace(priv,
705 base, priv->event_log.next_entry,
706 next_entry - priv->event_log.next_entry,
707 mode);
708 priv->event_log.non_wraps_count++;
709 } else {
710 if ((num_wraps - priv->event_log.num_wraps) > 1)
711 priv->event_log.wraps_more_count++;
712 else
713 priv->event_log.wraps_once_count++;
714 trace_iwlwifi_dev_ucode_wrap_event(priv,
715 num_wraps - priv->event_log.num_wraps,
716 next_entry, priv->event_log.next_entry);
717 if (next_entry < priv->event_log.next_entry) {
718 iwl_print_cont_event_trace(priv, base,
719 priv->event_log.next_entry,
720 capacity - priv->event_log.next_entry,
721 mode);
722
723 iwl_print_cont_event_trace(priv, base, 0,
724 next_entry, mode);
725 } else {
726 iwl_print_cont_event_trace(priv, base,
727 next_entry, capacity - next_entry,
728 mode);
729
730 iwl_print_cont_event_trace(priv, base, 0,
731 next_entry, mode);
732 }
733 }
734 priv->event_log.num_wraps = num_wraps;
735 priv->event_log.next_entry = next_entry;
736 }
737
738 /**
739 * iwl_bg_ucode_trace - Timer callback to log ucode event
740 *
741 * The timer is continually set to execute every
742 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
743 * this function is to perform continuous uCode event logging operation
744 * if enabled
745 */
746 static void iwl_bg_ucode_trace(unsigned long data)
747 {
748 struct iwl_priv *priv = (struct iwl_priv *)data;
749
750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
751 return;
752
753 if (priv->event_log.ucode_trace) {
754 iwl_continuous_event_trace(priv);
755 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
756 mod_timer(&priv->ucode_trace,
757 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
758 }
759 }
760
761 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
762 struct iwl_rx_mem_buffer *rxb)
763 {
764 #ifdef CONFIG_IWLWIFI_DEBUG
765 struct iwl_rx_packet *pkt = rxb_addr(rxb);
766 struct iwl4965_beacon_notif *beacon =
767 (struct iwl4965_beacon_notif *)pkt->u.raw;
768 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
769
770 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
771 "tsf %d %d rate %d\n",
772 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf),
776 le32_to_cpu(beacon->low_tsf), rate);
777 #endif
778
779 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
780 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
781 queue_work(priv->workqueue, &priv->beacon_update);
782 }
783
784 /* Handle notification from uCode that card's power state is changing
785 * due to software, hardware, or critical temperature RFKILL */
786 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
787 struct iwl_rx_mem_buffer *rxb)
788 {
789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
790 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
791 unsigned long status = priv->status;
792
793 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
794 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
795 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & CT_CARD_DISABLED) ?
797 "Reached" : "Not reached");
798
799 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
800 CT_CARD_DISABLED)) {
801
802 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
804
805 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
806 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
807
808 if (!(flags & RXON_CARD_DISABLED)) {
809 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
810 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
811 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
812 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
813 }
814 if (flags & CT_CARD_DISABLED)
815 iwl_tt_enter_ct_kill(priv);
816 }
817 if (!(flags & CT_CARD_DISABLED))
818 iwl_tt_exit_ct_kill(priv);
819
820 if (flags & HW_CARD_DISABLED)
821 set_bit(STATUS_RF_KILL_HW, &priv->status);
822 else
823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
824
825
826 if (!(flags & RXON_CARD_DISABLED))
827 iwl_scan_cancel(priv);
828
829 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
830 test_bit(STATUS_RF_KILL_HW, &priv->status)))
831 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
832 test_bit(STATUS_RF_KILL_HW, &priv->status));
833 else
834 wake_up_interruptible(&priv->wait_command_queue);
835 }
836
837 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
838 {
839 if (src == IWL_PWR_SRC_VAUX) {
840 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
841 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
842 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
843 ~APMG_PS_CTRL_MSK_PWR_SRC);
844 } else {
845 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
846 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
847 ~APMG_PS_CTRL_MSK_PWR_SRC);
848 }
849
850 return 0;
851 }
852
853 /**
854 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
855 *
856 * Setup the RX handlers for each of the reply types sent from the uCode
857 * to the host.
858 *
859 * This function chains into the hardware specific files for them to setup
860 * any hardware specific handlers as well.
861 */
862 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
863 {
864 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
865 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
866 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
867 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
868 iwl_rx_spectrum_measure_notif;
869 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
870 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
871 iwl_rx_pm_debug_statistics_notif;
872 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
873
874 /*
875 * The same handler is used for both the REPLY to a discrete
876 * statistics request from the host as well as for the periodic
877 * statistics notifications (after received beacons) from the uCode.
878 */
879 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
880 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
881
882 iwl_setup_rx_scan_handlers(priv);
883
884 /* status change handler */
885 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
886
887 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
888 iwl_rx_missed_beacon_notif;
889 /* Rx handlers */
890 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
891 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
892 /* block ack */
893 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
894 /* Set up hardware specific Rx handlers */
895 priv->cfg->ops->lib->rx_handler_setup(priv);
896 }
897
898 /**
899 * iwl_rx_handle - Main entry function for receiving responses from uCode
900 *
901 * Uses the priv->rx_handlers callback function array to invoke
902 * the appropriate handlers, including command responses,
903 * frame-received notifications, and other notifications.
904 */
905 void iwl_rx_handle(struct iwl_priv *priv)
906 {
907 struct iwl_rx_mem_buffer *rxb;
908 struct iwl_rx_packet *pkt;
909 struct iwl_rx_queue *rxq = &priv->rxq;
910 u32 r, i;
911 int reclaim;
912 unsigned long flags;
913 u8 fill_rx = 0;
914 u32 count = 8;
915 int total_empty;
916
917 /* uCode's read index (stored in shared DRAM) indicates the last Rx
918 * buffer that the driver may process (last buffer filled by ucode). */
919 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
920 i = rxq->read;
921
922 /* Rx interrupt, but nothing sent from uCode */
923 if (i == r)
924 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
925
926 /* calculate total frames need to be restock after handling RX */
927 total_empty = r - rxq->write_actual;
928 if (total_empty < 0)
929 total_empty += RX_QUEUE_SIZE;
930
931 if (total_empty > (RX_QUEUE_SIZE / 2))
932 fill_rx = 1;
933
934 while (i != r) {
935 rxb = rxq->queue[i];
936
937 /* If an RXB doesn't have a Rx queue slot associated with it,
938 * then a bug has been introduced in the queue refilling
939 * routines -- catch it here */
940 BUG_ON(rxb == NULL);
941
942 rxq->queue[i] = NULL;
943
944 pci_unmap_page(priv->pci_dev, rxb->page_dma,
945 PAGE_SIZE << priv->hw_params.rx_page_order,
946 PCI_DMA_FROMDEVICE);
947 pkt = rxb_addr(rxb);
948
949 trace_iwlwifi_dev_rx(priv, pkt,
950 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
951
952 /* Reclaim a command buffer only if this packet is a response
953 * to a (driver-originated) command.
954 * If the packet (e.g. Rx frame) originated from uCode,
955 * there is no command buffer to reclaim.
956 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
957 * but apparently a few don't get set; catch them here. */
958 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
959 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
960 (pkt->hdr.cmd != REPLY_RX) &&
961 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
962 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
963 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
964 (pkt->hdr.cmd != REPLY_TX);
965
966 /* Based on type of command response or notification,
967 * handle those that need handling via function in
968 * rx_handlers table. See iwl_setup_rx_handlers() */
969 if (priv->rx_handlers[pkt->hdr.cmd]) {
970 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
971 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
972 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
973 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
974 } else {
975 /* No handling needed */
976 IWL_DEBUG_RX(priv,
977 "r %d i %d No handler needed for %s, 0x%02x\n",
978 r, i, get_cmd_string(pkt->hdr.cmd),
979 pkt->hdr.cmd);
980 }
981
982 /*
983 * XXX: After here, we should always check rxb->page
984 * against NULL before touching it or its virtual
985 * memory (pkt). Because some rx_handler might have
986 * already taken or freed the pages.
987 */
988
989 if (reclaim) {
990 /* Invoke any callbacks, transfer the buffer to caller,
991 * and fire off the (possibly) blocking iwl_send_cmd()
992 * as we reclaim the driver command queue */
993 if (rxb->page)
994 iwl_tx_cmd_complete(priv, rxb);
995 else
996 IWL_WARN(priv, "Claim null rxb?\n");
997 }
998
999 /* Reuse the page if possible. For notification packets and
1000 * SKBs that fail to Rx correctly, add them back into the
1001 * rx_free list for reuse later. */
1002 spin_lock_irqsave(&rxq->lock, flags);
1003 if (rxb->page != NULL) {
1004 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1005 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1006 PCI_DMA_FROMDEVICE);
1007 list_add_tail(&rxb->list, &rxq->rx_free);
1008 rxq->free_count++;
1009 } else
1010 list_add_tail(&rxb->list, &rxq->rx_used);
1011
1012 spin_unlock_irqrestore(&rxq->lock, flags);
1013
1014 i = (i + 1) & RX_QUEUE_MASK;
1015 /* If there are a lot of unused frames,
1016 * restock the Rx queue so ucode wont assert. */
1017 if (fill_rx) {
1018 count++;
1019 if (count >= 8) {
1020 rxq->read = i;
1021 iwlagn_rx_replenish_now(priv);
1022 count = 0;
1023 }
1024 }
1025 }
1026
1027 /* Backtrack one entry */
1028 rxq->read = i;
1029 if (fill_rx)
1030 iwlagn_rx_replenish_now(priv);
1031 else
1032 iwlagn_rx_queue_restock(priv);
1033 }
1034
1035 /* call this function to flush any scheduled tasklet */
1036 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1037 {
1038 /* wait to make sure we flush pending tasklet*/
1039 synchronize_irq(priv->pci_dev->irq);
1040 tasklet_kill(&priv->irq_tasklet);
1041 }
1042
1043 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1044 {
1045 u32 inta, handled = 0;
1046 u32 inta_fh;
1047 unsigned long flags;
1048 u32 i;
1049 #ifdef CONFIG_IWLWIFI_DEBUG
1050 u32 inta_mask;
1051 #endif
1052
1053 spin_lock_irqsave(&priv->lock, flags);
1054
1055 /* Ack/clear/reset pending uCode interrupts.
1056 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1057 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1058 inta = iwl_read32(priv, CSR_INT);
1059 iwl_write32(priv, CSR_INT, inta);
1060
1061 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1062 * Any new interrupts that happen after this, either while we're
1063 * in this tasklet, or later, will show up in next ISR/tasklet. */
1064 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1065 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1066
1067 #ifdef CONFIG_IWLWIFI_DEBUG
1068 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1069 /* just for debug */
1070 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1071 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1072 inta, inta_mask, inta_fh);
1073 }
1074 #endif
1075
1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
1078 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1079 * atomic, make sure that inta covers all the interrupts that
1080 * we've discovered, even if FH interrupt came in just after
1081 * reading CSR_INT. */
1082 if (inta_fh & CSR49_FH_INT_RX_MASK)
1083 inta |= CSR_INT_BIT_FH_RX;
1084 if (inta_fh & CSR49_FH_INT_TX_MASK)
1085 inta |= CSR_INT_BIT_FH_TX;
1086
1087 /* Now service all interrupt bits discovered above. */
1088 if (inta & CSR_INT_BIT_HW_ERR) {
1089 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1090
1091 /* Tell the device to stop sending interrupts */
1092 iwl_disable_interrupts(priv);
1093
1094 priv->isr_stats.hw++;
1095 iwl_irq_handle_error(priv);
1096
1097 handled |= CSR_INT_BIT_HW_ERR;
1098
1099 return;
1100 }
1101
1102 #ifdef CONFIG_IWLWIFI_DEBUG
1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1105 if (inta & CSR_INT_BIT_SCD) {
1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1107 "the frame/frames.\n");
1108 priv->isr_stats.sch++;
1109 }
1110
1111 /* Alive notification via Rx interrupt will do the real work */
1112 if (inta & CSR_INT_BIT_ALIVE) {
1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1114 priv->isr_stats.alive++;
1115 }
1116 }
1117 #endif
1118 /* Safely ignore these bits for debug checks below */
1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1120
1121 /* HW RF KILL switch toggled */
1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1129 hw_rf_kill ? "disable radio" : "enable radio");
1130
1131 priv->isr_stats.rfkill++;
1132
1133 /* driver only loads ucode once setting the interface up.
1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
1137 */
1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1144 }
1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
1149 /* Chip got too hot and stopped itself */
1150 if (inta & CSR_INT_BIT_CT_KILL) {
1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1152 priv->isr_stats.ctkill++;
1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
1162 iwl_irq_handle_error(priv);
1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
1166 /*
1167 * uCode wakes up after power-down sleep.
1168 * Tell device about any new tx or host commands enqueued,
1169 * and about any Rx buffers made available while asleep.
1170 */
1171 if (inta & CSR_INT_BIT_WAKEUP) {
1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1174 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1175 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1176 priv->isr_stats.wakeup++;
1177 handled |= CSR_INT_BIT_WAKEUP;
1178 }
1179
1180 /* All uCode command responses, including Tx command responses,
1181 * Rx "responses" (frame-received notification), and other
1182 * notifications from uCode come through here*/
1183 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1184 iwl_rx_handle(priv);
1185 priv->isr_stats.rx++;
1186 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1187 }
1188
1189 /* This "Tx" DMA channel is used only for loading uCode */
1190 if (inta & CSR_INT_BIT_FH_TX) {
1191 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1192 priv->isr_stats.tx++;
1193 handled |= CSR_INT_BIT_FH_TX;
1194 /* Wake up uCode load routine, now that load is complete */
1195 priv->ucode_write_complete = 1;
1196 wake_up_interruptible(&priv->wait_command_queue);
1197 }
1198
1199 if (inta & ~handled) {
1200 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1201 priv->isr_stats.unhandled++;
1202 }
1203
1204 if (inta & ~(priv->inta_mask)) {
1205 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1206 inta & ~priv->inta_mask);
1207 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1208 }
1209
1210 /* Re-enable all interrupts */
1211 /* only Re-enable if diabled by irq */
1212 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1213 iwl_enable_interrupts(priv);
1214
1215 #ifdef CONFIG_IWLWIFI_DEBUG
1216 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1217 inta = iwl_read32(priv, CSR_INT);
1218 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1219 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1220 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1221 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1222 }
1223 #endif
1224 }
1225
1226 /* tasklet for iwlagn interrupt */
1227 static void iwl_irq_tasklet(struct iwl_priv *priv)
1228 {
1229 u32 inta = 0;
1230 u32 handled = 0;
1231 unsigned long flags;
1232 u32 i;
1233 #ifdef CONFIG_IWLWIFI_DEBUG
1234 u32 inta_mask;
1235 #endif
1236
1237 spin_lock_irqsave(&priv->lock, flags);
1238
1239 /* Ack/clear/reset pending uCode interrupts.
1240 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1241 */
1242 /* There is a hardware bug in the interrupt mask function that some
1243 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1244 * they are disabled in the CSR_INT_MASK register. Furthermore the
1245 * ICT interrupt handling mechanism has another bug that might cause
1246 * these unmasked interrupts fail to be detected. We workaround the
1247 * hardware bugs here by ACKing all the possible interrupts so that
1248 * interrupt coalescing can still be achieved.
1249 */
1250 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1251
1252 inta = priv->_agn.inta;
1253
1254 #ifdef CONFIG_IWLWIFI_DEBUG
1255 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1256 /* just for debug */
1257 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1258 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1259 inta, inta_mask);
1260 }
1261 #endif
1262
1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
1265 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1266 priv->_agn.inta = 0;
1267
1268 /* Now service all interrupt bits discovered above. */
1269 if (inta & CSR_INT_BIT_HW_ERR) {
1270 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1271
1272 /* Tell the device to stop sending interrupts */
1273 iwl_disable_interrupts(priv);
1274
1275 priv->isr_stats.hw++;
1276 iwl_irq_handle_error(priv);
1277
1278 handled |= CSR_INT_BIT_HW_ERR;
1279
1280 return;
1281 }
1282
1283 #ifdef CONFIG_IWLWIFI_DEBUG
1284 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1285 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1286 if (inta & CSR_INT_BIT_SCD) {
1287 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1288 "the frame/frames.\n");
1289 priv->isr_stats.sch++;
1290 }
1291
1292 /* Alive notification via Rx interrupt will do the real work */
1293 if (inta & CSR_INT_BIT_ALIVE) {
1294 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1295 priv->isr_stats.alive++;
1296 }
1297 }
1298 #endif
1299 /* Safely ignore these bits for debug checks below */
1300 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1301
1302 /* HW RF KILL switch toggled */
1303 if (inta & CSR_INT_BIT_RF_KILL) {
1304 int hw_rf_kill = 0;
1305 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1306 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1307 hw_rf_kill = 1;
1308
1309 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1310 hw_rf_kill ? "disable radio" : "enable radio");
1311
1312 priv->isr_stats.rfkill++;
1313
1314 /* driver only loads ucode once setting the interface up.
1315 * the driver allows loading the ucode even if the radio
1316 * is killed. Hence update the killswitch state here. The
1317 * rfkill handler will care about restarting if needed.
1318 */
1319 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1320 if (hw_rf_kill)
1321 set_bit(STATUS_RF_KILL_HW, &priv->status);
1322 else
1323 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1324 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1325 }
1326
1327 handled |= CSR_INT_BIT_RF_KILL;
1328 }
1329
1330 /* Chip got too hot and stopped itself */
1331 if (inta & CSR_INT_BIT_CT_KILL) {
1332 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1333 priv->isr_stats.ctkill++;
1334 handled |= CSR_INT_BIT_CT_KILL;
1335 }
1336
1337 /* Error detected by uCode */
1338 if (inta & CSR_INT_BIT_SW_ERR) {
1339 IWL_ERR(priv, "Microcode SW error detected. "
1340 " Restarting 0x%X.\n", inta);
1341 priv->isr_stats.sw++;
1342 priv->isr_stats.sw_err = inta;
1343 iwl_irq_handle_error(priv);
1344 handled |= CSR_INT_BIT_SW_ERR;
1345 }
1346
1347 /* uCode wakes up after power-down sleep */
1348 if (inta & CSR_INT_BIT_WAKEUP) {
1349 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1350 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1351 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1352 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1353
1354 priv->isr_stats.wakeup++;
1355
1356 handled |= CSR_INT_BIT_WAKEUP;
1357 }
1358
1359 /* All uCode command responses, including Tx command responses,
1360 * Rx "responses" (frame-received notification), and other
1361 * notifications from uCode come through here*/
1362 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1363 CSR_INT_BIT_RX_PERIODIC)) {
1364 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1365 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1366 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1367 iwl_write32(priv, CSR_FH_INT_STATUS,
1368 CSR49_FH_INT_RX_MASK);
1369 }
1370 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1371 handled |= CSR_INT_BIT_RX_PERIODIC;
1372 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1373 }
1374 /* Sending RX interrupt require many steps to be done in the
1375 * the device:
1376 * 1- write interrupt to current index in ICT table.
1377 * 2- dma RX frame.
1378 * 3- update RX shared data to indicate last write index.
1379 * 4- send interrupt.
1380 * This could lead to RX race, driver could receive RX interrupt
1381 * but the shared data changes does not reflect this;
1382 * periodic interrupt will detect any dangling Rx activity.
1383 */
1384
1385 /* Disable periodic interrupt; we use it as just a one-shot. */
1386 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1387 CSR_INT_PERIODIC_DIS);
1388 iwl_rx_handle(priv);
1389
1390 /*
1391 * Enable periodic interrupt in 8 msec only if we received
1392 * real RX interrupt (instead of just periodic int), to catch
1393 * any dangling Rx interrupt. If it was just the periodic
1394 * interrupt, there was no dangling Rx activity, and no need
1395 * to extend the periodic interrupt; one-shot is enough.
1396 */
1397 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1399 CSR_INT_PERIODIC_ENA);
1400
1401 priv->isr_stats.rx++;
1402 }
1403
1404 /* This "Tx" DMA channel is used only for loading uCode */
1405 if (inta & CSR_INT_BIT_FH_TX) {
1406 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1407 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1408 priv->isr_stats.tx++;
1409 handled |= CSR_INT_BIT_FH_TX;
1410 /* Wake up uCode load routine, now that load is complete */
1411 priv->ucode_write_complete = 1;
1412 wake_up_interruptible(&priv->wait_command_queue);
1413 }
1414
1415 if (inta & ~handled) {
1416 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1417 priv->isr_stats.unhandled++;
1418 }
1419
1420 if (inta & ~(priv->inta_mask)) {
1421 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1422 inta & ~priv->inta_mask);
1423 }
1424
1425 /* Re-enable all interrupts */
1426 /* only Re-enable if diabled by irq */
1427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1428 iwl_enable_interrupts(priv);
1429 }
1430
1431 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1432 #define ACK_CNT_RATIO (50)
1433 #define BA_TIMEOUT_CNT (5)
1434 #define BA_TIMEOUT_MAX (16)
1435
1436 /**
1437 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1438 *
1439 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1440 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1441 * operation state.
1442 */
1443 bool iwl_good_ack_health(struct iwl_priv *priv,
1444 struct iwl_rx_packet *pkt)
1445 {
1446 bool rc = true;
1447 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1448 int ba_timeout_delta;
1449
1450 actual_ack_cnt_delta =
1451 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1452 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
1453 expected_ack_cnt_delta =
1454 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1455 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
1456 ba_timeout_delta =
1457 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1458 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
1459 if ((priv->_agn.agg_tids_count > 0) &&
1460 (expected_ack_cnt_delta > 0) &&
1461 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1462 < ACK_CNT_RATIO) &&
1463 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1464 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1465 " expected_ack_cnt = %d\n",
1466 actual_ack_cnt_delta, expected_ack_cnt_delta);
1467
1468 #ifdef CONFIG_IWLWIFI_DEBUG
1469 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1470 priv->delta_statistics.tx.rx_detected_cnt);
1471 IWL_DEBUG_RADIO(priv,
1472 "ack_or_ba_timeout_collision delta = %d\n",
1473 priv->delta_statistics.tx.
1474 ack_or_ba_timeout_collision);
1475 #endif
1476 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1477 ba_timeout_delta);
1478 if (!actual_ack_cnt_delta &&
1479 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1480 rc = false;
1481 }
1482 return rc;
1483 }
1484
1485
1486 /******************************************************************************
1487 *
1488 * uCode download functions
1489 *
1490 ******************************************************************************/
1491
1492 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1493 {
1494 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1500 }
1501
1502 static void iwl_nic_start(struct iwl_priv *priv)
1503 {
1504 /* Remove all resets to allow NIC to operate */
1505 iwl_write32(priv, CSR_RESET, 0);
1506 }
1507
1508
1509 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1510 static int iwl_mac_setup_register(struct iwl_priv *priv);
1511
1512 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1513 {
1514 const char *name_pre = priv->cfg->fw_name_pre;
1515
1516 if (first)
1517 priv->fw_index = priv->cfg->ucode_api_max;
1518 else
1519 priv->fw_index--;
1520
1521 if (priv->fw_index < priv->cfg->ucode_api_min) {
1522 IWL_ERR(priv, "no suitable firmware found!\n");
1523 return -ENOENT;
1524 }
1525
1526 sprintf(priv->firmware_name, "%s%d%s",
1527 name_pre, priv->fw_index, ".ucode");
1528
1529 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1530 priv->firmware_name);
1531
1532 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1533 &priv->pci_dev->dev, GFP_KERNEL, priv,
1534 iwl_ucode_callback);
1535 }
1536
1537 struct iwlagn_firmware_pieces {
1538 const void *inst, *data, *init, *init_data, *boot;
1539 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1540
1541 u32 build;
1542 };
1543
1544 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1545 const struct firmware *ucode_raw,
1546 struct iwlagn_firmware_pieces *pieces)
1547 {
1548 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1549 u32 api_ver, hdr_size;
1550 const u8 *src;
1551
1552 priv->ucode_ver = le32_to_cpu(ucode->ver);
1553 api_ver = IWL_UCODE_API(priv->ucode_ver);
1554
1555 switch (api_ver) {
1556 default:
1557 /*
1558 * 4965 doesn't revision the firmware file format
1559 * along with the API version, it always uses v1
1560 * file format.
1561 */
1562 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1563 CSR_HW_REV_TYPE_4965) {
1564 hdr_size = 28;
1565 if (ucode_raw->size < hdr_size) {
1566 IWL_ERR(priv, "File size too small!\n");
1567 return -EINVAL;
1568 }
1569 pieces->build = le32_to_cpu(ucode->u.v2.build);
1570 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1571 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1572 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1573 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1574 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1575 src = ucode->u.v2.data;
1576 break;
1577 }
1578 /* fall through for 4965 */
1579 case 0:
1580 case 1:
1581 case 2:
1582 hdr_size = 24;
1583 if (ucode_raw->size < hdr_size) {
1584 IWL_ERR(priv, "File size too small!\n");
1585 return -EINVAL;
1586 }
1587 pieces->build = 0;
1588 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1589 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1590 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1591 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1592 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1593 src = ucode->u.v1.data;
1594 break;
1595 }
1596
1597 /* Verify size of file vs. image size info in file's header */
1598 if (ucode_raw->size != hdr_size + pieces->inst_size +
1599 pieces->data_size + pieces->init_size +
1600 pieces->init_data_size + pieces->boot_size) {
1601
1602 IWL_ERR(priv,
1603 "uCode file size %d does not match expected size\n",
1604 (int)ucode_raw->size);
1605 return -EINVAL;
1606 }
1607
1608 pieces->inst = src;
1609 src += pieces->inst_size;
1610 pieces->data = src;
1611 src += pieces->data_size;
1612 pieces->init = src;
1613 src += pieces->init_size;
1614 pieces->init_data = src;
1615 src += pieces->init_data_size;
1616 pieces->boot = src;
1617 src += pieces->boot_size;
1618
1619 return 0;
1620 }
1621
1622 /**
1623 * iwl_ucode_callback - callback when firmware was loaded
1624 *
1625 * If loaded successfully, copies the firmware into buffers
1626 * for the card to fetch (via DMA).
1627 */
1628 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1629 {
1630 struct iwl_priv *priv = context;
1631 struct iwl_ucode_header *ucode;
1632 int err;
1633 struct iwlagn_firmware_pieces pieces;
1634 const unsigned int api_max = priv->cfg->ucode_api_max;
1635 const unsigned int api_min = priv->cfg->ucode_api_min;
1636 u32 api_ver;
1637 char buildstr[25];
1638 u32 build;
1639
1640 memset(&pieces, 0, sizeof(pieces));
1641
1642 if (!ucode_raw) {
1643 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1644 priv->firmware_name);
1645 goto try_again;
1646 }
1647
1648 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1649 priv->firmware_name, ucode_raw->size);
1650
1651 /* Make sure that we got at least the API version number */
1652 if (ucode_raw->size < 4) {
1653 IWL_ERR(priv, "File size way too small!\n");
1654 goto try_again;
1655 }
1656
1657 /* Data from ucode file: header followed by uCode images */
1658 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1659
1660 if (ucode->ver)
1661 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1662 else
1663 err = -EINVAL;
1664
1665 if (err)
1666 goto try_again;
1667
1668 api_ver = IWL_UCODE_API(priv->ucode_ver);
1669 build = pieces.build;
1670
1671 /*
1672 * api_ver should match the api version forming part of the
1673 * firmware filename ... but we don't check for that and only rely
1674 * on the API version read from firmware header from here on forward
1675 */
1676 if (api_ver < api_min || api_ver > api_max) {
1677 IWL_ERR(priv, "Driver unable to support your firmware API. "
1678 "Driver supports v%u, firmware is v%u.\n",
1679 api_max, api_ver);
1680 goto try_again;
1681 }
1682
1683 if (api_ver != api_max)
1684 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1685 "got v%u. New firmware can be obtained "
1686 "from http://www.intellinuxwireless.org.\n",
1687 api_max, api_ver);
1688
1689 if (build)
1690 sprintf(buildstr, " build %u", build);
1691 else
1692 buildstr[0] = '\0';
1693
1694 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1695 IWL_UCODE_MAJOR(priv->ucode_ver),
1696 IWL_UCODE_MINOR(priv->ucode_ver),
1697 IWL_UCODE_API(priv->ucode_ver),
1698 IWL_UCODE_SERIAL(priv->ucode_ver),
1699 buildstr);
1700
1701 snprintf(priv->hw->wiphy->fw_version,
1702 sizeof(priv->hw->wiphy->fw_version),
1703 "%u.%u.%u.%u%s",
1704 IWL_UCODE_MAJOR(priv->ucode_ver),
1705 IWL_UCODE_MINOR(priv->ucode_ver),
1706 IWL_UCODE_API(priv->ucode_ver),
1707 IWL_UCODE_SERIAL(priv->ucode_ver),
1708 buildstr);
1709
1710 /*
1711 * For any of the failures below (before allocating pci memory)
1712 * we will try to load a version with a smaller API -- maybe the
1713 * user just got a corrupted version of the latest API.
1714 */
1715
1716 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1717 priv->ucode_ver);
1718 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1719 pieces.inst_size);
1720 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1721 pieces.data_size);
1722 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1723 pieces.init_size);
1724 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1725 pieces.init_data_size);
1726 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1727 pieces.boot_size);
1728
1729 /* Verify that uCode images will fit in card's SRAM */
1730 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1731 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1732 pieces.inst_size);
1733 goto try_again;
1734 }
1735
1736 if (pieces.data_size > priv->hw_params.max_data_size) {
1737 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1738 pieces.data_size);
1739 goto try_again;
1740 }
1741
1742 if (pieces.init_size > priv->hw_params.max_inst_size) {
1743 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1744 pieces.init_size);
1745 goto try_again;
1746 }
1747
1748 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1749 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1750 pieces.init_data_size);
1751 goto try_again;
1752 }
1753
1754 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1755 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1756 pieces.boot_size);
1757 goto try_again;
1758 }
1759
1760
1761 /* Allocate ucode buffers for card's bus-master loading ... */
1762
1763 /* Runtime instructions and 2 copies of data:
1764 * 1) unmodified from disk
1765 * 2) backup cache for save/restore during power-downs */
1766 priv->ucode_code.len = pieces.inst_size;
1767 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1768
1769 priv->ucode_data.len = pieces.data_size;
1770 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1771
1772 priv->ucode_data_backup.len = pieces.data_size;
1773 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1774
1775 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1776 !priv->ucode_data_backup.v_addr)
1777 goto err_pci_alloc;
1778
1779 /* Initialization instructions and data */
1780 if (pieces.init_size && pieces.init_data_size) {
1781 priv->ucode_init.len = pieces.init_size;
1782 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1783
1784 priv->ucode_init_data.len = pieces.init_data_size;
1785 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1786
1787 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1788 goto err_pci_alloc;
1789 }
1790
1791 /* Bootstrap (instructions only, no data) */
1792 if (pieces.boot_size) {
1793 priv->ucode_boot.len = pieces.boot_size;
1794 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1795
1796 if (!priv->ucode_boot.v_addr)
1797 goto err_pci_alloc;
1798 }
1799
1800 /* Copy images into buffers for card's bus-master reads ... */
1801
1802 /* Runtime instructions (first block of data in file) */
1803 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1804 pieces.inst_size);
1805 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1806
1807 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1808 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1809
1810 /*
1811 * Runtime data
1812 * NOTE: Copy into backup buffer will be done in iwl_up()
1813 */
1814 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1815 pieces.data_size);
1816 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1817 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1818
1819 /* Initialization instructions */
1820 if (pieces.init_size) {
1821 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1822 pieces.init_size);
1823 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1824 }
1825
1826 /* Initialization data */
1827 if (pieces.init_data_size) {
1828 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1829 pieces.init_data_size);
1830 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1831 pieces.init_data_size);
1832 }
1833
1834 /* Bootstrap instructions */
1835 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1836 pieces.boot_size);
1837 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1838
1839 /**************************************************
1840 * This is still part of probe() in a sense...
1841 *
1842 * 9. Setup and register with mac80211 and debugfs
1843 **************************************************/
1844 err = iwl_mac_setup_register(priv);
1845 if (err)
1846 goto out_unbind;
1847
1848 err = iwl_dbgfs_register(priv, DRV_NAME);
1849 if (err)
1850 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1851
1852 /* We have our copies now, allow OS release its copies */
1853 release_firmware(ucode_raw);
1854 complete(&priv->_agn.firmware_loading_complete);
1855 return;
1856
1857 try_again:
1858 /* try next, if any */
1859 if (iwl_request_firmware(priv, false))
1860 goto out_unbind;
1861 release_firmware(ucode_raw);
1862 return;
1863
1864 err_pci_alloc:
1865 IWL_ERR(priv, "failed to allocate pci memory\n");
1866 iwl_dealloc_ucode_pci(priv);
1867 out_unbind:
1868 complete(&priv->_agn.firmware_loading_complete);
1869 device_release_driver(&priv->pci_dev->dev);
1870 release_firmware(ucode_raw);
1871 }
1872
1873 static const char *desc_lookup_text[] = {
1874 "OK",
1875 "FAIL",
1876 "BAD_PARAM",
1877 "BAD_CHECKSUM",
1878 "NMI_INTERRUPT_WDG",
1879 "SYSASSERT",
1880 "FATAL_ERROR",
1881 "BAD_COMMAND",
1882 "HW_ERROR_TUNE_LOCK",
1883 "HW_ERROR_TEMPERATURE",
1884 "ILLEGAL_CHAN_FREQ",
1885 "VCC_NOT_STABLE",
1886 "FH_ERROR",
1887 "NMI_INTERRUPT_HOST",
1888 "NMI_INTERRUPT_ACTION_PT",
1889 "NMI_INTERRUPT_UNKNOWN",
1890 "UCODE_VERSION_MISMATCH",
1891 "HW_ERROR_ABS_LOCK",
1892 "HW_ERROR_CAL_LOCK_FAIL",
1893 "NMI_INTERRUPT_INST_ACTION_PT",
1894 "NMI_INTERRUPT_DATA_ACTION_PT",
1895 "NMI_TRM_HW_ER",
1896 "NMI_INTERRUPT_TRM",
1897 "NMI_INTERRUPT_BREAK_POINT"
1898 "DEBUG_0",
1899 "DEBUG_1",
1900 "DEBUG_2",
1901 "DEBUG_3",
1902 "ADVANCED SYSASSERT"
1903 };
1904
1905 static const char *desc_lookup(int i)
1906 {
1907 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1908
1909 if (i < 0 || i > max)
1910 i = max;
1911
1912 return desc_lookup_text[i];
1913 }
1914
1915 #define ERROR_START_OFFSET (1 * sizeof(u32))
1916 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1917
1918 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1919 {
1920 u32 data2, line;
1921 u32 desc, time, count, base, data1;
1922 u32 blink1, blink2, ilink1, ilink2;
1923 u32 pc, hcmd;
1924
1925 if (priv->ucode_type == UCODE_INIT)
1926 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1927 else
1928 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1929
1930 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1931 IWL_ERR(priv,
1932 "Not valid error log pointer 0x%08X for %s uCode\n",
1933 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1934 return;
1935 }
1936
1937 count = iwl_read_targ_mem(priv, base);
1938
1939 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1940 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1941 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1942 priv->status, count);
1943 }
1944
1945 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1946 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1947 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1948 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1949 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1950 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1951 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1952 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1953 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1954 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1955 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1956
1957 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1958 blink1, blink2, ilink1, ilink2);
1959
1960 IWL_ERR(priv, "Desc Time "
1961 "data1 data2 line\n");
1962 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1963 desc_lookup(desc), desc, time, data1, data2, line);
1964 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1965 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1966 pc, blink1, blink2, ilink1, ilink2, hcmd);
1967 }
1968
1969 #define EVENT_START_OFFSET (4 * sizeof(u32))
1970
1971 /**
1972 * iwl_print_event_log - Dump error event log to syslog
1973 *
1974 */
1975 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1976 u32 num_events, u32 mode,
1977 int pos, char **buf, size_t bufsz)
1978 {
1979 u32 i;
1980 u32 base; /* SRAM byte address of event log header */
1981 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1982 u32 ptr; /* SRAM byte address of log data */
1983 u32 ev, time, data; /* event log data */
1984 unsigned long reg_flags;
1985
1986 if (num_events == 0)
1987 return pos;
1988 if (priv->ucode_type == UCODE_INIT)
1989 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1990 else
1991 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1992
1993 if (mode == 0)
1994 event_size = 2 * sizeof(u32);
1995 else
1996 event_size = 3 * sizeof(u32);
1997
1998 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1999
2000 /* Make sure device is powered up for SRAM reads */
2001 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2002 iwl_grab_nic_access(priv);
2003
2004 /* Set starting address; reads will auto-increment */
2005 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2006 rmb();
2007
2008 /* "time" is actually "data" for mode 0 (no timestamp).
2009 * place event id # at far right for easier visual parsing. */
2010 for (i = 0; i < num_events; i++) {
2011 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2012 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2013 if (mode == 0) {
2014 /* data, ev */
2015 if (bufsz) {
2016 pos += scnprintf(*buf + pos, bufsz - pos,
2017 "EVT_LOG:0x%08x:%04u\n",
2018 time, ev);
2019 } else {
2020 trace_iwlwifi_dev_ucode_event(priv, 0,
2021 time, ev);
2022 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2023 time, ev);
2024 }
2025 } else {
2026 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2027 if (bufsz) {
2028 pos += scnprintf(*buf + pos, bufsz - pos,
2029 "EVT_LOGT:%010u:0x%08x:%04u\n",
2030 time, data, ev);
2031 } else {
2032 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2033 time, data, ev);
2034 trace_iwlwifi_dev_ucode_event(priv, time,
2035 data, ev);
2036 }
2037 }
2038 }
2039
2040 /* Allow device to power down */
2041 iwl_release_nic_access(priv);
2042 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2043 return pos;
2044 }
2045
2046 /**
2047 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2048 */
2049 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2050 u32 num_wraps, u32 next_entry,
2051 u32 size, u32 mode,
2052 int pos, char **buf, size_t bufsz)
2053 {
2054 /*
2055 * display the newest DEFAULT_LOG_ENTRIES entries
2056 * i.e the entries just before the next ont that uCode would fill.
2057 */
2058 if (num_wraps) {
2059 if (next_entry < size) {
2060 pos = iwl_print_event_log(priv,
2061 capacity - (size - next_entry),
2062 size - next_entry, mode,
2063 pos, buf, bufsz);
2064 pos = iwl_print_event_log(priv, 0,
2065 next_entry, mode,
2066 pos, buf, bufsz);
2067 } else
2068 pos = iwl_print_event_log(priv, next_entry - size,
2069 size, mode, pos, buf, bufsz);
2070 } else {
2071 if (next_entry < size) {
2072 pos = iwl_print_event_log(priv, 0, next_entry,
2073 mode, pos, buf, bufsz);
2074 } else {
2075 pos = iwl_print_event_log(priv, next_entry - size,
2076 size, mode, pos, buf, bufsz);
2077 }
2078 }
2079 return pos;
2080 }
2081
2082 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2083
2084 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2085 char **buf, bool display)
2086 {
2087 u32 base; /* SRAM byte address of event log header */
2088 u32 capacity; /* event log capacity in # entries */
2089 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2090 u32 num_wraps; /* # times uCode wrapped to top of log */
2091 u32 next_entry; /* index of next entry to be written by uCode */
2092 u32 size; /* # entries that we'll print */
2093 int pos = 0;
2094 size_t bufsz = 0;
2095
2096 if (priv->ucode_type == UCODE_INIT)
2097 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2098 else
2099 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2100
2101 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2102 IWL_ERR(priv,
2103 "Invalid event log pointer 0x%08X for %s uCode\n",
2104 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2105 return -EINVAL;
2106 }
2107
2108 /* event log header */
2109 capacity = iwl_read_targ_mem(priv, base);
2110 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2111 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2112 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2113
2114 if (capacity > priv->cfg->max_event_log_size) {
2115 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2116 capacity, priv->cfg->max_event_log_size);
2117 capacity = priv->cfg->max_event_log_size;
2118 }
2119
2120 if (next_entry > priv->cfg->max_event_log_size) {
2121 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2122 next_entry, priv->cfg->max_event_log_size);
2123 next_entry = priv->cfg->max_event_log_size;
2124 }
2125
2126 size = num_wraps ? capacity : next_entry;
2127
2128 /* bail out if nothing in log */
2129 if (size == 0) {
2130 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2131 return pos;
2132 }
2133
2134 #ifdef CONFIG_IWLWIFI_DEBUG
2135 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2136 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2137 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2138 #else
2139 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2140 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2141 #endif
2142 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2143 size);
2144
2145 #ifdef CONFIG_IWLWIFI_DEBUG
2146 if (display) {
2147 if (full_log)
2148 bufsz = capacity * 48;
2149 else
2150 bufsz = size * 48;
2151 *buf = kmalloc(bufsz, GFP_KERNEL);
2152 if (!*buf)
2153 return -ENOMEM;
2154 }
2155 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2156 /*
2157 * if uCode has wrapped back to top of log,
2158 * start at the oldest entry,
2159 * i.e the next one that uCode would fill.
2160 */
2161 if (num_wraps)
2162 pos = iwl_print_event_log(priv, next_entry,
2163 capacity - next_entry, mode,
2164 pos, buf, bufsz);
2165 /* (then/else) start at top of log */
2166 pos = iwl_print_event_log(priv, 0,
2167 next_entry, mode, pos, buf, bufsz);
2168 } else
2169 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2170 next_entry, size, mode,
2171 pos, buf, bufsz);
2172 #else
2173 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2174 next_entry, size, mode,
2175 pos, buf, bufsz);
2176 #endif
2177 return pos;
2178 }
2179
2180 /**
2181 * iwl_alive_start - called after REPLY_ALIVE notification received
2182 * from protocol/runtime uCode (initialization uCode's
2183 * Alive gets handled by iwl_init_alive_start()).
2184 */
2185 static void iwl_alive_start(struct iwl_priv *priv)
2186 {
2187 int ret = 0;
2188
2189 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2190
2191 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2192 /* We had an error bringing up the hardware, so take it
2193 * all the way back down so we can try again */
2194 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2195 goto restart;
2196 }
2197
2198 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2199 * This is a paranoid check, because we would not have gotten the
2200 * "runtime" alive if code weren't properly loaded. */
2201 if (iwl_verify_ucode(priv)) {
2202 /* Runtime instruction load was bad;
2203 * take it all the way back down so we can try again */
2204 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2205 goto restart;
2206 }
2207
2208 ret = priv->cfg->ops->lib->alive_notify(priv);
2209 if (ret) {
2210 IWL_WARN(priv,
2211 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2212 goto restart;
2213 }
2214
2215 /* After the ALIVE response, we can send host commands to the uCode */
2216 set_bit(STATUS_ALIVE, &priv->status);
2217
2218 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2219 /* Enable timer to monitor the driver queues */
2220 mod_timer(&priv->monitor_recover,
2221 jiffies +
2222 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2223 }
2224
2225 if (iwl_is_rfkill(priv))
2226 return;
2227
2228 ieee80211_wake_queues(priv->hw);
2229
2230 priv->active_rate = IWL_RATES_MASK;
2231
2232 /* Configure Tx antenna selection based on H/W config */
2233 if (priv->cfg->ops->hcmd->set_tx_ant)
2234 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2235
2236 if (iwl_is_associated(priv)) {
2237 struct iwl_rxon_cmd *active_rxon =
2238 (struct iwl_rxon_cmd *)&priv->active_rxon;
2239 /* apply any changes in staging */
2240 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2241 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2242 } else {
2243 /* Initialize our rx_config data */
2244 iwl_connection_init_rx_config(priv, priv->iw_mode);
2245
2246 if (priv->cfg->ops->hcmd->set_rxon_chain)
2247 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2248
2249 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2250 }
2251
2252 /* Configure Bluetooth device coexistence support */
2253 priv->cfg->ops->hcmd->send_bt_config(priv);
2254
2255 iwl_reset_run_time_calib(priv);
2256
2257 /* Configure the adapter for unassociated operation */
2258 iwlcore_commit_rxon(priv);
2259
2260 /* At this point, the NIC is initialized and operational */
2261 iwl_rf_kill_ct_config(priv);
2262
2263 iwl_leds_init(priv);
2264
2265 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2266 set_bit(STATUS_READY, &priv->status);
2267 wake_up_interruptible(&priv->wait_command_queue);
2268
2269 iwl_power_update_mode(priv, true);
2270 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2271
2272
2273 return;
2274
2275 restart:
2276 queue_work(priv->workqueue, &priv->restart);
2277 }
2278
2279 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2280
2281 static void __iwl_down(struct iwl_priv *priv)
2282 {
2283 unsigned long flags;
2284 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2285
2286 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2287
2288 if (!exit_pending)
2289 set_bit(STATUS_EXIT_PENDING, &priv->status);
2290
2291 iwl_clear_ucode_stations(priv, true);
2292
2293 /* Unblock any waiting calls */
2294 wake_up_interruptible_all(&priv->wait_command_queue);
2295
2296 /* Wipe out the EXIT_PENDING status bit if we are not actually
2297 * exiting the module */
2298 if (!exit_pending)
2299 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2300
2301 /* stop and reset the on-board processor */
2302 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2303
2304 /* tell the device to stop sending interrupts */
2305 spin_lock_irqsave(&priv->lock, flags);
2306 iwl_disable_interrupts(priv);
2307 spin_unlock_irqrestore(&priv->lock, flags);
2308 iwl_synchronize_irq(priv);
2309
2310 if (priv->mac80211_registered)
2311 ieee80211_stop_queues(priv->hw);
2312
2313 /* If we have not previously called iwl_init() then
2314 * clear all bits but the RF Kill bit and return */
2315 if (!iwl_is_init(priv)) {
2316 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2317 STATUS_RF_KILL_HW |
2318 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2319 STATUS_GEO_CONFIGURED |
2320 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2321 STATUS_EXIT_PENDING;
2322 goto exit;
2323 }
2324
2325 /* ...otherwise clear out all the status bits but the RF Kill
2326 * bit and continue taking the NIC down. */
2327 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2328 STATUS_RF_KILL_HW |
2329 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2330 STATUS_GEO_CONFIGURED |
2331 test_bit(STATUS_FW_ERROR, &priv->status) <<
2332 STATUS_FW_ERROR |
2333 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2334 STATUS_EXIT_PENDING;
2335
2336 /* device going down, Stop using ICT table */
2337 iwl_disable_ict(priv);
2338
2339 iwlagn_txq_ctx_stop(priv);
2340 iwlagn_rxq_stop(priv);
2341
2342 /* Power-down device's busmaster DMA clocks */
2343 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2344 udelay(5);
2345
2346 /* Make sure (redundant) we've released our request to stay awake */
2347 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2348
2349 /* Stop the device, and put it in low power state */
2350 priv->cfg->ops->lib->apm_ops.stop(priv);
2351
2352 exit:
2353 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2354
2355 if (priv->ibss_beacon)
2356 dev_kfree_skb(priv->ibss_beacon);
2357 priv->ibss_beacon = NULL;
2358
2359 /* clear out any free frames */
2360 iwl_clear_free_frames(priv);
2361 }
2362
2363 static void iwl_down(struct iwl_priv *priv)
2364 {
2365 mutex_lock(&priv->mutex);
2366 __iwl_down(priv);
2367 mutex_unlock(&priv->mutex);
2368
2369 iwl_cancel_deferred_work(priv);
2370 }
2371
2372 #define HW_READY_TIMEOUT (50)
2373
2374 static int iwl_set_hw_ready(struct iwl_priv *priv)
2375 {
2376 int ret = 0;
2377
2378 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2379 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2380
2381 /* See if we got it */
2382 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2383 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2384 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2385 HW_READY_TIMEOUT);
2386 if (ret != -ETIMEDOUT)
2387 priv->hw_ready = true;
2388 else
2389 priv->hw_ready = false;
2390
2391 IWL_DEBUG_INFO(priv, "hardware %s\n",
2392 (priv->hw_ready == 1) ? "ready" : "not ready");
2393 return ret;
2394 }
2395
2396 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2397 {
2398 int ret = 0;
2399
2400 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2401
2402 ret = iwl_set_hw_ready(priv);
2403 if (priv->hw_ready)
2404 return ret;
2405
2406 /* If HW is not ready, prepare the conditions to check again */
2407 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2408 CSR_HW_IF_CONFIG_REG_PREPARE);
2409
2410 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2411 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2412 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2413
2414 /* HW should be ready by now, check again. */
2415 if (ret != -ETIMEDOUT)
2416 iwl_set_hw_ready(priv);
2417
2418 return ret;
2419 }
2420
2421 #define MAX_HW_RESTARTS 5
2422
2423 static int __iwl_up(struct iwl_priv *priv)
2424 {
2425 int i;
2426 int ret;
2427
2428 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2429 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2430 return -EIO;
2431 }
2432
2433 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2434 IWL_ERR(priv, "ucode not available for device bringup\n");
2435 return -EIO;
2436 }
2437
2438 iwl_prepare_card_hw(priv);
2439
2440 if (!priv->hw_ready) {
2441 IWL_WARN(priv, "Exit HW not ready\n");
2442 return -EIO;
2443 }
2444
2445 /* If platform's RF_KILL switch is NOT set to KILL */
2446 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2447 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2448 else
2449 set_bit(STATUS_RF_KILL_HW, &priv->status);
2450
2451 if (iwl_is_rfkill(priv)) {
2452 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2453
2454 iwl_enable_interrupts(priv);
2455 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2456 return 0;
2457 }
2458
2459 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2460
2461 ret = iwlagn_hw_nic_init(priv);
2462 if (ret) {
2463 IWL_ERR(priv, "Unable to init nic\n");
2464 return ret;
2465 }
2466
2467 /* make sure rfkill handshake bits are cleared */
2468 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2469 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2470 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2471
2472 /* clear (again), then enable host interrupts */
2473 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2474 iwl_enable_interrupts(priv);
2475
2476 /* really make sure rfkill handshake bits are cleared */
2477 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2478 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2479
2480 /* Copy original ucode data image from disk into backup cache.
2481 * This will be used to initialize the on-board processor's
2482 * data SRAM for a clean start when the runtime program first loads. */
2483 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2484 priv->ucode_data.len);
2485
2486 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2487
2488 /* load bootstrap state machine,
2489 * load bootstrap program into processor's memory,
2490 * prepare to load the "initialize" uCode */
2491 ret = priv->cfg->ops->lib->load_ucode(priv);
2492
2493 if (ret) {
2494 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2495 ret);
2496 continue;
2497 }
2498
2499 /* start card; "initialize" will load runtime ucode */
2500 iwl_nic_start(priv);
2501
2502 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2503
2504 return 0;
2505 }
2506
2507 set_bit(STATUS_EXIT_PENDING, &priv->status);
2508 __iwl_down(priv);
2509 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2510
2511 /* tried to restart and config the device for as long as our
2512 * patience could withstand */
2513 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2514 return -EIO;
2515 }
2516
2517
2518 /*****************************************************************************
2519 *
2520 * Workqueue callbacks
2521 *
2522 *****************************************************************************/
2523
2524 static void iwl_bg_init_alive_start(struct work_struct *data)
2525 {
2526 struct iwl_priv *priv =
2527 container_of(data, struct iwl_priv, init_alive_start.work);
2528
2529 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2530 return;
2531
2532 mutex_lock(&priv->mutex);
2533 priv->cfg->ops->lib->init_alive_start(priv);
2534 mutex_unlock(&priv->mutex);
2535 }
2536
2537 static void iwl_bg_alive_start(struct work_struct *data)
2538 {
2539 struct iwl_priv *priv =
2540 container_of(data, struct iwl_priv, alive_start.work);
2541
2542 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2543 return;
2544
2545 /* enable dram interrupt */
2546 iwl_reset_ict(priv);
2547
2548 mutex_lock(&priv->mutex);
2549 iwl_alive_start(priv);
2550 mutex_unlock(&priv->mutex);
2551 }
2552
2553 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2554 {
2555 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2556 run_time_calib_work);
2557
2558 mutex_lock(&priv->mutex);
2559
2560 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2561 test_bit(STATUS_SCANNING, &priv->status)) {
2562 mutex_unlock(&priv->mutex);
2563 return;
2564 }
2565
2566 if (priv->start_calib) {
2567 iwl_chain_noise_calibration(priv, &priv->statistics);
2568
2569 iwl_sensitivity_calibration(priv, &priv->statistics);
2570 }
2571
2572 mutex_unlock(&priv->mutex);
2573 return;
2574 }
2575
2576 static void iwl_bg_restart(struct work_struct *data)
2577 {
2578 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2579
2580 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2581 return;
2582
2583 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2584 mutex_lock(&priv->mutex);
2585 priv->vif = NULL;
2586 priv->is_open = 0;
2587 mutex_unlock(&priv->mutex);
2588 iwl_down(priv);
2589 ieee80211_restart_hw(priv->hw);
2590 } else {
2591 iwl_down(priv);
2592
2593 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2594 return;
2595
2596 mutex_lock(&priv->mutex);
2597 __iwl_up(priv);
2598 mutex_unlock(&priv->mutex);
2599 }
2600 }
2601
2602 static void iwl_bg_rx_replenish(struct work_struct *data)
2603 {
2604 struct iwl_priv *priv =
2605 container_of(data, struct iwl_priv, rx_replenish);
2606
2607 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2608 return;
2609
2610 mutex_lock(&priv->mutex);
2611 iwlagn_rx_replenish(priv);
2612 mutex_unlock(&priv->mutex);
2613 }
2614
2615 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2616
2617 void iwl_post_associate(struct iwl_priv *priv)
2618 {
2619 struct ieee80211_conf *conf = NULL;
2620 int ret = 0;
2621
2622 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2623 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2624 return;
2625 }
2626
2627 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2628 return;
2629
2630
2631 if (!priv->vif || !priv->is_open)
2632 return;
2633
2634 iwl_scan_cancel_timeout(priv, 200);
2635
2636 conf = ieee80211_get_hw_conf(priv->hw);
2637
2638 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2639 iwlcore_commit_rxon(priv);
2640
2641 iwl_setup_rxon_timing(priv);
2642 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2643 sizeof(priv->rxon_timing), &priv->rxon_timing);
2644 if (ret)
2645 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2646 "Attempting to continue.\n");
2647
2648 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2649
2650 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2651
2652 if (priv->cfg->ops->hcmd->set_rxon_chain)
2653 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2654
2655 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2656
2657 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2658 priv->assoc_id, priv->beacon_int);
2659
2660 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2661 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2662 else
2663 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2664
2665 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2666 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2667 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2668 else
2669 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2670
2671 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2672 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2673
2674 }
2675
2676 iwlcore_commit_rxon(priv);
2677
2678 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2679 priv->assoc_id, priv->active_rxon.bssid_addr);
2680
2681 switch (priv->iw_mode) {
2682 case NL80211_IFTYPE_STATION:
2683 break;
2684 case NL80211_IFTYPE_ADHOC:
2685 /* assume default assoc id */
2686 priv->assoc_id = 1;
2687 iwl_send_beacon_cmd(priv);
2688 break;
2689 default:
2690 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2691 __func__, priv->iw_mode);
2692 break;
2693 }
2694
2695 /* the chain noise calibration will enabled PM upon completion
2696 * If chain noise has already been run, then we need to enable
2697 * power management here */
2698 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2699 iwl_power_update_mode(priv, false);
2700
2701 /* Enable Rx differential gain and sensitivity calibrations */
2702 iwl_chain_noise_reset(priv);
2703 priv->start_calib = 1;
2704
2705 }
2706
2707 /*****************************************************************************
2708 *
2709 * mac80211 entry point functions
2710 *
2711 *****************************************************************************/
2712
2713 #define UCODE_READY_TIMEOUT (4 * HZ)
2714
2715 /*
2716 * Not a mac80211 entry point function, but it fits in with all the
2717 * other mac80211 functions grouped here.
2718 */
2719 static int iwl_mac_setup_register(struct iwl_priv *priv)
2720 {
2721 int ret;
2722 struct ieee80211_hw *hw = priv->hw;
2723 hw->rate_control_algorithm = "iwl-agn-rs";
2724
2725 /* Tell mac80211 our characteristics */
2726 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2727 IEEE80211_HW_AMPDU_AGGREGATION |
2728 IEEE80211_HW_SPECTRUM_MGMT;
2729
2730 if (!priv->cfg->broken_powersave)
2731 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2732 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2733
2734 if (priv->cfg->sku & IWL_SKU_N)
2735 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2736 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2737
2738 hw->sta_data_size = sizeof(struct iwl_station_priv);
2739 hw->wiphy->interface_modes =
2740 BIT(NL80211_IFTYPE_STATION) |
2741 BIT(NL80211_IFTYPE_ADHOC);
2742
2743 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2744 WIPHY_FLAG_DISABLE_BEACON_HINTS;
2745
2746 /*
2747 * For now, disable PS by default because it affects
2748 * RX performance significantly.
2749 */
2750 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2751
2752 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2753 /* we create the 802.11 header and a zero-length SSID element */
2754 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2755
2756 /* Default value; 4 EDCA QOS priorities */
2757 hw->queues = 4;
2758
2759 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2760
2761 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2762 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2763 &priv->bands[IEEE80211_BAND_2GHZ];
2764 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2765 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2766 &priv->bands[IEEE80211_BAND_5GHZ];
2767
2768 ret = ieee80211_register_hw(priv->hw);
2769 if (ret) {
2770 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2771 return ret;
2772 }
2773 priv->mac80211_registered = 1;
2774
2775 return 0;
2776 }
2777
2778
2779 static int iwl_mac_start(struct ieee80211_hw *hw)
2780 {
2781 struct iwl_priv *priv = hw->priv;
2782 int ret;
2783
2784 IWL_DEBUG_MAC80211(priv, "enter\n");
2785
2786 /* we should be verifying the device is ready to be opened */
2787 mutex_lock(&priv->mutex);
2788 ret = __iwl_up(priv);
2789 mutex_unlock(&priv->mutex);
2790
2791 if (ret)
2792 return ret;
2793
2794 if (iwl_is_rfkill(priv))
2795 goto out;
2796
2797 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2798
2799 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2800 * mac80211 will not be run successfully. */
2801 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2802 test_bit(STATUS_READY, &priv->status),
2803 UCODE_READY_TIMEOUT);
2804 if (!ret) {
2805 if (!test_bit(STATUS_READY, &priv->status)) {
2806 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2807 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2808 return -ETIMEDOUT;
2809 }
2810 }
2811
2812 iwl_led_start(priv);
2813
2814 out:
2815 priv->is_open = 1;
2816 IWL_DEBUG_MAC80211(priv, "leave\n");
2817 return 0;
2818 }
2819
2820 static void iwl_mac_stop(struct ieee80211_hw *hw)
2821 {
2822 struct iwl_priv *priv = hw->priv;
2823
2824 IWL_DEBUG_MAC80211(priv, "enter\n");
2825
2826 if (!priv->is_open)
2827 return;
2828
2829 priv->is_open = 0;
2830
2831 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2832 /* stop mac, cancel any scan request and clear
2833 * RXON_FILTER_ASSOC_MSK BIT
2834 */
2835 mutex_lock(&priv->mutex);
2836 iwl_scan_cancel_timeout(priv, 100);
2837 mutex_unlock(&priv->mutex);
2838 }
2839
2840 iwl_down(priv);
2841
2842 flush_workqueue(priv->workqueue);
2843
2844 /* enable interrupts again in order to receive rfkill changes */
2845 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2846 iwl_enable_interrupts(priv);
2847
2848 IWL_DEBUG_MAC80211(priv, "leave\n");
2849 }
2850
2851 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2852 {
2853 struct iwl_priv *priv = hw->priv;
2854
2855 IWL_DEBUG_MACDUMP(priv, "enter\n");
2856
2857 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2858 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2859
2860 if (iwlagn_tx_skb(priv, skb))
2861 dev_kfree_skb_any(skb);
2862
2863 IWL_DEBUG_MACDUMP(priv, "leave\n");
2864 return NETDEV_TX_OK;
2865 }
2866
2867 void iwl_config_ap(struct iwl_priv *priv)
2868 {
2869 int ret = 0;
2870
2871 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2872 return;
2873
2874 /* The following should be done only at AP bring up */
2875 if (!iwl_is_associated(priv)) {
2876
2877 /* RXON - unassoc (to set timing command) */
2878 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2879 iwlcore_commit_rxon(priv);
2880
2881 /* RXON Timing */
2882 iwl_setup_rxon_timing(priv);
2883 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2884 sizeof(priv->rxon_timing), &priv->rxon_timing);
2885 if (ret)
2886 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2887 "Attempting to continue.\n");
2888
2889 /* AP has all antennas */
2890 priv->chain_noise_data.active_chains =
2891 priv->hw_params.valid_rx_ant;
2892 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2893 if (priv->cfg->ops->hcmd->set_rxon_chain)
2894 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2895
2896 /* FIXME: what should be the assoc_id for AP? */
2897 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2898 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2899 priv->staging_rxon.flags |=
2900 RXON_FLG_SHORT_PREAMBLE_MSK;
2901 else
2902 priv->staging_rxon.flags &=
2903 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2904
2905 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2906 if (priv->assoc_capability &
2907 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2908 priv->staging_rxon.flags |=
2909 RXON_FLG_SHORT_SLOT_MSK;
2910 else
2911 priv->staging_rxon.flags &=
2912 ~RXON_FLG_SHORT_SLOT_MSK;
2913
2914 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2915 priv->staging_rxon.flags &=
2916 ~RXON_FLG_SHORT_SLOT_MSK;
2917 }
2918 /* restore RXON assoc */
2919 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2920 iwlcore_commit_rxon(priv);
2921 iwl_add_bcast_station(priv);
2922 }
2923 iwl_send_beacon_cmd(priv);
2924
2925 /* FIXME - we need to add code here to detect a totally new
2926 * configuration, reset the AP, unassoc, rxon timing, assoc,
2927 * clear sta table, add BCAST sta... */
2928 }
2929
2930 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2931 struct ieee80211_vif *vif,
2932 struct ieee80211_key_conf *keyconf,
2933 struct ieee80211_sta *sta,
2934 u32 iv32, u16 *phase1key)
2935 {
2936
2937 struct iwl_priv *priv = hw->priv;
2938 IWL_DEBUG_MAC80211(priv, "enter\n");
2939
2940 iwl_update_tkip_key(priv, keyconf,
2941 sta ? sta->addr : iwl_bcast_addr,
2942 iv32, phase1key);
2943
2944 IWL_DEBUG_MAC80211(priv, "leave\n");
2945 }
2946
2947 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2948 struct ieee80211_vif *vif,
2949 struct ieee80211_sta *sta,
2950 struct ieee80211_key_conf *key)
2951 {
2952 struct iwl_priv *priv = hw->priv;
2953 const u8 *addr;
2954 int ret;
2955 u8 sta_id;
2956 bool is_default_wep_key = false;
2957
2958 IWL_DEBUG_MAC80211(priv, "enter\n");
2959
2960 if (priv->cfg->mod_params->sw_crypto) {
2961 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2962 return -EOPNOTSUPP;
2963 }
2964 addr = sta ? sta->addr : iwl_bcast_addr;
2965 sta_id = iwl_find_station(priv, addr);
2966 if (sta_id == IWL_INVALID_STATION) {
2967 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2968 addr);
2969 return -EINVAL;
2970
2971 }
2972
2973 mutex_lock(&priv->mutex);
2974 iwl_scan_cancel_timeout(priv, 100);
2975
2976 /*
2977 * If we are getting WEP group key and we didn't receive any key mapping
2978 * so far, we are in legacy wep mode (group key only), otherwise we are
2979 * in 1X mode.
2980 * In legacy wep mode, we use another host command to the uCode.
2981 */
2982 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
2983 if (cmd == SET_KEY)
2984 is_default_wep_key = !priv->key_mapping_key;
2985 else
2986 is_default_wep_key =
2987 (key->hw_key_idx == HW_KEY_DEFAULT);
2988 }
2989
2990 switch (cmd) {
2991 case SET_KEY:
2992 if (is_default_wep_key)
2993 ret = iwl_set_default_wep_key(priv, key);
2994 else
2995 ret = iwl_set_dynamic_key(priv, key, sta_id);
2996
2997 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2998 break;
2999 case DISABLE_KEY:
3000 if (is_default_wep_key)
3001 ret = iwl_remove_default_wep_key(priv, key);
3002 else
3003 ret = iwl_remove_dynamic_key(priv, key, sta_id);
3004
3005 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3006 break;
3007 default:
3008 ret = -EINVAL;
3009 }
3010
3011 mutex_unlock(&priv->mutex);
3012 IWL_DEBUG_MAC80211(priv, "leave\n");
3013
3014 return ret;
3015 }
3016
3017 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3018 struct ieee80211_vif *vif,
3019 enum ieee80211_ampdu_mlme_action action,
3020 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3021 {
3022 struct iwl_priv *priv = hw->priv;
3023 int ret;
3024
3025 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3026 sta->addr, tid);
3027
3028 if (!(priv->cfg->sku & IWL_SKU_N))
3029 return -EACCES;
3030
3031 switch (action) {
3032 case IEEE80211_AMPDU_RX_START:
3033 IWL_DEBUG_HT(priv, "start Rx\n");
3034 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
3035 case IEEE80211_AMPDU_RX_STOP:
3036 IWL_DEBUG_HT(priv, "stop Rx\n");
3037 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
3038 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3039 return 0;
3040 else
3041 return ret;
3042 case IEEE80211_AMPDU_TX_START:
3043 IWL_DEBUG_HT(priv, "start Tx\n");
3044 ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
3045 if (ret == 0) {
3046 priv->_agn.agg_tids_count++;
3047 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3048 priv->_agn.agg_tids_count);
3049 }
3050 return ret;
3051 case IEEE80211_AMPDU_TX_STOP:
3052 IWL_DEBUG_HT(priv, "stop Tx\n");
3053 ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
3054 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3055 priv->_agn.agg_tids_count--;
3056 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3057 priv->_agn.agg_tids_count);
3058 }
3059 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3060 return 0;
3061 else
3062 return ret;
3063 case IEEE80211_AMPDU_TX_OPERATIONAL:
3064 /* do nothing */
3065 return -EOPNOTSUPP;
3066 default:
3067 IWL_DEBUG_HT(priv, "unknown\n");
3068 return -EINVAL;
3069 break;
3070 }
3071 return 0;
3072 }
3073
3074 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3075 struct ieee80211_vif *vif,
3076 enum sta_notify_cmd cmd,
3077 struct ieee80211_sta *sta)
3078 {
3079 struct iwl_priv *priv = hw->priv;
3080 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3081 int sta_id;
3082
3083 switch (cmd) {
3084 case STA_NOTIFY_SLEEP:
3085 WARN_ON(!sta_priv->client);
3086 sta_priv->asleep = true;
3087 if (atomic_read(&sta_priv->pending_frames) > 0)
3088 ieee80211_sta_block_awake(hw, sta, true);
3089 break;
3090 case STA_NOTIFY_AWAKE:
3091 WARN_ON(!sta_priv->client);
3092 if (!sta_priv->asleep)
3093 break;
3094 sta_priv->asleep = false;
3095 sta_id = iwl_find_station(priv, sta->addr);
3096 if (sta_id != IWL_INVALID_STATION)
3097 iwl_sta_modify_ps_wake(priv, sta_id);
3098 break;
3099 default:
3100 break;
3101 }
3102 }
3103
3104 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3105 struct ieee80211_vif *vif,
3106 struct ieee80211_sta *sta)
3107 {
3108 struct iwl_priv *priv = hw->priv;
3109 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3110 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
3111 int ret;
3112 u8 sta_id;
3113
3114 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3115 sta->addr);
3116
3117 atomic_set(&sta_priv->pending_frames, 0);
3118 if (vif->type == NL80211_IFTYPE_AP)
3119 sta_priv->client = true;
3120
3121 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3122 &sta_id);
3123 if (ret) {
3124 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3125 sta->addr, ret);
3126 /* Should we return success if return code is EEXIST ? */
3127 return ret;
3128 }
3129
3130 /* Initialize rate scaling */
3131 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3132 sta->addr);
3133 iwl_rs_rate_init(priv, sta, sta_id);
3134
3135 return ret;
3136 }
3137
3138 /*****************************************************************************
3139 *
3140 * sysfs attributes
3141 *
3142 *****************************************************************************/
3143
3144 #ifdef CONFIG_IWLWIFI_DEBUG
3145
3146 /*
3147 * The following adds a new attribute to the sysfs representation
3148 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
3149 * used for controlling the debug level.
3150 *
3151 * See the level definitions in iwl for details.
3152 *
3153 * The debug_level being managed using sysfs below is a per device debug
3154 * level that is used instead of the global debug level if it (the per
3155 * device debug level) is set.
3156 */
3157 static ssize_t show_debug_level(struct device *d,
3158 struct device_attribute *attr, char *buf)
3159 {
3160 struct iwl_priv *priv = dev_get_drvdata(d);
3161 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
3162 }
3163 static ssize_t store_debug_level(struct device *d,
3164 struct device_attribute *attr,
3165 const char *buf, size_t count)
3166 {
3167 struct iwl_priv *priv = dev_get_drvdata(d);
3168 unsigned long val;
3169 int ret;
3170
3171 ret = strict_strtoul(buf, 0, &val);
3172 if (ret)
3173 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
3174 else {
3175 priv->debug_level = val;
3176 if (iwl_alloc_traffic_mem(priv))
3177 IWL_ERR(priv,
3178 "Not enough memory to generate traffic log\n");
3179 }
3180 return strnlen(buf, count);
3181 }
3182
3183 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3184 show_debug_level, store_debug_level);
3185
3186
3187 #endif /* CONFIG_IWLWIFI_DEBUG */
3188
3189
3190 static ssize_t show_temperature(struct device *d,
3191 struct device_attribute *attr, char *buf)
3192 {
3193 struct iwl_priv *priv = dev_get_drvdata(d);
3194
3195 if (!iwl_is_alive(priv))
3196 return -EAGAIN;
3197
3198 return sprintf(buf, "%d\n", priv->temperature);
3199 }
3200
3201 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3202
3203 static ssize_t show_tx_power(struct device *d,
3204 struct device_attribute *attr, char *buf)
3205 {
3206 struct iwl_priv *priv = dev_get_drvdata(d);
3207
3208 if (!iwl_is_ready_rf(priv))
3209 return sprintf(buf, "off\n");
3210 else
3211 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
3212 }
3213
3214 static ssize_t store_tx_power(struct device *d,
3215 struct device_attribute *attr,
3216 const char *buf, size_t count)
3217 {
3218 struct iwl_priv *priv = dev_get_drvdata(d);
3219 unsigned long val;
3220 int ret;
3221
3222 ret = strict_strtoul(buf, 10, &val);
3223 if (ret)
3224 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
3225 else {
3226 ret = iwl_set_tx_power(priv, val, false);
3227 if (ret)
3228 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3229 ret);
3230 else
3231 ret = count;
3232 }
3233 return ret;
3234 }
3235
3236 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3237
3238 static ssize_t show_rts_ht_protection(struct device *d,
3239 struct device_attribute *attr, char *buf)
3240 {
3241 struct iwl_priv *priv = dev_get_drvdata(d);
3242
3243 return sprintf(buf, "%s\n",
3244 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3245 }
3246
3247 static ssize_t store_rts_ht_protection(struct device *d,
3248 struct device_attribute *attr,
3249 const char *buf, size_t count)
3250 {
3251 struct iwl_priv *priv = dev_get_drvdata(d);
3252 unsigned long val;
3253 int ret;
3254
3255 ret = strict_strtoul(buf, 10, &val);
3256 if (ret)
3257 IWL_INFO(priv, "Input is not in decimal form.\n");
3258 else {
3259 if (!iwl_is_associated(priv))
3260 priv->cfg->use_rts_for_ht = val ? true : false;
3261 else
3262 IWL_ERR(priv, "Sta associated with AP - "
3263 "Change protection mechanism is not allowed\n");
3264 ret = count;
3265 }
3266 return ret;
3267 }
3268
3269 static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3270 show_rts_ht_protection, store_rts_ht_protection);
3271
3272
3273 /*****************************************************************************
3274 *
3275 * driver setup and teardown
3276 *
3277 *****************************************************************************/
3278
3279 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3280 {
3281 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3282
3283 init_waitqueue_head(&priv->wait_command_queue);
3284
3285 INIT_WORK(&priv->restart, iwl_bg_restart);
3286 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3287 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3288 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3289 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3290 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3291
3292 iwl_setup_scan_deferred_work(priv);
3293
3294 if (priv->cfg->ops->lib->setup_deferred_work)
3295 priv->cfg->ops->lib->setup_deferred_work(priv);
3296
3297 init_timer(&priv->statistics_periodic);
3298 priv->statistics_periodic.data = (unsigned long)priv;
3299 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3300
3301 init_timer(&priv->ucode_trace);
3302 priv->ucode_trace.data = (unsigned long)priv;
3303 priv->ucode_trace.function = iwl_bg_ucode_trace;
3304
3305 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3306 init_timer(&priv->monitor_recover);
3307 priv->monitor_recover.data = (unsigned long)priv;
3308 priv->monitor_recover.function =
3309 priv->cfg->ops->lib->recover_from_tx_stall;
3310 }
3311
3312 if (!priv->cfg->use_isr_legacy)
3313 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3314 iwl_irq_tasklet, (unsigned long)priv);
3315 else
3316 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3317 iwl_irq_tasklet_legacy, (unsigned long)priv);
3318 }
3319
3320 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3321 {
3322 if (priv->cfg->ops->lib->cancel_deferred_work)
3323 priv->cfg->ops->lib->cancel_deferred_work(priv);
3324
3325 cancel_delayed_work_sync(&priv->init_alive_start);
3326 cancel_delayed_work(&priv->scan_check);
3327 cancel_work_sync(&priv->start_internal_scan);
3328 cancel_delayed_work(&priv->alive_start);
3329 cancel_work_sync(&priv->beacon_update);
3330 del_timer_sync(&priv->statistics_periodic);
3331 del_timer_sync(&priv->ucode_trace);
3332 if (priv->cfg->ops->lib->recover_from_tx_stall)
3333 del_timer_sync(&priv->monitor_recover);
3334 }
3335
3336 static void iwl_init_hw_rates(struct iwl_priv *priv,
3337 struct ieee80211_rate *rates)
3338 {
3339 int i;
3340
3341 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3342 rates[i].bitrate = iwl_rates[i].ieee * 5;
3343 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3344 rates[i].hw_value_short = i;
3345 rates[i].flags = 0;
3346 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3347 /*
3348 * If CCK != 1M then set short preamble rate flag.
3349 */
3350 rates[i].flags |=
3351 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3352 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3353 }
3354 }
3355 }
3356
3357 static int iwl_init_drv(struct iwl_priv *priv)
3358 {
3359 int ret;
3360
3361 priv->ibss_beacon = NULL;
3362
3363 spin_lock_init(&priv->sta_lock);
3364 spin_lock_init(&priv->hcmd_lock);
3365
3366 INIT_LIST_HEAD(&priv->free_frames);
3367
3368 mutex_init(&priv->mutex);
3369 mutex_init(&priv->sync_cmd_mutex);
3370
3371 priv->ieee_channels = NULL;
3372 priv->ieee_rates = NULL;
3373 priv->band = IEEE80211_BAND_2GHZ;
3374
3375 priv->iw_mode = NL80211_IFTYPE_STATION;
3376 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3377 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3378 priv->_agn.agg_tids_count = 0;
3379
3380 /* initialize force reset */
3381 priv->force_reset[IWL_RF_RESET].reset_duration =
3382 IWL_DELAY_NEXT_FORCE_RF_RESET;
3383 priv->force_reset[IWL_FW_RESET].reset_duration =
3384 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3385
3386 /* Choose which receivers/antennas to use */
3387 if (priv->cfg->ops->hcmd->set_rxon_chain)
3388 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3389
3390 iwl_init_scan_params(priv);
3391
3392 /* Set the tx_power_user_lmt to the lowest power level
3393 * this value will get overwritten by channel max power avg
3394 * from eeprom */
3395 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3396
3397 ret = iwl_init_channel_map(priv);
3398 if (ret) {
3399 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3400 goto err;
3401 }
3402
3403 ret = iwlcore_init_geos(priv);
3404 if (ret) {
3405 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3406 goto err_free_channel_map;
3407 }
3408 iwl_init_hw_rates(priv, priv->ieee_rates);
3409
3410 return 0;
3411
3412 err_free_channel_map:
3413 iwl_free_channel_map(priv);
3414 err:
3415 return ret;
3416 }
3417
3418 static void iwl_uninit_drv(struct iwl_priv *priv)
3419 {
3420 iwl_calib_free_results(priv);
3421 iwlcore_free_geos(priv);
3422 iwl_free_channel_map(priv);
3423 kfree(priv->scan_cmd);
3424 }
3425
3426 static struct attribute *iwl_sysfs_entries[] = {
3427 &dev_attr_temperature.attr,
3428 &dev_attr_tx_power.attr,
3429 &dev_attr_rts_ht_protection.attr,
3430 #ifdef CONFIG_IWLWIFI_DEBUG
3431 &dev_attr_debug_level.attr,
3432 #endif
3433 NULL
3434 };
3435
3436 static struct attribute_group iwl_attribute_group = {
3437 .name = NULL, /* put in device directory */
3438 .attrs = iwl_sysfs_entries,
3439 };
3440
3441 static struct ieee80211_ops iwl_hw_ops = {
3442 .tx = iwl_mac_tx,
3443 .start = iwl_mac_start,
3444 .stop = iwl_mac_stop,
3445 .add_interface = iwl_mac_add_interface,
3446 .remove_interface = iwl_mac_remove_interface,
3447 .config = iwl_mac_config,
3448 .configure_filter = iwl_configure_filter,
3449 .set_key = iwl_mac_set_key,
3450 .update_tkip_key = iwl_mac_update_tkip_key,
3451 .conf_tx = iwl_mac_conf_tx,
3452 .reset_tsf = iwl_mac_reset_tsf,
3453 .bss_info_changed = iwl_bss_info_changed,
3454 .ampdu_action = iwl_mac_ampdu_action,
3455 .hw_scan = iwl_mac_hw_scan,
3456 .sta_notify = iwl_mac_sta_notify,
3457 .sta_add = iwlagn_mac_sta_add,
3458 .sta_remove = iwl_mac_sta_remove,
3459 };
3460
3461 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3462 {
3463 int err = 0;
3464 struct iwl_priv *priv;
3465 struct ieee80211_hw *hw;
3466 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3467 unsigned long flags;
3468 u16 pci_cmd;
3469
3470 /************************
3471 * 1. Allocating HW data
3472 ************************/
3473
3474 /* Disabling hardware scan means that mac80211 will perform scans
3475 * "the hard way", rather than using device's scan. */
3476 if (cfg->mod_params->disable_hw_scan) {
3477 if (iwl_debug_level & IWL_DL_INFO)
3478 dev_printk(KERN_DEBUG, &(pdev->dev),
3479 "Disabling hw_scan\n");
3480 iwl_hw_ops.hw_scan = NULL;
3481 }
3482
3483 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3484 if (!hw) {
3485 err = -ENOMEM;
3486 goto out;
3487 }
3488 priv = hw->priv;
3489 /* At this point both hw and priv are allocated. */
3490
3491 SET_IEEE80211_DEV(hw, &pdev->dev);
3492
3493 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3494 priv->cfg = cfg;
3495 priv->pci_dev = pdev;
3496 priv->inta_mask = CSR_INI_SET_MASK;
3497
3498 #ifdef CONFIG_IWLWIFI_DEBUG
3499 atomic_set(&priv->restrict_refcnt, 0);
3500 #endif
3501 if (iwl_alloc_traffic_mem(priv))
3502 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3503
3504 /**************************
3505 * 2. Initializing PCI bus
3506 **************************/
3507 if (pci_enable_device(pdev)) {
3508 err = -ENODEV;
3509 goto out_ieee80211_free_hw;
3510 }
3511
3512 pci_set_master(pdev);
3513
3514 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3515 if (!err)
3516 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3517 if (err) {
3518 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3519 if (!err)
3520 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3521 /* both attempts failed: */
3522 if (err) {
3523 IWL_WARN(priv, "No suitable DMA available.\n");
3524 goto out_pci_disable_device;
3525 }
3526 }
3527
3528 err = pci_request_regions(pdev, DRV_NAME);
3529 if (err)
3530 goto out_pci_disable_device;
3531
3532 pci_set_drvdata(pdev, priv);
3533
3534
3535 /***********************
3536 * 3. Read REV register
3537 ***********************/
3538 priv->hw_base = pci_iomap(pdev, 0, 0);
3539 if (!priv->hw_base) {
3540 err = -ENODEV;
3541 goto out_pci_release_regions;
3542 }
3543
3544 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3545 (unsigned long long) pci_resource_len(pdev, 0));
3546 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3547
3548 /* these spin locks will be used in apm_ops.init and EEPROM access
3549 * we should init now
3550 */
3551 spin_lock_init(&priv->reg_lock);
3552 spin_lock_init(&priv->lock);
3553
3554 /*
3555 * stop and reset the on-board processor just in case it is in a
3556 * strange state ... like being left stranded by a primary kernel
3557 * and this is now the kdump kernel trying to start up
3558 */
3559 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3560
3561 iwl_hw_detect(priv);
3562 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3563 priv->cfg->name, priv->hw_rev);
3564
3565 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3566 * PCI Tx retries from interfering with C3 CPU state */
3567 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3568
3569 iwl_prepare_card_hw(priv);
3570 if (!priv->hw_ready) {
3571 IWL_WARN(priv, "Failed, HW not ready\n");
3572 goto out_iounmap;
3573 }
3574
3575 /*****************
3576 * 4. Read EEPROM
3577 *****************/
3578 /* Read the EEPROM */
3579 err = iwl_eeprom_init(priv);
3580 if (err) {
3581 IWL_ERR(priv, "Unable to init EEPROM\n");
3582 goto out_iounmap;
3583 }
3584 err = iwl_eeprom_check_version(priv);
3585 if (err)
3586 goto out_free_eeprom;
3587
3588 /* extract MAC Address */
3589 iwl_eeprom_get_mac(priv, priv->mac_addr);
3590 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3591 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3592
3593 /************************
3594 * 5. Setup HW constants
3595 ************************/
3596 if (iwl_set_hw_params(priv)) {
3597 IWL_ERR(priv, "failed to set hw parameters\n");
3598 goto out_free_eeprom;
3599 }
3600
3601 /*******************
3602 * 6. Setup priv
3603 *******************/
3604
3605 err = iwl_init_drv(priv);
3606 if (err)
3607 goto out_free_eeprom;
3608 /* At this point both hw and priv are initialized. */
3609
3610 /********************
3611 * 7. Setup services
3612 ********************/
3613 spin_lock_irqsave(&priv->lock, flags);
3614 iwl_disable_interrupts(priv);
3615 spin_unlock_irqrestore(&priv->lock, flags);
3616
3617 pci_enable_msi(priv->pci_dev);
3618
3619 iwl_alloc_isr_ict(priv);
3620 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3621 IRQF_SHARED, DRV_NAME, priv);
3622 if (err) {
3623 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3624 goto out_disable_msi;
3625 }
3626 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3627 if (err) {
3628 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3629 goto out_free_irq;
3630 }
3631
3632 iwl_setup_deferred_work(priv);
3633 iwl_setup_rx_handlers(priv);
3634
3635 /*********************************************
3636 * 8. Enable interrupts and read RFKILL state
3637 *********************************************/
3638
3639 /* enable interrupts if needed: hw bug w/a */
3640 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3641 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3642 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3643 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3644 }
3645
3646 iwl_enable_interrupts(priv);
3647
3648 /* If platform's RF_KILL switch is NOT set to KILL */
3649 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3650 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3651 else
3652 set_bit(STATUS_RF_KILL_HW, &priv->status);
3653
3654 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3655 test_bit(STATUS_RF_KILL_HW, &priv->status));
3656
3657 iwl_power_initialize(priv);
3658 iwl_tt_initialize(priv);
3659
3660 init_completion(&priv->_agn.firmware_loading_complete);
3661
3662 err = iwl_request_firmware(priv, true);
3663 if (err)
3664 goto out_remove_sysfs;
3665
3666 return 0;
3667
3668 out_remove_sysfs:
3669 destroy_workqueue(priv->workqueue);
3670 priv->workqueue = NULL;
3671 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3672 out_free_irq:
3673 free_irq(priv->pci_dev->irq, priv);
3674 iwl_free_isr_ict(priv);
3675 out_disable_msi:
3676 pci_disable_msi(priv->pci_dev);
3677 iwl_uninit_drv(priv);
3678 out_free_eeprom:
3679 iwl_eeprom_free(priv);
3680 out_iounmap:
3681 pci_iounmap(pdev, priv->hw_base);
3682 out_pci_release_regions:
3683 pci_set_drvdata(pdev, NULL);
3684 pci_release_regions(pdev);
3685 out_pci_disable_device:
3686 pci_disable_device(pdev);
3687 out_ieee80211_free_hw:
3688 iwl_free_traffic_mem(priv);
3689 ieee80211_free_hw(priv->hw);
3690 out:
3691 return err;
3692 }
3693
3694 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3695 {
3696 struct iwl_priv *priv = pci_get_drvdata(pdev);
3697 unsigned long flags;
3698
3699 if (!priv)
3700 return;
3701
3702 wait_for_completion(&priv->_agn.firmware_loading_complete);
3703
3704 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3705
3706 iwl_dbgfs_unregister(priv);
3707 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3708
3709 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3710 * to be called and iwl_down since we are removing the device
3711 * we need to set STATUS_EXIT_PENDING bit.
3712 */
3713 set_bit(STATUS_EXIT_PENDING, &priv->status);
3714 if (priv->mac80211_registered) {
3715 ieee80211_unregister_hw(priv->hw);
3716 priv->mac80211_registered = 0;
3717 } else {
3718 iwl_down(priv);
3719 }
3720
3721 /*
3722 * Make sure device is reset to low power before unloading driver.
3723 * This may be redundant with iwl_down(), but there are paths to
3724 * run iwl_down() without calling apm_ops.stop(), and there are
3725 * paths to avoid running iwl_down() at all before leaving driver.
3726 * This (inexpensive) call *makes sure* device is reset.
3727 */
3728 priv->cfg->ops->lib->apm_ops.stop(priv);
3729
3730 iwl_tt_exit(priv);
3731
3732 /* make sure we flush any pending irq or
3733 * tasklet for the driver
3734 */
3735 spin_lock_irqsave(&priv->lock, flags);
3736 iwl_disable_interrupts(priv);
3737 spin_unlock_irqrestore(&priv->lock, flags);
3738
3739 iwl_synchronize_irq(priv);
3740
3741 iwl_dealloc_ucode_pci(priv);
3742
3743 if (priv->rxq.bd)
3744 iwlagn_rx_queue_free(priv, &priv->rxq);
3745 iwlagn_hw_txq_ctx_free(priv);
3746
3747 iwl_eeprom_free(priv);
3748
3749
3750 /*netif_stop_queue(dev); */
3751 flush_workqueue(priv->workqueue);
3752
3753 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3754 * priv->workqueue... so we can't take down the workqueue
3755 * until now... */
3756 destroy_workqueue(priv->workqueue);
3757 priv->workqueue = NULL;
3758 iwl_free_traffic_mem(priv);
3759
3760 free_irq(priv->pci_dev->irq, priv);
3761 pci_disable_msi(priv->pci_dev);
3762 pci_iounmap(pdev, priv->hw_base);
3763 pci_release_regions(pdev);
3764 pci_disable_device(pdev);
3765 pci_set_drvdata(pdev, NULL);
3766
3767 iwl_uninit_drv(priv);
3768
3769 iwl_free_isr_ict(priv);
3770
3771 if (priv->ibss_beacon)
3772 dev_kfree_skb(priv->ibss_beacon);
3773
3774 ieee80211_free_hw(priv->hw);
3775 }
3776
3777
3778 /*****************************************************************************
3779 *
3780 * driver and module entry point
3781 *
3782 *****************************************************************************/
3783
3784 /* Hardware specific file defines the PCI IDs table for that hardware module */
3785 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3786 #ifdef CONFIG_IWL4965
3787 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3788 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3789 #endif /* CONFIG_IWL4965 */
3790 #ifdef CONFIG_IWL5000
3791 /* 5100 Series WiFi */
3792 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3793 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3794 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3795 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3796 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3797 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3798 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3799 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3800 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3801 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3802 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3803 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3804 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3805 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3806 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3807 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3808 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3809 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3810 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3811 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3812 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3813 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3814 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3815 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3816
3817 /* 5300 Series WiFi */
3818 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3819 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3820 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3821 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3822 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3823 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3824 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3825 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3826 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3827 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3828 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3829 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3830
3831 /* 5350 Series WiFi/WiMax */
3832 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3833 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3834 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3835
3836 /* 5150 Series Wifi/WiMax */
3837 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3838 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3839 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3840 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3841 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3842 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3843
3844 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3845 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3846 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3847 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3848
3849 /* 6x00 Series */
3850 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3851 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3852 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3853 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3854 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3855 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3856 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3857 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3858 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3859 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3860
3861 /* 6x00 Series Gen2a */
3862 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
3863 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
3864 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
3865
3866 /* 6x50 WiFi/WiMax Series */
3867 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3868 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3869 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3870 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3871 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3872 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3873
3874 /* 1000 Series WiFi */
3875 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3876 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3877 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3878 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3879 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3880 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3881 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3882 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3883 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3884 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3885 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3886 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3887 #endif /* CONFIG_IWL5000 */
3888
3889 {0}
3890 };
3891 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3892
3893 static struct pci_driver iwl_driver = {
3894 .name = DRV_NAME,
3895 .id_table = iwl_hw_card_ids,
3896 .probe = iwl_pci_probe,
3897 .remove = __devexit_p(iwl_pci_remove),
3898 #ifdef CONFIG_PM
3899 .suspend = iwl_pci_suspend,
3900 .resume = iwl_pci_resume,
3901 #endif
3902 };
3903
3904 static int __init iwl_init(void)
3905 {
3906
3907 int ret;
3908 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3909 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3910
3911 ret = iwlagn_rate_control_register();
3912 if (ret) {
3913 printk(KERN_ERR DRV_NAME
3914 "Unable to register rate control algorithm: %d\n", ret);
3915 return ret;
3916 }
3917
3918 ret = pci_register_driver(&iwl_driver);
3919 if (ret) {
3920 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3921 goto error_register;
3922 }
3923
3924 return ret;
3925
3926 error_register:
3927 iwlagn_rate_control_unregister();
3928 return ret;
3929 }
3930
3931 static void __exit iwl_exit(void)
3932 {
3933 pci_unregister_driver(&iwl_driver);
3934 iwlagn_rate_control_unregister();
3935 }
3936
3937 module_exit(iwl_exit);
3938 module_init(iwl_init);
3939
3940 #ifdef CONFIG_IWLWIFI_DEBUG
3941 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
3942 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3943 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
3944 MODULE_PARM_DESC(debug, "debug output mask");
3945 #endif
3946
3947 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
3948 MODULE_PARM_DESC(swcrypto50,
3949 "using crypto in software (default 0 [hardware]) (deprecated)");
3950 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
3951 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3952 module_param_named(queues_num50,
3953 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3954 MODULE_PARM_DESC(queues_num50,
3955 "number of hw queues in 50xx series (deprecated)");
3956 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3957 MODULE_PARM_DESC(queues_num, "number of hw queues.");
3958 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3959 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
3960 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3961 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3962 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
3963 int, S_IRUGO);
3964 MODULE_PARM_DESC(amsdu_size_8K50,
3965 "enable 8K amsdu size in 50XX series (deprecated)");
3966 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
3967 int, S_IRUGO);
3968 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3969 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3970 MODULE_PARM_DESC(fw_restart50,
3971 "restart firmware in case of error (deprecated)");
3972 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3973 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3974 module_param_named(
3975 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
3976 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
Linux kernel - Deliverables
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