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iwlagn: delay ict interrupt.
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/wireless.h>
39 #include <linux/firmware.h>
40 #include <linux/etherdevice.h>
41 #include <linux/if_arp.h>
42
43 #include <net/mac80211.h>
44
45 #include <asm/div64.h>
46
47 #define DRV_NAME "iwlagn"
48
49 #include "iwl-eeprom.h"
50 #include "iwl-dev.h"
51 #include "iwl-core.h"
52 #include "iwl-io.h"
53 #include "iwl-helpers.h"
54 #include "iwl-sta.h"
55 #include "iwl-calib.h"
56
57
58 /******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
64 /*
65 * module name, copyright, version, etc.
66 */
67 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
68
69 #ifdef CONFIG_IWLWIFI_DEBUG
70 #define VD "d"
71 #else
72 #define VD
73 #endif
74
75 #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
76 #define VS "s"
77 #else
78 #define VS
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD VS
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
89
90 /*************** STATION TABLE MANAGEMENT ****
91 * mac80211 should be examined to determine if sta_info is duplicating
92 * the functionality provided here
93 */
94
95 /**************************************************************/
96
97 /**
98 * iwl_commit_rxon - commit staging_rxon to hardware
99 *
100 * The RXON command in staging_rxon is committed to the hardware and
101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
105 int iwl_commit_rxon(struct iwl_priv *priv)
106 {
107 /* cast away the const for active_rxon in this function */
108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
112
113 if (!iwl_is_alive(priv))
114 return -EBUSY;
115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
121
122 ret = iwl_check_rxon_cmd(priv);
123 if (ret) {
124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
130 * and other flags for the current radio configuration. */
131 if (!iwl_full_rxon_required(priv)) {
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
135 return ret;
136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
149 if (iwl_is_associated(priv) && new_assoc) {
150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
154 sizeof(struct iwl_rxon_cmd),
155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
159 if (ret) {
160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
162 return ret;
163 }
164 }
165
166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
169 "* bssid = %pM\n",
170 (new_assoc ? "" : "out"),
171 le16_to_cpu(priv->staging_rxon.channel),
172 priv->staging_rxon.bssid_addr);
173
174 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
184 if (ret) {
185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
189 }
190
191 iwl_clear_stations_table(priv);
192
193 priv->start_calib = 0;
194
195 /* Add the broadcast address so we can send broadcast frames */
196 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
197 IWL_INVALID_STATION) {
198 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
199 return -EIO;
200 }
201
202 /* If we have set the ASSOC_MSK and we are in BSS mode then
203 * add the IWL_AP_ID to the station rate table */
204 if (new_assoc) {
205 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
206 ret = iwl_rxon_add_station(priv,
207 priv->active_rxon.bssid_addr, 1);
208 if (ret == IWL_INVALID_STATION) {
209 IWL_ERR(priv,
210 "Error adding AP address for TX.\n");
211 return -EIO;
212 }
213 priv->assoc_station_added = 1;
214 if (priv->default_wep_key &&
215 iwl_send_static_wepkey_cmd(priv, 0))
216 IWL_ERR(priv,
217 "Could not send WEP static key.\n");
218 }
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
230 }
231
232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
239 return ret;
240 }
241
242 return 0;
243 }
244
245 void iwl_update_chain_flags(struct iwl_priv *priv)
246 {
247
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
250 iwlcore_commit_rxon(priv);
251 }
252
253 static void iwl_clear_free_frames(struct iwl_priv *priv)
254 {
255 struct list_head *element;
256
257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
263 kfree(list_entry(element, struct iwl_frame, list));
264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272 }
273
274 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
275 {
276 struct iwl_frame *frame;
277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
281 IWL_ERR(priv, "Could not allocate frame!\n");
282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
291 return list_entry(element, struct iwl_frame, list);
292 }
293
294 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
295 {
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298 }
299
300 static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
302 int left)
303 {
304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315 }
316
317 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
318 struct iwl_frame *frame, u8 rate)
319 {
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347 }
348 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
349 {
350 struct iwl_frame *frame;
351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
355 frame = iwl_get_free_frame(priv);
356
357 if (!frame) {
358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
359 "command.\n");
360 return -ENOMEM;
361 }
362
363 rate = iwl_rate_get_lowest_plcp(priv);
364
365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
366
367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
368 &frame->u.cmd[0]);
369
370 iwl_free_frame(priv, frame);
371
372 return rc;
373 }
374
375 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376 {
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385 }
386
387 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388 {
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392 }
393
394 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396 {
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407 }
408
409 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410 {
411 return tfd->num_tbs & 0x1f;
412 }
413
414 /**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423 {
424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
446 pci_unmap_len(&txq->cmd[index]->meta, len),
447 PCI_DMA_BIDIRECTIONAL);
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459 }
460
461 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465 {
466 struct iwl_queue *q;
467 struct iwl_tfd *tfd, *tfd_tmp;
468 u32 num_tbs;
469
470 q = &txq->q;
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494 }
495
496 /*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505 {
506 int txq_id = txq->q.id;
507
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
512 return 0;
513 }
514
515
516 /******************************************************************************
517 *
518 * Misc. internal state and helper functions
519 *
520 ******************************************************************************/
521
522 #define MAX_UCODE_BEACON_INTERVAL 4096
523
524 static u16 iwl_adjust_beacon_interval(u16 beacon_val)
525 {
526 u16 new_val = 0;
527 u16 beacon_factor = 0;
528
529 beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
530 / MAX_UCODE_BEACON_INTERVAL;
531 new_val = beacon_val / beacon_factor;
532
533 if (!new_val)
534 new_val = MAX_UCODE_BEACON_INTERVAL;
535
536 return new_val;
537 }
538
539 static void iwl_setup_rxon_timing(struct iwl_priv *priv)
540 {
541 u64 tsf;
542 s32 interval_tm, rem;
543 unsigned long flags;
544 struct ieee80211_conf *conf = NULL;
545 u16 beacon_int = 0;
546
547 conf = ieee80211_get_hw_conf(priv->hw);
548
549 spin_lock_irqsave(&priv->lock, flags);
550 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
551 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
552
553 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
554 beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
555 priv->rxon_timing.atim_window = 0;
556 } else {
557 beacon_int = iwl_adjust_beacon_interval(
558 priv->vif->bss_conf.beacon_int);
559
560 /* TODO: we need to get atim_window from upper stack
561 * for now we set to 0 */
562 priv->rxon_timing.atim_window = 0;
563 }
564
565 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
566
567 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
568 interval_tm = beacon_int * 1024;
569 rem = do_div(tsf, interval_tm);
570 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
571
572 spin_unlock_irqrestore(&priv->lock, flags);
573 IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
574 le16_to_cpu(priv->rxon_timing.beacon_interval),
575 le32_to_cpu(priv->rxon_timing.beacon_init_val),
576 le16_to_cpu(priv->rxon_timing.atim_window));
577 }
578
579 /******************************************************************************
580 *
581 * Generic RX handler implementations
582 *
583 ******************************************************************************/
584 static void iwl_rx_reply_alive(struct iwl_priv *priv,
585 struct iwl_rx_mem_buffer *rxb)
586 {
587 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
588 struct iwl_alive_resp *palive;
589 struct delayed_work *pwork;
590
591 palive = &pkt->u.alive_frame;
592
593 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
594 "0x%01X 0x%01X\n",
595 palive->is_valid, palive->ver_type,
596 palive->ver_subtype);
597
598 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
599 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
600 memcpy(&priv->card_alive_init,
601 &pkt->u.alive_frame,
602 sizeof(struct iwl_init_alive_resp));
603 pwork = &priv->init_alive_start;
604 } else {
605 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
606 memcpy(&priv->card_alive, &pkt->u.alive_frame,
607 sizeof(struct iwl_alive_resp));
608 pwork = &priv->alive_start;
609 }
610
611 /* We delay the ALIVE response by 5ms to
612 * give the HW RF Kill time to activate... */
613 if (palive->is_valid == UCODE_VALID_OK)
614 queue_delayed_work(priv->workqueue, pwork,
615 msecs_to_jiffies(5));
616 else
617 IWL_WARN(priv, "uCode did not respond OK.\n");
618 }
619
620 static void iwl_bg_beacon_update(struct work_struct *work)
621 {
622 struct iwl_priv *priv =
623 container_of(work, struct iwl_priv, beacon_update);
624 struct sk_buff *beacon;
625
626 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
627 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
628
629 if (!beacon) {
630 IWL_ERR(priv, "update beacon failed\n");
631 return;
632 }
633
634 mutex_lock(&priv->mutex);
635 /* new beacon skb is allocated every time; dispose previous.*/
636 if (priv->ibss_beacon)
637 dev_kfree_skb(priv->ibss_beacon);
638
639 priv->ibss_beacon = beacon;
640 mutex_unlock(&priv->mutex);
641
642 iwl_send_beacon_cmd(priv);
643 }
644
645 /**
646 * iwl_bg_statistics_periodic - Timer callback to queue statistics
647 *
648 * This callback is provided in order to send a statistics request.
649 *
650 * This timer function is continually reset to execute within
651 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
652 * was received. We need to ensure we receive the statistics in order
653 * to update the temperature used for calibrating the TXPOWER.
654 */
655 static void iwl_bg_statistics_periodic(unsigned long data)
656 {
657 struct iwl_priv *priv = (struct iwl_priv *)data;
658
659 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
660 return;
661
662 /* dont send host command if rf-kill is on */
663 if (!iwl_is_ready_rf(priv))
664 return;
665
666 iwl_send_statistics_request(priv, CMD_ASYNC);
667 }
668
669 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
670 struct iwl_rx_mem_buffer *rxb)
671 {
672 #ifdef CONFIG_IWLWIFI_DEBUG
673 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
674 struct iwl4965_beacon_notif *beacon =
675 (struct iwl4965_beacon_notif *)pkt->u.raw;
676 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
677
678 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
679 "tsf %d %d rate %d\n",
680 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
681 beacon->beacon_notify_hdr.failure_frame,
682 le32_to_cpu(beacon->ibss_mgr_status),
683 le32_to_cpu(beacon->high_tsf),
684 le32_to_cpu(beacon->low_tsf), rate);
685 #endif
686
687 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
688 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
689 queue_work(priv->workqueue, &priv->beacon_update);
690 }
691
692 /* Handle notification from uCode that card's power state is changing
693 * due to software, hardware, or critical temperature RFKILL */
694 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
695 struct iwl_rx_mem_buffer *rxb)
696 {
697 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
698 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
699 unsigned long status = priv->status;
700 unsigned long reg_flags;
701
702 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
703 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
704 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
705
706 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
707 RF_CARD_DISABLED)) {
708
709 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
710 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
711
712 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
713 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
714
715 if (!(flags & RXON_CARD_DISABLED)) {
716 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
717 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
718 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
719 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
720
721 }
722
723 if (flags & RF_CARD_DISABLED) {
724 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
725 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
726 iwl_read32(priv, CSR_UCODE_DRV_GP1);
727 spin_lock_irqsave(&priv->reg_lock, reg_flags);
728 if (!iwl_grab_nic_access(priv))
729 iwl_release_nic_access(priv);
730 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
731 }
732 }
733
734 if (flags & HW_CARD_DISABLED)
735 set_bit(STATUS_RF_KILL_HW, &priv->status);
736 else
737 clear_bit(STATUS_RF_KILL_HW, &priv->status);
738
739
740 if (flags & SW_CARD_DISABLED)
741 set_bit(STATUS_RF_KILL_SW, &priv->status);
742 else
743 clear_bit(STATUS_RF_KILL_SW, &priv->status);
744
745 if (!(flags & RXON_CARD_DISABLED))
746 iwl_scan_cancel(priv);
747
748 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
749 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
750 (test_bit(STATUS_RF_KILL_SW, &status) !=
751 test_bit(STATUS_RF_KILL_SW, &priv->status)))
752 queue_work(priv->workqueue, &priv->rf_kill);
753 else
754 wake_up_interruptible(&priv->wait_command_queue);
755 }
756
757 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
758 {
759 if (src == IWL_PWR_SRC_VAUX) {
760 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
761 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
762 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
763 ~APMG_PS_CTRL_MSK_PWR_SRC);
764 } else {
765 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
766 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
767 ~APMG_PS_CTRL_MSK_PWR_SRC);
768 }
769
770 return 0;
771 }
772
773 /**
774 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
775 *
776 * Setup the RX handlers for each of the reply types sent from the uCode
777 * to the host.
778 *
779 * This function chains into the hardware specific files for them to setup
780 * any hardware specific handlers as well.
781 */
782 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
783 {
784 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
785 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
786 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
787 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
788 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
789 iwl_rx_pm_debug_statistics_notif;
790 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
791
792 /*
793 * The same handler is used for both the REPLY to a discrete
794 * statistics request from the host as well as for the periodic
795 * statistics notifications (after received beacons) from the uCode.
796 */
797 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
798 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
799
800 iwl_setup_spectrum_handlers(priv);
801 iwl_setup_rx_scan_handlers(priv);
802
803 /* status change handler */
804 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
805
806 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
807 iwl_rx_missed_beacon_notif;
808 /* Rx handlers */
809 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
810 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
811 /* block ack */
812 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
813 /* Set up hardware specific Rx handlers */
814 priv->cfg->ops->lib->rx_handler_setup(priv);
815 }
816
817 /**
818 * iwl_rx_handle - Main entry function for receiving responses from uCode
819 *
820 * Uses the priv->rx_handlers callback function array to invoke
821 * the appropriate handlers, including command responses,
822 * frame-received notifications, and other notifications.
823 */
824 void iwl_rx_handle(struct iwl_priv *priv)
825 {
826 struct iwl_rx_mem_buffer *rxb;
827 struct iwl_rx_packet *pkt;
828 struct iwl_rx_queue *rxq = &priv->rxq;
829 u32 r, i;
830 int reclaim;
831 unsigned long flags;
832 u8 fill_rx = 0;
833 u32 count = 8;
834 int total_empty;
835
836 /* uCode's read index (stored in shared DRAM) indicates the last Rx
837 * buffer that the driver may process (last buffer filled by ucode). */
838 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
839 i = rxq->read;
840
841 /* Rx interrupt, but nothing sent from uCode */
842 if (i == r)
843 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
844
845 /* calculate total frames need to be restock after handling RX */
846 total_empty = r - priv->rxq.write_actual;
847 if (total_empty < 0)
848 total_empty += RX_QUEUE_SIZE;
849
850 if (total_empty > (RX_QUEUE_SIZE / 2))
851 fill_rx = 1;
852
853 while (i != r) {
854 rxb = rxq->queue[i];
855
856 /* If an RXB doesn't have a Rx queue slot associated with it,
857 * then a bug has been introduced in the queue refilling
858 * routines -- catch it here */
859 BUG_ON(rxb == NULL);
860
861 rxq->queue[i] = NULL;
862
863 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
864 priv->hw_params.rx_buf_size + 256,
865 PCI_DMA_FROMDEVICE);
866 pkt = (struct iwl_rx_packet *)rxb->skb->data;
867
868 /* Reclaim a command buffer only if this packet is a response
869 * to a (driver-originated) command.
870 * If the packet (e.g. Rx frame) originated from uCode,
871 * there is no command buffer to reclaim.
872 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
873 * but apparently a few don't get set; catch them here. */
874 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
875 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
876 (pkt->hdr.cmd != REPLY_RX) &&
877 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
878 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
879 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
880 (pkt->hdr.cmd != REPLY_TX);
881
882 /* Based on type of command response or notification,
883 * handle those that need handling via function in
884 * rx_handlers table. See iwl_setup_rx_handlers() */
885 if (priv->rx_handlers[pkt->hdr.cmd]) {
886 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
887 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
888 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
889 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
890 } else {
891 /* No handling needed */
892 IWL_DEBUG_RX(priv,
893 "r %d i %d No handler needed for %s, 0x%02x\n",
894 r, i, get_cmd_string(pkt->hdr.cmd),
895 pkt->hdr.cmd);
896 }
897
898 if (reclaim) {
899 /* Invoke any callbacks, transfer the skb to caller, and
900 * fire off the (possibly) blocking iwl_send_cmd()
901 * as we reclaim the driver command queue */
902 if (rxb && rxb->skb)
903 iwl_tx_cmd_complete(priv, rxb);
904 else
905 IWL_WARN(priv, "Claim null rxb?\n");
906 }
907
908 /* For now we just don't re-use anything. We can tweak this
909 * later to try and re-use notification packets and SKBs that
910 * fail to Rx correctly */
911 if (rxb->skb != NULL) {
912 priv->alloc_rxb_skb--;
913 dev_kfree_skb_any(rxb->skb);
914 rxb->skb = NULL;
915 }
916
917 spin_lock_irqsave(&rxq->lock, flags);
918 list_add_tail(&rxb->list, &priv->rxq.rx_used);
919 spin_unlock_irqrestore(&rxq->lock, flags);
920 i = (i + 1) & RX_QUEUE_MASK;
921 /* If there are a lot of unused frames,
922 * restock the Rx queue so ucode wont assert. */
923 if (fill_rx) {
924 count++;
925 if (count >= 8) {
926 priv->rxq.read = i;
927 iwl_rx_replenish_now(priv);
928 count = 0;
929 }
930 }
931 }
932
933 /* Backtrack one entry */
934 priv->rxq.read = i;
935 if (fill_rx)
936 iwl_rx_replenish_now(priv);
937 else
938 iwl_rx_queue_restock(priv);
939 }
940
941 /* call this function to flush any scheduled tasklet */
942 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
943 {
944 /* wait to make sure we flush pending tasklet*/
945 synchronize_irq(priv->pci_dev->irq);
946 tasklet_kill(&priv->irq_tasklet);
947 }
948
949 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
950 {
951 u32 inta, handled = 0;
952 u32 inta_fh;
953 unsigned long flags;
954 #ifdef CONFIG_IWLWIFI_DEBUG
955 u32 inta_mask;
956 #endif
957
958 spin_lock_irqsave(&priv->lock, flags);
959
960 /* Ack/clear/reset pending uCode interrupts.
961 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
962 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
963 inta = iwl_read32(priv, CSR_INT);
964 iwl_write32(priv, CSR_INT, inta);
965
966 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
967 * Any new interrupts that happen after this, either while we're
968 * in this tasklet, or later, will show up in next ISR/tasklet. */
969 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
970 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
971
972 #ifdef CONFIG_IWLWIFI_DEBUG
973 if (priv->debug_level & IWL_DL_ISR) {
974 /* just for debug */
975 inta_mask = iwl_read32(priv, CSR_INT_MASK);
976 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
977 inta, inta_mask, inta_fh);
978 }
979 #endif
980
981 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
982 * atomic, make sure that inta covers all the interrupts that
983 * we've discovered, even if FH interrupt came in just after
984 * reading CSR_INT. */
985 if (inta_fh & CSR49_FH_INT_RX_MASK)
986 inta |= CSR_INT_BIT_FH_RX;
987 if (inta_fh & CSR49_FH_INT_TX_MASK)
988 inta |= CSR_INT_BIT_FH_TX;
989
990 /* Now service all interrupt bits discovered above. */
991 if (inta & CSR_INT_BIT_HW_ERR) {
992 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
993
994 /* Tell the device to stop sending interrupts */
995 iwl_disable_interrupts(priv);
996
997 priv->isr_stats.hw++;
998 iwl_irq_handle_error(priv);
999
1000 handled |= CSR_INT_BIT_HW_ERR;
1001
1002 spin_unlock_irqrestore(&priv->lock, flags);
1003
1004 return;
1005 }
1006
1007 #ifdef CONFIG_IWLWIFI_DEBUG
1008 if (priv->debug_level & (IWL_DL_ISR)) {
1009 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1010 if (inta & CSR_INT_BIT_SCD) {
1011 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1012 "the frame/frames.\n");
1013 priv->isr_stats.sch++;
1014 }
1015
1016 /* Alive notification via Rx interrupt will do the real work */
1017 if (inta & CSR_INT_BIT_ALIVE) {
1018 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1019 priv->isr_stats.alive++;
1020 }
1021 }
1022 #endif
1023 /* Safely ignore these bits for debug checks below */
1024 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1025
1026 /* HW RF KILL switch toggled */
1027 if (inta & CSR_INT_BIT_RF_KILL) {
1028 int hw_rf_kill = 0;
1029 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1030 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1031 hw_rf_kill = 1;
1032
1033 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
1034 hw_rf_kill ? "disable radio" : "enable radio");
1035
1036 priv->isr_stats.rfkill++;
1037
1038 /* driver only loads ucode once setting the interface up.
1039 * the driver allows loading the ucode even if the radio
1040 * is killed. Hence update the killswitch state here. The
1041 * rfkill handler will care about restarting if needed.
1042 */
1043 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1044 if (hw_rf_kill)
1045 set_bit(STATUS_RF_KILL_HW, &priv->status);
1046 else
1047 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1048 queue_work(priv->workqueue, &priv->rf_kill);
1049 }
1050
1051 handled |= CSR_INT_BIT_RF_KILL;
1052 }
1053
1054 /* Chip got too hot and stopped itself */
1055 if (inta & CSR_INT_BIT_CT_KILL) {
1056 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1057 priv->isr_stats.ctkill++;
1058 handled |= CSR_INT_BIT_CT_KILL;
1059 }
1060
1061 /* Error detected by uCode */
1062 if (inta & CSR_INT_BIT_SW_ERR) {
1063 IWL_ERR(priv, "Microcode SW error detected. "
1064 " Restarting 0x%X.\n", inta);
1065 priv->isr_stats.sw++;
1066 priv->isr_stats.sw_err = inta;
1067 iwl_irq_handle_error(priv);
1068 handled |= CSR_INT_BIT_SW_ERR;
1069 }
1070
1071 /* uCode wakes up after power-down sleep */
1072 if (inta & CSR_INT_BIT_WAKEUP) {
1073 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1074 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1075 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1076 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1077 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1078 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1079 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1080 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1081
1082 priv->isr_stats.wakeup++;
1083
1084 handled |= CSR_INT_BIT_WAKEUP;
1085 }
1086
1087 /* All uCode command responses, including Tx command responses,
1088 * Rx "responses" (frame-received notification), and other
1089 * notifications from uCode come through here*/
1090 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1091 iwl_rx_handle(priv);
1092 priv->isr_stats.rx++;
1093 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1094 }
1095
1096 if (inta & CSR_INT_BIT_FH_TX) {
1097 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1098 priv->isr_stats.tx++;
1099 handled |= CSR_INT_BIT_FH_TX;
1100 /* FH finished to write, send event */
1101 priv->ucode_write_complete = 1;
1102 wake_up_interruptible(&priv->wait_command_queue);
1103 }
1104
1105 if (inta & ~handled) {
1106 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1107 priv->isr_stats.unhandled++;
1108 }
1109
1110 if (inta & ~(priv->inta_mask)) {
1111 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1112 inta & ~priv->inta_mask);
1113 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1114 }
1115
1116 /* Re-enable all interrupts */
1117 /* only Re-enable if diabled by irq */
1118 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1119 iwl_enable_interrupts(priv);
1120
1121 #ifdef CONFIG_IWLWIFI_DEBUG
1122 if (priv->debug_level & (IWL_DL_ISR)) {
1123 inta = iwl_read32(priv, CSR_INT);
1124 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1125 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1126 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1127 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1128 }
1129 #endif
1130 spin_unlock_irqrestore(&priv->lock, flags);
1131 }
1132
1133 /* tasklet for iwlagn interrupt */
1134 static void iwl_irq_tasklet(struct iwl_priv *priv)
1135 {
1136 u32 inta = 0;
1137 u32 handled = 0;
1138 unsigned long flags;
1139 #ifdef CONFIG_IWLWIFI_DEBUG
1140 u32 inta_mask;
1141 #endif
1142
1143 spin_lock_irqsave(&priv->lock, flags);
1144
1145 /* Ack/clear/reset pending uCode interrupts.
1146 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1147 */
1148 iwl_write32(priv, CSR_INT, priv->inta);
1149
1150 inta = priv->inta;
1151
1152 #ifdef CONFIG_IWLWIFI_DEBUG
1153 if (priv->debug_level & IWL_DL_ISR) {
1154 /* just for debug */
1155 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1156 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1157 inta, inta_mask);
1158 }
1159 #endif
1160 /* saved interrupt in inta variable now we can reset priv->inta */
1161 priv->inta = 0;
1162
1163 /* Now service all interrupt bits discovered above. */
1164 if (inta & CSR_INT_BIT_HW_ERR) {
1165 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
1166
1167 /* Tell the device to stop sending interrupts */
1168 iwl_disable_interrupts(priv);
1169
1170 priv->isr_stats.hw++;
1171 iwl_irq_handle_error(priv);
1172
1173 handled |= CSR_INT_BIT_HW_ERR;
1174
1175 spin_unlock_irqrestore(&priv->lock, flags);
1176
1177 return;
1178 }
1179
1180 #ifdef CONFIG_IWLWIFI_DEBUG
1181 if (priv->debug_level & (IWL_DL_ISR)) {
1182 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1183 if (inta & CSR_INT_BIT_SCD) {
1184 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1185 "the frame/frames.\n");
1186 priv->isr_stats.sch++;
1187 }
1188
1189 /* Alive notification via Rx interrupt will do the real work */
1190 if (inta & CSR_INT_BIT_ALIVE) {
1191 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1192 priv->isr_stats.alive++;
1193 }
1194 }
1195 #endif
1196 /* Safely ignore these bits for debug checks below */
1197 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1198
1199 /* HW RF KILL switch toggled */
1200 if (inta & CSR_INT_BIT_RF_KILL) {
1201 int hw_rf_kill = 0;
1202 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1203 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1204 hw_rf_kill = 1;
1205
1206 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
1207 hw_rf_kill ? "disable radio" : "enable radio");
1208
1209 priv->isr_stats.rfkill++;
1210
1211 /* driver only loads ucode once setting the interface up.
1212 * the driver allows loading the ucode even if the radio
1213 * is killed. Hence update the killswitch state here. The
1214 * rfkill handler will care about restarting if needed.
1215 */
1216 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1217 if (hw_rf_kill)
1218 set_bit(STATUS_RF_KILL_HW, &priv->status);
1219 else
1220 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1221 queue_work(priv->workqueue, &priv->rf_kill);
1222 }
1223
1224 handled |= CSR_INT_BIT_RF_KILL;
1225 }
1226
1227 /* Chip got too hot and stopped itself */
1228 if (inta & CSR_INT_BIT_CT_KILL) {
1229 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1230 priv->isr_stats.ctkill++;
1231 handled |= CSR_INT_BIT_CT_KILL;
1232 }
1233
1234 /* Error detected by uCode */
1235 if (inta & CSR_INT_BIT_SW_ERR) {
1236 IWL_ERR(priv, "Microcode SW error detected. "
1237 " Restarting 0x%X.\n", inta);
1238 priv->isr_stats.sw++;
1239 priv->isr_stats.sw_err = inta;
1240 iwl_irq_handle_error(priv);
1241 handled |= CSR_INT_BIT_SW_ERR;
1242 }
1243
1244 /* uCode wakes up after power-down sleep */
1245 if (inta & CSR_INT_BIT_WAKEUP) {
1246 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1247 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1248 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1249 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1250 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1251 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1252 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1253 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1254
1255 priv->isr_stats.wakeup++;
1256
1257 handled |= CSR_INT_BIT_WAKEUP;
1258 }
1259
1260 /* All uCode command responses, including Tx command responses,
1261 * Rx "responses" (frame-received notification), and other
1262 * notifications from uCode come through here*/
1263 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1264 CSR_INT_BIT_RX_PERIODIC)) {
1265 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1266 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1267 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1268 iwl_write32(priv, CSR_FH_INT_STATUS,
1269 CSR49_FH_INT_RX_MASK);
1270 }
1271 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1272 handled |= CSR_INT_BIT_RX_PERIODIC;
1273 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1274 }
1275 /* Sending RX interrupt require many steps to be done in the
1276 * the device:
1277 * 1- write interrupt to current index in ICT table.
1278 * 2- dma RX frame.
1279 * 3- update RX shared data to indicate last write index.
1280 * 4- send interrupt.
1281 * This could lead to RX race, driver could receive RX interrupt
1282 * but the shared data changes does not reflect this.
1283 * this could lead to RX race, RX periodic will solve this race
1284 */
1285 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1286 CSR_INT_PERIODIC_DIS);
1287 iwl_rx_handle(priv);
1288 /* Only set RX periodic if real RX is received. */
1289 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1290 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1291 CSR_INT_PERIODIC_ENA);
1292
1293 priv->isr_stats.rx++;
1294 }
1295
1296 if (inta & CSR_INT_BIT_FH_TX) {
1297 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1298 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1299 priv->isr_stats.tx++;
1300 handled |= CSR_INT_BIT_FH_TX;
1301 /* FH finished to write, send event */
1302 priv->ucode_write_complete = 1;
1303 wake_up_interruptible(&priv->wait_command_queue);
1304 }
1305
1306 if (inta & ~handled) {
1307 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1308 priv->isr_stats.unhandled++;
1309 }
1310
1311 if (inta & ~(priv->inta_mask)) {
1312 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1313 inta & ~priv->inta_mask);
1314 }
1315
1316
1317 /* Re-enable all interrupts */
1318 /* only Re-enable if diabled by irq */
1319 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1320 iwl_enable_interrupts(priv);
1321
1322 spin_unlock_irqrestore(&priv->lock, flags);
1323
1324 }
1325
1326
1327 /******************************************************************************
1328 *
1329 * uCode download functions
1330 *
1331 ******************************************************************************/
1332
1333 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1334 {
1335 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1336 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1337 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1338 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1339 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1340 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1341 }
1342
1343 static void iwl_nic_start(struct iwl_priv *priv)
1344 {
1345 /* Remove all resets to allow NIC to operate */
1346 iwl_write32(priv, CSR_RESET, 0);
1347 }
1348
1349
1350 /**
1351 * iwl_read_ucode - Read uCode images from disk file.
1352 *
1353 * Copy into buffers for card to fetch via bus-mastering
1354 */
1355 static int iwl_read_ucode(struct iwl_priv *priv)
1356 {
1357 struct iwl_ucode *ucode;
1358 int ret = -EINVAL, index;
1359 const struct firmware *ucode_raw;
1360 const char *name_pre = priv->cfg->fw_name_pre;
1361 const unsigned int api_max = priv->cfg->ucode_api_max;
1362 const unsigned int api_min = priv->cfg->ucode_api_min;
1363 char buf[25];
1364 u8 *src;
1365 size_t len;
1366 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1367
1368 /* Ask kernel firmware_class module to get the boot firmware off disk.
1369 * request_firmware() is synchronous, file is in memory on return. */
1370 for (index = api_max; index >= api_min; index--) {
1371 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1372 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1373 if (ret < 0) {
1374 IWL_ERR(priv, "%s firmware file req failed: %d\n",
1375 buf, ret);
1376 if (ret == -ENOENT)
1377 continue;
1378 else
1379 goto error;
1380 } else {
1381 if (index < api_max)
1382 IWL_ERR(priv, "Loaded firmware %s, "
1383 "which is deprecated. "
1384 "Please use API v%u instead.\n",
1385 buf, api_max);
1386
1387 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
1388 buf, ucode_raw->size);
1389 break;
1390 }
1391 }
1392
1393 if (ret < 0)
1394 goto error;
1395
1396 /* Make sure that we got at least our header! */
1397 if (ucode_raw->size < sizeof(*ucode)) {
1398 IWL_ERR(priv, "File size way too small!\n");
1399 ret = -EINVAL;
1400 goto err_release;
1401 }
1402
1403 /* Data from ucode file: header followed by uCode images */
1404 ucode = (void *)ucode_raw->data;
1405
1406 priv->ucode_ver = le32_to_cpu(ucode->ver);
1407 api_ver = IWL_UCODE_API(priv->ucode_ver);
1408 inst_size = le32_to_cpu(ucode->inst_size);
1409 data_size = le32_to_cpu(ucode->data_size);
1410 init_size = le32_to_cpu(ucode->init_size);
1411 init_data_size = le32_to_cpu(ucode->init_data_size);
1412 boot_size = le32_to_cpu(ucode->boot_size);
1413
1414 /* api_ver should match the api version forming part of the
1415 * firmware filename ... but we don't check for that and only rely
1416 * on the API version read from firmware header from here on forward */
1417
1418 if (api_ver < api_min || api_ver > api_max) {
1419 IWL_ERR(priv, "Driver unable to support your firmware API. "
1420 "Driver supports v%u, firmware is v%u.\n",
1421 api_max, api_ver);
1422 priv->ucode_ver = 0;
1423 ret = -EINVAL;
1424 goto err_release;
1425 }
1426 if (api_ver != api_max)
1427 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1428 "got v%u. New firmware can be obtained "
1429 "from http://www.intellinuxwireless.org.\n",
1430 api_max, api_ver);
1431
1432 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1433 IWL_UCODE_MAJOR(priv->ucode_ver),
1434 IWL_UCODE_MINOR(priv->ucode_ver),
1435 IWL_UCODE_API(priv->ucode_ver),
1436 IWL_UCODE_SERIAL(priv->ucode_ver));
1437
1438 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1439 priv->ucode_ver);
1440 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
1441 inst_size);
1442 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
1443 data_size);
1444 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
1445 init_size);
1446 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
1447 init_data_size);
1448 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
1449 boot_size);
1450
1451 /* Verify size of file vs. image size info in file's header */
1452 if (ucode_raw->size < sizeof(*ucode) +
1453 inst_size + data_size + init_size +
1454 init_data_size + boot_size) {
1455
1456 IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
1457 (int)ucode_raw->size);
1458 ret = -EINVAL;
1459 goto err_release;
1460 }
1461
1462 /* Verify that uCode images will fit in card's SRAM */
1463 if (inst_size > priv->hw_params.max_inst_size) {
1464 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
1465 inst_size);
1466 ret = -EINVAL;
1467 goto err_release;
1468 }
1469
1470 if (data_size > priv->hw_params.max_data_size) {
1471 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
1472 data_size);
1473 ret = -EINVAL;
1474 goto err_release;
1475 }
1476 if (init_size > priv->hw_params.max_inst_size) {
1477 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1478 init_size);
1479 ret = -EINVAL;
1480 goto err_release;
1481 }
1482 if (init_data_size > priv->hw_params.max_data_size) {
1483 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
1484 init_data_size);
1485 ret = -EINVAL;
1486 goto err_release;
1487 }
1488 if (boot_size > priv->hw_params.max_bsm_size) {
1489 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1490 boot_size);
1491 ret = -EINVAL;
1492 goto err_release;
1493 }
1494
1495 /* Allocate ucode buffers for card's bus-master loading ... */
1496
1497 /* Runtime instructions and 2 copies of data:
1498 * 1) unmodified from disk
1499 * 2) backup cache for save/restore during power-downs */
1500 priv->ucode_code.len = inst_size;
1501 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1502
1503 priv->ucode_data.len = data_size;
1504 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1505
1506 priv->ucode_data_backup.len = data_size;
1507 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1508
1509 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1510 !priv->ucode_data_backup.v_addr)
1511 goto err_pci_alloc;
1512
1513 /* Initialization instructions and data */
1514 if (init_size && init_data_size) {
1515 priv->ucode_init.len = init_size;
1516 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1517
1518 priv->ucode_init_data.len = init_data_size;
1519 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1520
1521 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1522 goto err_pci_alloc;
1523 }
1524
1525 /* Bootstrap (instructions only, no data) */
1526 if (boot_size) {
1527 priv->ucode_boot.len = boot_size;
1528 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1529
1530 if (!priv->ucode_boot.v_addr)
1531 goto err_pci_alloc;
1532 }
1533
1534 /* Copy images into buffers for card's bus-master reads ... */
1535
1536 /* Runtime instructions (first block of data in file) */
1537 src = &ucode->data[0];
1538 len = priv->ucode_code.len;
1539 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
1540 memcpy(priv->ucode_code.v_addr, src, len);
1541 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1542 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1543
1544 /* Runtime data (2nd block)
1545 * NOTE: Copy into backup buffer will be done in iwl_up() */
1546 src = &ucode->data[inst_size];
1547 len = priv->ucode_data.len;
1548 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
1549 memcpy(priv->ucode_data.v_addr, src, len);
1550 memcpy(priv->ucode_data_backup.v_addr, src, len);
1551
1552 /* Initialization instructions (3rd block) */
1553 if (init_size) {
1554 src = &ucode->data[inst_size + data_size];
1555 len = priv->ucode_init.len;
1556 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1557 len);
1558 memcpy(priv->ucode_init.v_addr, src, len);
1559 }
1560
1561 /* Initialization data (4th block) */
1562 if (init_data_size) {
1563 src = &ucode->data[inst_size + data_size + init_size];
1564 len = priv->ucode_init_data.len;
1565 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1566 len);
1567 memcpy(priv->ucode_init_data.v_addr, src, len);
1568 }
1569
1570 /* Bootstrap instructions (5th block) */
1571 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
1572 len = priv->ucode_boot.len;
1573 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
1574 memcpy(priv->ucode_boot.v_addr, src, len);
1575
1576 /* We have our copies now, allow OS release its copies */
1577 release_firmware(ucode_raw);
1578 return 0;
1579
1580 err_pci_alloc:
1581 IWL_ERR(priv, "failed to allocate pci memory\n");
1582 ret = -ENOMEM;
1583 iwl_dealloc_ucode_pci(priv);
1584
1585 err_release:
1586 release_firmware(ucode_raw);
1587
1588 error:
1589 return ret;
1590 }
1591
1592 /**
1593 * iwl_alive_start - called after REPLY_ALIVE notification received
1594 * from protocol/runtime uCode (initialization uCode's
1595 * Alive gets handled by iwl_init_alive_start()).
1596 */
1597 static void iwl_alive_start(struct iwl_priv *priv)
1598 {
1599 int ret = 0;
1600
1601 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1602
1603 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1604 /* We had an error bringing up the hardware, so take it
1605 * all the way back down so we can try again */
1606 IWL_DEBUG_INFO(priv, "Alive failed.\n");
1607 goto restart;
1608 }
1609
1610 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1611 * This is a paranoid check, because we would not have gotten the
1612 * "runtime" alive if code weren't properly loaded. */
1613 if (iwl_verify_ucode(priv)) {
1614 /* Runtime instruction load was bad;
1615 * take it all the way back down so we can try again */
1616 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
1617 goto restart;
1618 }
1619
1620 iwl_clear_stations_table(priv);
1621 ret = priv->cfg->ops->lib->alive_notify(priv);
1622 if (ret) {
1623 IWL_WARN(priv,
1624 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1625 goto restart;
1626 }
1627
1628 /* After the ALIVE response, we can send host commands to the uCode */
1629 set_bit(STATUS_ALIVE, &priv->status);
1630
1631 if (iwl_is_rfkill(priv))
1632 return;
1633
1634 ieee80211_wake_queues(priv->hw);
1635
1636 priv->active_rate = priv->rates_mask;
1637 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1638
1639 if (iwl_is_associated(priv)) {
1640 struct iwl_rxon_cmd *active_rxon =
1641 (struct iwl_rxon_cmd *)&priv->active_rxon;
1642 /* apply any changes in staging */
1643 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1644 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1645 } else {
1646 /* Initialize our rx_config data */
1647 iwl_connection_init_rx_config(priv, priv->iw_mode);
1648
1649 if (priv->cfg->ops->hcmd->set_rxon_chain)
1650 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1651
1652 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1653 }
1654
1655 /* Configure Bluetooth device coexistence support */
1656 iwl_send_bt_config(priv);
1657
1658 iwl_reset_run_time_calib(priv);
1659
1660 /* Configure the adapter for unassociated operation */
1661 iwlcore_commit_rxon(priv);
1662
1663 /* At this point, the NIC is initialized and operational */
1664 iwl_rf_kill_ct_config(priv);
1665
1666 iwl_leds_register(priv);
1667
1668 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
1669 set_bit(STATUS_READY, &priv->status);
1670 wake_up_interruptible(&priv->wait_command_queue);
1671
1672 iwl_power_update_mode(priv, 1);
1673
1674 /* reassociate for ADHOC mode */
1675 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1676 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1677 priv->vif);
1678 if (beacon)
1679 iwl_mac_beacon_update(priv->hw, beacon);
1680 }
1681
1682
1683 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
1684 iwl_set_mode(priv, priv->iw_mode);
1685
1686 return;
1687
1688 restart:
1689 queue_work(priv->workqueue, &priv->restart);
1690 }
1691
1692 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
1693
1694 static void __iwl_down(struct iwl_priv *priv)
1695 {
1696 unsigned long flags;
1697 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
1698
1699 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
1700
1701 if (!exit_pending)
1702 set_bit(STATUS_EXIT_PENDING, &priv->status);
1703
1704 iwl_leds_unregister(priv);
1705
1706 iwl_clear_stations_table(priv);
1707
1708 /* Unblock any waiting calls */
1709 wake_up_interruptible_all(&priv->wait_command_queue);
1710
1711 /* Wipe out the EXIT_PENDING status bit if we are not actually
1712 * exiting the module */
1713 if (!exit_pending)
1714 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1715
1716 /* stop and reset the on-board processor */
1717 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1718
1719 /* tell the device to stop sending interrupts */
1720 spin_lock_irqsave(&priv->lock, flags);
1721 iwl_disable_interrupts(priv);
1722 spin_unlock_irqrestore(&priv->lock, flags);
1723 iwl_synchronize_irq(priv);
1724
1725 if (priv->mac80211_registered)
1726 ieee80211_stop_queues(priv->hw);
1727
1728 /* If we have not previously called iwl_init() then
1729 * clear all bits but the RF Kill bits and return */
1730 if (!iwl_is_init(priv)) {
1731 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1732 STATUS_RF_KILL_HW |
1733 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1734 STATUS_RF_KILL_SW |
1735 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1736 STATUS_GEO_CONFIGURED |
1737 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1738 STATUS_EXIT_PENDING;
1739 goto exit;
1740 }
1741
1742 /* ...otherwise clear out all the status bits but the RF Kill
1743 * bits and continue taking the NIC down. */
1744 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1745 STATUS_RF_KILL_HW |
1746 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1747 STATUS_RF_KILL_SW |
1748 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1749 STATUS_GEO_CONFIGURED |
1750 test_bit(STATUS_FW_ERROR, &priv->status) <<
1751 STATUS_FW_ERROR |
1752 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1753 STATUS_EXIT_PENDING;
1754
1755 /* device going down, Stop using ICT table */
1756 iwl_disable_ict(priv);
1757 spin_lock_irqsave(&priv->lock, flags);
1758 iwl_clear_bit(priv, CSR_GP_CNTRL,
1759 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1760 spin_unlock_irqrestore(&priv->lock, flags);
1761
1762 iwl_txq_ctx_stop(priv);
1763 iwl_rxq_stop(priv);
1764
1765 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1766 APMG_CLK_VAL_DMA_CLK_RQT);
1767
1768 udelay(5);
1769
1770 /* FIXME: apm_ops.suspend(priv) */
1771 if (exit_pending)
1772 priv->cfg->ops->lib->apm_ops.stop(priv);
1773 else
1774 priv->cfg->ops->lib->apm_ops.reset(priv);
1775 exit:
1776 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
1777
1778 if (priv->ibss_beacon)
1779 dev_kfree_skb(priv->ibss_beacon);
1780 priv->ibss_beacon = NULL;
1781
1782 /* clear out any free frames */
1783 iwl_clear_free_frames(priv);
1784 }
1785
1786 static void iwl_down(struct iwl_priv *priv)
1787 {
1788 mutex_lock(&priv->mutex);
1789 __iwl_down(priv);
1790 mutex_unlock(&priv->mutex);
1791
1792 iwl_cancel_deferred_work(priv);
1793 }
1794
1795 #define HW_READY_TIMEOUT (50)
1796
1797 static int iwl_set_hw_ready(struct iwl_priv *priv)
1798 {
1799 int ret = 0;
1800
1801 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1802 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1803
1804 /* See if we got it */
1805 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1806 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1807 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1808 HW_READY_TIMEOUT);
1809 if (ret != -ETIMEDOUT)
1810 priv->hw_ready = true;
1811 else
1812 priv->hw_ready = false;
1813
1814 IWL_DEBUG_INFO(priv, "hardware %s\n",
1815 (priv->hw_ready == 1) ? "ready" : "not ready");
1816 return ret;
1817 }
1818
1819 static int iwl_prepare_card_hw(struct iwl_priv *priv)
1820 {
1821 int ret = 0;
1822
1823 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1824
1825 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1826 CSR_HW_IF_CONFIG_REG_PREPARE);
1827
1828 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1829 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1830 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1831
1832 if (ret != -ETIMEDOUT)
1833 iwl_set_hw_ready(priv);
1834
1835 return ret;
1836 }
1837
1838 #define MAX_HW_RESTARTS 5
1839
1840 static int __iwl_up(struct iwl_priv *priv)
1841 {
1842 int i;
1843 int ret;
1844
1845 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1846 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
1847 return -EIO;
1848 }
1849
1850 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
1851 IWL_ERR(priv, "ucode not available for device bringup\n");
1852 return -EIO;
1853 }
1854
1855 iwl_prepare_card_hw(priv);
1856
1857 if (!priv->hw_ready) {
1858 IWL_WARN(priv, "Exit HW not ready\n");
1859 return -EIO;
1860 }
1861
1862 /* If platform's RF_KILL switch is NOT set to KILL */
1863 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1864 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1865 else
1866 set_bit(STATUS_RF_KILL_HW, &priv->status);
1867
1868 if (iwl_is_rfkill(priv)) {
1869 iwl_enable_interrupts(priv);
1870 IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
1871 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
1872 return 0;
1873 }
1874
1875 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
1876
1877 ret = iwl_hw_nic_init(priv);
1878 if (ret) {
1879 IWL_ERR(priv, "Unable to init nic\n");
1880 return ret;
1881 }
1882
1883 /* make sure rfkill handshake bits are cleared */
1884 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1885 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1886 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1887
1888 /* clear (again), then enable host interrupts */
1889 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
1890 iwl_enable_interrupts(priv);
1891
1892 /* really make sure rfkill handshake bits are cleared */
1893 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1894 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1895
1896 /* Copy original ucode data image from disk into backup cache.
1897 * This will be used to initialize the on-board processor's
1898 * data SRAM for a clean start when the runtime program first loads. */
1899 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
1900 priv->ucode_data.len);
1901
1902 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1903
1904 iwl_clear_stations_table(priv);
1905
1906 /* load bootstrap state machine,
1907 * load bootstrap program into processor's memory,
1908 * prepare to load the "initialize" uCode */
1909 ret = priv->cfg->ops->lib->load_ucode(priv);
1910
1911 if (ret) {
1912 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1913 ret);
1914 continue;
1915 }
1916
1917 /* start card; "initialize" will load runtime ucode */
1918 iwl_nic_start(priv);
1919
1920 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
1921
1922 return 0;
1923 }
1924
1925 set_bit(STATUS_EXIT_PENDING, &priv->status);
1926 __iwl_down(priv);
1927 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1928
1929 /* tried to restart and config the device for as long as our
1930 * patience could withstand */
1931 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
1932 return -EIO;
1933 }
1934
1935
1936 /*****************************************************************************
1937 *
1938 * Workqueue callbacks
1939 *
1940 *****************************************************************************/
1941
1942 static void iwl_bg_init_alive_start(struct work_struct *data)
1943 {
1944 struct iwl_priv *priv =
1945 container_of(data, struct iwl_priv, init_alive_start.work);
1946
1947 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1948 return;
1949
1950 mutex_lock(&priv->mutex);
1951 priv->cfg->ops->lib->init_alive_start(priv);
1952 mutex_unlock(&priv->mutex);
1953 }
1954
1955 static void iwl_bg_alive_start(struct work_struct *data)
1956 {
1957 struct iwl_priv *priv =
1958 container_of(data, struct iwl_priv, alive_start.work);
1959
1960 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1961 return;
1962
1963 /* enable dram interrupt */
1964 iwl_reset_ict(priv);
1965
1966 mutex_lock(&priv->mutex);
1967 iwl_alive_start(priv);
1968 mutex_unlock(&priv->mutex);
1969 }
1970
1971 static void iwl_bg_run_time_calib_work(struct work_struct *work)
1972 {
1973 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1974 run_time_calib_work);
1975
1976 mutex_lock(&priv->mutex);
1977
1978 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1979 test_bit(STATUS_SCANNING, &priv->status)) {
1980 mutex_unlock(&priv->mutex);
1981 return;
1982 }
1983
1984 if (priv->start_calib) {
1985 iwl_chain_noise_calibration(priv, &priv->statistics);
1986
1987 iwl_sensitivity_calibration(priv, &priv->statistics);
1988 }
1989
1990 mutex_unlock(&priv->mutex);
1991 return;
1992 }
1993
1994 static void iwl_bg_up(struct work_struct *data)
1995 {
1996 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
1997
1998 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1999 return;
2000
2001 mutex_lock(&priv->mutex);
2002 __iwl_up(priv);
2003 mutex_unlock(&priv->mutex);
2004 iwl_rfkill_set_hw_state(priv);
2005 }
2006
2007 static void iwl_bg_restart(struct work_struct *data)
2008 {
2009 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2010
2011 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2012 return;
2013
2014 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2015 mutex_lock(&priv->mutex);
2016 priv->vif = NULL;
2017 priv->is_open = 0;
2018 mutex_unlock(&priv->mutex);
2019 iwl_down(priv);
2020 ieee80211_restart_hw(priv->hw);
2021 } else {
2022 iwl_down(priv);
2023 queue_work(priv->workqueue, &priv->up);
2024 }
2025 }
2026
2027 static void iwl_bg_rx_replenish(struct work_struct *data)
2028 {
2029 struct iwl_priv *priv =
2030 container_of(data, struct iwl_priv, rx_replenish);
2031
2032 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2033 return;
2034
2035 mutex_lock(&priv->mutex);
2036 iwl_rx_replenish(priv);
2037 mutex_unlock(&priv->mutex);
2038 }
2039
2040 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2041
2042 void iwl_post_associate(struct iwl_priv *priv)
2043 {
2044 struct ieee80211_conf *conf = NULL;
2045 int ret = 0;
2046 unsigned long flags;
2047
2048 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2049 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2050 return;
2051 }
2052
2053 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2054 priv->assoc_id, priv->active_rxon.bssid_addr);
2055
2056
2057 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2058 return;
2059
2060
2061 if (!priv->vif || !priv->is_open)
2062 return;
2063
2064 iwl_scan_cancel_timeout(priv, 200);
2065
2066 conf = ieee80211_get_hw_conf(priv->hw);
2067
2068 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2069 iwlcore_commit_rxon(priv);
2070
2071 iwl_setup_rxon_timing(priv);
2072 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2073 sizeof(priv->rxon_timing), &priv->rxon_timing);
2074 if (ret)
2075 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2076 "Attempting to continue.\n");
2077
2078 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2079
2080 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2081
2082 if (priv->cfg->ops->hcmd->set_rxon_chain)
2083 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2084
2085 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2086
2087 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2088 priv->assoc_id, priv->beacon_int);
2089
2090 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2091 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2092 else
2093 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2094
2095 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2096 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2097 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2098 else
2099 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2100
2101 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2102 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2103
2104 }
2105
2106 iwlcore_commit_rxon(priv);
2107
2108 switch (priv->iw_mode) {
2109 case NL80211_IFTYPE_STATION:
2110 break;
2111
2112 case NL80211_IFTYPE_ADHOC:
2113
2114 /* assume default assoc id */
2115 priv->assoc_id = 1;
2116
2117 iwl_rxon_add_station(priv, priv->bssid, 0);
2118 iwl_send_beacon_cmd(priv);
2119
2120 break;
2121
2122 default:
2123 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2124 __func__, priv->iw_mode);
2125 break;
2126 }
2127
2128 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2129 priv->assoc_station_added = 1;
2130
2131 spin_lock_irqsave(&priv->lock, flags);
2132 iwl_activate_qos(priv, 0);
2133 spin_unlock_irqrestore(&priv->lock, flags);
2134
2135 /* the chain noise calibration will enabled PM upon completion
2136 * If chain noise has already been run, then we need to enable
2137 * power management here */
2138 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2139 iwl_power_update_mode(priv, 0);
2140
2141 /* Enable Rx differential gain and sensitivity calibrations */
2142 iwl_chain_noise_reset(priv);
2143 priv->start_calib = 1;
2144
2145 }
2146
2147 /*****************************************************************************
2148 *
2149 * mac80211 entry point functions
2150 *
2151 *****************************************************************************/
2152
2153 #define UCODE_READY_TIMEOUT (4 * HZ)
2154
2155 static int iwl_mac_start(struct ieee80211_hw *hw)
2156 {
2157 struct iwl_priv *priv = hw->priv;
2158 int ret;
2159
2160 IWL_DEBUG_MAC80211(priv, "enter\n");
2161
2162 /* we should be verifying the device is ready to be opened */
2163 mutex_lock(&priv->mutex);
2164
2165 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
2166 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2167 * ucode filename and max sizes are card-specific. */
2168
2169 if (!priv->ucode_code.len) {
2170 ret = iwl_read_ucode(priv);
2171 if (ret) {
2172 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
2173 mutex_unlock(&priv->mutex);
2174 return ret;
2175 }
2176 }
2177
2178 ret = __iwl_up(priv);
2179
2180 mutex_unlock(&priv->mutex);
2181
2182 iwl_rfkill_set_hw_state(priv);
2183
2184 if (ret)
2185 return ret;
2186
2187 if (iwl_is_rfkill(priv))
2188 goto out;
2189
2190 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2191
2192 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2193 * mac80211 will not be run successfully. */
2194 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2195 test_bit(STATUS_READY, &priv->status),
2196 UCODE_READY_TIMEOUT);
2197 if (!ret) {
2198 if (!test_bit(STATUS_READY, &priv->status)) {
2199 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2200 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2201 return -ETIMEDOUT;
2202 }
2203 }
2204
2205 out:
2206 priv->is_open = 1;
2207 IWL_DEBUG_MAC80211(priv, "leave\n");
2208 return 0;
2209 }
2210
2211 static void iwl_mac_stop(struct ieee80211_hw *hw)
2212 {
2213 struct iwl_priv *priv = hw->priv;
2214
2215 IWL_DEBUG_MAC80211(priv, "enter\n");
2216
2217 if (!priv->is_open)
2218 return;
2219
2220 priv->is_open = 0;
2221
2222 if (iwl_is_ready_rf(priv)) {
2223 /* stop mac, cancel any scan request and clear
2224 * RXON_FILTER_ASSOC_MSK BIT
2225 */
2226 mutex_lock(&priv->mutex);
2227 iwl_scan_cancel_timeout(priv, 100);
2228 mutex_unlock(&priv->mutex);
2229 }
2230
2231 iwl_down(priv);
2232
2233 flush_workqueue(priv->workqueue);
2234
2235 /* enable interrupts again in order to receive rfkill changes */
2236 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2237 iwl_enable_interrupts(priv);
2238
2239 IWL_DEBUG_MAC80211(priv, "leave\n");
2240 }
2241
2242 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2243 {
2244 struct iwl_priv *priv = hw->priv;
2245
2246 IWL_DEBUG_MACDUMP(priv, "enter\n");
2247
2248 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2249 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2250
2251 if (iwl_tx_skb(priv, skb))
2252 dev_kfree_skb_any(skb);
2253
2254 IWL_DEBUG_MACDUMP(priv, "leave\n");
2255 return NETDEV_TX_OK;
2256 }
2257
2258 void iwl_config_ap(struct iwl_priv *priv)
2259 {
2260 int ret = 0;
2261 unsigned long flags;
2262
2263 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2264 return;
2265
2266 /* The following should be done only at AP bring up */
2267 if (!iwl_is_associated(priv)) {
2268
2269 /* RXON - unassoc (to set timing command) */
2270 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2271 iwlcore_commit_rxon(priv);
2272
2273 /* RXON Timing */
2274 iwl_setup_rxon_timing(priv);
2275 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2276 sizeof(priv->rxon_timing), &priv->rxon_timing);
2277 if (ret)
2278 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2279 "Attempting to continue.\n");
2280
2281 if (priv->cfg->ops->hcmd->set_rxon_chain)
2282 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2283
2284 /* FIXME: what should be the assoc_id for AP? */
2285 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2286 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2287 priv->staging_rxon.flags |=
2288 RXON_FLG_SHORT_PREAMBLE_MSK;
2289 else
2290 priv->staging_rxon.flags &=
2291 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2292
2293 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2294 if (priv->assoc_capability &
2295 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2296 priv->staging_rxon.flags |=
2297 RXON_FLG_SHORT_SLOT_MSK;
2298 else
2299 priv->staging_rxon.flags &=
2300 ~RXON_FLG_SHORT_SLOT_MSK;
2301
2302 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2303 priv->staging_rxon.flags &=
2304 ~RXON_FLG_SHORT_SLOT_MSK;
2305 }
2306 /* restore RXON assoc */
2307 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2308 iwlcore_commit_rxon(priv);
2309 spin_lock_irqsave(&priv->lock, flags);
2310 iwl_activate_qos(priv, 1);
2311 spin_unlock_irqrestore(&priv->lock, flags);
2312 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
2313 }
2314 iwl_send_beacon_cmd(priv);
2315
2316 /* FIXME - we need to add code here to detect a totally new
2317 * configuration, reset the AP, unassoc, rxon timing, assoc,
2318 * clear sta table, add BCAST sta... */
2319 }
2320
2321 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2322 struct ieee80211_key_conf *keyconf, const u8 *addr,
2323 u32 iv32, u16 *phase1key)
2324 {
2325
2326 struct iwl_priv *priv = hw->priv;
2327 IWL_DEBUG_MAC80211(priv, "enter\n");
2328
2329 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
2330
2331 IWL_DEBUG_MAC80211(priv, "leave\n");
2332 }
2333
2334 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2335 struct ieee80211_vif *vif,
2336 struct ieee80211_sta *sta,
2337 struct ieee80211_key_conf *key)
2338 {
2339 struct iwl_priv *priv = hw->priv;
2340 const u8 *addr;
2341 int ret;
2342 u8 sta_id;
2343 bool is_default_wep_key = false;
2344
2345 IWL_DEBUG_MAC80211(priv, "enter\n");
2346
2347 if (priv->hw_params.sw_crypto) {
2348 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2349 return -EOPNOTSUPP;
2350 }
2351 addr = sta ? sta->addr : iwl_bcast_addr;
2352 sta_id = iwl_find_station(priv, addr);
2353 if (sta_id == IWL_INVALID_STATION) {
2354 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2355 addr);
2356 return -EINVAL;
2357
2358 }
2359
2360 mutex_lock(&priv->mutex);
2361 iwl_scan_cancel_timeout(priv, 100);
2362 mutex_unlock(&priv->mutex);
2363
2364 /* If we are getting WEP group key and we didn't receive any key mapping
2365 * so far, we are in legacy wep mode (group key only), otherwise we are
2366 * in 1X mode.
2367 * In legacy wep mode, we use another host command to the uCode */
2368 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
2369 priv->iw_mode != NL80211_IFTYPE_AP) {
2370 if (cmd == SET_KEY)
2371 is_default_wep_key = !priv->key_mapping_key;
2372 else
2373 is_default_wep_key =
2374 (key->hw_key_idx == HW_KEY_DEFAULT);
2375 }
2376
2377 switch (cmd) {
2378 case SET_KEY:
2379 if (is_default_wep_key)
2380 ret = iwl_set_default_wep_key(priv, key);
2381 else
2382 ret = iwl_set_dynamic_key(priv, key, sta_id);
2383
2384 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2385 break;
2386 case DISABLE_KEY:
2387 if (is_default_wep_key)
2388 ret = iwl_remove_default_wep_key(priv, key);
2389 else
2390 ret = iwl_remove_dynamic_key(priv, key, sta_id);
2391
2392 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2393 break;
2394 default:
2395 ret = -EINVAL;
2396 }
2397
2398 IWL_DEBUG_MAC80211(priv, "leave\n");
2399
2400 return ret;
2401 }
2402
2403 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
2404 enum ieee80211_ampdu_mlme_action action,
2405 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2406 {
2407 struct iwl_priv *priv = hw->priv;
2408 int ret;
2409
2410 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2411 sta->addr, tid);
2412
2413 if (!(priv->cfg->sku & IWL_SKU_N))
2414 return -EACCES;
2415
2416 switch (action) {
2417 case IEEE80211_AMPDU_RX_START:
2418 IWL_DEBUG_HT(priv, "start Rx\n");
2419 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
2420 case IEEE80211_AMPDU_RX_STOP:
2421 IWL_DEBUG_HT(priv, "stop Rx\n");
2422 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2423 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2424 return 0;
2425 else
2426 return ret;
2427 case IEEE80211_AMPDU_TX_START:
2428 IWL_DEBUG_HT(priv, "start Tx\n");
2429 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
2430 case IEEE80211_AMPDU_TX_STOP:
2431 IWL_DEBUG_HT(priv, "stop Tx\n");
2432 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2433 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2434 return 0;
2435 else
2436 return ret;
2437 default:
2438 IWL_DEBUG_HT(priv, "unknown\n");
2439 return -EINVAL;
2440 break;
2441 }
2442 return 0;
2443 }
2444
2445 static int iwl_mac_get_stats(struct ieee80211_hw *hw,
2446 struct ieee80211_low_level_stats *stats)
2447 {
2448 struct iwl_priv *priv = hw->priv;
2449
2450 priv = hw->priv;
2451 IWL_DEBUG_MAC80211(priv, "enter\n");
2452 IWL_DEBUG_MAC80211(priv, "leave\n");
2453
2454 return 0;
2455 }
2456
2457 /*****************************************************************************
2458 *
2459 * sysfs attributes
2460 *
2461 *****************************************************************************/
2462
2463 #ifdef CONFIG_IWLWIFI_DEBUG
2464
2465 /*
2466 * The following adds a new attribute to the sysfs representation
2467 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
2468 * used for controlling the debug level.
2469 *
2470 * See the level definitions in iwl for details.
2471 */
2472
2473 static ssize_t show_debug_level(struct device *d,
2474 struct device_attribute *attr, char *buf)
2475 {
2476 struct iwl_priv *priv = dev_get_drvdata(d);
2477
2478 return sprintf(buf, "0x%08X\n", priv->debug_level);
2479 }
2480 static ssize_t store_debug_level(struct device *d,
2481 struct device_attribute *attr,
2482 const char *buf, size_t count)
2483 {
2484 struct iwl_priv *priv = dev_get_drvdata(d);
2485 unsigned long val;
2486 int ret;
2487
2488 ret = strict_strtoul(buf, 0, &val);
2489 if (ret)
2490 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
2491 else
2492 priv->debug_level = val;
2493
2494 return strnlen(buf, count);
2495 }
2496
2497 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2498 show_debug_level, store_debug_level);
2499
2500
2501 #endif /* CONFIG_IWLWIFI_DEBUG */
2502
2503
2504 static ssize_t show_version(struct device *d,
2505 struct device_attribute *attr, char *buf)
2506 {
2507 struct iwl_priv *priv = dev_get_drvdata(d);
2508 struct iwl_alive_resp *palive = &priv->card_alive;
2509 ssize_t pos = 0;
2510 u16 eeprom_ver;
2511
2512 if (palive->is_valid)
2513 pos += sprintf(buf + pos,
2514 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
2515 "fw type: 0x%01X 0x%01X\n",
2516 palive->ucode_major, palive->ucode_minor,
2517 palive->sw_rev[0], palive->sw_rev[1],
2518 palive->ver_type, palive->ver_subtype);
2519 else
2520 pos += sprintf(buf + pos, "fw not loaded\n");
2521
2522 if (priv->eeprom) {
2523 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
2524 pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
2525 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
2526 ? "OTP" : "EEPROM", eeprom_ver);
2527
2528 } else {
2529 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
2530 }
2531
2532 return pos;
2533 }
2534
2535 static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
2536
2537 static ssize_t show_temperature(struct device *d,
2538 struct device_attribute *attr, char *buf)
2539 {
2540 struct iwl_priv *priv = dev_get_drvdata(d);
2541
2542 if (!iwl_is_alive(priv))
2543 return -EAGAIN;
2544
2545 return sprintf(buf, "%d\n", priv->temperature);
2546 }
2547
2548 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2549
2550 static ssize_t show_tx_power(struct device *d,
2551 struct device_attribute *attr, char *buf)
2552 {
2553 struct iwl_priv *priv = dev_get_drvdata(d);
2554
2555 if (!iwl_is_ready_rf(priv))
2556 return sprintf(buf, "off\n");
2557 else
2558 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
2559 }
2560
2561 static ssize_t store_tx_power(struct device *d,
2562 struct device_attribute *attr,
2563 const char *buf, size_t count)
2564 {
2565 struct iwl_priv *priv = dev_get_drvdata(d);
2566 unsigned long val;
2567 int ret;
2568
2569 ret = strict_strtoul(buf, 10, &val);
2570 if (ret)
2571 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
2572 else
2573 iwl_set_tx_power(priv, val, false);
2574
2575 return count;
2576 }
2577
2578 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2579
2580 static ssize_t show_flags(struct device *d,
2581 struct device_attribute *attr, char *buf)
2582 {
2583 struct iwl_priv *priv = dev_get_drvdata(d);
2584
2585 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2586 }
2587
2588 static ssize_t store_flags(struct device *d,
2589 struct device_attribute *attr,
2590 const char *buf, size_t count)
2591 {
2592 struct iwl_priv *priv = dev_get_drvdata(d);
2593 unsigned long val;
2594 u32 flags;
2595 int ret = strict_strtoul(buf, 0, &val);
2596 if (ret)
2597 return ret;
2598 flags = (u32)val;
2599
2600 mutex_lock(&priv->mutex);
2601 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2602 /* Cancel any currently running scans... */
2603 if (iwl_scan_cancel_timeout(priv, 100))
2604 IWL_WARN(priv, "Could not cancel scan.\n");
2605 else {
2606 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
2607 priv->staging_rxon.flags = cpu_to_le32(flags);
2608 iwlcore_commit_rxon(priv);
2609 }
2610 }
2611 mutex_unlock(&priv->mutex);
2612
2613 return count;
2614 }
2615
2616 static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2617
2618 static ssize_t show_filter_flags(struct device *d,
2619 struct device_attribute *attr, char *buf)
2620 {
2621 struct iwl_priv *priv = dev_get_drvdata(d);
2622
2623 return sprintf(buf, "0x%04X\n",
2624 le32_to_cpu(priv->active_rxon.filter_flags));
2625 }
2626
2627 static ssize_t store_filter_flags(struct device *d,
2628 struct device_attribute *attr,
2629 const char *buf, size_t count)
2630 {
2631 struct iwl_priv *priv = dev_get_drvdata(d);
2632 unsigned long val;
2633 u32 filter_flags;
2634 int ret = strict_strtoul(buf, 0, &val);
2635 if (ret)
2636 return ret;
2637 filter_flags = (u32)val;
2638
2639 mutex_lock(&priv->mutex);
2640 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2641 /* Cancel any currently running scans... */
2642 if (iwl_scan_cancel_timeout(priv, 100))
2643 IWL_WARN(priv, "Could not cancel scan.\n");
2644 else {
2645 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
2646 "0x%04X\n", filter_flags);
2647 priv->staging_rxon.filter_flags =
2648 cpu_to_le32(filter_flags);
2649 iwlcore_commit_rxon(priv);
2650 }
2651 }
2652 mutex_unlock(&priv->mutex);
2653
2654 return count;
2655 }
2656
2657 static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2658 store_filter_flags);
2659
2660 static ssize_t store_power_level(struct device *d,
2661 struct device_attribute *attr,
2662 const char *buf, size_t count)
2663 {
2664 struct iwl_priv *priv = dev_get_drvdata(d);
2665 int ret;
2666 unsigned long mode;
2667
2668
2669 mutex_lock(&priv->mutex);
2670
2671 ret = strict_strtoul(buf, 10, &mode);
2672 if (ret)
2673 goto out;
2674
2675 ret = iwl_power_set_user_mode(priv, mode);
2676 if (ret) {
2677 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
2678 goto out;
2679 }
2680 ret = count;
2681
2682 out:
2683 mutex_unlock(&priv->mutex);
2684 return ret;
2685 }
2686
2687 static ssize_t show_power_level(struct device *d,
2688 struct device_attribute *attr, char *buf)
2689 {
2690 struct iwl_priv *priv = dev_get_drvdata(d);
2691 int mode = priv->power_data.user_power_setting;
2692 int level = priv->power_data.power_mode;
2693 char *p = buf;
2694
2695 p += sprintf(p, "INDEX:%d\t", level);
2696 p += sprintf(p, "USER:%d\n", mode);
2697 return p - buf + 1;
2698 }
2699
2700 static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2701 store_power_level);
2702
2703 static ssize_t show_qos(struct device *d,
2704 struct device_attribute *attr, char *buf)
2705 {
2706 struct iwl_priv *priv = dev_get_drvdata(d);
2707 char *p = buf;
2708 int q;
2709
2710 for (q = 0; q < AC_NUM; q++) {
2711 p += sprintf(p, "\tcw_min\tcw_max\taifsn\ttxop\n");
2712 p += sprintf(p, "AC[%d]\t%u\t%u\t%u\t%u\n", q,
2713 priv->qos_data.def_qos_parm.ac[q].cw_min,
2714 priv->qos_data.def_qos_parm.ac[q].cw_max,
2715 priv->qos_data.def_qos_parm.ac[q].aifsn,
2716 priv->qos_data.def_qos_parm.ac[q].edca_txop);
2717 }
2718
2719 return p - buf + 1;
2720 }
2721
2722 static DEVICE_ATTR(qos, S_IRUGO, show_qos, NULL);
2723
2724 static ssize_t show_statistics(struct device *d,
2725 struct device_attribute *attr, char *buf)
2726 {
2727 struct iwl_priv *priv = dev_get_drvdata(d);
2728 u32 size = sizeof(struct iwl_notif_statistics);
2729 u32 len = 0, ofs = 0;
2730 u8 *data = (u8 *)&priv->statistics;
2731 int rc = 0;
2732
2733 if (!iwl_is_alive(priv))
2734 return -EAGAIN;
2735
2736 mutex_lock(&priv->mutex);
2737 rc = iwl_send_statistics_request(priv, 0);
2738 mutex_unlock(&priv->mutex);
2739
2740 if (rc) {
2741 len = sprintf(buf,
2742 "Error sending statistics request: 0x%08X\n", rc);
2743 return len;
2744 }
2745
2746 while (size && (PAGE_SIZE - len)) {
2747 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2748 PAGE_SIZE - len, 1);
2749 len = strlen(buf);
2750 if (PAGE_SIZE - len)
2751 buf[len++] = '\n';
2752
2753 ofs += 16;
2754 size -= min(size, 16U);
2755 }
2756
2757 return len;
2758 }
2759
2760 static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2761
2762
2763 /*****************************************************************************
2764 *
2765 * driver setup and teardown
2766 *
2767 *****************************************************************************/
2768
2769 static void iwl_setup_deferred_work(struct iwl_priv *priv)
2770 {
2771 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
2772
2773 init_waitqueue_head(&priv->wait_command_queue);
2774
2775 INIT_WORK(&priv->up, iwl_bg_up);
2776 INIT_WORK(&priv->restart, iwl_bg_restart);
2777 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2778 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
2779 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
2780 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
2781 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2782 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2783
2784 iwl_setup_scan_deferred_work(priv);
2785
2786 if (priv->cfg->ops->lib->setup_deferred_work)
2787 priv->cfg->ops->lib->setup_deferred_work(priv);
2788
2789 init_timer(&priv->statistics_periodic);
2790 priv->statistics_periodic.data = (unsigned long)priv;
2791 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
2792
2793 if (!priv->cfg->use_isr_legacy)
2794 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2795 iwl_irq_tasklet, (unsigned long)priv);
2796 else
2797 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2798 iwl_irq_tasklet_legacy, (unsigned long)priv);
2799 }
2800
2801 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
2802 {
2803 if (priv->cfg->ops->lib->cancel_deferred_work)
2804 priv->cfg->ops->lib->cancel_deferred_work(priv);
2805
2806 cancel_delayed_work_sync(&priv->init_alive_start);
2807 cancel_delayed_work(&priv->scan_check);
2808 cancel_delayed_work(&priv->alive_start);
2809 cancel_work_sync(&priv->beacon_update);
2810 del_timer_sync(&priv->statistics_periodic);
2811 }
2812
2813 static struct attribute *iwl_sysfs_entries[] = {
2814 &dev_attr_flags.attr,
2815 &dev_attr_filter_flags.attr,
2816 &dev_attr_power_level.attr,
2817 &dev_attr_statistics.attr,
2818 &dev_attr_temperature.attr,
2819 &dev_attr_tx_power.attr,
2820 #ifdef CONFIG_IWLWIFI_DEBUG
2821 &dev_attr_debug_level.attr,
2822 #endif
2823 &dev_attr_version.attr,
2824 &dev_attr_qos.attr,
2825 NULL
2826 };
2827
2828 static struct attribute_group iwl_attribute_group = {
2829 .name = NULL, /* put in device directory */
2830 .attrs = iwl_sysfs_entries,
2831 };
2832
2833 static struct ieee80211_ops iwl_hw_ops = {
2834 .tx = iwl_mac_tx,
2835 .start = iwl_mac_start,
2836 .stop = iwl_mac_stop,
2837 .add_interface = iwl_mac_add_interface,
2838 .remove_interface = iwl_mac_remove_interface,
2839 .config = iwl_mac_config,
2840 .configure_filter = iwl_configure_filter,
2841 .set_key = iwl_mac_set_key,
2842 .update_tkip_key = iwl_mac_update_tkip_key,
2843 .get_stats = iwl_mac_get_stats,
2844 .get_tx_stats = iwl_mac_get_tx_stats,
2845 .conf_tx = iwl_mac_conf_tx,
2846 .reset_tsf = iwl_mac_reset_tsf,
2847 .bss_info_changed = iwl_bss_info_changed,
2848 .ampdu_action = iwl_mac_ampdu_action,
2849 .hw_scan = iwl_mac_hw_scan
2850 };
2851
2852 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2853 {
2854 int err = 0;
2855 struct iwl_priv *priv;
2856 struct ieee80211_hw *hw;
2857 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
2858 unsigned long flags;
2859 u16 pci_cmd;
2860
2861 /************************
2862 * 1. Allocating HW data
2863 ************************/
2864
2865 /* Disabling hardware scan means that mac80211 will perform scans
2866 * "the hard way", rather than using device's scan. */
2867 if (cfg->mod_params->disable_hw_scan) {
2868 if (cfg->mod_params->debug & IWL_DL_INFO)
2869 dev_printk(KERN_DEBUG, &(pdev->dev),
2870 "Disabling hw_scan\n");
2871 iwl_hw_ops.hw_scan = NULL;
2872 }
2873
2874 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
2875 if (!hw) {
2876 err = -ENOMEM;
2877 goto out;
2878 }
2879 priv = hw->priv;
2880 /* At this point both hw and priv are allocated. */
2881
2882 SET_IEEE80211_DEV(hw, &pdev->dev);
2883
2884 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
2885 priv->cfg = cfg;
2886 priv->pci_dev = pdev;
2887 priv->inta_mask = CSR_INI_SET_MASK;
2888
2889 #ifdef CONFIG_IWLWIFI_DEBUG
2890 priv->debug_level = priv->cfg->mod_params->debug;
2891 atomic_set(&priv->restrict_refcnt, 0);
2892 #endif
2893
2894 /**************************
2895 * 2. Initializing PCI bus
2896 **************************/
2897 if (pci_enable_device(pdev)) {
2898 err = -ENODEV;
2899 goto out_ieee80211_free_hw;
2900 }
2901
2902 pci_set_master(pdev);
2903
2904 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2905 if (!err)
2906 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2907 if (err) {
2908 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2909 if (!err)
2910 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2911 /* both attempts failed: */
2912 if (err) {
2913 IWL_WARN(priv, "No suitable DMA available.\n");
2914 goto out_pci_disable_device;
2915 }
2916 }
2917
2918 err = pci_request_regions(pdev, DRV_NAME);
2919 if (err)
2920 goto out_pci_disable_device;
2921
2922 pci_set_drvdata(pdev, priv);
2923
2924
2925 /***********************
2926 * 3. Read REV register
2927 ***********************/
2928 priv->hw_base = pci_iomap(pdev, 0, 0);
2929 if (!priv->hw_base) {
2930 err = -ENODEV;
2931 goto out_pci_release_regions;
2932 }
2933
2934 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
2935 (unsigned long long) pci_resource_len(pdev, 0));
2936 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
2937
2938 /* this spin lock will be used in apm_ops.init and EEPROM access
2939 * we should init now
2940 */
2941 spin_lock_init(&priv->reg_lock);
2942 iwl_hw_detect(priv);
2943 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
2944 priv->cfg->name, priv->hw_rev);
2945
2946 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2947 * PCI Tx retries from interfering with C3 CPU state */
2948 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2949
2950 iwl_prepare_card_hw(priv);
2951 if (!priv->hw_ready) {
2952 IWL_WARN(priv, "Failed, HW not ready\n");
2953 goto out_iounmap;
2954 }
2955
2956 /* amp init */
2957 err = priv->cfg->ops->lib->apm_ops.init(priv);
2958 if (err < 0) {
2959 IWL_ERR(priv, "Failed to init APMG\n");
2960 goto out_iounmap;
2961 }
2962 /*****************
2963 * 4. Read EEPROM
2964 *****************/
2965 /* Read the EEPROM */
2966 err = iwl_eeprom_init(priv);
2967 if (err) {
2968 IWL_ERR(priv, "Unable to init EEPROM\n");
2969 goto out_iounmap;
2970 }
2971 err = iwl_eeprom_check_version(priv);
2972 if (err)
2973 goto out_free_eeprom;
2974
2975 /* extract MAC Address */
2976 iwl_eeprom_get_mac(priv, priv->mac_addr);
2977 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
2978 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
2979
2980 /************************
2981 * 5. Setup HW constants
2982 ************************/
2983 if (iwl_set_hw_params(priv)) {
2984 IWL_ERR(priv, "failed to set hw parameters\n");
2985 goto out_free_eeprom;
2986 }
2987
2988 /*******************
2989 * 6. Setup priv
2990 *******************/
2991
2992 err = iwl_init_drv(priv);
2993 if (err)
2994 goto out_free_eeprom;
2995 /* At this point both hw and priv are initialized. */
2996
2997 /********************
2998 * 7. Setup services
2999 ********************/
3000 spin_lock_irqsave(&priv->lock, flags);
3001 iwl_disable_interrupts(priv);
3002 spin_unlock_irqrestore(&priv->lock, flags);
3003
3004 pci_enable_msi(priv->pci_dev);
3005
3006 iwl_alloc_isr_ict(priv);
3007 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3008 IRQF_SHARED, DRV_NAME, priv);
3009 if (err) {
3010 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3011 goto out_disable_msi;
3012 }
3013 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3014 if (err) {
3015 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3016 goto out_free_irq;
3017 }
3018
3019 iwl_setup_deferred_work(priv);
3020 iwl_setup_rx_handlers(priv);
3021
3022 /**********************************
3023 * 8. Setup and register mac80211
3024 **********************************/
3025
3026 /* enable interrupts if needed: hw bug w/a */
3027 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3028 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3029 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3030 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3031 }
3032
3033 iwl_enable_interrupts(priv);
3034
3035 err = iwl_setup_mac(priv);
3036 if (err)
3037 goto out_remove_sysfs;
3038
3039 err = iwl_dbgfs_register(priv, DRV_NAME);
3040 if (err)
3041 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
3042
3043 /* If platform's RF_KILL switch is NOT set to KILL */
3044 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3045 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3046 else
3047 set_bit(STATUS_RF_KILL_HW, &priv->status);
3048
3049 err = iwl_rfkill_init(priv);
3050 if (err)
3051 IWL_ERR(priv, "Unable to initialize RFKILL system. "
3052 "Ignoring error: %d\n", err);
3053 else
3054 iwl_rfkill_set_hw_state(priv);
3055
3056 iwl_power_initialize(priv);
3057 return 0;
3058
3059 out_remove_sysfs:
3060 destroy_workqueue(priv->workqueue);
3061 priv->workqueue = NULL;
3062 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3063 out_free_irq:
3064 free_irq(priv->pci_dev->irq, priv);
3065 iwl_free_isr_ict(priv);
3066 out_disable_msi:
3067 pci_disable_msi(priv->pci_dev);
3068 iwl_uninit_drv(priv);
3069 out_free_eeprom:
3070 iwl_eeprom_free(priv);
3071 out_iounmap:
3072 pci_iounmap(pdev, priv->hw_base);
3073 out_pci_release_regions:
3074 pci_set_drvdata(pdev, NULL);
3075 pci_release_regions(pdev);
3076 out_pci_disable_device:
3077 pci_disable_device(pdev);
3078 out_ieee80211_free_hw:
3079 ieee80211_free_hw(priv->hw);
3080 out:
3081 return err;
3082 }
3083
3084 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3085 {
3086 struct iwl_priv *priv = pci_get_drvdata(pdev);
3087 unsigned long flags;
3088
3089 if (!priv)
3090 return;
3091
3092 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3093
3094 iwl_dbgfs_unregister(priv);
3095 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3096
3097 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3098 * to be called and iwl_down since we are removing the device
3099 * we need to set STATUS_EXIT_PENDING bit.
3100 */
3101 set_bit(STATUS_EXIT_PENDING, &priv->status);
3102 if (priv->mac80211_registered) {
3103 ieee80211_unregister_hw(priv->hw);
3104 priv->mac80211_registered = 0;
3105 } else {
3106 iwl_down(priv);
3107 }
3108
3109 /* make sure we flush any pending irq or
3110 * tasklet for the driver
3111 */
3112 spin_lock_irqsave(&priv->lock, flags);
3113 iwl_disable_interrupts(priv);
3114 spin_unlock_irqrestore(&priv->lock, flags);
3115
3116 iwl_synchronize_irq(priv);
3117
3118 iwl_rfkill_unregister(priv);
3119 iwl_dealloc_ucode_pci(priv);
3120
3121 if (priv->rxq.bd)
3122 iwl_rx_queue_free(priv, &priv->rxq);
3123 iwl_hw_txq_ctx_free(priv);
3124
3125 iwl_clear_stations_table(priv);
3126 iwl_eeprom_free(priv);
3127
3128
3129 /*netif_stop_queue(dev); */
3130 flush_workqueue(priv->workqueue);
3131
3132 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3133 * priv->workqueue... so we can't take down the workqueue
3134 * until now... */
3135 destroy_workqueue(priv->workqueue);
3136 priv->workqueue = NULL;
3137
3138 free_irq(priv->pci_dev->irq, priv);
3139 pci_disable_msi(priv->pci_dev);
3140 pci_iounmap(pdev, priv->hw_base);
3141 pci_release_regions(pdev);
3142 pci_disable_device(pdev);
3143 pci_set_drvdata(pdev, NULL);
3144
3145 iwl_uninit_drv(priv);
3146
3147 iwl_free_isr_ict(priv);
3148
3149 if (priv->ibss_beacon)
3150 dev_kfree_skb(priv->ibss_beacon);
3151
3152 ieee80211_free_hw(priv->hw);
3153 }
3154
3155
3156 /*****************************************************************************
3157 *
3158 * driver and module entry point
3159 *
3160 *****************************************************************************/
3161
3162 /* Hardware specific file defines the PCI IDs table for that hardware module */
3163 static struct pci_device_id iwl_hw_card_ids[] = {
3164 #ifdef CONFIG_IWL4965
3165 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3166 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3167 #endif /* CONFIG_IWL4965 */
3168 #ifdef CONFIG_IWL5000
3169 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3170 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3171 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3172 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3173 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3174 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
3175 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
3176 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3177 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3178 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
3179 /* 5350 WiFi/WiMax */
3180 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3181 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3182 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
3183 /* 5150 Wifi/WiMax */
3184 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3185 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
3186 /* 6000/6050 Series */
3187 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3188 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3189 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3190 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
3191 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
3192 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
3193 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
3194 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3195 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3196 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3197 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3198 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3199 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
3200 /* 1000 Series WiFi */
3201 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3202 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
3203 #endif /* CONFIG_IWL5000 */
3204
3205 {0}
3206 };
3207 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3208
3209 static struct pci_driver iwl_driver = {
3210 .name = DRV_NAME,
3211 .id_table = iwl_hw_card_ids,
3212 .probe = iwl_pci_probe,
3213 .remove = __devexit_p(iwl_pci_remove),
3214 #ifdef CONFIG_PM
3215 .suspend = iwl_pci_suspend,
3216 .resume = iwl_pci_resume,
3217 #endif
3218 };
3219
3220 static int __init iwl_init(void)
3221 {
3222
3223 int ret;
3224 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3225 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3226
3227 ret = iwlagn_rate_control_register();
3228 if (ret) {
3229 printk(KERN_ERR DRV_NAME
3230 "Unable to register rate control algorithm: %d\n", ret);
3231 return ret;
3232 }
3233
3234 ret = pci_register_driver(&iwl_driver);
3235 if (ret) {
3236 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3237 goto error_register;
3238 }
3239
3240 return ret;
3241
3242 error_register:
3243 iwlagn_rate_control_unregister();
3244 return ret;
3245 }
3246
3247 static void __exit iwl_exit(void)
3248 {
3249 pci_unregister_driver(&iwl_driver);
3250 iwlagn_rate_control_unregister();
3251 }
3252
3253 module_exit(iwl_exit);
3254 module_init(iwl_init);
Linux kernel - Deliverables
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