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iwlagn: refactor up path
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70 /*
71 * module name, copyright, version, etc.
72 */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94 struct iwl_rxon_context *ctx;
95
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 }
103 }
104
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
106 {
107 struct list_head *element;
108
109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
110 priv->frames_count);
111
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
114 list_del(element);
115 kfree(list_entry(element, struct iwl_frame, list));
116 priv->frames_count--;
117 }
118
119 if (priv->frames_count) {
120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
121 priv->frames_count);
122 priv->frames_count = 0;
123 }
124 }
125
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
127 {
128 struct iwl_frame *frame;
129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132 if (!frame) {
133 IWL_ERR(priv, "Could not allocate frame!\n");
134 return NULL;
135 }
136
137 priv->frames_count++;
138 return frame;
139 }
140
141 element = priv->free_frames.next;
142 list_del(element);
143 return list_entry(element, struct iwl_frame, list);
144 }
145
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
147 {
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
150 }
151
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153 struct ieee80211_hdr *hdr,
154 int left)
155 {
156 lockdep_assert_held(&priv->mutex);
157
158 if (!priv->beacon_skb)
159 return 0;
160
161 if (priv->beacon_skb->len > left)
162 return 0;
163
164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
165
166 return priv->beacon_skb->len;
167 }
168
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
173 {
174 u16 tim_idx;
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177 /*
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
180 */
181 tim_idx = mgmt->u.beacon.variable - beacon;
182
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
187
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192 } else
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194 }
195
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197 struct iwl_frame *frame)
198 {
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
200 u32 frame_size;
201 u32 rate_flags;
202 u32 rate;
203 /*
204 * We have to set up the TX command, the TX Beacon command, and the
205 * beacon contents.
206 */
207
208 lockdep_assert_held(&priv->mutex);
209
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
212 return 0;
213 }
214
215 /* Initialize memory */
216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
219 /* Set up TX beacon contents */
220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223 return 0;
224 if (!frame_size)
225 return 0;
226
227 /* Set up TX command fields */
228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
233
234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
236 frame_size);
237
238 /* Set up packet rate and flags */
239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246 rate_flags);
247
248 return sizeof(*tx_beacon_cmd) + frame_size;
249 }
250
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
252 {
253 struct iwl_frame *frame;
254 unsigned int frame_size;
255 int rc;
256 struct iwl_host_cmd cmd = {
257 .id = REPLY_TX_BEACON,
258 .flags = CMD_SIZE_HUGE,
259 };
260
261 frame = iwl_get_free_frame(priv);
262 if (!frame) {
263 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
264 "command.\n");
265 return -ENOMEM;
266 }
267
268 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
269 if (!frame_size) {
270 IWL_ERR(priv, "Error configuring the beacon command\n");
271 iwl_free_frame(priv, frame);
272 return -EINVAL;
273 }
274
275 cmd.len = frame_size;
276 cmd.data = &frame->u.cmd[0];
277
278 rc = iwl_send_cmd_sync(priv, &cmd);
279
280 iwl_free_frame(priv, frame);
281
282 return rc;
283 }
284
285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
286 {
287 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
288
289 dma_addr_t addr = get_unaligned_le32(&tb->lo);
290 if (sizeof(dma_addr_t) > sizeof(u32))
291 addr |=
292 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
293
294 return addr;
295 }
296
297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
298 {
299 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
300
301 return le16_to_cpu(tb->hi_n_len) >> 4;
302 }
303
304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
305 dma_addr_t addr, u16 len)
306 {
307 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
308 u16 hi_n_len = len << 4;
309
310 put_unaligned_le32(addr, &tb->lo);
311 if (sizeof(dma_addr_t) > sizeof(u32))
312 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
313
314 tb->hi_n_len = cpu_to_le16(hi_n_len);
315
316 tfd->num_tbs = idx + 1;
317 }
318
319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
320 {
321 return tfd->num_tbs & 0x1f;
322 }
323
324 /**
325 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
326 * @priv - driver private data
327 * @txq - tx queue
328 *
329 * Does NOT advance any TFD circular buffer read/write indexes
330 * Does NOT free the TFD itself (which is within circular buffer)
331 */
332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
333 {
334 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
335 struct iwl_tfd *tfd;
336 struct pci_dev *dev = priv->pci_dev;
337 int index = txq->q.read_ptr;
338 int i;
339 int num_tbs;
340
341 tfd = &tfd_tmp[index];
342
343 /* Sanity check on number of chunks */
344 num_tbs = iwl_tfd_get_num_tbs(tfd);
345
346 if (num_tbs >= IWL_NUM_OF_TBS) {
347 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
348 /* @todo issue fatal error, it is quite serious situation */
349 return;
350 }
351
352 /* Unmap tx_cmd */
353 if (num_tbs)
354 pci_unmap_single(dev,
355 dma_unmap_addr(&txq->meta[index], mapping),
356 dma_unmap_len(&txq->meta[index], len),
357 PCI_DMA_BIDIRECTIONAL);
358
359 /* Unmap chunks, if any. */
360 for (i = 1; i < num_tbs; i++)
361 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
362 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
363
364 /* free SKB */
365 if (txq->txb) {
366 struct sk_buff *skb;
367
368 skb = txq->txb[txq->q.read_ptr].skb;
369
370 /* can be called from irqs-disabled context */
371 if (skb) {
372 dev_kfree_skb_any(skb);
373 txq->txb[txq->q.read_ptr].skb = NULL;
374 }
375 }
376 }
377
378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
379 struct iwl_tx_queue *txq,
380 dma_addr_t addr, u16 len,
381 u8 reset, u8 pad)
382 {
383 struct iwl_queue *q;
384 struct iwl_tfd *tfd, *tfd_tmp;
385 u32 num_tbs;
386
387 q = &txq->q;
388 tfd_tmp = (struct iwl_tfd *)txq->tfds;
389 tfd = &tfd_tmp[q->write_ptr];
390
391 if (reset)
392 memset(tfd, 0, sizeof(*tfd));
393
394 num_tbs = iwl_tfd_get_num_tbs(tfd);
395
396 /* Each TFD can point to a maximum 20 Tx buffers */
397 if (num_tbs >= IWL_NUM_OF_TBS) {
398 IWL_ERR(priv, "Error can not send more than %d chunks\n",
399 IWL_NUM_OF_TBS);
400 return -EINVAL;
401 }
402
403 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
404 return -EINVAL;
405
406 if (unlikely(addr & ~IWL_TX_DMA_MASK))
407 IWL_ERR(priv, "Unaligned address = %llx\n",
408 (unsigned long long)addr);
409
410 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
411
412 return 0;
413 }
414
415 /*
416 * Tell nic where to find circular buffer of Tx Frame Descriptors for
417 * given Tx queue, and enable the DMA channel used for that queue.
418 *
419 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
420 * channels supported in hardware.
421 */
422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
423 struct iwl_tx_queue *txq)
424 {
425 int txq_id = txq->q.id;
426
427 /* Circular buffer (TFD queue in DRAM) physical base address */
428 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
429 txq->q.dma_addr >> 8);
430
431 return 0;
432 }
433
434 static void iwl_bg_beacon_update(struct work_struct *work)
435 {
436 struct iwl_priv *priv =
437 container_of(work, struct iwl_priv, beacon_update);
438 struct sk_buff *beacon;
439
440 mutex_lock(&priv->mutex);
441 if (!priv->beacon_ctx) {
442 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
443 goto out;
444 }
445
446 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
447 /*
448 * The ucode will send beacon notifications even in
449 * IBSS mode, but we don't want to process them. But
450 * we need to defer the type check to here due to
451 * requiring locking around the beacon_ctx access.
452 */
453 goto out;
454 }
455
456 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
457 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
458 if (!beacon) {
459 IWL_ERR(priv, "update beacon failed -- keeping old\n");
460 goto out;
461 }
462
463 /* new beacon skb is allocated every time; dispose previous.*/
464 dev_kfree_skb(priv->beacon_skb);
465
466 priv->beacon_skb = beacon;
467
468 iwlagn_send_beacon_cmd(priv);
469 out:
470 mutex_unlock(&priv->mutex);
471 }
472
473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
474 {
475 struct iwl_priv *priv =
476 container_of(work, struct iwl_priv, bt_runtime_config);
477
478 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
479 return;
480
481 /* dont send host command if rf-kill is on */
482 if (!iwl_is_ready_rf(priv))
483 return;
484 priv->cfg->ops->hcmd->send_bt_config(priv);
485 }
486
487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
488 {
489 struct iwl_priv *priv =
490 container_of(work, struct iwl_priv, bt_full_concurrency);
491 struct iwl_rxon_context *ctx;
492
493 mutex_lock(&priv->mutex);
494
495 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
496 goto out;
497
498 /* dont send host command if rf-kill is on */
499 if (!iwl_is_ready_rf(priv))
500 goto out;
501
502 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
503 priv->bt_full_concurrent ?
504 "full concurrency" : "3-wire");
505
506 /*
507 * LQ & RXON updated cmds must be sent before BT Config cmd
508 * to avoid 3-wire collisions
509 */
510 for_each_context(priv, ctx) {
511 if (priv->cfg->ops->hcmd->set_rxon_chain)
512 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
513 iwlcore_commit_rxon(priv, ctx);
514 }
515
516 priv->cfg->ops->hcmd->send_bt_config(priv);
517 out:
518 mutex_unlock(&priv->mutex);
519 }
520
521 /**
522 * iwl_bg_statistics_periodic - Timer callback to queue statistics
523 *
524 * This callback is provided in order to send a statistics request.
525 *
526 * This timer function is continually reset to execute within
527 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
528 * was received. We need to ensure we receive the statistics in order
529 * to update the temperature used for calibrating the TXPOWER.
530 */
531 static void iwl_bg_statistics_periodic(unsigned long data)
532 {
533 struct iwl_priv *priv = (struct iwl_priv *)data;
534
535 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
536 return;
537
538 /* dont send host command if rf-kill is on */
539 if (!iwl_is_ready_rf(priv))
540 return;
541
542 iwl_send_statistics_request(priv, CMD_ASYNC, false);
543 }
544
545
546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
547 u32 start_idx, u32 num_events,
548 u32 mode)
549 {
550 u32 i;
551 u32 ptr; /* SRAM byte address of log data */
552 u32 ev, time, data; /* event log data */
553 unsigned long reg_flags;
554
555 if (mode == 0)
556 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
557 else
558 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
559
560 /* Make sure device is powered up for SRAM reads */
561 spin_lock_irqsave(&priv->reg_lock, reg_flags);
562 if (iwl_grab_nic_access(priv)) {
563 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
564 return;
565 }
566
567 /* Set starting address; reads will auto-increment */
568 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
569 rmb();
570
571 /*
572 * "time" is actually "data" for mode 0 (no timestamp).
573 * place event id # at far right for easier visual parsing.
574 */
575 for (i = 0; i < num_events; i++) {
576 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
578 if (mode == 0) {
579 trace_iwlwifi_dev_ucode_cont_event(priv,
580 0, time, ev);
581 } else {
582 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
583 trace_iwlwifi_dev_ucode_cont_event(priv,
584 time, data, ev);
585 }
586 }
587 /* Allow device to power down */
588 iwl_release_nic_access(priv);
589 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
590 }
591
592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
593 {
594 u32 capacity; /* event log capacity in # entries */
595 u32 base; /* SRAM byte address of event log header */
596 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
597 u32 num_wraps; /* # times uCode wrapped to top of log */
598 u32 next_entry; /* index of next entry to be written by uCode */
599
600 base = priv->device_pointers.error_event_table;
601 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
602 capacity = iwl_read_targ_mem(priv, base);
603 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
604 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
605 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
606 } else
607 return;
608
609 if (num_wraps == priv->event_log.num_wraps) {
610 iwl_print_cont_event_trace(priv,
611 base, priv->event_log.next_entry,
612 next_entry - priv->event_log.next_entry,
613 mode);
614 priv->event_log.non_wraps_count++;
615 } else {
616 if ((num_wraps - priv->event_log.num_wraps) > 1)
617 priv->event_log.wraps_more_count++;
618 else
619 priv->event_log.wraps_once_count++;
620 trace_iwlwifi_dev_ucode_wrap_event(priv,
621 num_wraps - priv->event_log.num_wraps,
622 next_entry, priv->event_log.next_entry);
623 if (next_entry < priv->event_log.next_entry) {
624 iwl_print_cont_event_trace(priv, base,
625 priv->event_log.next_entry,
626 capacity - priv->event_log.next_entry,
627 mode);
628
629 iwl_print_cont_event_trace(priv, base, 0,
630 next_entry, mode);
631 } else {
632 iwl_print_cont_event_trace(priv, base,
633 next_entry, capacity - next_entry,
634 mode);
635
636 iwl_print_cont_event_trace(priv, base, 0,
637 next_entry, mode);
638 }
639 }
640 priv->event_log.num_wraps = num_wraps;
641 priv->event_log.next_entry = next_entry;
642 }
643
644 /**
645 * iwl_bg_ucode_trace - Timer callback to log ucode event
646 *
647 * The timer is continually set to execute every
648 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
649 * this function is to perform continuous uCode event logging operation
650 * if enabled
651 */
652 static void iwl_bg_ucode_trace(unsigned long data)
653 {
654 struct iwl_priv *priv = (struct iwl_priv *)data;
655
656 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
657 return;
658
659 if (priv->event_log.ucode_trace) {
660 iwl_continuous_event_trace(priv);
661 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
662 mod_timer(&priv->ucode_trace,
663 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
664 }
665 }
666
667 static void iwl_bg_tx_flush(struct work_struct *work)
668 {
669 struct iwl_priv *priv =
670 container_of(work, struct iwl_priv, tx_flush);
671
672 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
673 return;
674
675 /* do nothing if rf-kill is on */
676 if (!iwl_is_ready_rf(priv))
677 return;
678
679 if (priv->cfg->ops->lib->txfifo_flush) {
680 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
681 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
682 }
683 }
684
685 /**
686 * iwl_rx_handle - Main entry function for receiving responses from uCode
687 *
688 * Uses the priv->rx_handlers callback function array to invoke
689 * the appropriate handlers, including command responses,
690 * frame-received notifications, and other notifications.
691 */
692 static void iwl_rx_handle(struct iwl_priv *priv)
693 {
694 struct iwl_rx_mem_buffer *rxb;
695 struct iwl_rx_packet *pkt;
696 struct iwl_rx_queue *rxq = &priv->rxq;
697 u32 r, i;
698 int reclaim;
699 unsigned long flags;
700 u8 fill_rx = 0;
701 u32 count = 8;
702 int total_empty;
703
704 /* uCode's read index (stored in shared DRAM) indicates the last Rx
705 * buffer that the driver may process (last buffer filled by ucode). */
706 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
707 i = rxq->read;
708
709 /* Rx interrupt, but nothing sent from uCode */
710 if (i == r)
711 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
712
713 /* calculate total frames need to be restock after handling RX */
714 total_empty = r - rxq->write_actual;
715 if (total_empty < 0)
716 total_empty += RX_QUEUE_SIZE;
717
718 if (total_empty > (RX_QUEUE_SIZE / 2))
719 fill_rx = 1;
720
721 while (i != r) {
722 int len;
723
724 rxb = rxq->queue[i];
725
726 /* If an RXB doesn't have a Rx queue slot associated with it,
727 * then a bug has been introduced in the queue refilling
728 * routines -- catch it here */
729 if (WARN_ON(rxb == NULL)) {
730 i = (i + 1) & RX_QUEUE_MASK;
731 continue;
732 }
733
734 rxq->queue[i] = NULL;
735
736 pci_unmap_page(priv->pci_dev, rxb->page_dma,
737 PAGE_SIZE << priv->hw_params.rx_page_order,
738 PCI_DMA_FROMDEVICE);
739 pkt = rxb_addr(rxb);
740
741 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
742 len += sizeof(u32); /* account for status word */
743 trace_iwlwifi_dev_rx(priv, pkt, len);
744
745 /* Reclaim a command buffer only if this packet is a response
746 * to a (driver-originated) command.
747 * If the packet (e.g. Rx frame) originated from uCode,
748 * there is no command buffer to reclaim.
749 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
750 * but apparently a few don't get set; catch them here. */
751 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
752 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
753 (pkt->hdr.cmd != REPLY_RX) &&
754 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
755 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
756 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
757 (pkt->hdr.cmd != REPLY_TX);
758
759 /*
760 * Do the notification wait before RX handlers so
761 * even if the RX handler consumes the RXB we have
762 * access to it in the notification wait entry.
763 */
764 if (!list_empty(&priv->_agn.notif_waits)) {
765 struct iwl_notification_wait *w;
766
767 spin_lock(&priv->_agn.notif_wait_lock);
768 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
769 if (w->cmd == pkt->hdr.cmd) {
770 w->triggered = true;
771 if (w->fn)
772 w->fn(priv, pkt);
773 }
774 }
775 spin_unlock(&priv->_agn.notif_wait_lock);
776
777 wake_up_all(&priv->_agn.notif_waitq);
778 }
779
780 /* Based on type of command response or notification,
781 * handle those that need handling via function in
782 * rx_handlers table. See iwl_setup_rx_handlers() */
783 if (priv->rx_handlers[pkt->hdr.cmd]) {
784 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
785 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
786 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
787 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
788 } else {
789 /* No handling needed */
790 IWL_DEBUG_RX(priv,
791 "r %d i %d No handler needed for %s, 0x%02x\n",
792 r, i, get_cmd_string(pkt->hdr.cmd),
793 pkt->hdr.cmd);
794 }
795
796 /*
797 * XXX: After here, we should always check rxb->page
798 * against NULL before touching it or its virtual
799 * memory (pkt). Because some rx_handler might have
800 * already taken or freed the pages.
801 */
802
803 if (reclaim) {
804 /* Invoke any callbacks, transfer the buffer to caller,
805 * and fire off the (possibly) blocking iwl_send_cmd()
806 * as we reclaim the driver command queue */
807 if (rxb->page)
808 iwl_tx_cmd_complete(priv, rxb);
809 else
810 IWL_WARN(priv, "Claim null rxb?\n");
811 }
812
813 /* Reuse the page if possible. For notification packets and
814 * SKBs that fail to Rx correctly, add them back into the
815 * rx_free list for reuse later. */
816 spin_lock_irqsave(&rxq->lock, flags);
817 if (rxb->page != NULL) {
818 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
819 0, PAGE_SIZE << priv->hw_params.rx_page_order,
820 PCI_DMA_FROMDEVICE);
821 list_add_tail(&rxb->list, &rxq->rx_free);
822 rxq->free_count++;
823 } else
824 list_add_tail(&rxb->list, &rxq->rx_used);
825
826 spin_unlock_irqrestore(&rxq->lock, flags);
827
828 i = (i + 1) & RX_QUEUE_MASK;
829 /* If there are a lot of unused frames,
830 * restock the Rx queue so ucode wont assert. */
831 if (fill_rx) {
832 count++;
833 if (count >= 8) {
834 rxq->read = i;
835 iwlagn_rx_replenish_now(priv);
836 count = 0;
837 }
838 }
839 }
840
841 /* Backtrack one entry */
842 rxq->read = i;
843 if (fill_rx)
844 iwlagn_rx_replenish_now(priv);
845 else
846 iwlagn_rx_queue_restock(priv);
847 }
848
849 /* tasklet for iwlagn interrupt */
850 static void iwl_irq_tasklet(struct iwl_priv *priv)
851 {
852 u32 inta = 0;
853 u32 handled = 0;
854 unsigned long flags;
855 u32 i;
856 #ifdef CONFIG_IWLWIFI_DEBUG
857 u32 inta_mask;
858 #endif
859
860 spin_lock_irqsave(&priv->lock, flags);
861
862 /* Ack/clear/reset pending uCode interrupts.
863 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
864 */
865 /* There is a hardware bug in the interrupt mask function that some
866 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
867 * they are disabled in the CSR_INT_MASK register. Furthermore the
868 * ICT interrupt handling mechanism has another bug that might cause
869 * these unmasked interrupts fail to be detected. We workaround the
870 * hardware bugs here by ACKing all the possible interrupts so that
871 * interrupt coalescing can still be achieved.
872 */
873 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
874
875 inta = priv->_agn.inta;
876
877 #ifdef CONFIG_IWLWIFI_DEBUG
878 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
879 /* just for debug */
880 inta_mask = iwl_read32(priv, CSR_INT_MASK);
881 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
882 inta, inta_mask);
883 }
884 #endif
885
886 spin_unlock_irqrestore(&priv->lock, flags);
887
888 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
889 priv->_agn.inta = 0;
890
891 /* Now service all interrupt bits discovered above. */
892 if (inta & CSR_INT_BIT_HW_ERR) {
893 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
894
895 /* Tell the device to stop sending interrupts */
896 iwl_disable_interrupts(priv);
897
898 priv->isr_stats.hw++;
899 iwl_irq_handle_error(priv);
900
901 handled |= CSR_INT_BIT_HW_ERR;
902
903 return;
904 }
905
906 #ifdef CONFIG_IWLWIFI_DEBUG
907 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
908 /* NIC fires this, but we don't use it, redundant with WAKEUP */
909 if (inta & CSR_INT_BIT_SCD) {
910 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
911 "the frame/frames.\n");
912 priv->isr_stats.sch++;
913 }
914
915 /* Alive notification via Rx interrupt will do the real work */
916 if (inta & CSR_INT_BIT_ALIVE) {
917 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
918 priv->isr_stats.alive++;
919 }
920 }
921 #endif
922 /* Safely ignore these bits for debug checks below */
923 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
924
925 /* HW RF KILL switch toggled */
926 if (inta & CSR_INT_BIT_RF_KILL) {
927 int hw_rf_kill = 0;
928 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
929 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
930 hw_rf_kill = 1;
931
932 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
933 hw_rf_kill ? "disable radio" : "enable radio");
934
935 priv->isr_stats.rfkill++;
936
937 /* driver only loads ucode once setting the interface up.
938 * the driver allows loading the ucode even if the radio
939 * is killed. Hence update the killswitch state here. The
940 * rfkill handler will care about restarting if needed.
941 */
942 if (!test_bit(STATUS_ALIVE, &priv->status)) {
943 if (hw_rf_kill)
944 set_bit(STATUS_RF_KILL_HW, &priv->status);
945 else
946 clear_bit(STATUS_RF_KILL_HW, &priv->status);
947 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
948 }
949
950 handled |= CSR_INT_BIT_RF_KILL;
951 }
952
953 /* Chip got too hot and stopped itself */
954 if (inta & CSR_INT_BIT_CT_KILL) {
955 IWL_ERR(priv, "Microcode CT kill error detected.\n");
956 priv->isr_stats.ctkill++;
957 handled |= CSR_INT_BIT_CT_KILL;
958 }
959
960 /* Error detected by uCode */
961 if (inta & CSR_INT_BIT_SW_ERR) {
962 IWL_ERR(priv, "Microcode SW error detected. "
963 " Restarting 0x%X.\n", inta);
964 priv->isr_stats.sw++;
965 iwl_irq_handle_error(priv);
966 handled |= CSR_INT_BIT_SW_ERR;
967 }
968
969 /* uCode wakes up after power-down sleep */
970 if (inta & CSR_INT_BIT_WAKEUP) {
971 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
972 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
973 for (i = 0; i < priv->hw_params.max_txq_num; i++)
974 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
975
976 priv->isr_stats.wakeup++;
977
978 handled |= CSR_INT_BIT_WAKEUP;
979 }
980
981 /* All uCode command responses, including Tx command responses,
982 * Rx "responses" (frame-received notification), and other
983 * notifications from uCode come through here*/
984 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
985 CSR_INT_BIT_RX_PERIODIC)) {
986 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
987 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
988 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
989 iwl_write32(priv, CSR_FH_INT_STATUS,
990 CSR_FH_INT_RX_MASK);
991 }
992 if (inta & CSR_INT_BIT_RX_PERIODIC) {
993 handled |= CSR_INT_BIT_RX_PERIODIC;
994 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
995 }
996 /* Sending RX interrupt require many steps to be done in the
997 * the device:
998 * 1- write interrupt to current index in ICT table.
999 * 2- dma RX frame.
1000 * 3- update RX shared data to indicate last write index.
1001 * 4- send interrupt.
1002 * This could lead to RX race, driver could receive RX interrupt
1003 * but the shared data changes does not reflect this;
1004 * periodic interrupt will detect any dangling Rx activity.
1005 */
1006
1007 /* Disable periodic interrupt; we use it as just a one-shot. */
1008 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1009 CSR_INT_PERIODIC_DIS);
1010 iwl_rx_handle(priv);
1011
1012 /*
1013 * Enable periodic interrupt in 8 msec only if we received
1014 * real RX interrupt (instead of just periodic int), to catch
1015 * any dangling Rx interrupt. If it was just the periodic
1016 * interrupt, there was no dangling Rx activity, and no need
1017 * to extend the periodic interrupt; one-shot is enough.
1018 */
1019 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1020 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1021 CSR_INT_PERIODIC_ENA);
1022
1023 priv->isr_stats.rx++;
1024 }
1025
1026 /* This "Tx" DMA channel is used only for loading uCode */
1027 if (inta & CSR_INT_BIT_FH_TX) {
1028 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1029 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1030 priv->isr_stats.tx++;
1031 handled |= CSR_INT_BIT_FH_TX;
1032 /* Wake up uCode load routine, now that load is complete */
1033 priv->ucode_write_complete = 1;
1034 wake_up_interruptible(&priv->wait_command_queue);
1035 }
1036
1037 if (inta & ~handled) {
1038 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1039 priv->isr_stats.unhandled++;
1040 }
1041
1042 if (inta & ~(priv->inta_mask)) {
1043 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1044 inta & ~priv->inta_mask);
1045 }
1046
1047 /* Re-enable all interrupts */
1048 /* only Re-enable if disabled by irq */
1049 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1050 iwl_enable_interrupts(priv);
1051 /* Re-enable RF_KILL if it occurred */
1052 else if (handled & CSR_INT_BIT_RF_KILL)
1053 iwl_enable_rfkill_int(priv);
1054 }
1055
1056 /*****************************************************************************
1057 *
1058 * sysfs attributes
1059 *
1060 *****************************************************************************/
1061
1062 #ifdef CONFIG_IWLWIFI_DEBUG
1063
1064 /*
1065 * The following adds a new attribute to the sysfs representation
1066 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1067 * used for controlling the debug level.
1068 *
1069 * See the level definitions in iwl for details.
1070 *
1071 * The debug_level being managed using sysfs below is a per device debug
1072 * level that is used instead of the global debug level if it (the per
1073 * device debug level) is set.
1074 */
1075 static ssize_t show_debug_level(struct device *d,
1076 struct device_attribute *attr, char *buf)
1077 {
1078 struct iwl_priv *priv = dev_get_drvdata(d);
1079 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1080 }
1081 static ssize_t store_debug_level(struct device *d,
1082 struct device_attribute *attr,
1083 const char *buf, size_t count)
1084 {
1085 struct iwl_priv *priv = dev_get_drvdata(d);
1086 unsigned long val;
1087 int ret;
1088
1089 ret = strict_strtoul(buf, 0, &val);
1090 if (ret)
1091 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1092 else {
1093 priv->debug_level = val;
1094 if (iwl_alloc_traffic_mem(priv))
1095 IWL_ERR(priv,
1096 "Not enough memory to generate traffic log\n");
1097 }
1098 return strnlen(buf, count);
1099 }
1100
1101 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1102 show_debug_level, store_debug_level);
1103
1104
1105 #endif /* CONFIG_IWLWIFI_DEBUG */
1106
1107
1108 static ssize_t show_temperature(struct device *d,
1109 struct device_attribute *attr, char *buf)
1110 {
1111 struct iwl_priv *priv = dev_get_drvdata(d);
1112
1113 if (!iwl_is_alive(priv))
1114 return -EAGAIN;
1115
1116 return sprintf(buf, "%d\n", priv->temperature);
1117 }
1118
1119 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1120
1121 static ssize_t show_tx_power(struct device *d,
1122 struct device_attribute *attr, char *buf)
1123 {
1124 struct iwl_priv *priv = dev_get_drvdata(d);
1125
1126 if (!iwl_is_ready_rf(priv))
1127 return sprintf(buf, "off\n");
1128 else
1129 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1130 }
1131
1132 static ssize_t store_tx_power(struct device *d,
1133 struct device_attribute *attr,
1134 const char *buf, size_t count)
1135 {
1136 struct iwl_priv *priv = dev_get_drvdata(d);
1137 unsigned long val;
1138 int ret;
1139
1140 ret = strict_strtoul(buf, 10, &val);
1141 if (ret)
1142 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1143 else {
1144 ret = iwl_set_tx_power(priv, val, false);
1145 if (ret)
1146 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1147 ret);
1148 else
1149 ret = count;
1150 }
1151 return ret;
1152 }
1153
1154 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1155
1156 static struct attribute *iwl_sysfs_entries[] = {
1157 &dev_attr_temperature.attr,
1158 &dev_attr_tx_power.attr,
1159 #ifdef CONFIG_IWLWIFI_DEBUG
1160 &dev_attr_debug_level.attr,
1161 #endif
1162 NULL
1163 };
1164
1165 static struct attribute_group iwl_attribute_group = {
1166 .name = NULL, /* put in device directory */
1167 .attrs = iwl_sysfs_entries,
1168 };
1169
1170 /******************************************************************************
1171 *
1172 * uCode download functions
1173 *
1174 ******************************************************************************/
1175
1176 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1177 {
1178 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1179 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1180 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1181 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1182 }
1183
1184 static void iwl_nic_start(struct iwl_priv *priv)
1185 {
1186 /* Remove all resets to allow NIC to operate */
1187 iwl_write32(priv, CSR_RESET, 0);
1188 }
1189
1190 struct iwlagn_ucode_capabilities {
1191 u32 max_probe_length;
1192 u32 standard_phy_calibration_size;
1193 u32 flags;
1194 };
1195
1196 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1197 static int iwl_mac_setup_register(struct iwl_priv *priv,
1198 struct iwlagn_ucode_capabilities *capa);
1199
1200 #define UCODE_EXPERIMENTAL_INDEX 100
1201 #define UCODE_EXPERIMENTAL_TAG "exp"
1202
1203 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1204 {
1205 const char *name_pre = priv->cfg->fw_name_pre;
1206 char tag[8];
1207
1208 if (first) {
1209 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1210 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1211 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1212 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1213 #endif
1214 priv->fw_index = priv->cfg->ucode_api_max;
1215 sprintf(tag, "%d", priv->fw_index);
1216 } else {
1217 priv->fw_index--;
1218 sprintf(tag, "%d", priv->fw_index);
1219 }
1220
1221 if (priv->fw_index < priv->cfg->ucode_api_min) {
1222 IWL_ERR(priv, "no suitable firmware found!\n");
1223 return -ENOENT;
1224 }
1225
1226 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1227
1228 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1229 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1230 ? "EXPERIMENTAL " : "",
1231 priv->firmware_name);
1232
1233 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1234 &priv->pci_dev->dev, GFP_KERNEL, priv,
1235 iwl_ucode_callback);
1236 }
1237
1238 struct iwlagn_firmware_pieces {
1239 const void *inst, *data, *init, *init_data;
1240 size_t inst_size, data_size, init_size, init_data_size;
1241
1242 u32 build;
1243
1244 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1245 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1246 };
1247
1248 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1249 const struct firmware *ucode_raw,
1250 struct iwlagn_firmware_pieces *pieces)
1251 {
1252 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1253 u32 api_ver, hdr_size;
1254 const u8 *src;
1255
1256 priv->ucode_ver = le32_to_cpu(ucode->ver);
1257 api_ver = IWL_UCODE_API(priv->ucode_ver);
1258
1259 switch (api_ver) {
1260 default:
1261 hdr_size = 28;
1262 if (ucode_raw->size < hdr_size) {
1263 IWL_ERR(priv, "File size too small!\n");
1264 return -EINVAL;
1265 }
1266 pieces->build = le32_to_cpu(ucode->u.v2.build);
1267 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1268 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1269 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1270 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1271 src = ucode->u.v2.data;
1272 break;
1273 case 0:
1274 case 1:
1275 case 2:
1276 hdr_size = 24;
1277 if (ucode_raw->size < hdr_size) {
1278 IWL_ERR(priv, "File size too small!\n");
1279 return -EINVAL;
1280 }
1281 pieces->build = 0;
1282 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1283 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1284 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1285 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1286 src = ucode->u.v1.data;
1287 break;
1288 }
1289
1290 /* Verify size of file vs. image size info in file's header */
1291 if (ucode_raw->size != hdr_size + pieces->inst_size +
1292 pieces->data_size + pieces->init_size +
1293 pieces->init_data_size) {
1294
1295 IWL_ERR(priv,
1296 "uCode file size %d does not match expected size\n",
1297 (int)ucode_raw->size);
1298 return -EINVAL;
1299 }
1300
1301 pieces->inst = src;
1302 src += pieces->inst_size;
1303 pieces->data = src;
1304 src += pieces->data_size;
1305 pieces->init = src;
1306 src += pieces->init_size;
1307 pieces->init_data = src;
1308 src += pieces->init_data_size;
1309
1310 return 0;
1311 }
1312
1313 static int iwlagn_wanted_ucode_alternative = 1;
1314
1315 static int iwlagn_load_firmware(struct iwl_priv *priv,
1316 const struct firmware *ucode_raw,
1317 struct iwlagn_firmware_pieces *pieces,
1318 struct iwlagn_ucode_capabilities *capa)
1319 {
1320 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1321 struct iwl_ucode_tlv *tlv;
1322 size_t len = ucode_raw->size;
1323 const u8 *data;
1324 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1325 u64 alternatives;
1326 u32 tlv_len;
1327 enum iwl_ucode_tlv_type tlv_type;
1328 const u8 *tlv_data;
1329
1330 if (len < sizeof(*ucode)) {
1331 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1332 return -EINVAL;
1333 }
1334
1335 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1336 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1337 le32_to_cpu(ucode->magic));
1338 return -EINVAL;
1339 }
1340
1341 /*
1342 * Check which alternatives are present, and "downgrade"
1343 * when the chosen alternative is not present, warning
1344 * the user when that happens. Some files may not have
1345 * any alternatives, so don't warn in that case.
1346 */
1347 alternatives = le64_to_cpu(ucode->alternatives);
1348 tmp = wanted_alternative;
1349 if (wanted_alternative > 63)
1350 wanted_alternative = 63;
1351 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1352 wanted_alternative--;
1353 if (wanted_alternative && wanted_alternative != tmp)
1354 IWL_WARN(priv,
1355 "uCode alternative %d not available, choosing %d\n",
1356 tmp, wanted_alternative);
1357
1358 priv->ucode_ver = le32_to_cpu(ucode->ver);
1359 pieces->build = le32_to_cpu(ucode->build);
1360 data = ucode->data;
1361
1362 len -= sizeof(*ucode);
1363
1364 while (len >= sizeof(*tlv)) {
1365 u16 tlv_alt;
1366
1367 len -= sizeof(*tlv);
1368 tlv = (void *)data;
1369
1370 tlv_len = le32_to_cpu(tlv->length);
1371 tlv_type = le16_to_cpu(tlv->type);
1372 tlv_alt = le16_to_cpu(tlv->alternative);
1373 tlv_data = tlv->data;
1374
1375 if (len < tlv_len) {
1376 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1377 len, tlv_len);
1378 return -EINVAL;
1379 }
1380 len -= ALIGN(tlv_len, 4);
1381 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1382
1383 /*
1384 * Alternative 0 is always valid.
1385 *
1386 * Skip alternative TLVs that are not selected.
1387 */
1388 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1389 continue;
1390
1391 switch (tlv_type) {
1392 case IWL_UCODE_TLV_INST:
1393 pieces->inst = tlv_data;
1394 pieces->inst_size = tlv_len;
1395 break;
1396 case IWL_UCODE_TLV_DATA:
1397 pieces->data = tlv_data;
1398 pieces->data_size = tlv_len;
1399 break;
1400 case IWL_UCODE_TLV_INIT:
1401 pieces->init = tlv_data;
1402 pieces->init_size = tlv_len;
1403 break;
1404 case IWL_UCODE_TLV_INIT_DATA:
1405 pieces->init_data = tlv_data;
1406 pieces->init_data_size = tlv_len;
1407 break;
1408 case IWL_UCODE_TLV_BOOT:
1409 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1410 break;
1411 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1412 if (tlv_len != sizeof(u32))
1413 goto invalid_tlv_len;
1414 capa->max_probe_length =
1415 le32_to_cpup((__le32 *)tlv_data);
1416 break;
1417 case IWL_UCODE_TLV_PAN:
1418 if (tlv_len)
1419 goto invalid_tlv_len;
1420 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1421 break;
1422 case IWL_UCODE_TLV_FLAGS:
1423 /* must be at least one u32 */
1424 if (tlv_len < sizeof(u32))
1425 goto invalid_tlv_len;
1426 /* and a proper number of u32s */
1427 if (tlv_len % sizeof(u32))
1428 goto invalid_tlv_len;
1429 /*
1430 * This driver only reads the first u32 as
1431 * right now no more features are defined,
1432 * if that changes then either the driver
1433 * will not work with the new firmware, or
1434 * it'll not take advantage of new features.
1435 */
1436 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1437 break;
1438 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1439 if (tlv_len != sizeof(u32))
1440 goto invalid_tlv_len;
1441 pieces->init_evtlog_ptr =
1442 le32_to_cpup((__le32 *)tlv_data);
1443 break;
1444 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1445 if (tlv_len != sizeof(u32))
1446 goto invalid_tlv_len;
1447 pieces->init_evtlog_size =
1448 le32_to_cpup((__le32 *)tlv_data);
1449 break;
1450 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1451 if (tlv_len != sizeof(u32))
1452 goto invalid_tlv_len;
1453 pieces->init_errlog_ptr =
1454 le32_to_cpup((__le32 *)tlv_data);
1455 break;
1456 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1457 if (tlv_len != sizeof(u32))
1458 goto invalid_tlv_len;
1459 pieces->inst_evtlog_ptr =
1460 le32_to_cpup((__le32 *)tlv_data);
1461 break;
1462 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1463 if (tlv_len != sizeof(u32))
1464 goto invalid_tlv_len;
1465 pieces->inst_evtlog_size =
1466 le32_to_cpup((__le32 *)tlv_data);
1467 break;
1468 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1469 if (tlv_len != sizeof(u32))
1470 goto invalid_tlv_len;
1471 pieces->inst_errlog_ptr =
1472 le32_to_cpup((__le32 *)tlv_data);
1473 break;
1474 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1475 if (tlv_len)
1476 goto invalid_tlv_len;
1477 priv->enhance_sensitivity_table = true;
1478 break;
1479 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1480 if (tlv_len != sizeof(u32))
1481 goto invalid_tlv_len;
1482 capa->standard_phy_calibration_size =
1483 le32_to_cpup((__le32 *)tlv_data);
1484 break;
1485 default:
1486 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1487 break;
1488 }
1489 }
1490
1491 if (len) {
1492 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1493 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1494 return -EINVAL;
1495 }
1496
1497 return 0;
1498
1499 invalid_tlv_len:
1500 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1501 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1502
1503 return -EINVAL;
1504 }
1505
1506 /**
1507 * iwl_ucode_callback - callback when firmware was loaded
1508 *
1509 * If loaded successfully, copies the firmware into buffers
1510 * for the card to fetch (via DMA).
1511 */
1512 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1513 {
1514 struct iwl_priv *priv = context;
1515 struct iwl_ucode_header *ucode;
1516 int err;
1517 struct iwlagn_firmware_pieces pieces;
1518 const unsigned int api_max = priv->cfg->ucode_api_max;
1519 const unsigned int api_min = priv->cfg->ucode_api_min;
1520 u32 api_ver;
1521 char buildstr[25];
1522 u32 build;
1523 struct iwlagn_ucode_capabilities ucode_capa = {
1524 .max_probe_length = 200,
1525 .standard_phy_calibration_size =
1526 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1527 };
1528
1529 memset(&pieces, 0, sizeof(pieces));
1530
1531 if (!ucode_raw) {
1532 if (priv->fw_index <= priv->cfg->ucode_api_max)
1533 IWL_ERR(priv,
1534 "request for firmware file '%s' failed.\n",
1535 priv->firmware_name);
1536 goto try_again;
1537 }
1538
1539 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1540 priv->firmware_name, ucode_raw->size);
1541
1542 /* Make sure that we got at least the API version number */
1543 if (ucode_raw->size < 4) {
1544 IWL_ERR(priv, "File size way too small!\n");
1545 goto try_again;
1546 }
1547
1548 /* Data from ucode file: header followed by uCode images */
1549 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1550
1551 if (ucode->ver)
1552 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1553 else
1554 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1555 &ucode_capa);
1556
1557 if (err)
1558 goto try_again;
1559
1560 api_ver = IWL_UCODE_API(priv->ucode_ver);
1561 build = pieces.build;
1562
1563 /*
1564 * api_ver should match the api version forming part of the
1565 * firmware filename ... but we don't check for that and only rely
1566 * on the API version read from firmware header from here on forward
1567 */
1568 /* no api version check required for experimental uCode */
1569 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1570 if (api_ver < api_min || api_ver > api_max) {
1571 IWL_ERR(priv,
1572 "Driver unable to support your firmware API. "
1573 "Driver supports v%u, firmware is v%u.\n",
1574 api_max, api_ver);
1575 goto try_again;
1576 }
1577
1578 if (api_ver != api_max)
1579 IWL_ERR(priv,
1580 "Firmware has old API version. Expected v%u, "
1581 "got v%u. New firmware can be obtained "
1582 "from http://www.intellinuxwireless.org.\n",
1583 api_max, api_ver);
1584 }
1585
1586 if (build)
1587 sprintf(buildstr, " build %u%s", build,
1588 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1589 ? " (EXP)" : "");
1590 else
1591 buildstr[0] = '\0';
1592
1593 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1594 IWL_UCODE_MAJOR(priv->ucode_ver),
1595 IWL_UCODE_MINOR(priv->ucode_ver),
1596 IWL_UCODE_API(priv->ucode_ver),
1597 IWL_UCODE_SERIAL(priv->ucode_ver),
1598 buildstr);
1599
1600 snprintf(priv->hw->wiphy->fw_version,
1601 sizeof(priv->hw->wiphy->fw_version),
1602 "%u.%u.%u.%u%s",
1603 IWL_UCODE_MAJOR(priv->ucode_ver),
1604 IWL_UCODE_MINOR(priv->ucode_ver),
1605 IWL_UCODE_API(priv->ucode_ver),
1606 IWL_UCODE_SERIAL(priv->ucode_ver),
1607 buildstr);
1608
1609 /*
1610 * For any of the failures below (before allocating pci memory)
1611 * we will try to load a version with a smaller API -- maybe the
1612 * user just got a corrupted version of the latest API.
1613 */
1614
1615 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1616 priv->ucode_ver);
1617 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1618 pieces.inst_size);
1619 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1620 pieces.data_size);
1621 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1622 pieces.init_size);
1623 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1624 pieces.init_data_size);
1625
1626 /* Verify that uCode images will fit in card's SRAM */
1627 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1628 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1629 pieces.inst_size);
1630 goto try_again;
1631 }
1632
1633 if (pieces.data_size > priv->hw_params.max_data_size) {
1634 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1635 pieces.data_size);
1636 goto try_again;
1637 }
1638
1639 if (pieces.init_size > priv->hw_params.max_inst_size) {
1640 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1641 pieces.init_size);
1642 goto try_again;
1643 }
1644
1645 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1646 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1647 pieces.init_data_size);
1648 goto try_again;
1649 }
1650
1651 /* Allocate ucode buffers for card's bus-master loading ... */
1652
1653 /* Runtime instructions and 2 copies of data:
1654 * 1) unmodified from disk
1655 * 2) backup cache for save/restore during power-downs */
1656 priv->ucode_code.len = pieces.inst_size;
1657 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1658
1659 priv->ucode_data.len = pieces.data_size;
1660 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1661
1662 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1663 goto err_pci_alloc;
1664
1665 /* Initialization instructions and data */
1666 if (pieces.init_size && pieces.init_data_size) {
1667 priv->ucode_init.len = pieces.init_size;
1668 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1669
1670 priv->ucode_init_data.len = pieces.init_data_size;
1671 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1672
1673 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1674 goto err_pci_alloc;
1675 }
1676
1677 /* Now that we can no longer fail, copy information */
1678
1679 /*
1680 * The (size - 16) / 12 formula is based on the information recorded
1681 * for each event, which is of mode 1 (including timestamp) for all
1682 * new microcodes that include this information.
1683 */
1684 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1685 if (pieces.init_evtlog_size)
1686 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1687 else
1688 priv->_agn.init_evtlog_size =
1689 priv->cfg->base_params->max_event_log_size;
1690 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1691 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1692 if (pieces.inst_evtlog_size)
1693 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1694 else
1695 priv->_agn.inst_evtlog_size =
1696 priv->cfg->base_params->max_event_log_size;
1697 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1698
1699 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1700 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1701 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1702 } else
1703 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1704
1705 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1706 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1707 else
1708 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1709
1710 /* Copy images into buffers for card's bus-master reads ... */
1711
1712 /* Runtime instructions (first block of data in file) */
1713 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1714 pieces.inst_size);
1715 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1716
1717 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1718 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1719
1720 /*
1721 * Runtime data
1722 * NOTE: Copy into backup buffer will be done in iwl_up()
1723 */
1724 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1725 pieces.data_size);
1726 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1727
1728 /* Initialization instructions */
1729 if (pieces.init_size) {
1730 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1731 pieces.init_size);
1732 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1733 }
1734
1735 /* Initialization data */
1736 if (pieces.init_data_size) {
1737 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1738 pieces.init_data_size);
1739 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1740 pieces.init_data_size);
1741 }
1742
1743 /*
1744 * figure out the offset of chain noise reset and gain commands
1745 * base on the size of standard phy calibration commands table size
1746 */
1747 if (ucode_capa.standard_phy_calibration_size >
1748 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1749 ucode_capa.standard_phy_calibration_size =
1750 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1751
1752 priv->_agn.phy_calib_chain_noise_reset_cmd =
1753 ucode_capa.standard_phy_calibration_size;
1754 priv->_agn.phy_calib_chain_noise_gain_cmd =
1755 ucode_capa.standard_phy_calibration_size + 1;
1756
1757 /**************************************************
1758 * This is still part of probe() in a sense...
1759 *
1760 * 9. Setup and register with mac80211 and debugfs
1761 **************************************************/
1762 err = iwl_mac_setup_register(priv, &ucode_capa);
1763 if (err)
1764 goto out_unbind;
1765
1766 err = iwl_dbgfs_register(priv, DRV_NAME);
1767 if (err)
1768 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1769
1770 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1771 &iwl_attribute_group);
1772 if (err) {
1773 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1774 goto out_unbind;
1775 }
1776
1777 /* We have our copies now, allow OS release its copies */
1778 release_firmware(ucode_raw);
1779 complete(&priv->_agn.firmware_loading_complete);
1780 return;
1781
1782 try_again:
1783 /* try next, if any */
1784 if (iwl_request_firmware(priv, false))
1785 goto out_unbind;
1786 release_firmware(ucode_raw);
1787 return;
1788
1789 err_pci_alloc:
1790 IWL_ERR(priv, "failed to allocate pci memory\n");
1791 iwl_dealloc_ucode_pci(priv);
1792 out_unbind:
1793 complete(&priv->_agn.firmware_loading_complete);
1794 device_release_driver(&priv->pci_dev->dev);
1795 release_firmware(ucode_raw);
1796 }
1797
1798 static const char *desc_lookup_text[] = {
1799 "OK",
1800 "FAIL",
1801 "BAD_PARAM",
1802 "BAD_CHECKSUM",
1803 "NMI_INTERRUPT_WDG",
1804 "SYSASSERT",
1805 "FATAL_ERROR",
1806 "BAD_COMMAND",
1807 "HW_ERROR_TUNE_LOCK",
1808 "HW_ERROR_TEMPERATURE",
1809 "ILLEGAL_CHAN_FREQ",
1810 "VCC_NOT_STABLE",
1811 "FH_ERROR",
1812 "NMI_INTERRUPT_HOST",
1813 "NMI_INTERRUPT_ACTION_PT",
1814 "NMI_INTERRUPT_UNKNOWN",
1815 "UCODE_VERSION_MISMATCH",
1816 "HW_ERROR_ABS_LOCK",
1817 "HW_ERROR_CAL_LOCK_FAIL",
1818 "NMI_INTERRUPT_INST_ACTION_PT",
1819 "NMI_INTERRUPT_DATA_ACTION_PT",
1820 "NMI_TRM_HW_ER",
1821 "NMI_INTERRUPT_TRM",
1822 "NMI_INTERRUPT_BREAK_POINT"
1823 "DEBUG_0",
1824 "DEBUG_1",
1825 "DEBUG_2",
1826 "DEBUG_3",
1827 };
1828
1829 static struct { char *name; u8 num; } advanced_lookup[] = {
1830 { "NMI_INTERRUPT_WDG", 0x34 },
1831 { "SYSASSERT", 0x35 },
1832 { "UCODE_VERSION_MISMATCH", 0x37 },
1833 { "BAD_COMMAND", 0x38 },
1834 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1835 { "FATAL_ERROR", 0x3D },
1836 { "NMI_TRM_HW_ERR", 0x46 },
1837 { "NMI_INTERRUPT_TRM", 0x4C },
1838 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1839 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1840 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1841 { "NMI_INTERRUPT_HOST", 0x66 },
1842 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1843 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1844 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1845 { "ADVANCED_SYSASSERT", 0 },
1846 };
1847
1848 static const char *desc_lookup(u32 num)
1849 {
1850 int i;
1851 int max = ARRAY_SIZE(desc_lookup_text);
1852
1853 if (num < max)
1854 return desc_lookup_text[num];
1855
1856 max = ARRAY_SIZE(advanced_lookup) - 1;
1857 for (i = 0; i < max; i++) {
1858 if (advanced_lookup[i].num == num)
1859 break;;
1860 }
1861 return advanced_lookup[i].name;
1862 }
1863
1864 #define ERROR_START_OFFSET (1 * sizeof(u32))
1865 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1866
1867 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1868 {
1869 u32 data2, line;
1870 u32 desc, time, count, base, data1;
1871 u32 blink1, blink2, ilink1, ilink2;
1872 u32 pc, hcmd;
1873 struct iwl_error_event_table table;
1874
1875 base = priv->device_pointers.error_event_table;
1876 if (priv->ucode_type == UCODE_INIT) {
1877 if (!base)
1878 base = priv->_agn.init_errlog_ptr;
1879 } else {
1880 if (!base)
1881 base = priv->_agn.inst_errlog_ptr;
1882 }
1883
1884 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1885 IWL_ERR(priv,
1886 "Not valid error log pointer 0x%08X for %s uCode\n",
1887 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1888 return;
1889 }
1890
1891 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1892
1893 count = table.valid;
1894
1895 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1896 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1897 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1898 priv->status, count);
1899 }
1900
1901 desc = table.error_id;
1902 priv->isr_stats.err_code = desc;
1903 pc = table.pc;
1904 blink1 = table.blink1;
1905 blink2 = table.blink2;
1906 ilink1 = table.ilink1;
1907 ilink2 = table.ilink2;
1908 data1 = table.data1;
1909 data2 = table.data2;
1910 line = table.line;
1911 time = table.tsf_low;
1912 hcmd = table.hcmd;
1913
1914 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1915 blink1, blink2, ilink1, ilink2);
1916
1917 IWL_ERR(priv, "Desc Time "
1918 "data1 data2 line\n");
1919 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1920 desc_lookup(desc), desc, time, data1, data2, line);
1921 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1922 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1923 pc, blink1, blink2, ilink1, ilink2, hcmd);
1924 }
1925
1926 #define EVENT_START_OFFSET (4 * sizeof(u32))
1927
1928 /**
1929 * iwl_print_event_log - Dump error event log to syslog
1930 *
1931 */
1932 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1933 u32 num_events, u32 mode,
1934 int pos, char **buf, size_t bufsz)
1935 {
1936 u32 i;
1937 u32 base; /* SRAM byte address of event log header */
1938 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1939 u32 ptr; /* SRAM byte address of log data */
1940 u32 ev, time, data; /* event log data */
1941 unsigned long reg_flags;
1942
1943 if (num_events == 0)
1944 return pos;
1945
1946 base = priv->device_pointers.log_event_table;
1947 if (priv->ucode_type == UCODE_INIT) {
1948 if (!base)
1949 base = priv->_agn.init_evtlog_ptr;
1950 } else {
1951 if (!base)
1952 base = priv->_agn.inst_evtlog_ptr;
1953 }
1954
1955 if (mode == 0)
1956 event_size = 2 * sizeof(u32);
1957 else
1958 event_size = 3 * sizeof(u32);
1959
1960 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1961
1962 /* Make sure device is powered up for SRAM reads */
1963 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1964 iwl_grab_nic_access(priv);
1965
1966 /* Set starting address; reads will auto-increment */
1967 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1968 rmb();
1969
1970 /* "time" is actually "data" for mode 0 (no timestamp).
1971 * place event id # at far right for easier visual parsing. */
1972 for (i = 0; i < num_events; i++) {
1973 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1974 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1975 if (mode == 0) {
1976 /* data, ev */
1977 if (bufsz) {
1978 pos += scnprintf(*buf + pos, bufsz - pos,
1979 "EVT_LOG:0x%08x:%04u\n",
1980 time, ev);
1981 } else {
1982 trace_iwlwifi_dev_ucode_event(priv, 0,
1983 time, ev);
1984 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1985 time, ev);
1986 }
1987 } else {
1988 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1989 if (bufsz) {
1990 pos += scnprintf(*buf + pos, bufsz - pos,
1991 "EVT_LOGT:%010u:0x%08x:%04u\n",
1992 time, data, ev);
1993 } else {
1994 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1995 time, data, ev);
1996 trace_iwlwifi_dev_ucode_event(priv, time,
1997 data, ev);
1998 }
1999 }
2000 }
2001
2002 /* Allow device to power down */
2003 iwl_release_nic_access(priv);
2004 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2005 return pos;
2006 }
2007
2008 /**
2009 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2010 */
2011 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2012 u32 num_wraps, u32 next_entry,
2013 u32 size, u32 mode,
2014 int pos, char **buf, size_t bufsz)
2015 {
2016 /*
2017 * display the newest DEFAULT_LOG_ENTRIES entries
2018 * i.e the entries just before the next ont that uCode would fill.
2019 */
2020 if (num_wraps) {
2021 if (next_entry < size) {
2022 pos = iwl_print_event_log(priv,
2023 capacity - (size - next_entry),
2024 size - next_entry, mode,
2025 pos, buf, bufsz);
2026 pos = iwl_print_event_log(priv, 0,
2027 next_entry, mode,
2028 pos, buf, bufsz);
2029 } else
2030 pos = iwl_print_event_log(priv, next_entry - size,
2031 size, mode, pos, buf, bufsz);
2032 } else {
2033 if (next_entry < size) {
2034 pos = iwl_print_event_log(priv, 0, next_entry,
2035 mode, pos, buf, bufsz);
2036 } else {
2037 pos = iwl_print_event_log(priv, next_entry - size,
2038 size, mode, pos, buf, bufsz);
2039 }
2040 }
2041 return pos;
2042 }
2043
2044 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2045
2046 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2047 char **buf, bool display)
2048 {
2049 u32 base; /* SRAM byte address of event log header */
2050 u32 capacity; /* event log capacity in # entries */
2051 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2052 u32 num_wraps; /* # times uCode wrapped to top of log */
2053 u32 next_entry; /* index of next entry to be written by uCode */
2054 u32 size; /* # entries that we'll print */
2055 u32 logsize;
2056 int pos = 0;
2057 size_t bufsz = 0;
2058
2059 base = priv->device_pointers.log_event_table;
2060 if (priv->ucode_type == UCODE_INIT) {
2061 logsize = priv->_agn.init_evtlog_size;
2062 if (!base)
2063 base = priv->_agn.init_evtlog_ptr;
2064 } else {
2065 logsize = priv->_agn.inst_evtlog_size;
2066 if (!base)
2067 base = priv->_agn.inst_evtlog_ptr;
2068 }
2069
2070 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2071 IWL_ERR(priv,
2072 "Invalid event log pointer 0x%08X for %s uCode\n",
2073 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2074 return -EINVAL;
2075 }
2076
2077 /* event log header */
2078 capacity = iwl_read_targ_mem(priv, base);
2079 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2080 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2081 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2082
2083 if (capacity > logsize) {
2084 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2085 capacity, logsize);
2086 capacity = logsize;
2087 }
2088
2089 if (next_entry > logsize) {
2090 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2091 next_entry, logsize);
2092 next_entry = logsize;
2093 }
2094
2095 size = num_wraps ? capacity : next_entry;
2096
2097 /* bail out if nothing in log */
2098 if (size == 0) {
2099 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2100 return pos;
2101 }
2102
2103 /* enable/disable bt channel inhibition */
2104 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2105
2106 #ifdef CONFIG_IWLWIFI_DEBUG
2107 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2108 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2109 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2110 #else
2111 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2112 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2113 #endif
2114 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2115 size);
2116
2117 #ifdef CONFIG_IWLWIFI_DEBUG
2118 if (display) {
2119 if (full_log)
2120 bufsz = capacity * 48;
2121 else
2122 bufsz = size * 48;
2123 *buf = kmalloc(bufsz, GFP_KERNEL);
2124 if (!*buf)
2125 return -ENOMEM;
2126 }
2127 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2128 /*
2129 * if uCode has wrapped back to top of log,
2130 * start at the oldest entry,
2131 * i.e the next one that uCode would fill.
2132 */
2133 if (num_wraps)
2134 pos = iwl_print_event_log(priv, next_entry,
2135 capacity - next_entry, mode,
2136 pos, buf, bufsz);
2137 /* (then/else) start at top of log */
2138 pos = iwl_print_event_log(priv, 0,
2139 next_entry, mode, pos, buf, bufsz);
2140 } else
2141 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2142 next_entry, size, mode,
2143 pos, buf, bufsz);
2144 #else
2145 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2146 next_entry, size, mode,
2147 pos, buf, bufsz);
2148 #endif
2149 return pos;
2150 }
2151
2152 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2153 {
2154 struct iwl_ct_kill_config cmd;
2155 struct iwl_ct_kill_throttling_config adv_cmd;
2156 unsigned long flags;
2157 int ret = 0;
2158
2159 spin_lock_irqsave(&priv->lock, flags);
2160 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2161 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2162 spin_unlock_irqrestore(&priv->lock, flags);
2163 priv->thermal_throttle.ct_kill_toggle = false;
2164
2165 if (priv->cfg->base_params->support_ct_kill_exit) {
2166 adv_cmd.critical_temperature_enter =
2167 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2168 adv_cmd.critical_temperature_exit =
2169 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2170
2171 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2172 sizeof(adv_cmd), &adv_cmd);
2173 if (ret)
2174 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2175 else
2176 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2177 "succeeded, "
2178 "critical temperature enter is %d,"
2179 "exit is %d\n",
2180 priv->hw_params.ct_kill_threshold,
2181 priv->hw_params.ct_kill_exit_threshold);
2182 } else {
2183 cmd.critical_temperature_R =
2184 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2185
2186 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2187 sizeof(cmd), &cmd);
2188 if (ret)
2189 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2190 else
2191 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2192 "succeeded, "
2193 "critical temperature is %d\n",
2194 priv->hw_params.ct_kill_threshold);
2195 }
2196 }
2197
2198 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2199 {
2200 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2201 struct iwl_host_cmd cmd = {
2202 .id = CALIBRATION_CFG_CMD,
2203 .len = sizeof(struct iwl_calib_cfg_cmd),
2204 .data = &calib_cfg_cmd,
2205 };
2206
2207 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2208 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2209 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2210
2211 return iwl_send_cmd(priv, &cmd);
2212 }
2213
2214
2215 /**
2216 * iwl_alive_start - called after REPLY_ALIVE notification received
2217 * from protocol/runtime uCode (initialization uCode's
2218 * Alive gets handled by iwl_init_alive_start()).
2219 */
2220 static void iwl_alive_start(struct iwl_priv *priv)
2221 {
2222 int ret = 0;
2223 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2224
2225 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2226
2227 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2228 * This is a paranoid check, because we would not have gotten the
2229 * "runtime" alive if code weren't properly loaded. */
2230 if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2231 /* Runtime instruction load was bad;
2232 * take it all the way back down so we can try again */
2233 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2234 goto restart;
2235 }
2236
2237 ret = iwlagn_alive_notify(priv);
2238 if (ret) {
2239 IWL_WARN(priv,
2240 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2241 goto restart;
2242 }
2243
2244
2245 /* After the ALIVE response, we can send host commands to the uCode */
2246 set_bit(STATUS_ALIVE, &priv->status);
2247
2248 /* Enable watchdog to monitor the driver tx queues */
2249 iwl_setup_watchdog(priv);
2250
2251 if (iwl_is_rfkill(priv))
2252 return;
2253
2254 /* download priority table before any calibration request */
2255 if (priv->cfg->bt_params &&
2256 priv->cfg->bt_params->advanced_bt_coexist) {
2257 /* Configure Bluetooth device coexistence support */
2258 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2259 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2260 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2261 priv->cfg->ops->hcmd->send_bt_config(priv);
2262 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2263 iwlagn_send_prio_tbl(priv);
2264
2265 /* FIXME: w/a to force change uCode BT state machine */
2266 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2267 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2268 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2269 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2270 }
2271 if (priv->hw_params.calib_rt_cfg)
2272 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2273
2274 ieee80211_wake_queues(priv->hw);
2275
2276 priv->active_rate = IWL_RATES_MASK;
2277
2278 /* Configure Tx antenna selection based on H/W config */
2279 if (priv->cfg->ops->hcmd->set_tx_ant)
2280 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2281
2282 if (iwl_is_associated_ctx(ctx)) {
2283 struct iwl_rxon_cmd *active_rxon =
2284 (struct iwl_rxon_cmd *)&ctx->active;
2285 /* apply any changes in staging */
2286 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2287 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2288 } else {
2289 struct iwl_rxon_context *tmp;
2290 /* Initialize our rx_config data */
2291 for_each_context(priv, tmp)
2292 iwl_connection_init_rx_config(priv, tmp);
2293
2294 if (priv->cfg->ops->hcmd->set_rxon_chain)
2295 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2296 }
2297
2298 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2299 !priv->cfg->bt_params->advanced_bt_coexist)) {
2300 /*
2301 * default is 2-wire BT coexexistence support
2302 */
2303 priv->cfg->ops->hcmd->send_bt_config(priv);
2304 }
2305
2306 iwl_reset_run_time_calib(priv);
2307
2308 set_bit(STATUS_READY, &priv->status);
2309
2310 /* Configure the adapter for unassociated operation */
2311 iwlcore_commit_rxon(priv, ctx);
2312
2313 /* At this point, the NIC is initialized and operational */
2314 iwl_rf_kill_ct_config(priv);
2315
2316 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2317 wake_up_interruptible(&priv->wait_command_queue);
2318
2319 iwl_power_update_mode(priv, true);
2320 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2321
2322
2323 return;
2324
2325 restart:
2326 queue_work(priv->workqueue, &priv->restart);
2327 }
2328
2329 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2330
2331 static void __iwl_down(struct iwl_priv *priv)
2332 {
2333 int exit_pending;
2334
2335 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2336
2337 iwl_scan_cancel_timeout(priv, 200);
2338
2339 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2340
2341 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2342 * to prevent rearm timer */
2343 del_timer_sync(&priv->watchdog);
2344
2345 iwl_clear_ucode_stations(priv, NULL);
2346 iwl_dealloc_bcast_stations(priv);
2347 iwl_clear_driver_stations(priv);
2348
2349 /* reset BT coex data */
2350 priv->bt_status = 0;
2351 if (priv->cfg->bt_params)
2352 priv->bt_traffic_load =
2353 priv->cfg->bt_params->bt_init_traffic_load;
2354 else
2355 priv->bt_traffic_load = 0;
2356 priv->bt_full_concurrent = false;
2357 priv->bt_ci_compliance = 0;
2358
2359 /* Wipe out the EXIT_PENDING status bit if we are not actually
2360 * exiting the module */
2361 if (!exit_pending)
2362 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2363
2364 if (priv->mac80211_registered)
2365 ieee80211_stop_queues(priv->hw);
2366
2367 /* Clear out all status bits but a few that are stable across reset */
2368 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2369 STATUS_RF_KILL_HW |
2370 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2371 STATUS_GEO_CONFIGURED |
2372 test_bit(STATUS_FW_ERROR, &priv->status) <<
2373 STATUS_FW_ERROR |
2374 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2375 STATUS_EXIT_PENDING;
2376
2377 iwlagn_stop_device(priv);
2378
2379 dev_kfree_skb(priv->beacon_skb);
2380 priv->beacon_skb = NULL;
2381
2382 /* clear out any free frames */
2383 iwl_clear_free_frames(priv);
2384 }
2385
2386 static void iwl_down(struct iwl_priv *priv)
2387 {
2388 mutex_lock(&priv->mutex);
2389 __iwl_down(priv);
2390 mutex_unlock(&priv->mutex);
2391
2392 iwl_cancel_deferred_work(priv);
2393 }
2394
2395 #define HW_READY_TIMEOUT (50)
2396
2397 static int iwl_set_hw_ready(struct iwl_priv *priv)
2398 {
2399 int ret = 0;
2400
2401 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2402 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2403
2404 /* See if we got it */
2405 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2406 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2407 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2408 HW_READY_TIMEOUT);
2409 if (ret != -ETIMEDOUT)
2410 priv->hw_ready = true;
2411 else
2412 priv->hw_ready = false;
2413
2414 IWL_DEBUG_INFO(priv, "hardware %s\n",
2415 (priv->hw_ready == 1) ? "ready" : "not ready");
2416 return ret;
2417 }
2418
2419 int iwl_prepare_card_hw(struct iwl_priv *priv)
2420 {
2421 int ret = 0;
2422
2423 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2424
2425 ret = iwl_set_hw_ready(priv);
2426 if (priv->hw_ready)
2427 return ret;
2428
2429 /* If HW is not ready, prepare the conditions to check again */
2430 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2431 CSR_HW_IF_CONFIG_REG_PREPARE);
2432
2433 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2434 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2435 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2436
2437 /* HW should be ready by now, check again. */
2438 if (ret != -ETIMEDOUT)
2439 iwl_set_hw_ready(priv);
2440
2441 return ret;
2442 }
2443
2444 #define MAX_HW_RESTARTS 5
2445
2446 static int __iwl_up(struct iwl_priv *priv)
2447 {
2448 struct iwl_rxon_context *ctx;
2449 int i;
2450 int ret;
2451
2452 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2453 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2454 return -EIO;
2455 }
2456
2457 for_each_context(priv, ctx) {
2458 ret = iwlagn_alloc_bcast_station(priv, ctx);
2459 if (ret) {
2460 iwl_dealloc_bcast_stations(priv);
2461 return ret;
2462 }
2463 }
2464
2465 ret = iwlagn_start_device(priv);
2466 if (ret)
2467 return ret;
2468
2469 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2470
2471 /* load bootstrap state machine,
2472 * load bootstrap program into processor's memory,
2473 * prepare to load the "initialize" uCode */
2474 ret = iwlagn_load_ucode(priv);
2475
2476 if (ret) {
2477 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2478 ret);
2479 continue;
2480 }
2481
2482 /* start card; "initialize" will load runtime ucode */
2483 iwl_nic_start(priv);
2484
2485 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2486
2487 return 0;
2488 }
2489
2490 set_bit(STATUS_EXIT_PENDING, &priv->status);
2491 __iwl_down(priv);
2492 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2493
2494 /* tried to restart and config the device for as long as our
2495 * patience could withstand */
2496 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2497 return -EIO;
2498 }
2499
2500
2501 /*****************************************************************************
2502 *
2503 * Workqueue callbacks
2504 *
2505 *****************************************************************************/
2506
2507 static void iwl_bg_init_alive_start(struct work_struct *data)
2508 {
2509 struct iwl_priv *priv =
2510 container_of(data, struct iwl_priv, init_alive_start.work);
2511
2512 mutex_lock(&priv->mutex);
2513
2514 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2515 mutex_unlock(&priv->mutex);
2516 return;
2517 }
2518
2519 iwlagn_init_alive_start(priv);
2520 mutex_unlock(&priv->mutex);
2521 }
2522
2523 static void iwl_bg_alive_start(struct work_struct *data)
2524 {
2525 struct iwl_priv *priv =
2526 container_of(data, struct iwl_priv, alive_start.work);
2527
2528 mutex_lock(&priv->mutex);
2529 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2530 goto unlock;
2531
2532 /* enable dram interrupt */
2533 iwl_reset_ict(priv);
2534
2535 iwl_alive_start(priv);
2536 unlock:
2537 mutex_unlock(&priv->mutex);
2538 }
2539
2540 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2541 {
2542 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2543 run_time_calib_work);
2544
2545 mutex_lock(&priv->mutex);
2546
2547 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2548 test_bit(STATUS_SCANNING, &priv->status)) {
2549 mutex_unlock(&priv->mutex);
2550 return;
2551 }
2552
2553 if (priv->start_calib) {
2554 iwl_chain_noise_calibration(priv);
2555 iwl_sensitivity_calibration(priv);
2556 }
2557
2558 mutex_unlock(&priv->mutex);
2559 }
2560
2561 static void iwl_bg_restart(struct work_struct *data)
2562 {
2563 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2564
2565 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2566 return;
2567
2568 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2569 struct iwl_rxon_context *ctx;
2570 bool bt_full_concurrent;
2571 u8 bt_ci_compliance;
2572 u8 bt_load;
2573 u8 bt_status;
2574
2575 mutex_lock(&priv->mutex);
2576 for_each_context(priv, ctx)
2577 ctx->vif = NULL;
2578 priv->is_open = 0;
2579
2580 /*
2581 * __iwl_down() will clear the BT status variables,
2582 * which is correct, but when we restart we really
2583 * want to keep them so restore them afterwards.
2584 *
2585 * The restart process will later pick them up and
2586 * re-configure the hw when we reconfigure the BT
2587 * command.
2588 */
2589 bt_full_concurrent = priv->bt_full_concurrent;
2590 bt_ci_compliance = priv->bt_ci_compliance;
2591 bt_load = priv->bt_traffic_load;
2592 bt_status = priv->bt_status;
2593
2594 __iwl_down(priv);
2595
2596 priv->bt_full_concurrent = bt_full_concurrent;
2597 priv->bt_ci_compliance = bt_ci_compliance;
2598 priv->bt_traffic_load = bt_load;
2599 priv->bt_status = bt_status;
2600
2601 mutex_unlock(&priv->mutex);
2602 iwl_cancel_deferred_work(priv);
2603 ieee80211_restart_hw(priv->hw);
2604 } else {
2605 iwl_down(priv);
2606
2607 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2608 return;
2609
2610 mutex_lock(&priv->mutex);
2611 __iwl_up(priv);
2612 mutex_unlock(&priv->mutex);
2613 }
2614 }
2615
2616 static void iwl_bg_rx_replenish(struct work_struct *data)
2617 {
2618 struct iwl_priv *priv =
2619 container_of(data, struct iwl_priv, rx_replenish);
2620
2621 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2622 return;
2623
2624 mutex_lock(&priv->mutex);
2625 iwlagn_rx_replenish(priv);
2626 mutex_unlock(&priv->mutex);
2627 }
2628
2629 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2630 struct ieee80211_channel *chan,
2631 enum nl80211_channel_type channel_type,
2632 unsigned int wait)
2633 {
2634 struct iwl_priv *priv = hw->priv;
2635 int ret;
2636
2637 /* Not supported if we don't have PAN */
2638 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2639 ret = -EOPNOTSUPP;
2640 goto free;
2641 }
2642
2643 /* Not supported on pre-P2P firmware */
2644 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2645 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2646 ret = -EOPNOTSUPP;
2647 goto free;
2648 }
2649
2650 mutex_lock(&priv->mutex);
2651
2652 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2653 /*
2654 * If the PAN context is free, use the normal
2655 * way of doing remain-on-channel offload + TX.
2656 */
2657 ret = 1;
2658 goto out;
2659 }
2660
2661 /* TODO: queue up if scanning? */
2662 if (test_bit(STATUS_SCANNING, &priv->status) ||
2663 priv->_agn.offchan_tx_skb) {
2664 ret = -EBUSY;
2665 goto out;
2666 }
2667
2668 /*
2669 * max_scan_ie_len doesn't include the blank SSID or the header,
2670 * so need to add that again here.
2671 */
2672 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2673 ret = -ENOBUFS;
2674 goto out;
2675 }
2676
2677 priv->_agn.offchan_tx_skb = skb;
2678 priv->_agn.offchan_tx_timeout = wait;
2679 priv->_agn.offchan_tx_chan = chan;
2680
2681 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2682 IWL_SCAN_OFFCH_TX, chan->band);
2683 if (ret)
2684 priv->_agn.offchan_tx_skb = NULL;
2685 out:
2686 mutex_unlock(&priv->mutex);
2687 free:
2688 if (ret < 0)
2689 kfree_skb(skb);
2690
2691 return ret;
2692 }
2693
2694 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2695 {
2696 struct iwl_priv *priv = hw->priv;
2697 int ret;
2698
2699 mutex_lock(&priv->mutex);
2700
2701 if (!priv->_agn.offchan_tx_skb) {
2702 ret = -EINVAL;
2703 goto unlock;
2704 }
2705
2706 priv->_agn.offchan_tx_skb = NULL;
2707
2708 ret = iwl_scan_cancel_timeout(priv, 200);
2709 if (ret)
2710 ret = -EIO;
2711 unlock:
2712 mutex_unlock(&priv->mutex);
2713
2714 return ret;
2715 }
2716
2717 /*****************************************************************************
2718 *
2719 * mac80211 entry point functions
2720 *
2721 *****************************************************************************/
2722
2723 #define UCODE_READY_TIMEOUT (4 * HZ)
2724
2725 /*
2726 * Not a mac80211 entry point function, but it fits in with all the
2727 * other mac80211 functions grouped here.
2728 */
2729 static int iwl_mac_setup_register(struct iwl_priv *priv,
2730 struct iwlagn_ucode_capabilities *capa)
2731 {
2732 int ret;
2733 struct ieee80211_hw *hw = priv->hw;
2734 struct iwl_rxon_context *ctx;
2735
2736 hw->rate_control_algorithm = "iwl-agn-rs";
2737
2738 /* Tell mac80211 our characteristics */
2739 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2740 IEEE80211_HW_AMPDU_AGGREGATION |
2741 IEEE80211_HW_NEED_DTIM_PERIOD |
2742 IEEE80211_HW_SPECTRUM_MGMT |
2743 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2744
2745 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2746
2747 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2748 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2749
2750 if (priv->cfg->sku & IWL_SKU_N)
2751 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2752 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2753
2754 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2755 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2756
2757 hw->sta_data_size = sizeof(struct iwl_station_priv);
2758 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2759
2760 for_each_context(priv, ctx) {
2761 hw->wiphy->interface_modes |= ctx->interface_modes;
2762 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2763 }
2764
2765 hw->wiphy->max_remain_on_channel_duration = 1000;
2766
2767 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2768 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2769 WIPHY_FLAG_IBSS_RSN;
2770
2771 /*
2772 * For now, disable PS by default because it affects
2773 * RX performance significantly.
2774 */
2775 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2776
2777 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2778 /* we create the 802.11 header and a zero-length SSID element */
2779 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2780
2781 /* Default value; 4 EDCA QOS priorities */
2782 hw->queues = 4;
2783
2784 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2785
2786 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2787 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2788 &priv->bands[IEEE80211_BAND_2GHZ];
2789 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2790 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2791 &priv->bands[IEEE80211_BAND_5GHZ];
2792
2793 iwl_leds_init(priv);
2794
2795 ret = ieee80211_register_hw(priv->hw);
2796 if (ret) {
2797 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2798 return ret;
2799 }
2800 priv->mac80211_registered = 1;
2801
2802 return 0;
2803 }
2804
2805
2806 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2807 {
2808 struct iwl_priv *priv = hw->priv;
2809 int ret;
2810
2811 IWL_DEBUG_MAC80211(priv, "enter\n");
2812
2813 /* we should be verifying the device is ready to be opened */
2814 mutex_lock(&priv->mutex);
2815 ret = __iwl_up(priv);
2816 mutex_unlock(&priv->mutex);
2817
2818 if (ret)
2819 return ret;
2820
2821 if (iwl_is_rfkill(priv))
2822 goto out;
2823
2824 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2825
2826 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2827 * mac80211 will not be run successfully. */
2828 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2829 test_bit(STATUS_READY, &priv->status),
2830 UCODE_READY_TIMEOUT);
2831 if (!ret) {
2832 if (!test_bit(STATUS_READY, &priv->status)) {
2833 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2834 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2835 return -ETIMEDOUT;
2836 }
2837 }
2838
2839 iwlagn_led_enable(priv);
2840
2841 out:
2842 priv->is_open = 1;
2843 IWL_DEBUG_MAC80211(priv, "leave\n");
2844 return 0;
2845 }
2846
2847 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2848 {
2849 struct iwl_priv *priv = hw->priv;
2850
2851 IWL_DEBUG_MAC80211(priv, "enter\n");
2852
2853 if (!priv->is_open)
2854 return;
2855
2856 priv->is_open = 0;
2857
2858 iwl_down(priv);
2859
2860 flush_workqueue(priv->workqueue);
2861
2862 /* User space software may expect getting rfkill changes
2863 * even if interface is down */
2864 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2865 iwl_enable_rfkill_int(priv);
2866
2867 IWL_DEBUG_MAC80211(priv, "leave\n");
2868 }
2869
2870 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2871 {
2872 struct iwl_priv *priv = hw->priv;
2873
2874 IWL_DEBUG_MACDUMP(priv, "enter\n");
2875
2876 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2877 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2878
2879 if (iwlagn_tx_skb(priv, skb))
2880 dev_kfree_skb_any(skb);
2881
2882 IWL_DEBUG_MACDUMP(priv, "leave\n");
2883 }
2884
2885 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2886 struct ieee80211_vif *vif,
2887 struct ieee80211_key_conf *keyconf,
2888 struct ieee80211_sta *sta,
2889 u32 iv32, u16 *phase1key)
2890 {
2891 struct iwl_priv *priv = hw->priv;
2892 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2893
2894 IWL_DEBUG_MAC80211(priv, "enter\n");
2895
2896 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2897 iv32, phase1key);
2898
2899 IWL_DEBUG_MAC80211(priv, "leave\n");
2900 }
2901
2902 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2903 struct ieee80211_vif *vif,
2904 struct ieee80211_sta *sta,
2905 struct ieee80211_key_conf *key)
2906 {
2907 struct iwl_priv *priv = hw->priv;
2908 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2909 struct iwl_rxon_context *ctx = vif_priv->ctx;
2910 int ret;
2911 u8 sta_id;
2912 bool is_default_wep_key = false;
2913
2914 IWL_DEBUG_MAC80211(priv, "enter\n");
2915
2916 if (priv->cfg->mod_params->sw_crypto) {
2917 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2918 return -EOPNOTSUPP;
2919 }
2920
2921 /*
2922 * To support IBSS RSN, don't program group keys in IBSS, the
2923 * hardware will then not attempt to decrypt the frames.
2924 */
2925 if (vif->type == NL80211_IFTYPE_ADHOC &&
2926 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2927 return -EOPNOTSUPP;
2928
2929 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2930 if (sta_id == IWL_INVALID_STATION)
2931 return -EINVAL;
2932
2933 mutex_lock(&priv->mutex);
2934 iwl_scan_cancel_timeout(priv, 100);
2935
2936 /*
2937 * If we are getting WEP group key and we didn't receive any key mapping
2938 * so far, we are in legacy wep mode (group key only), otherwise we are
2939 * in 1X mode.
2940 * In legacy wep mode, we use another host command to the uCode.
2941 */
2942 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2943 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2944 !sta) {
2945 if (cmd == SET_KEY)
2946 is_default_wep_key = !ctx->key_mapping_keys;
2947 else
2948 is_default_wep_key =
2949 (key->hw_key_idx == HW_KEY_DEFAULT);
2950 }
2951
2952 switch (cmd) {
2953 case SET_KEY:
2954 if (is_default_wep_key)
2955 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2956 else
2957 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2958 key, sta_id);
2959
2960 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2961 break;
2962 case DISABLE_KEY:
2963 if (is_default_wep_key)
2964 ret = iwl_remove_default_wep_key(priv, ctx, key);
2965 else
2966 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
2967
2968 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2969 break;
2970 default:
2971 ret = -EINVAL;
2972 }
2973
2974 mutex_unlock(&priv->mutex);
2975 IWL_DEBUG_MAC80211(priv, "leave\n");
2976
2977 return ret;
2978 }
2979
2980 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2981 struct ieee80211_vif *vif,
2982 enum ieee80211_ampdu_mlme_action action,
2983 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2984 u8 buf_size)
2985 {
2986 struct iwl_priv *priv = hw->priv;
2987 int ret = -EINVAL;
2988 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
2989
2990 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2991 sta->addr, tid);
2992
2993 if (!(priv->cfg->sku & IWL_SKU_N))
2994 return -EACCES;
2995
2996 mutex_lock(&priv->mutex);
2997
2998 switch (action) {
2999 case IEEE80211_AMPDU_RX_START:
3000 IWL_DEBUG_HT(priv, "start Rx\n");
3001 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3002 break;
3003 case IEEE80211_AMPDU_RX_STOP:
3004 IWL_DEBUG_HT(priv, "stop Rx\n");
3005 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3006 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3007 ret = 0;
3008 break;
3009 case IEEE80211_AMPDU_TX_START:
3010 IWL_DEBUG_HT(priv, "start Tx\n");
3011 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3012 if (ret == 0) {
3013 priv->_agn.agg_tids_count++;
3014 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3015 priv->_agn.agg_tids_count);
3016 }
3017 break;
3018 case IEEE80211_AMPDU_TX_STOP:
3019 IWL_DEBUG_HT(priv, "stop Tx\n");
3020 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3021 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3022 priv->_agn.agg_tids_count--;
3023 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3024 priv->_agn.agg_tids_count);
3025 }
3026 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3027 ret = 0;
3028 if (priv->cfg->ht_params &&
3029 priv->cfg->ht_params->use_rts_for_aggregation) {
3030 struct iwl_station_priv *sta_priv =
3031 (void *) sta->drv_priv;
3032 /*
3033 * switch off RTS/CTS if it was previously enabled
3034 */
3035
3036 sta_priv->lq_sta.lq.general_params.flags &=
3037 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3038 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3039 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3040 }
3041 break;
3042 case IEEE80211_AMPDU_TX_OPERATIONAL:
3043 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3044
3045 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3046
3047 /*
3048 * If the limit is 0, then it wasn't initialised yet,
3049 * use the default. We can do that since we take the
3050 * minimum below, and we don't want to go above our
3051 * default due to hardware restrictions.
3052 */
3053 if (sta_priv->max_agg_bufsize == 0)
3054 sta_priv->max_agg_bufsize =
3055 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3056
3057 /*
3058 * Even though in theory the peer could have different
3059 * aggregation reorder buffer sizes for different sessions,
3060 * our ucode doesn't allow for that and has a global limit
3061 * for each station. Therefore, use the minimum of all the
3062 * aggregation sessions and our default value.
3063 */
3064 sta_priv->max_agg_bufsize =
3065 min(sta_priv->max_agg_bufsize, buf_size);
3066
3067 if (priv->cfg->ht_params &&
3068 priv->cfg->ht_params->use_rts_for_aggregation) {
3069 /*
3070 * switch to RTS/CTS if it is the prefer protection
3071 * method for HT traffic
3072 */
3073
3074 sta_priv->lq_sta.lq.general_params.flags |=
3075 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3076 }
3077
3078 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3079 sta_priv->max_agg_bufsize;
3080
3081 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3082 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3083 ret = 0;
3084 break;
3085 }
3086 mutex_unlock(&priv->mutex);
3087
3088 return ret;
3089 }
3090
3091 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3092 struct ieee80211_vif *vif,
3093 struct ieee80211_sta *sta)
3094 {
3095 struct iwl_priv *priv = hw->priv;
3096 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3097 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3098 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3099 int ret;
3100 u8 sta_id;
3101
3102 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3103 sta->addr);
3104 mutex_lock(&priv->mutex);
3105 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3106 sta->addr);
3107 sta_priv->common.sta_id = IWL_INVALID_STATION;
3108
3109 atomic_set(&sta_priv->pending_frames, 0);
3110 if (vif->type == NL80211_IFTYPE_AP)
3111 sta_priv->client = true;
3112
3113 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3114 is_ap, sta, &sta_id);
3115 if (ret) {
3116 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3117 sta->addr, ret);
3118 /* Should we return success if return code is EEXIST ? */
3119 mutex_unlock(&priv->mutex);
3120 return ret;
3121 }
3122
3123 sta_priv->common.sta_id = sta_id;
3124
3125 /* Initialize rate scaling */
3126 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3127 sta->addr);
3128 iwl_rs_rate_init(priv, sta, sta_id);
3129 mutex_unlock(&priv->mutex);
3130
3131 return 0;
3132 }
3133
3134 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3135 struct ieee80211_channel_switch *ch_switch)
3136 {
3137 struct iwl_priv *priv = hw->priv;
3138 const struct iwl_channel_info *ch_info;
3139 struct ieee80211_conf *conf = &hw->conf;
3140 struct ieee80211_channel *channel = ch_switch->channel;
3141 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3142 /*
3143 * MULTI-FIXME
3144 * When we add support for multiple interfaces, we need to
3145 * revisit this. The channel switch command in the device
3146 * only affects the BSS context, but what does that really
3147 * mean? And what if we get a CSA on the second interface?
3148 * This needs a lot of work.
3149 */
3150 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3151 u16 ch;
3152 unsigned long flags = 0;
3153
3154 IWL_DEBUG_MAC80211(priv, "enter\n");
3155
3156 mutex_lock(&priv->mutex);
3157
3158 if (iwl_is_rfkill(priv))
3159 goto out;
3160
3161 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3162 test_bit(STATUS_SCANNING, &priv->status))
3163 goto out;
3164
3165 if (!iwl_is_associated_ctx(ctx))
3166 goto out;
3167
3168 /* channel switch in progress */
3169 if (priv->switch_rxon.switch_in_progress == true)
3170 goto out;
3171
3172 if (priv->cfg->ops->lib->set_channel_switch) {
3173
3174 ch = channel->hw_value;
3175 if (le16_to_cpu(ctx->active.channel) != ch) {
3176 ch_info = iwl_get_channel_info(priv,
3177 channel->band,
3178 ch);
3179 if (!is_channel_valid(ch_info)) {
3180 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3181 goto out;
3182 }
3183 spin_lock_irqsave(&priv->lock, flags);
3184
3185 priv->current_ht_config.smps = conf->smps_mode;
3186
3187 /* Configure HT40 channels */
3188 ctx->ht.enabled = conf_is_ht(conf);
3189 if (ctx->ht.enabled) {
3190 if (conf_is_ht40_minus(conf)) {
3191 ctx->ht.extension_chan_offset =
3192 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3193 ctx->ht.is_40mhz = true;
3194 } else if (conf_is_ht40_plus(conf)) {
3195 ctx->ht.extension_chan_offset =
3196 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3197 ctx->ht.is_40mhz = true;
3198 } else {
3199 ctx->ht.extension_chan_offset =
3200 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3201 ctx->ht.is_40mhz = false;
3202 }
3203 } else
3204 ctx->ht.is_40mhz = false;
3205
3206 if ((le16_to_cpu(ctx->staging.channel) != ch))
3207 ctx->staging.flags = 0;
3208
3209 iwl_set_rxon_channel(priv, channel, ctx);
3210 iwl_set_rxon_ht(priv, ht_conf);
3211 iwl_set_flags_for_band(priv, ctx, channel->band,
3212 ctx->vif);
3213 spin_unlock_irqrestore(&priv->lock, flags);
3214
3215 iwl_set_rate(priv);
3216 /*
3217 * at this point, staging_rxon has the
3218 * configuration for channel switch
3219 */
3220 if (priv->cfg->ops->lib->set_channel_switch(priv,
3221 ch_switch))
3222 priv->switch_rxon.switch_in_progress = false;
3223 }
3224 }
3225 out:
3226 mutex_unlock(&priv->mutex);
3227 if (!priv->switch_rxon.switch_in_progress)
3228 ieee80211_chswitch_done(ctx->vif, false);
3229 IWL_DEBUG_MAC80211(priv, "leave\n");
3230 }
3231
3232 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3233 unsigned int changed_flags,
3234 unsigned int *total_flags,
3235 u64 multicast)
3236 {
3237 struct iwl_priv *priv = hw->priv;
3238 __le32 filter_or = 0, filter_nand = 0;
3239 struct iwl_rxon_context *ctx;
3240
3241 #define CHK(test, flag) do { \
3242 if (*total_flags & (test)) \
3243 filter_or |= (flag); \
3244 else \
3245 filter_nand |= (flag); \
3246 } while (0)
3247
3248 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3249 changed_flags, *total_flags);
3250
3251 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3252 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3253 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3254 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3255
3256 #undef CHK
3257
3258 mutex_lock(&priv->mutex);
3259
3260 for_each_context(priv, ctx) {
3261 ctx->staging.filter_flags &= ~filter_nand;
3262 ctx->staging.filter_flags |= filter_or;
3263
3264 /*
3265 * Not committing directly because hardware can perform a scan,
3266 * but we'll eventually commit the filter flags change anyway.
3267 */
3268 }
3269
3270 mutex_unlock(&priv->mutex);
3271
3272 /*
3273 * Receiving all multicast frames is always enabled by the
3274 * default flags setup in iwl_connection_init_rx_config()
3275 * since we currently do not support programming multicast
3276 * filters into the device.
3277 */
3278 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3279 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3280 }
3281
3282 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3283 {
3284 struct iwl_priv *priv = hw->priv;
3285
3286 mutex_lock(&priv->mutex);
3287 IWL_DEBUG_MAC80211(priv, "enter\n");
3288
3289 /* do not support "flush" */
3290 if (!priv->cfg->ops->lib->txfifo_flush)
3291 goto done;
3292
3293 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3294 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3295 goto done;
3296 }
3297 if (iwl_is_rfkill(priv)) {
3298 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3299 goto done;
3300 }
3301
3302 /*
3303 * mac80211 will not push any more frames for transmit
3304 * until the flush is completed
3305 */
3306 if (drop) {
3307 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3308 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3309 IWL_ERR(priv, "flush request fail\n");
3310 goto done;
3311 }
3312 }
3313 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3314 iwlagn_wait_tx_queue_empty(priv);
3315 done:
3316 mutex_unlock(&priv->mutex);
3317 IWL_DEBUG_MAC80211(priv, "leave\n");
3318 }
3319
3320 static void iwlagn_disable_roc(struct iwl_priv *priv)
3321 {
3322 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3323 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3324
3325 lockdep_assert_held(&priv->mutex);
3326
3327 if (!ctx->is_active)
3328 return;
3329
3330 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3331 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3332 iwl_set_rxon_channel(priv, chan, ctx);
3333 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3334
3335 priv->_agn.hw_roc_channel = NULL;
3336
3337 iwlcore_commit_rxon(priv, ctx);
3338
3339 ctx->is_active = false;
3340 }
3341
3342 static void iwlagn_bg_roc_done(struct work_struct *work)
3343 {
3344 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3345 _agn.hw_roc_work.work);
3346
3347 mutex_lock(&priv->mutex);
3348 ieee80211_remain_on_channel_expired(priv->hw);
3349 iwlagn_disable_roc(priv);
3350 mutex_unlock(&priv->mutex);
3351 }
3352
3353 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3354 struct ieee80211_channel *channel,
3355 enum nl80211_channel_type channel_type,
3356 int duration)
3357 {
3358 struct iwl_priv *priv = hw->priv;
3359 int err = 0;
3360
3361 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3362 return -EOPNOTSUPP;
3363
3364 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3365 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3366 return -EOPNOTSUPP;
3367
3368 mutex_lock(&priv->mutex);
3369
3370 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3371 test_bit(STATUS_SCAN_HW, &priv->status)) {
3372 err = -EBUSY;
3373 goto out;
3374 }
3375
3376 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3377 priv->_agn.hw_roc_channel = channel;
3378 priv->_agn.hw_roc_chantype = channel_type;
3379 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3380 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3381 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3382 msecs_to_jiffies(duration + 20));
3383
3384 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3385 ieee80211_ready_on_channel(priv->hw);
3386
3387 out:
3388 mutex_unlock(&priv->mutex);
3389
3390 return err;
3391 }
3392
3393 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3394 {
3395 struct iwl_priv *priv = hw->priv;
3396
3397 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3398 return -EOPNOTSUPP;
3399
3400 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3401
3402 mutex_lock(&priv->mutex);
3403 iwlagn_disable_roc(priv);
3404 mutex_unlock(&priv->mutex);
3405
3406 return 0;
3407 }
3408
3409 /*****************************************************************************
3410 *
3411 * driver setup and teardown
3412 *
3413 *****************************************************************************/
3414
3415 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3416 {
3417 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3418
3419 init_waitqueue_head(&priv->wait_command_queue);
3420
3421 INIT_WORK(&priv->restart, iwl_bg_restart);
3422 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3423 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3424 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3425 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3426 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3427 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3428 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3429 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3430 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3431
3432 iwl_setup_scan_deferred_work(priv);
3433
3434 if (priv->cfg->ops->lib->setup_deferred_work)
3435 priv->cfg->ops->lib->setup_deferred_work(priv);
3436
3437 init_timer(&priv->statistics_periodic);
3438 priv->statistics_periodic.data = (unsigned long)priv;
3439 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3440
3441 init_timer(&priv->ucode_trace);
3442 priv->ucode_trace.data = (unsigned long)priv;
3443 priv->ucode_trace.function = iwl_bg_ucode_trace;
3444
3445 init_timer(&priv->watchdog);
3446 priv->watchdog.data = (unsigned long)priv;
3447 priv->watchdog.function = iwl_bg_watchdog;
3448
3449 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3450 iwl_irq_tasklet, (unsigned long)priv);
3451 }
3452
3453 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3454 {
3455 if (priv->cfg->ops->lib->cancel_deferred_work)
3456 priv->cfg->ops->lib->cancel_deferred_work(priv);
3457
3458 cancel_delayed_work_sync(&priv->init_alive_start);
3459 cancel_delayed_work(&priv->alive_start);
3460 cancel_work_sync(&priv->run_time_calib_work);
3461 cancel_work_sync(&priv->beacon_update);
3462
3463 iwl_cancel_scan_deferred_work(priv);
3464
3465 cancel_work_sync(&priv->bt_full_concurrency);
3466 cancel_work_sync(&priv->bt_runtime_config);
3467
3468 del_timer_sync(&priv->statistics_periodic);
3469 del_timer_sync(&priv->ucode_trace);
3470 }
3471
3472 static void iwl_init_hw_rates(struct iwl_priv *priv,
3473 struct ieee80211_rate *rates)
3474 {
3475 int i;
3476
3477 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3478 rates[i].bitrate = iwl_rates[i].ieee * 5;
3479 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3480 rates[i].hw_value_short = i;
3481 rates[i].flags = 0;
3482 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3483 /*
3484 * If CCK != 1M then set short preamble rate flag.
3485 */
3486 rates[i].flags |=
3487 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3488 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3489 }
3490 }
3491 }
3492
3493 static int iwl_init_drv(struct iwl_priv *priv)
3494 {
3495 int ret;
3496
3497 spin_lock_init(&priv->sta_lock);
3498 spin_lock_init(&priv->hcmd_lock);
3499
3500 INIT_LIST_HEAD(&priv->free_frames);
3501
3502 mutex_init(&priv->mutex);
3503
3504 priv->ieee_channels = NULL;
3505 priv->ieee_rates = NULL;
3506 priv->band = IEEE80211_BAND_2GHZ;
3507
3508 priv->iw_mode = NL80211_IFTYPE_STATION;
3509 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3510 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3511 priv->_agn.agg_tids_count = 0;
3512
3513 /* initialize force reset */
3514 priv->force_reset[IWL_RF_RESET].reset_duration =
3515 IWL_DELAY_NEXT_FORCE_RF_RESET;
3516 priv->force_reset[IWL_FW_RESET].reset_duration =
3517 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3518
3519 priv->rx_statistics_jiffies = jiffies;
3520
3521 /* Choose which receivers/antennas to use */
3522 if (priv->cfg->ops->hcmd->set_rxon_chain)
3523 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3524 &priv->contexts[IWL_RXON_CTX_BSS]);
3525
3526 iwl_init_scan_params(priv);
3527
3528 /* init bt coex */
3529 if (priv->cfg->bt_params &&
3530 priv->cfg->bt_params->advanced_bt_coexist) {
3531 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3532 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3533 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3534 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3535 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3536 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3537 }
3538
3539 /* Set the tx_power_user_lmt to the lowest power level
3540 * this value will get overwritten by channel max power avg
3541 * from eeprom */
3542 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3543 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3544
3545 ret = iwl_init_channel_map(priv);
3546 if (ret) {
3547 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3548 goto err;
3549 }
3550
3551 ret = iwlcore_init_geos(priv);
3552 if (ret) {
3553 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3554 goto err_free_channel_map;
3555 }
3556 iwl_init_hw_rates(priv, priv->ieee_rates);
3557
3558 return 0;
3559
3560 err_free_channel_map:
3561 iwl_free_channel_map(priv);
3562 err:
3563 return ret;
3564 }
3565
3566 static void iwl_uninit_drv(struct iwl_priv *priv)
3567 {
3568 iwl_calib_free_results(priv);
3569 iwlcore_free_geos(priv);
3570 iwl_free_channel_map(priv);
3571 kfree(priv->scan_cmd);
3572 }
3573
3574 struct ieee80211_ops iwlagn_hw_ops = {
3575 .tx = iwlagn_mac_tx,
3576 .start = iwlagn_mac_start,
3577 .stop = iwlagn_mac_stop,
3578 .add_interface = iwl_mac_add_interface,
3579 .remove_interface = iwl_mac_remove_interface,
3580 .change_interface = iwl_mac_change_interface,
3581 .config = iwlagn_mac_config,
3582 .configure_filter = iwlagn_configure_filter,
3583 .set_key = iwlagn_mac_set_key,
3584 .update_tkip_key = iwlagn_mac_update_tkip_key,
3585 .conf_tx = iwl_mac_conf_tx,
3586 .bss_info_changed = iwlagn_bss_info_changed,
3587 .ampdu_action = iwlagn_mac_ampdu_action,
3588 .hw_scan = iwl_mac_hw_scan,
3589 .sta_notify = iwlagn_mac_sta_notify,
3590 .sta_add = iwlagn_mac_sta_add,
3591 .sta_remove = iwl_mac_sta_remove,
3592 .channel_switch = iwlagn_mac_channel_switch,
3593 .flush = iwlagn_mac_flush,
3594 .tx_last_beacon = iwl_mac_tx_last_beacon,
3595 .remain_on_channel = iwl_mac_remain_on_channel,
3596 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3597 .offchannel_tx = iwl_mac_offchannel_tx,
3598 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3599 };
3600
3601 static u32 iwl_hw_detect(struct iwl_priv *priv)
3602 {
3603 u8 rev_id;
3604
3605 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3606 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3607 return iwl_read32(priv, CSR_HW_REV);
3608 }
3609
3610 static int iwl_set_hw_params(struct iwl_priv *priv)
3611 {
3612 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3613 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3614 if (priv->cfg->mod_params->amsdu_size_8K)
3615 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3616 else
3617 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3618
3619 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3620
3621 if (priv->cfg->mod_params->disable_11n)
3622 priv->cfg->sku &= ~IWL_SKU_N;
3623
3624 /* Device-specific setup */
3625 return priv->cfg->ops->lib->set_hw_params(priv);
3626 }
3627
3628 static const u8 iwlagn_bss_ac_to_fifo[] = {
3629 IWL_TX_FIFO_VO,
3630 IWL_TX_FIFO_VI,
3631 IWL_TX_FIFO_BE,
3632 IWL_TX_FIFO_BK,
3633 };
3634
3635 static const u8 iwlagn_bss_ac_to_queue[] = {
3636 0, 1, 2, 3,
3637 };
3638
3639 static const u8 iwlagn_pan_ac_to_fifo[] = {
3640 IWL_TX_FIFO_VO_IPAN,
3641 IWL_TX_FIFO_VI_IPAN,
3642 IWL_TX_FIFO_BE_IPAN,
3643 IWL_TX_FIFO_BK_IPAN,
3644 };
3645
3646 static const u8 iwlagn_pan_ac_to_queue[] = {
3647 7, 6, 5, 4,
3648 };
3649
3650 /* This function both allocates and initializes hw and priv. */
3651 static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3652 {
3653 struct iwl_priv *priv;
3654 /* mac80211 allocates memory for this device instance, including
3655 * space for this driver's private structure */
3656 struct ieee80211_hw *hw;
3657
3658 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3659 if (hw == NULL) {
3660 pr_err("%s: Can not allocate network device\n",
3661 cfg->name);
3662 goto out;
3663 }
3664
3665 priv = hw->priv;
3666 priv->hw = hw;
3667
3668 out:
3669 return hw;
3670 }
3671
3672 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3673 {
3674 int err = 0, i;
3675 struct iwl_priv *priv;
3676 struct ieee80211_hw *hw;
3677 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3678 unsigned long flags;
3679 u16 pci_cmd, num_mac;
3680 u32 hw_rev;
3681
3682 /************************
3683 * 1. Allocating HW data
3684 ************************/
3685
3686 hw = iwl_alloc_all(cfg);
3687 if (!hw) {
3688 err = -ENOMEM;
3689 goto out;
3690 }
3691 priv = hw->priv;
3692 /* At this point both hw and priv are allocated. */
3693
3694 /*
3695 * The default context is always valid,
3696 * more may be discovered when firmware
3697 * is loaded.
3698 */
3699 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3700
3701 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3702 priv->contexts[i].ctxid = i;
3703
3704 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3705 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3706 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3707 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3708 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3709 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3710 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3711 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3712 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3713 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3714 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3715 BIT(NL80211_IFTYPE_ADHOC);
3716 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3717 BIT(NL80211_IFTYPE_STATION);
3718 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3719 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3720 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3721 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3722
3723 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3724 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3725 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3726 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3727 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3728 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3729 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3730 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3731 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3732 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3733 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3734 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3735 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3736 #ifdef CONFIG_IWL_P2P
3737 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3738 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3739 #endif
3740 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3741 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3742 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3743
3744 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3745
3746 SET_IEEE80211_DEV(hw, &pdev->dev);
3747
3748 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3749 priv->cfg = cfg;
3750 priv->pci_dev = pdev;
3751 priv->inta_mask = CSR_INI_SET_MASK;
3752
3753 /* is antenna coupling more than 35dB ? */
3754 priv->bt_ant_couple_ok =
3755 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3756 true : false;
3757
3758 /* enable/disable bt channel inhibition */
3759 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3760 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3761 (priv->bt_ch_announce) ? "On" : "Off");
3762
3763 if (iwl_alloc_traffic_mem(priv))
3764 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3765
3766 /**************************
3767 * 2. Initializing PCI bus
3768 **************************/
3769 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3770 PCIE_LINK_STATE_CLKPM);
3771
3772 if (pci_enable_device(pdev)) {
3773 err = -ENODEV;
3774 goto out_ieee80211_free_hw;
3775 }
3776
3777 pci_set_master(pdev);
3778
3779 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3780 if (!err)
3781 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3782 if (err) {
3783 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3784 if (!err)
3785 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3786 /* both attempts failed: */
3787 if (err) {
3788 IWL_WARN(priv, "No suitable DMA available.\n");
3789 goto out_pci_disable_device;
3790 }
3791 }
3792
3793 err = pci_request_regions(pdev, DRV_NAME);
3794 if (err)
3795 goto out_pci_disable_device;
3796
3797 pci_set_drvdata(pdev, priv);
3798
3799
3800 /***********************
3801 * 3. Read REV register
3802 ***********************/
3803 priv->hw_base = pci_iomap(pdev, 0, 0);
3804 if (!priv->hw_base) {
3805 err = -ENODEV;
3806 goto out_pci_release_regions;
3807 }
3808
3809 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3810 (unsigned long long) pci_resource_len(pdev, 0));
3811 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3812
3813 /* these spin locks will be used in apm_ops.init and EEPROM access
3814 * we should init now
3815 */
3816 spin_lock_init(&priv->reg_lock);
3817 spin_lock_init(&priv->lock);
3818
3819 /*
3820 * stop and reset the on-board processor just in case it is in a
3821 * strange state ... like being left stranded by a primary kernel
3822 * and this is now the kdump kernel trying to start up
3823 */
3824 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3825
3826 hw_rev = iwl_hw_detect(priv);
3827 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3828 priv->cfg->name, hw_rev);
3829
3830 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3831 * PCI Tx retries from interfering with C3 CPU state */
3832 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3833
3834 iwl_prepare_card_hw(priv);
3835 if (!priv->hw_ready) {
3836 IWL_WARN(priv, "Failed, HW not ready\n");
3837 goto out_iounmap;
3838 }
3839
3840 /*****************
3841 * 4. Read EEPROM
3842 *****************/
3843 /* Read the EEPROM */
3844 err = iwl_eeprom_init(priv, hw_rev);
3845 if (err) {
3846 IWL_ERR(priv, "Unable to init EEPROM\n");
3847 goto out_iounmap;
3848 }
3849 err = iwl_eeprom_check_version(priv);
3850 if (err)
3851 goto out_free_eeprom;
3852
3853 err = iwl_eeprom_check_sku(priv);
3854 if (err)
3855 goto out_free_eeprom;
3856
3857 /* extract MAC Address */
3858 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3859 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3860 priv->hw->wiphy->addresses = priv->addresses;
3861 priv->hw->wiphy->n_addresses = 1;
3862 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3863 if (num_mac > 1) {
3864 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3865 ETH_ALEN);
3866 priv->addresses[1].addr[5]++;
3867 priv->hw->wiphy->n_addresses++;
3868 }
3869
3870 /************************
3871 * 5. Setup HW constants
3872 ************************/
3873 if (iwl_set_hw_params(priv)) {
3874 IWL_ERR(priv, "failed to set hw parameters\n");
3875 goto out_free_eeprom;
3876 }
3877
3878 /*******************
3879 * 6. Setup priv
3880 *******************/
3881
3882 err = iwl_init_drv(priv);
3883 if (err)
3884 goto out_free_eeprom;
3885 /* At this point both hw and priv are initialized. */
3886
3887 /********************
3888 * 7. Setup services
3889 ********************/
3890 spin_lock_irqsave(&priv->lock, flags);
3891 iwl_disable_interrupts(priv);
3892 spin_unlock_irqrestore(&priv->lock, flags);
3893
3894 pci_enable_msi(priv->pci_dev);
3895
3896 iwl_alloc_isr_ict(priv);
3897
3898 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3899 IRQF_SHARED, DRV_NAME, priv);
3900 if (err) {
3901 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3902 goto out_disable_msi;
3903 }
3904
3905 iwl_setup_deferred_work(priv);
3906 iwl_setup_rx_handlers(priv);
3907
3908 /*********************************************
3909 * 8. Enable interrupts and read RFKILL state
3910 *********************************************/
3911
3912 /* enable rfkill interrupt: hw bug w/a */
3913 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3914 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3915 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3916 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3917 }
3918
3919 iwl_enable_rfkill_int(priv);
3920
3921 /* If platform's RF_KILL switch is NOT set to KILL */
3922 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3923 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3924 else
3925 set_bit(STATUS_RF_KILL_HW, &priv->status);
3926
3927 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3928 test_bit(STATUS_RF_KILL_HW, &priv->status));
3929
3930 iwl_power_initialize(priv);
3931 iwl_tt_initialize(priv);
3932
3933 init_completion(&priv->_agn.firmware_loading_complete);
3934
3935 err = iwl_request_firmware(priv, true);
3936 if (err)
3937 goto out_destroy_workqueue;
3938
3939 return 0;
3940
3941 out_destroy_workqueue:
3942 destroy_workqueue(priv->workqueue);
3943 priv->workqueue = NULL;
3944 free_irq(priv->pci_dev->irq, priv);
3945 iwl_free_isr_ict(priv);
3946 out_disable_msi:
3947 pci_disable_msi(priv->pci_dev);
3948 iwl_uninit_drv(priv);
3949 out_free_eeprom:
3950 iwl_eeprom_free(priv);
3951 out_iounmap:
3952 pci_iounmap(pdev, priv->hw_base);
3953 out_pci_release_regions:
3954 pci_set_drvdata(pdev, NULL);
3955 pci_release_regions(pdev);
3956 out_pci_disable_device:
3957 pci_disable_device(pdev);
3958 out_ieee80211_free_hw:
3959 iwl_free_traffic_mem(priv);
3960 ieee80211_free_hw(priv->hw);
3961 out:
3962 return err;
3963 }
3964
3965 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3966 {
3967 struct iwl_priv *priv = pci_get_drvdata(pdev);
3968 unsigned long flags;
3969
3970 if (!priv)
3971 return;
3972
3973 wait_for_completion(&priv->_agn.firmware_loading_complete);
3974
3975 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3976
3977 iwl_dbgfs_unregister(priv);
3978 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3979
3980 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3981 * to be called and iwl_down since we are removing the device
3982 * we need to set STATUS_EXIT_PENDING bit.
3983 */
3984 set_bit(STATUS_EXIT_PENDING, &priv->status);
3985
3986 iwl_leds_exit(priv);
3987
3988 if (priv->mac80211_registered) {
3989 ieee80211_unregister_hw(priv->hw);
3990 priv->mac80211_registered = 0;
3991 }
3992
3993 /* Reset to low power before unloading driver. */
3994 iwl_apm_stop(priv);
3995
3996 iwl_tt_exit(priv);
3997
3998 /* make sure we flush any pending irq or
3999 * tasklet for the driver
4000 */
4001 spin_lock_irqsave(&priv->lock, flags);
4002 iwl_disable_interrupts(priv);
4003 spin_unlock_irqrestore(&priv->lock, flags);
4004
4005 iwl_synchronize_irq(priv);
4006
4007 iwl_dealloc_ucode_pci(priv);
4008
4009 if (priv->rxq.bd)
4010 iwlagn_rx_queue_free(priv, &priv->rxq);
4011 iwlagn_hw_txq_ctx_free(priv);
4012
4013 iwl_eeprom_free(priv);
4014
4015
4016 /*netif_stop_queue(dev); */
4017 flush_workqueue(priv->workqueue);
4018
4019 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4020 * priv->workqueue... so we can't take down the workqueue
4021 * until now... */
4022 destroy_workqueue(priv->workqueue);
4023 priv->workqueue = NULL;
4024 iwl_free_traffic_mem(priv);
4025
4026 free_irq(priv->pci_dev->irq, priv);
4027 pci_disable_msi(priv->pci_dev);
4028 pci_iounmap(pdev, priv->hw_base);
4029 pci_release_regions(pdev);
4030 pci_disable_device(pdev);
4031 pci_set_drvdata(pdev, NULL);
4032
4033 iwl_uninit_drv(priv);
4034
4035 iwl_free_isr_ict(priv);
4036
4037 dev_kfree_skb(priv->beacon_skb);
4038
4039 ieee80211_free_hw(priv->hw);
4040 }
4041
4042
4043 /*****************************************************************************
4044 *
4045 * driver and module entry point
4046 *
4047 *****************************************************************************/
4048
4049 /* Hardware specific file defines the PCI IDs table for that hardware module */
4050 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4051 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4052 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4053 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4054 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4055 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4056 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4057 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4058 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4059 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4060 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4061 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4062 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4063 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4064 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4065 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4066 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4067 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4068 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4069 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4070 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4071 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4072 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4073 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4074 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4075
4076 /* 5300 Series WiFi */
4077 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4078 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4079 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4080 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4081 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4082 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4083 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4084 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4085 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4086 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4087 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4088 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4089
4090 /* 5350 Series WiFi/WiMax */
4091 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4092 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4093 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4094
4095 /* 5150 Series Wifi/WiMax */
4096 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4097 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4098 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4099 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4100 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4101 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4102
4103 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4104 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4105 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4106 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4107
4108 /* 6x00 Series */
4109 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4110 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4111 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4112 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4113 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4114 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4115 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4116 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4117 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4118 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4119
4120 /* 6x05 Series */
4121 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4122 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4123 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4124 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4125 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4126 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4127 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4128
4129 /* 6x30 Series */
4130 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4131 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4132 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4133 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4134 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4135 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4136 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4137 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4138 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4139 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4140 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4141 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4142 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4143 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4144 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4145 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4146
4147 /* 6x50 WiFi/WiMax Series */
4148 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4149 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4150 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4151 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4152 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4153 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4154
4155 /* 6150 WiFi/WiMax Series */
4156 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4157 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4158 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4159 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4160 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4161 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4162
4163 /* 1000 Series WiFi */
4164 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4165 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4166 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4167 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4168 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4169 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4170 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4171 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4172 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4173 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4174 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4175 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4176
4177 /* 100 Series WiFi */
4178 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4179 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4180 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4181 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4182 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4183 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4184
4185 /* 130 Series WiFi */
4186 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4187 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4188 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4189 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4190 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4191 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4192
4193 /* 2x00 Series */
4194 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4195 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4196 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4197 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4198 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4199 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4200
4201 /* 2x30 Series */
4202 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4203 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4204 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4205 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4206 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4207 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4208
4209 /* 6x35 Series */
4210 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4211 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4212 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4213 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4214 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4215 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4216 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4217 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4218 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4219
4220 /* 200 Series */
4221 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4222 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4223 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4224 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4225 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4226 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4227
4228 /* 230 Series */
4229 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4230 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4231 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4232 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4233 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4234 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4235
4236 {0}
4237 };
4238 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4239
4240 static struct pci_driver iwl_driver = {
4241 .name = DRV_NAME,
4242 .id_table = iwl_hw_card_ids,
4243 .probe = iwl_pci_probe,
4244 .remove = __devexit_p(iwl_pci_remove),
4245 .driver.pm = IWL_PM_OPS,
4246 };
4247
4248 static int __init iwl_init(void)
4249 {
4250
4251 int ret;
4252 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4253 pr_info(DRV_COPYRIGHT "\n");
4254
4255 ret = iwlagn_rate_control_register();
4256 if (ret) {
4257 pr_err("Unable to register rate control algorithm: %d\n", ret);
4258 return ret;
4259 }
4260
4261 ret = pci_register_driver(&iwl_driver);
4262 if (ret) {
4263 pr_err("Unable to initialize PCI module\n");
4264 goto error_register;
4265 }
4266
4267 return ret;
4268
4269 error_register:
4270 iwlagn_rate_control_unregister();
4271 return ret;
4272 }
4273
4274 static void __exit iwl_exit(void)
4275 {
4276 pci_unregister_driver(&iwl_driver);
4277 iwlagn_rate_control_unregister();
4278 }
4279
4280 module_exit(iwl_exit);
4281 module_init(iwl_init);
4282
4283 #ifdef CONFIG_IWLWIFI_DEBUG
4284 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4285 MODULE_PARM_DESC(debug, "debug output mask");
4286 #endif
4287
4288 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4289 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4290 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4291 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4292 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4293 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4294 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4295 int, S_IRUGO);
4296 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4297 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4298 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4299
4300 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4301 S_IRUGO);
4302 MODULE_PARM_DESC(ucode_alternative,
4303 "specify ucode alternative to use from ucode file");
4304
4305 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4306 MODULE_PARM_DESC(antenna_coupling,
4307 "specify antenna coupling in dB (defualt: 0 dB)");
4308
4309 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4310 MODULE_PARM_DESC(bt_ch_inhibition,
4311 "Disable BT channel inhibition (default: enable)");
4312
4313 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4314 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4315
4316 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4317 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
Linux kernel - Deliverables
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