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iwlagn: remove most BUG_ON instances
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70 /*
71 * module name, copyright, version, etc.
72 */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94 struct iwl_rxon_context *ctx;
95
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 }
103 }
104
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
106 {
107 struct list_head *element;
108
109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
110 priv->frames_count);
111
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
114 list_del(element);
115 kfree(list_entry(element, struct iwl_frame, list));
116 priv->frames_count--;
117 }
118
119 if (priv->frames_count) {
120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
121 priv->frames_count);
122 priv->frames_count = 0;
123 }
124 }
125
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
127 {
128 struct iwl_frame *frame;
129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132 if (!frame) {
133 IWL_ERR(priv, "Could not allocate frame!\n");
134 return NULL;
135 }
136
137 priv->frames_count++;
138 return frame;
139 }
140
141 element = priv->free_frames.next;
142 list_del(element);
143 return list_entry(element, struct iwl_frame, list);
144 }
145
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
147 {
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
150 }
151
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153 struct ieee80211_hdr *hdr,
154 int left)
155 {
156 lockdep_assert_held(&priv->mutex);
157
158 if (!priv->beacon_skb)
159 return 0;
160
161 if (priv->beacon_skb->len > left)
162 return 0;
163
164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
165
166 return priv->beacon_skb->len;
167 }
168
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
173 {
174 u16 tim_idx;
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177 /*
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
180 */
181 tim_idx = mgmt->u.beacon.variable - beacon;
182
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
187
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192 } else
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194 }
195
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197 struct iwl_frame *frame)
198 {
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
200 u32 frame_size;
201 u32 rate_flags;
202 u32 rate;
203 /*
204 * We have to set up the TX command, the TX Beacon command, and the
205 * beacon contents.
206 */
207
208 lockdep_assert_held(&priv->mutex);
209
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
212 return 0;
213 }
214
215 /* Initialize memory */
216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
219 /* Set up TX beacon contents */
220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223 return 0;
224 if (!frame_size)
225 return 0;
226
227 /* Set up TX command fields */
228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
233
234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
236 frame_size);
237
238 /* Set up packet rate and flags */
239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246 rate_flags);
247
248 return sizeof(*tx_beacon_cmd) + frame_size;
249 }
250
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
252 {
253 struct iwl_frame *frame;
254 unsigned int frame_size;
255 int rc;
256
257 frame = iwl_get_free_frame(priv);
258 if (!frame) {
259 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
260 "command.\n");
261 return -ENOMEM;
262 }
263
264 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
265 if (!frame_size) {
266 IWL_ERR(priv, "Error configuring the beacon command\n");
267 iwl_free_frame(priv, frame);
268 return -EINVAL;
269 }
270
271 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
272 &frame->u.cmd[0]);
273
274 iwl_free_frame(priv, frame);
275
276 return rc;
277 }
278
279 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
280 {
281 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
282
283 dma_addr_t addr = get_unaligned_le32(&tb->lo);
284 if (sizeof(dma_addr_t) > sizeof(u32))
285 addr |=
286 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
287
288 return addr;
289 }
290
291 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
292 {
293 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
294
295 return le16_to_cpu(tb->hi_n_len) >> 4;
296 }
297
298 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
299 dma_addr_t addr, u16 len)
300 {
301 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
302 u16 hi_n_len = len << 4;
303
304 put_unaligned_le32(addr, &tb->lo);
305 if (sizeof(dma_addr_t) > sizeof(u32))
306 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
307
308 tb->hi_n_len = cpu_to_le16(hi_n_len);
309
310 tfd->num_tbs = idx + 1;
311 }
312
313 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
314 {
315 return tfd->num_tbs & 0x1f;
316 }
317
318 /**
319 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
320 * @priv - driver private data
321 * @txq - tx queue
322 *
323 * Does NOT advance any TFD circular buffer read/write indexes
324 * Does NOT free the TFD itself (which is within circular buffer)
325 */
326 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
327 {
328 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
329 struct iwl_tfd *tfd;
330 struct pci_dev *dev = priv->pci_dev;
331 int index = txq->q.read_ptr;
332 int i;
333 int num_tbs;
334
335 tfd = &tfd_tmp[index];
336
337 /* Sanity check on number of chunks */
338 num_tbs = iwl_tfd_get_num_tbs(tfd);
339
340 if (num_tbs >= IWL_NUM_OF_TBS) {
341 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
342 /* @todo issue fatal error, it is quite serious situation */
343 return;
344 }
345
346 /* Unmap tx_cmd */
347 if (num_tbs)
348 pci_unmap_single(dev,
349 dma_unmap_addr(&txq->meta[index], mapping),
350 dma_unmap_len(&txq->meta[index], len),
351 PCI_DMA_BIDIRECTIONAL);
352
353 /* Unmap chunks, if any. */
354 for (i = 1; i < num_tbs; i++)
355 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
356 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
357
358 /* free SKB */
359 if (txq->txb) {
360 struct sk_buff *skb;
361
362 skb = txq->txb[txq->q.read_ptr].skb;
363
364 /* can be called from irqs-disabled context */
365 if (skb) {
366 dev_kfree_skb_any(skb);
367 txq->txb[txq->q.read_ptr].skb = NULL;
368 }
369 }
370 }
371
372 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
373 struct iwl_tx_queue *txq,
374 dma_addr_t addr, u16 len,
375 u8 reset, u8 pad)
376 {
377 struct iwl_queue *q;
378 struct iwl_tfd *tfd, *tfd_tmp;
379 u32 num_tbs;
380
381 q = &txq->q;
382 tfd_tmp = (struct iwl_tfd *)txq->tfds;
383 tfd = &tfd_tmp[q->write_ptr];
384
385 if (reset)
386 memset(tfd, 0, sizeof(*tfd));
387
388 num_tbs = iwl_tfd_get_num_tbs(tfd);
389
390 /* Each TFD can point to a maximum 20 Tx buffers */
391 if (num_tbs >= IWL_NUM_OF_TBS) {
392 IWL_ERR(priv, "Error can not send more than %d chunks\n",
393 IWL_NUM_OF_TBS);
394 return -EINVAL;
395 }
396
397 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
398 return -EINVAL;
399
400 if (unlikely(addr & ~IWL_TX_DMA_MASK))
401 IWL_ERR(priv, "Unaligned address = %llx\n",
402 (unsigned long long)addr);
403
404 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
405
406 return 0;
407 }
408
409 /*
410 * Tell nic where to find circular buffer of Tx Frame Descriptors for
411 * given Tx queue, and enable the DMA channel used for that queue.
412 *
413 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
414 * channels supported in hardware.
415 */
416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
417 struct iwl_tx_queue *txq)
418 {
419 int txq_id = txq->q.id;
420
421 /* Circular buffer (TFD queue in DRAM) physical base address */
422 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
423 txq->q.dma_addr >> 8);
424
425 return 0;
426 }
427
428 static void iwl_bg_beacon_update(struct work_struct *work)
429 {
430 struct iwl_priv *priv =
431 container_of(work, struct iwl_priv, beacon_update);
432 struct sk_buff *beacon;
433
434 mutex_lock(&priv->mutex);
435 if (!priv->beacon_ctx) {
436 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
437 goto out;
438 }
439
440 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
441 /*
442 * The ucode will send beacon notifications even in
443 * IBSS mode, but we don't want to process them. But
444 * we need to defer the type check to here due to
445 * requiring locking around the beacon_ctx access.
446 */
447 goto out;
448 }
449
450 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
451 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
452 if (!beacon) {
453 IWL_ERR(priv, "update beacon failed -- keeping old\n");
454 goto out;
455 }
456
457 /* new beacon skb is allocated every time; dispose previous.*/
458 dev_kfree_skb(priv->beacon_skb);
459
460 priv->beacon_skb = beacon;
461
462 iwlagn_send_beacon_cmd(priv);
463 out:
464 mutex_unlock(&priv->mutex);
465 }
466
467 static void iwl_bg_bt_runtime_config(struct work_struct *work)
468 {
469 struct iwl_priv *priv =
470 container_of(work, struct iwl_priv, bt_runtime_config);
471
472 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
473 return;
474
475 /* dont send host command if rf-kill is on */
476 if (!iwl_is_ready_rf(priv))
477 return;
478 priv->cfg->ops->hcmd->send_bt_config(priv);
479 }
480
481 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
482 {
483 struct iwl_priv *priv =
484 container_of(work, struct iwl_priv, bt_full_concurrency);
485 struct iwl_rxon_context *ctx;
486
487 mutex_lock(&priv->mutex);
488
489 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
490 goto out;
491
492 /* dont send host command if rf-kill is on */
493 if (!iwl_is_ready_rf(priv))
494 goto out;
495
496 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
497 priv->bt_full_concurrent ?
498 "full concurrency" : "3-wire");
499
500 /*
501 * LQ & RXON updated cmds must be sent before BT Config cmd
502 * to avoid 3-wire collisions
503 */
504 for_each_context(priv, ctx) {
505 if (priv->cfg->ops->hcmd->set_rxon_chain)
506 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
507 iwlcore_commit_rxon(priv, ctx);
508 }
509
510 priv->cfg->ops->hcmd->send_bt_config(priv);
511 out:
512 mutex_unlock(&priv->mutex);
513 }
514
515 /**
516 * iwl_bg_statistics_periodic - Timer callback to queue statistics
517 *
518 * This callback is provided in order to send a statistics request.
519 *
520 * This timer function is continually reset to execute within
521 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
522 * was received. We need to ensure we receive the statistics in order
523 * to update the temperature used for calibrating the TXPOWER.
524 */
525 static void iwl_bg_statistics_periodic(unsigned long data)
526 {
527 struct iwl_priv *priv = (struct iwl_priv *)data;
528
529 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
530 return;
531
532 /* dont send host command if rf-kill is on */
533 if (!iwl_is_ready_rf(priv))
534 return;
535
536 iwl_send_statistics_request(priv, CMD_ASYNC, false);
537 }
538
539
540 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
541 u32 start_idx, u32 num_events,
542 u32 mode)
543 {
544 u32 i;
545 u32 ptr; /* SRAM byte address of log data */
546 u32 ev, time, data; /* event log data */
547 unsigned long reg_flags;
548
549 if (mode == 0)
550 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
551 else
552 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
553
554 /* Make sure device is powered up for SRAM reads */
555 spin_lock_irqsave(&priv->reg_lock, reg_flags);
556 if (iwl_grab_nic_access(priv)) {
557 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
558 return;
559 }
560
561 /* Set starting address; reads will auto-increment */
562 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
563 rmb();
564
565 /*
566 * "time" is actually "data" for mode 0 (no timestamp).
567 * place event id # at far right for easier visual parsing.
568 */
569 for (i = 0; i < num_events; i++) {
570 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
571 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
572 if (mode == 0) {
573 trace_iwlwifi_dev_ucode_cont_event(priv,
574 0, time, ev);
575 } else {
576 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577 trace_iwlwifi_dev_ucode_cont_event(priv,
578 time, data, ev);
579 }
580 }
581 /* Allow device to power down */
582 iwl_release_nic_access(priv);
583 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
584 }
585
586 static void iwl_continuous_event_trace(struct iwl_priv *priv)
587 {
588 u32 capacity; /* event log capacity in # entries */
589 u32 base; /* SRAM byte address of event log header */
590 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
591 u32 num_wraps; /* # times uCode wrapped to top of log */
592 u32 next_entry; /* index of next entry to be written by uCode */
593
594 base = priv->device_pointers.error_event_table;
595 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
596 capacity = iwl_read_targ_mem(priv, base);
597 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
598 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
599 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
600 } else
601 return;
602
603 if (num_wraps == priv->event_log.num_wraps) {
604 iwl_print_cont_event_trace(priv,
605 base, priv->event_log.next_entry,
606 next_entry - priv->event_log.next_entry,
607 mode);
608 priv->event_log.non_wraps_count++;
609 } else {
610 if ((num_wraps - priv->event_log.num_wraps) > 1)
611 priv->event_log.wraps_more_count++;
612 else
613 priv->event_log.wraps_once_count++;
614 trace_iwlwifi_dev_ucode_wrap_event(priv,
615 num_wraps - priv->event_log.num_wraps,
616 next_entry, priv->event_log.next_entry);
617 if (next_entry < priv->event_log.next_entry) {
618 iwl_print_cont_event_trace(priv, base,
619 priv->event_log.next_entry,
620 capacity - priv->event_log.next_entry,
621 mode);
622
623 iwl_print_cont_event_trace(priv, base, 0,
624 next_entry, mode);
625 } else {
626 iwl_print_cont_event_trace(priv, base,
627 next_entry, capacity - next_entry,
628 mode);
629
630 iwl_print_cont_event_trace(priv, base, 0,
631 next_entry, mode);
632 }
633 }
634 priv->event_log.num_wraps = num_wraps;
635 priv->event_log.next_entry = next_entry;
636 }
637
638 /**
639 * iwl_bg_ucode_trace - Timer callback to log ucode event
640 *
641 * The timer is continually set to execute every
642 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
643 * this function is to perform continuous uCode event logging operation
644 * if enabled
645 */
646 static void iwl_bg_ucode_trace(unsigned long data)
647 {
648 struct iwl_priv *priv = (struct iwl_priv *)data;
649
650 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
651 return;
652
653 if (priv->event_log.ucode_trace) {
654 iwl_continuous_event_trace(priv);
655 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
656 mod_timer(&priv->ucode_trace,
657 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
658 }
659 }
660
661 static void iwl_bg_tx_flush(struct work_struct *work)
662 {
663 struct iwl_priv *priv =
664 container_of(work, struct iwl_priv, tx_flush);
665
666 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
667 return;
668
669 /* do nothing if rf-kill is on */
670 if (!iwl_is_ready_rf(priv))
671 return;
672
673 if (priv->cfg->ops->lib->txfifo_flush) {
674 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
675 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
676 }
677 }
678
679 /**
680 * iwl_rx_handle - Main entry function for receiving responses from uCode
681 *
682 * Uses the priv->rx_handlers callback function array to invoke
683 * the appropriate handlers, including command responses,
684 * frame-received notifications, and other notifications.
685 */
686 static void iwl_rx_handle(struct iwl_priv *priv)
687 {
688 struct iwl_rx_mem_buffer *rxb;
689 struct iwl_rx_packet *pkt;
690 struct iwl_rx_queue *rxq = &priv->rxq;
691 u32 r, i;
692 int reclaim;
693 unsigned long flags;
694 u8 fill_rx = 0;
695 u32 count = 8;
696 int total_empty;
697
698 /* uCode's read index (stored in shared DRAM) indicates the last Rx
699 * buffer that the driver may process (last buffer filled by ucode). */
700 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
701 i = rxq->read;
702
703 /* Rx interrupt, but nothing sent from uCode */
704 if (i == r)
705 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
706
707 /* calculate total frames need to be restock after handling RX */
708 total_empty = r - rxq->write_actual;
709 if (total_empty < 0)
710 total_empty += RX_QUEUE_SIZE;
711
712 if (total_empty > (RX_QUEUE_SIZE / 2))
713 fill_rx = 1;
714
715 while (i != r) {
716 int len;
717
718 rxb = rxq->queue[i];
719
720 /* If an RXB doesn't have a Rx queue slot associated with it,
721 * then a bug has been introduced in the queue refilling
722 * routines -- catch it here */
723 if (WARN_ON(rxb == NULL)) {
724 i = (i + 1) & RX_QUEUE_MASK;
725 continue;
726 }
727
728 rxq->queue[i] = NULL;
729
730 pci_unmap_page(priv->pci_dev, rxb->page_dma,
731 PAGE_SIZE << priv->hw_params.rx_page_order,
732 PCI_DMA_FROMDEVICE);
733 pkt = rxb_addr(rxb);
734
735 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
736 len += sizeof(u32); /* account for status word */
737 trace_iwlwifi_dev_rx(priv, pkt, len);
738
739 /* Reclaim a command buffer only if this packet is a response
740 * to a (driver-originated) command.
741 * If the packet (e.g. Rx frame) originated from uCode,
742 * there is no command buffer to reclaim.
743 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
744 * but apparently a few don't get set; catch them here. */
745 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
746 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
747 (pkt->hdr.cmd != REPLY_RX) &&
748 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
749 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
750 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
751 (pkt->hdr.cmd != REPLY_TX);
752
753 /*
754 * Do the notification wait before RX handlers so
755 * even if the RX handler consumes the RXB we have
756 * access to it in the notification wait entry.
757 */
758 if (!list_empty(&priv->_agn.notif_waits)) {
759 struct iwl_notification_wait *w;
760
761 spin_lock(&priv->_agn.notif_wait_lock);
762 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
763 if (w->cmd == pkt->hdr.cmd) {
764 w->triggered = true;
765 if (w->fn)
766 w->fn(priv, pkt);
767 }
768 }
769 spin_unlock(&priv->_agn.notif_wait_lock);
770
771 wake_up_all(&priv->_agn.notif_waitq);
772 }
773
774 /* Based on type of command response or notification,
775 * handle those that need handling via function in
776 * rx_handlers table. See iwl_setup_rx_handlers() */
777 if (priv->rx_handlers[pkt->hdr.cmd]) {
778 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
779 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
780 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
781 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
782 } else {
783 /* No handling needed */
784 IWL_DEBUG_RX(priv,
785 "r %d i %d No handler needed for %s, 0x%02x\n",
786 r, i, get_cmd_string(pkt->hdr.cmd),
787 pkt->hdr.cmd);
788 }
789
790 /*
791 * XXX: After here, we should always check rxb->page
792 * against NULL before touching it or its virtual
793 * memory (pkt). Because some rx_handler might have
794 * already taken or freed the pages.
795 */
796
797 if (reclaim) {
798 /* Invoke any callbacks, transfer the buffer to caller,
799 * and fire off the (possibly) blocking iwl_send_cmd()
800 * as we reclaim the driver command queue */
801 if (rxb->page)
802 iwl_tx_cmd_complete(priv, rxb);
803 else
804 IWL_WARN(priv, "Claim null rxb?\n");
805 }
806
807 /* Reuse the page if possible. For notification packets and
808 * SKBs that fail to Rx correctly, add them back into the
809 * rx_free list for reuse later. */
810 spin_lock_irqsave(&rxq->lock, flags);
811 if (rxb->page != NULL) {
812 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
813 0, PAGE_SIZE << priv->hw_params.rx_page_order,
814 PCI_DMA_FROMDEVICE);
815 list_add_tail(&rxb->list, &rxq->rx_free);
816 rxq->free_count++;
817 } else
818 list_add_tail(&rxb->list, &rxq->rx_used);
819
820 spin_unlock_irqrestore(&rxq->lock, flags);
821
822 i = (i + 1) & RX_QUEUE_MASK;
823 /* If there are a lot of unused frames,
824 * restock the Rx queue so ucode wont assert. */
825 if (fill_rx) {
826 count++;
827 if (count >= 8) {
828 rxq->read = i;
829 iwlagn_rx_replenish_now(priv);
830 count = 0;
831 }
832 }
833 }
834
835 /* Backtrack one entry */
836 rxq->read = i;
837 if (fill_rx)
838 iwlagn_rx_replenish_now(priv);
839 else
840 iwlagn_rx_queue_restock(priv);
841 }
842
843 /* call this function to flush any scheduled tasklet */
844 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
845 {
846 /* wait to make sure we flush pending tasklet*/
847 synchronize_irq(priv->pci_dev->irq);
848 tasklet_kill(&priv->irq_tasklet);
849 }
850
851 /* tasklet for iwlagn interrupt */
852 static void iwl_irq_tasklet(struct iwl_priv *priv)
853 {
854 u32 inta = 0;
855 u32 handled = 0;
856 unsigned long flags;
857 u32 i;
858 #ifdef CONFIG_IWLWIFI_DEBUG
859 u32 inta_mask;
860 #endif
861
862 spin_lock_irqsave(&priv->lock, flags);
863
864 /* Ack/clear/reset pending uCode interrupts.
865 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
866 */
867 /* There is a hardware bug in the interrupt mask function that some
868 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
869 * they are disabled in the CSR_INT_MASK register. Furthermore the
870 * ICT interrupt handling mechanism has another bug that might cause
871 * these unmasked interrupts fail to be detected. We workaround the
872 * hardware bugs here by ACKing all the possible interrupts so that
873 * interrupt coalescing can still be achieved.
874 */
875 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
876
877 inta = priv->_agn.inta;
878
879 #ifdef CONFIG_IWLWIFI_DEBUG
880 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
881 /* just for debug */
882 inta_mask = iwl_read32(priv, CSR_INT_MASK);
883 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
884 inta, inta_mask);
885 }
886 #endif
887
888 spin_unlock_irqrestore(&priv->lock, flags);
889
890 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
891 priv->_agn.inta = 0;
892
893 /* Now service all interrupt bits discovered above. */
894 if (inta & CSR_INT_BIT_HW_ERR) {
895 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
896
897 /* Tell the device to stop sending interrupts */
898 iwl_disable_interrupts(priv);
899
900 priv->isr_stats.hw++;
901 iwl_irq_handle_error(priv);
902
903 handled |= CSR_INT_BIT_HW_ERR;
904
905 return;
906 }
907
908 #ifdef CONFIG_IWLWIFI_DEBUG
909 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
910 /* NIC fires this, but we don't use it, redundant with WAKEUP */
911 if (inta & CSR_INT_BIT_SCD) {
912 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
913 "the frame/frames.\n");
914 priv->isr_stats.sch++;
915 }
916
917 /* Alive notification via Rx interrupt will do the real work */
918 if (inta & CSR_INT_BIT_ALIVE) {
919 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
920 priv->isr_stats.alive++;
921 }
922 }
923 #endif
924 /* Safely ignore these bits for debug checks below */
925 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
926
927 /* HW RF KILL switch toggled */
928 if (inta & CSR_INT_BIT_RF_KILL) {
929 int hw_rf_kill = 0;
930 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
931 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
932 hw_rf_kill = 1;
933
934 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
935 hw_rf_kill ? "disable radio" : "enable radio");
936
937 priv->isr_stats.rfkill++;
938
939 /* driver only loads ucode once setting the interface up.
940 * the driver allows loading the ucode even if the radio
941 * is killed. Hence update the killswitch state here. The
942 * rfkill handler will care about restarting if needed.
943 */
944 if (!test_bit(STATUS_ALIVE, &priv->status)) {
945 if (hw_rf_kill)
946 set_bit(STATUS_RF_KILL_HW, &priv->status);
947 else
948 clear_bit(STATUS_RF_KILL_HW, &priv->status);
949 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
950 }
951
952 handled |= CSR_INT_BIT_RF_KILL;
953 }
954
955 /* Chip got too hot and stopped itself */
956 if (inta & CSR_INT_BIT_CT_KILL) {
957 IWL_ERR(priv, "Microcode CT kill error detected.\n");
958 priv->isr_stats.ctkill++;
959 handled |= CSR_INT_BIT_CT_KILL;
960 }
961
962 /* Error detected by uCode */
963 if (inta & CSR_INT_BIT_SW_ERR) {
964 IWL_ERR(priv, "Microcode SW error detected. "
965 " Restarting 0x%X.\n", inta);
966 priv->isr_stats.sw++;
967 iwl_irq_handle_error(priv);
968 handled |= CSR_INT_BIT_SW_ERR;
969 }
970
971 /* uCode wakes up after power-down sleep */
972 if (inta & CSR_INT_BIT_WAKEUP) {
973 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
974 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
975 for (i = 0; i < priv->hw_params.max_txq_num; i++)
976 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
977
978 priv->isr_stats.wakeup++;
979
980 handled |= CSR_INT_BIT_WAKEUP;
981 }
982
983 /* All uCode command responses, including Tx command responses,
984 * Rx "responses" (frame-received notification), and other
985 * notifications from uCode come through here*/
986 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
987 CSR_INT_BIT_RX_PERIODIC)) {
988 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
989 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
990 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
991 iwl_write32(priv, CSR_FH_INT_STATUS,
992 CSR_FH_INT_RX_MASK);
993 }
994 if (inta & CSR_INT_BIT_RX_PERIODIC) {
995 handled |= CSR_INT_BIT_RX_PERIODIC;
996 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
997 }
998 /* Sending RX interrupt require many steps to be done in the
999 * the device:
1000 * 1- write interrupt to current index in ICT table.
1001 * 2- dma RX frame.
1002 * 3- update RX shared data to indicate last write index.
1003 * 4- send interrupt.
1004 * This could lead to RX race, driver could receive RX interrupt
1005 * but the shared data changes does not reflect this;
1006 * periodic interrupt will detect any dangling Rx activity.
1007 */
1008
1009 /* Disable periodic interrupt; we use it as just a one-shot. */
1010 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1011 CSR_INT_PERIODIC_DIS);
1012 iwl_rx_handle(priv);
1013
1014 /*
1015 * Enable periodic interrupt in 8 msec only if we received
1016 * real RX interrupt (instead of just periodic int), to catch
1017 * any dangling Rx interrupt. If it was just the periodic
1018 * interrupt, there was no dangling Rx activity, and no need
1019 * to extend the periodic interrupt; one-shot is enough.
1020 */
1021 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1022 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1023 CSR_INT_PERIODIC_ENA);
1024
1025 priv->isr_stats.rx++;
1026 }
1027
1028 /* This "Tx" DMA channel is used only for loading uCode */
1029 if (inta & CSR_INT_BIT_FH_TX) {
1030 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1031 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1032 priv->isr_stats.tx++;
1033 handled |= CSR_INT_BIT_FH_TX;
1034 /* Wake up uCode load routine, now that load is complete */
1035 priv->ucode_write_complete = 1;
1036 wake_up_interruptible(&priv->wait_command_queue);
1037 }
1038
1039 if (inta & ~handled) {
1040 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1041 priv->isr_stats.unhandled++;
1042 }
1043
1044 if (inta & ~(priv->inta_mask)) {
1045 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1046 inta & ~priv->inta_mask);
1047 }
1048
1049 /* Re-enable all interrupts */
1050 /* only Re-enable if disabled by irq */
1051 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1052 iwl_enable_interrupts(priv);
1053 /* Re-enable RF_KILL if it occurred */
1054 else if (handled & CSR_INT_BIT_RF_KILL)
1055 iwl_enable_rfkill_int(priv);
1056 }
1057
1058 /*****************************************************************************
1059 *
1060 * sysfs attributes
1061 *
1062 *****************************************************************************/
1063
1064 #ifdef CONFIG_IWLWIFI_DEBUG
1065
1066 /*
1067 * The following adds a new attribute to the sysfs representation
1068 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1069 * used for controlling the debug level.
1070 *
1071 * See the level definitions in iwl for details.
1072 *
1073 * The debug_level being managed using sysfs below is a per device debug
1074 * level that is used instead of the global debug level if it (the per
1075 * device debug level) is set.
1076 */
1077 static ssize_t show_debug_level(struct device *d,
1078 struct device_attribute *attr, char *buf)
1079 {
1080 struct iwl_priv *priv = dev_get_drvdata(d);
1081 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1082 }
1083 static ssize_t store_debug_level(struct device *d,
1084 struct device_attribute *attr,
1085 const char *buf, size_t count)
1086 {
1087 struct iwl_priv *priv = dev_get_drvdata(d);
1088 unsigned long val;
1089 int ret;
1090
1091 ret = strict_strtoul(buf, 0, &val);
1092 if (ret)
1093 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1094 else {
1095 priv->debug_level = val;
1096 if (iwl_alloc_traffic_mem(priv))
1097 IWL_ERR(priv,
1098 "Not enough memory to generate traffic log\n");
1099 }
1100 return strnlen(buf, count);
1101 }
1102
1103 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1104 show_debug_level, store_debug_level);
1105
1106
1107 #endif /* CONFIG_IWLWIFI_DEBUG */
1108
1109
1110 static ssize_t show_temperature(struct device *d,
1111 struct device_attribute *attr, char *buf)
1112 {
1113 struct iwl_priv *priv = dev_get_drvdata(d);
1114
1115 if (!iwl_is_alive(priv))
1116 return -EAGAIN;
1117
1118 return sprintf(buf, "%d\n", priv->temperature);
1119 }
1120
1121 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1122
1123 static ssize_t show_tx_power(struct device *d,
1124 struct device_attribute *attr, char *buf)
1125 {
1126 struct iwl_priv *priv = dev_get_drvdata(d);
1127
1128 if (!iwl_is_ready_rf(priv))
1129 return sprintf(buf, "off\n");
1130 else
1131 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1132 }
1133
1134 static ssize_t store_tx_power(struct device *d,
1135 struct device_attribute *attr,
1136 const char *buf, size_t count)
1137 {
1138 struct iwl_priv *priv = dev_get_drvdata(d);
1139 unsigned long val;
1140 int ret;
1141
1142 ret = strict_strtoul(buf, 10, &val);
1143 if (ret)
1144 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1145 else {
1146 ret = iwl_set_tx_power(priv, val, false);
1147 if (ret)
1148 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1149 ret);
1150 else
1151 ret = count;
1152 }
1153 return ret;
1154 }
1155
1156 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1157
1158 static struct attribute *iwl_sysfs_entries[] = {
1159 &dev_attr_temperature.attr,
1160 &dev_attr_tx_power.attr,
1161 #ifdef CONFIG_IWLWIFI_DEBUG
1162 &dev_attr_debug_level.attr,
1163 #endif
1164 NULL
1165 };
1166
1167 static struct attribute_group iwl_attribute_group = {
1168 .name = NULL, /* put in device directory */
1169 .attrs = iwl_sysfs_entries,
1170 };
1171
1172 /******************************************************************************
1173 *
1174 * uCode download functions
1175 *
1176 ******************************************************************************/
1177
1178 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1179 {
1180 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1181 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1182 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1183 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1184 }
1185
1186 static void iwl_nic_start(struct iwl_priv *priv)
1187 {
1188 /* Remove all resets to allow NIC to operate */
1189 iwl_write32(priv, CSR_RESET, 0);
1190 }
1191
1192 struct iwlagn_ucode_capabilities {
1193 u32 max_probe_length;
1194 u32 standard_phy_calibration_size;
1195 u32 flags;
1196 };
1197
1198 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1199 static int iwl_mac_setup_register(struct iwl_priv *priv,
1200 struct iwlagn_ucode_capabilities *capa);
1201
1202 #define UCODE_EXPERIMENTAL_INDEX 100
1203 #define UCODE_EXPERIMENTAL_TAG "exp"
1204
1205 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1206 {
1207 const char *name_pre = priv->cfg->fw_name_pre;
1208 char tag[8];
1209
1210 if (first) {
1211 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1212 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1213 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1214 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1215 #endif
1216 priv->fw_index = priv->cfg->ucode_api_max;
1217 sprintf(tag, "%d", priv->fw_index);
1218 } else {
1219 priv->fw_index--;
1220 sprintf(tag, "%d", priv->fw_index);
1221 }
1222
1223 if (priv->fw_index < priv->cfg->ucode_api_min) {
1224 IWL_ERR(priv, "no suitable firmware found!\n");
1225 return -ENOENT;
1226 }
1227
1228 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1229
1230 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1231 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1232 ? "EXPERIMENTAL " : "",
1233 priv->firmware_name);
1234
1235 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1236 &priv->pci_dev->dev, GFP_KERNEL, priv,
1237 iwl_ucode_callback);
1238 }
1239
1240 struct iwlagn_firmware_pieces {
1241 const void *inst, *data, *init, *init_data;
1242 size_t inst_size, data_size, init_size, init_data_size;
1243
1244 u32 build;
1245
1246 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1247 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1248 };
1249
1250 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1251 const struct firmware *ucode_raw,
1252 struct iwlagn_firmware_pieces *pieces)
1253 {
1254 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1255 u32 api_ver, hdr_size;
1256 const u8 *src;
1257
1258 priv->ucode_ver = le32_to_cpu(ucode->ver);
1259 api_ver = IWL_UCODE_API(priv->ucode_ver);
1260
1261 switch (api_ver) {
1262 default:
1263 hdr_size = 28;
1264 if (ucode_raw->size < hdr_size) {
1265 IWL_ERR(priv, "File size too small!\n");
1266 return -EINVAL;
1267 }
1268 pieces->build = le32_to_cpu(ucode->u.v2.build);
1269 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1270 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1271 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1272 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1273 src = ucode->u.v2.data;
1274 break;
1275 case 0:
1276 case 1:
1277 case 2:
1278 hdr_size = 24;
1279 if (ucode_raw->size < hdr_size) {
1280 IWL_ERR(priv, "File size too small!\n");
1281 return -EINVAL;
1282 }
1283 pieces->build = 0;
1284 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1285 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1286 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1287 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1288 src = ucode->u.v1.data;
1289 break;
1290 }
1291
1292 /* Verify size of file vs. image size info in file's header */
1293 if (ucode_raw->size != hdr_size + pieces->inst_size +
1294 pieces->data_size + pieces->init_size +
1295 pieces->init_data_size) {
1296
1297 IWL_ERR(priv,
1298 "uCode file size %d does not match expected size\n",
1299 (int)ucode_raw->size);
1300 return -EINVAL;
1301 }
1302
1303 pieces->inst = src;
1304 src += pieces->inst_size;
1305 pieces->data = src;
1306 src += pieces->data_size;
1307 pieces->init = src;
1308 src += pieces->init_size;
1309 pieces->init_data = src;
1310 src += pieces->init_data_size;
1311
1312 return 0;
1313 }
1314
1315 static int iwlagn_wanted_ucode_alternative = 1;
1316
1317 static int iwlagn_load_firmware(struct iwl_priv *priv,
1318 const struct firmware *ucode_raw,
1319 struct iwlagn_firmware_pieces *pieces,
1320 struct iwlagn_ucode_capabilities *capa)
1321 {
1322 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1323 struct iwl_ucode_tlv *tlv;
1324 size_t len = ucode_raw->size;
1325 const u8 *data;
1326 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1327 u64 alternatives;
1328 u32 tlv_len;
1329 enum iwl_ucode_tlv_type tlv_type;
1330 const u8 *tlv_data;
1331
1332 if (len < sizeof(*ucode)) {
1333 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1334 return -EINVAL;
1335 }
1336
1337 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1338 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1339 le32_to_cpu(ucode->magic));
1340 return -EINVAL;
1341 }
1342
1343 /*
1344 * Check which alternatives are present, and "downgrade"
1345 * when the chosen alternative is not present, warning
1346 * the user when that happens. Some files may not have
1347 * any alternatives, so don't warn in that case.
1348 */
1349 alternatives = le64_to_cpu(ucode->alternatives);
1350 tmp = wanted_alternative;
1351 if (wanted_alternative > 63)
1352 wanted_alternative = 63;
1353 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1354 wanted_alternative--;
1355 if (wanted_alternative && wanted_alternative != tmp)
1356 IWL_WARN(priv,
1357 "uCode alternative %d not available, choosing %d\n",
1358 tmp, wanted_alternative);
1359
1360 priv->ucode_ver = le32_to_cpu(ucode->ver);
1361 pieces->build = le32_to_cpu(ucode->build);
1362 data = ucode->data;
1363
1364 len -= sizeof(*ucode);
1365
1366 while (len >= sizeof(*tlv)) {
1367 u16 tlv_alt;
1368
1369 len -= sizeof(*tlv);
1370 tlv = (void *)data;
1371
1372 tlv_len = le32_to_cpu(tlv->length);
1373 tlv_type = le16_to_cpu(tlv->type);
1374 tlv_alt = le16_to_cpu(tlv->alternative);
1375 tlv_data = tlv->data;
1376
1377 if (len < tlv_len) {
1378 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1379 len, tlv_len);
1380 return -EINVAL;
1381 }
1382 len -= ALIGN(tlv_len, 4);
1383 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1384
1385 /*
1386 * Alternative 0 is always valid.
1387 *
1388 * Skip alternative TLVs that are not selected.
1389 */
1390 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1391 continue;
1392
1393 switch (tlv_type) {
1394 case IWL_UCODE_TLV_INST:
1395 pieces->inst = tlv_data;
1396 pieces->inst_size = tlv_len;
1397 break;
1398 case IWL_UCODE_TLV_DATA:
1399 pieces->data = tlv_data;
1400 pieces->data_size = tlv_len;
1401 break;
1402 case IWL_UCODE_TLV_INIT:
1403 pieces->init = tlv_data;
1404 pieces->init_size = tlv_len;
1405 break;
1406 case IWL_UCODE_TLV_INIT_DATA:
1407 pieces->init_data = tlv_data;
1408 pieces->init_data_size = tlv_len;
1409 break;
1410 case IWL_UCODE_TLV_BOOT:
1411 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1412 break;
1413 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1414 if (tlv_len != sizeof(u32))
1415 goto invalid_tlv_len;
1416 capa->max_probe_length =
1417 le32_to_cpup((__le32 *)tlv_data);
1418 break;
1419 case IWL_UCODE_TLV_PAN:
1420 if (tlv_len)
1421 goto invalid_tlv_len;
1422 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1423 break;
1424 case IWL_UCODE_TLV_FLAGS:
1425 /* must be at least one u32 */
1426 if (tlv_len < sizeof(u32))
1427 goto invalid_tlv_len;
1428 /* and a proper number of u32s */
1429 if (tlv_len % sizeof(u32))
1430 goto invalid_tlv_len;
1431 /*
1432 * This driver only reads the first u32 as
1433 * right now no more features are defined,
1434 * if that changes then either the driver
1435 * will not work with the new firmware, or
1436 * it'll not take advantage of new features.
1437 */
1438 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1439 break;
1440 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1441 if (tlv_len != sizeof(u32))
1442 goto invalid_tlv_len;
1443 pieces->init_evtlog_ptr =
1444 le32_to_cpup((__le32 *)tlv_data);
1445 break;
1446 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1447 if (tlv_len != sizeof(u32))
1448 goto invalid_tlv_len;
1449 pieces->init_evtlog_size =
1450 le32_to_cpup((__le32 *)tlv_data);
1451 break;
1452 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1453 if (tlv_len != sizeof(u32))
1454 goto invalid_tlv_len;
1455 pieces->init_errlog_ptr =
1456 le32_to_cpup((__le32 *)tlv_data);
1457 break;
1458 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1459 if (tlv_len != sizeof(u32))
1460 goto invalid_tlv_len;
1461 pieces->inst_evtlog_ptr =
1462 le32_to_cpup((__le32 *)tlv_data);
1463 break;
1464 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1465 if (tlv_len != sizeof(u32))
1466 goto invalid_tlv_len;
1467 pieces->inst_evtlog_size =
1468 le32_to_cpup((__le32 *)tlv_data);
1469 break;
1470 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1471 if (tlv_len != sizeof(u32))
1472 goto invalid_tlv_len;
1473 pieces->inst_errlog_ptr =
1474 le32_to_cpup((__le32 *)tlv_data);
1475 break;
1476 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1477 if (tlv_len)
1478 goto invalid_tlv_len;
1479 priv->enhance_sensitivity_table = true;
1480 break;
1481 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1482 if (tlv_len != sizeof(u32))
1483 goto invalid_tlv_len;
1484 capa->standard_phy_calibration_size =
1485 le32_to_cpup((__le32 *)tlv_data);
1486 break;
1487 default:
1488 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1489 break;
1490 }
1491 }
1492
1493 if (len) {
1494 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1495 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1496 return -EINVAL;
1497 }
1498
1499 return 0;
1500
1501 invalid_tlv_len:
1502 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1503 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1504
1505 return -EINVAL;
1506 }
1507
1508 /**
1509 * iwl_ucode_callback - callback when firmware was loaded
1510 *
1511 * If loaded successfully, copies the firmware into buffers
1512 * for the card to fetch (via DMA).
1513 */
1514 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1515 {
1516 struct iwl_priv *priv = context;
1517 struct iwl_ucode_header *ucode;
1518 int err;
1519 struct iwlagn_firmware_pieces pieces;
1520 const unsigned int api_max = priv->cfg->ucode_api_max;
1521 const unsigned int api_min = priv->cfg->ucode_api_min;
1522 u32 api_ver;
1523 char buildstr[25];
1524 u32 build;
1525 struct iwlagn_ucode_capabilities ucode_capa = {
1526 .max_probe_length = 200,
1527 .standard_phy_calibration_size =
1528 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1529 };
1530
1531 memset(&pieces, 0, sizeof(pieces));
1532
1533 if (!ucode_raw) {
1534 if (priv->fw_index <= priv->cfg->ucode_api_max)
1535 IWL_ERR(priv,
1536 "request for firmware file '%s' failed.\n",
1537 priv->firmware_name);
1538 goto try_again;
1539 }
1540
1541 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1542 priv->firmware_name, ucode_raw->size);
1543
1544 /* Make sure that we got at least the API version number */
1545 if (ucode_raw->size < 4) {
1546 IWL_ERR(priv, "File size way too small!\n");
1547 goto try_again;
1548 }
1549
1550 /* Data from ucode file: header followed by uCode images */
1551 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1552
1553 if (ucode->ver)
1554 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1555 else
1556 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1557 &ucode_capa);
1558
1559 if (err)
1560 goto try_again;
1561
1562 api_ver = IWL_UCODE_API(priv->ucode_ver);
1563 build = pieces.build;
1564
1565 /*
1566 * api_ver should match the api version forming part of the
1567 * firmware filename ... but we don't check for that and only rely
1568 * on the API version read from firmware header from here on forward
1569 */
1570 /* no api version check required for experimental uCode */
1571 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1572 if (api_ver < api_min || api_ver > api_max) {
1573 IWL_ERR(priv,
1574 "Driver unable to support your firmware API. "
1575 "Driver supports v%u, firmware is v%u.\n",
1576 api_max, api_ver);
1577 goto try_again;
1578 }
1579
1580 if (api_ver != api_max)
1581 IWL_ERR(priv,
1582 "Firmware has old API version. Expected v%u, "
1583 "got v%u. New firmware can be obtained "
1584 "from http://www.intellinuxwireless.org.\n",
1585 api_max, api_ver);
1586 }
1587
1588 if (build)
1589 sprintf(buildstr, " build %u%s", build,
1590 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1591 ? " (EXP)" : "");
1592 else
1593 buildstr[0] = '\0';
1594
1595 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1596 IWL_UCODE_MAJOR(priv->ucode_ver),
1597 IWL_UCODE_MINOR(priv->ucode_ver),
1598 IWL_UCODE_API(priv->ucode_ver),
1599 IWL_UCODE_SERIAL(priv->ucode_ver),
1600 buildstr);
1601
1602 snprintf(priv->hw->wiphy->fw_version,
1603 sizeof(priv->hw->wiphy->fw_version),
1604 "%u.%u.%u.%u%s",
1605 IWL_UCODE_MAJOR(priv->ucode_ver),
1606 IWL_UCODE_MINOR(priv->ucode_ver),
1607 IWL_UCODE_API(priv->ucode_ver),
1608 IWL_UCODE_SERIAL(priv->ucode_ver),
1609 buildstr);
1610
1611 /*
1612 * For any of the failures below (before allocating pci memory)
1613 * we will try to load a version with a smaller API -- maybe the
1614 * user just got a corrupted version of the latest API.
1615 */
1616
1617 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1618 priv->ucode_ver);
1619 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1620 pieces.inst_size);
1621 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1622 pieces.data_size);
1623 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1624 pieces.init_size);
1625 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1626 pieces.init_data_size);
1627
1628 /* Verify that uCode images will fit in card's SRAM */
1629 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1630 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1631 pieces.inst_size);
1632 goto try_again;
1633 }
1634
1635 if (pieces.data_size > priv->hw_params.max_data_size) {
1636 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1637 pieces.data_size);
1638 goto try_again;
1639 }
1640
1641 if (pieces.init_size > priv->hw_params.max_inst_size) {
1642 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1643 pieces.init_size);
1644 goto try_again;
1645 }
1646
1647 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1648 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1649 pieces.init_data_size);
1650 goto try_again;
1651 }
1652
1653 /* Allocate ucode buffers for card's bus-master loading ... */
1654
1655 /* Runtime instructions and 2 copies of data:
1656 * 1) unmodified from disk
1657 * 2) backup cache for save/restore during power-downs */
1658 priv->ucode_code.len = pieces.inst_size;
1659 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1660
1661 priv->ucode_data.len = pieces.data_size;
1662 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1663
1664 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1665 goto err_pci_alloc;
1666
1667 /* Initialization instructions and data */
1668 if (pieces.init_size && pieces.init_data_size) {
1669 priv->ucode_init.len = pieces.init_size;
1670 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1671
1672 priv->ucode_init_data.len = pieces.init_data_size;
1673 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1674
1675 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1676 goto err_pci_alloc;
1677 }
1678
1679 /* Now that we can no longer fail, copy information */
1680
1681 /*
1682 * The (size - 16) / 12 formula is based on the information recorded
1683 * for each event, which is of mode 1 (including timestamp) for all
1684 * new microcodes that include this information.
1685 */
1686 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1687 if (pieces.init_evtlog_size)
1688 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1689 else
1690 priv->_agn.init_evtlog_size =
1691 priv->cfg->base_params->max_event_log_size;
1692 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1693 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1694 if (pieces.inst_evtlog_size)
1695 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1696 else
1697 priv->_agn.inst_evtlog_size =
1698 priv->cfg->base_params->max_event_log_size;
1699 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1700
1701 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1702 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1703 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1704 } else
1705 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1706
1707 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1708 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1709 else
1710 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1711
1712 /* Copy images into buffers for card's bus-master reads ... */
1713
1714 /* Runtime instructions (first block of data in file) */
1715 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1716 pieces.inst_size);
1717 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1718
1719 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1720 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1721
1722 /*
1723 * Runtime data
1724 * NOTE: Copy into backup buffer will be done in iwl_up()
1725 */
1726 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1727 pieces.data_size);
1728 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1729
1730 /* Initialization instructions */
1731 if (pieces.init_size) {
1732 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1733 pieces.init_size);
1734 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1735 }
1736
1737 /* Initialization data */
1738 if (pieces.init_data_size) {
1739 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1740 pieces.init_data_size);
1741 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1742 pieces.init_data_size);
1743 }
1744
1745 /*
1746 * figure out the offset of chain noise reset and gain commands
1747 * base on the size of standard phy calibration commands table size
1748 */
1749 if (ucode_capa.standard_phy_calibration_size >
1750 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1751 ucode_capa.standard_phy_calibration_size =
1752 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1753
1754 priv->_agn.phy_calib_chain_noise_reset_cmd =
1755 ucode_capa.standard_phy_calibration_size;
1756 priv->_agn.phy_calib_chain_noise_gain_cmd =
1757 ucode_capa.standard_phy_calibration_size + 1;
1758
1759 /**************************************************
1760 * This is still part of probe() in a sense...
1761 *
1762 * 9. Setup and register with mac80211 and debugfs
1763 **************************************************/
1764 err = iwl_mac_setup_register(priv, &ucode_capa);
1765 if (err)
1766 goto out_unbind;
1767
1768 err = iwl_dbgfs_register(priv, DRV_NAME);
1769 if (err)
1770 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1771
1772 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1773 &iwl_attribute_group);
1774 if (err) {
1775 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1776 goto out_unbind;
1777 }
1778
1779 /* We have our copies now, allow OS release its copies */
1780 release_firmware(ucode_raw);
1781 complete(&priv->_agn.firmware_loading_complete);
1782 return;
1783
1784 try_again:
1785 /* try next, if any */
1786 if (iwl_request_firmware(priv, false))
1787 goto out_unbind;
1788 release_firmware(ucode_raw);
1789 return;
1790
1791 err_pci_alloc:
1792 IWL_ERR(priv, "failed to allocate pci memory\n");
1793 iwl_dealloc_ucode_pci(priv);
1794 out_unbind:
1795 complete(&priv->_agn.firmware_loading_complete);
1796 device_release_driver(&priv->pci_dev->dev);
1797 release_firmware(ucode_raw);
1798 }
1799
1800 static const char *desc_lookup_text[] = {
1801 "OK",
1802 "FAIL",
1803 "BAD_PARAM",
1804 "BAD_CHECKSUM",
1805 "NMI_INTERRUPT_WDG",
1806 "SYSASSERT",
1807 "FATAL_ERROR",
1808 "BAD_COMMAND",
1809 "HW_ERROR_TUNE_LOCK",
1810 "HW_ERROR_TEMPERATURE",
1811 "ILLEGAL_CHAN_FREQ",
1812 "VCC_NOT_STABLE",
1813 "FH_ERROR",
1814 "NMI_INTERRUPT_HOST",
1815 "NMI_INTERRUPT_ACTION_PT",
1816 "NMI_INTERRUPT_UNKNOWN",
1817 "UCODE_VERSION_MISMATCH",
1818 "HW_ERROR_ABS_LOCK",
1819 "HW_ERROR_CAL_LOCK_FAIL",
1820 "NMI_INTERRUPT_INST_ACTION_PT",
1821 "NMI_INTERRUPT_DATA_ACTION_PT",
1822 "NMI_TRM_HW_ER",
1823 "NMI_INTERRUPT_TRM",
1824 "NMI_INTERRUPT_BREAK_POINT"
1825 "DEBUG_0",
1826 "DEBUG_1",
1827 "DEBUG_2",
1828 "DEBUG_3",
1829 };
1830
1831 static struct { char *name; u8 num; } advanced_lookup[] = {
1832 { "NMI_INTERRUPT_WDG", 0x34 },
1833 { "SYSASSERT", 0x35 },
1834 { "UCODE_VERSION_MISMATCH", 0x37 },
1835 { "BAD_COMMAND", 0x38 },
1836 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1837 { "FATAL_ERROR", 0x3D },
1838 { "NMI_TRM_HW_ERR", 0x46 },
1839 { "NMI_INTERRUPT_TRM", 0x4C },
1840 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1841 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1842 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1843 { "NMI_INTERRUPT_HOST", 0x66 },
1844 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1845 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1846 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1847 { "ADVANCED_SYSASSERT", 0 },
1848 };
1849
1850 static const char *desc_lookup(u32 num)
1851 {
1852 int i;
1853 int max = ARRAY_SIZE(desc_lookup_text);
1854
1855 if (num < max)
1856 return desc_lookup_text[num];
1857
1858 max = ARRAY_SIZE(advanced_lookup) - 1;
1859 for (i = 0; i < max; i++) {
1860 if (advanced_lookup[i].num == num)
1861 break;;
1862 }
1863 return advanced_lookup[i].name;
1864 }
1865
1866 #define ERROR_START_OFFSET (1 * sizeof(u32))
1867 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1868
1869 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1870 {
1871 u32 data2, line;
1872 u32 desc, time, count, base, data1;
1873 u32 blink1, blink2, ilink1, ilink2;
1874 u32 pc, hcmd;
1875
1876 base = priv->device_pointers.error_event_table;
1877 if (priv->ucode_type == UCODE_INIT) {
1878 if (!base)
1879 base = priv->_agn.init_errlog_ptr;
1880 } else {
1881 if (!base)
1882 base = priv->_agn.inst_errlog_ptr;
1883 }
1884
1885 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1886 IWL_ERR(priv,
1887 "Not valid error log pointer 0x%08X for %s uCode\n",
1888 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1889 return;
1890 }
1891
1892 count = iwl_read_targ_mem(priv, base);
1893
1894 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1895 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1896 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1897 priv->status, count);
1898 }
1899
1900 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1901 priv->isr_stats.err_code = desc;
1902 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1903 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1904 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1905 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1906 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1907 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1908 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1909 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1910 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1911 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1912
1913 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1914 blink1, blink2, ilink1, ilink2);
1915
1916 IWL_ERR(priv, "Desc Time "
1917 "data1 data2 line\n");
1918 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1919 desc_lookup(desc), desc, time, data1, data2, line);
1920 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1921 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1922 pc, blink1, blink2, ilink1, ilink2, hcmd);
1923 }
1924
1925 #define EVENT_START_OFFSET (4 * sizeof(u32))
1926
1927 /**
1928 * iwl_print_event_log - Dump error event log to syslog
1929 *
1930 */
1931 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1932 u32 num_events, u32 mode,
1933 int pos, char **buf, size_t bufsz)
1934 {
1935 u32 i;
1936 u32 base; /* SRAM byte address of event log header */
1937 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1938 u32 ptr; /* SRAM byte address of log data */
1939 u32 ev, time, data; /* event log data */
1940 unsigned long reg_flags;
1941
1942 if (num_events == 0)
1943 return pos;
1944
1945 base = priv->device_pointers.log_event_table;
1946 if (priv->ucode_type == UCODE_INIT) {
1947 if (!base)
1948 base = priv->_agn.init_evtlog_ptr;
1949 } else {
1950 if (!base)
1951 base = priv->_agn.inst_evtlog_ptr;
1952 }
1953
1954 if (mode == 0)
1955 event_size = 2 * sizeof(u32);
1956 else
1957 event_size = 3 * sizeof(u32);
1958
1959 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1960
1961 /* Make sure device is powered up for SRAM reads */
1962 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1963 iwl_grab_nic_access(priv);
1964
1965 /* Set starting address; reads will auto-increment */
1966 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1967 rmb();
1968
1969 /* "time" is actually "data" for mode 0 (no timestamp).
1970 * place event id # at far right for easier visual parsing. */
1971 for (i = 0; i < num_events; i++) {
1972 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1973 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1974 if (mode == 0) {
1975 /* data, ev */
1976 if (bufsz) {
1977 pos += scnprintf(*buf + pos, bufsz - pos,
1978 "EVT_LOG:0x%08x:%04u\n",
1979 time, ev);
1980 } else {
1981 trace_iwlwifi_dev_ucode_event(priv, 0,
1982 time, ev);
1983 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1984 time, ev);
1985 }
1986 } else {
1987 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1988 if (bufsz) {
1989 pos += scnprintf(*buf + pos, bufsz - pos,
1990 "EVT_LOGT:%010u:0x%08x:%04u\n",
1991 time, data, ev);
1992 } else {
1993 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1994 time, data, ev);
1995 trace_iwlwifi_dev_ucode_event(priv, time,
1996 data, ev);
1997 }
1998 }
1999 }
2000
2001 /* Allow device to power down */
2002 iwl_release_nic_access(priv);
2003 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2004 return pos;
2005 }
2006
2007 /**
2008 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2009 */
2010 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2011 u32 num_wraps, u32 next_entry,
2012 u32 size, u32 mode,
2013 int pos, char **buf, size_t bufsz)
2014 {
2015 /*
2016 * display the newest DEFAULT_LOG_ENTRIES entries
2017 * i.e the entries just before the next ont that uCode would fill.
2018 */
2019 if (num_wraps) {
2020 if (next_entry < size) {
2021 pos = iwl_print_event_log(priv,
2022 capacity - (size - next_entry),
2023 size - next_entry, mode,
2024 pos, buf, bufsz);
2025 pos = iwl_print_event_log(priv, 0,
2026 next_entry, mode,
2027 pos, buf, bufsz);
2028 } else
2029 pos = iwl_print_event_log(priv, next_entry - size,
2030 size, mode, pos, buf, bufsz);
2031 } else {
2032 if (next_entry < size) {
2033 pos = iwl_print_event_log(priv, 0, next_entry,
2034 mode, pos, buf, bufsz);
2035 } else {
2036 pos = iwl_print_event_log(priv, next_entry - size,
2037 size, mode, pos, buf, bufsz);
2038 }
2039 }
2040 return pos;
2041 }
2042
2043 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2044
2045 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2046 char **buf, bool display)
2047 {
2048 u32 base; /* SRAM byte address of event log header */
2049 u32 capacity; /* event log capacity in # entries */
2050 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2051 u32 num_wraps; /* # times uCode wrapped to top of log */
2052 u32 next_entry; /* index of next entry to be written by uCode */
2053 u32 size; /* # entries that we'll print */
2054 u32 logsize;
2055 int pos = 0;
2056 size_t bufsz = 0;
2057
2058 base = priv->device_pointers.log_event_table;
2059 if (priv->ucode_type == UCODE_INIT) {
2060 logsize = priv->_agn.init_evtlog_size;
2061 if (!base)
2062 base = priv->_agn.init_evtlog_ptr;
2063 } else {
2064 logsize = priv->_agn.inst_evtlog_size;
2065 if (!base)
2066 base = priv->_agn.inst_evtlog_ptr;
2067 }
2068
2069 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2070 IWL_ERR(priv,
2071 "Invalid event log pointer 0x%08X for %s uCode\n",
2072 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2073 return -EINVAL;
2074 }
2075
2076 /* event log header */
2077 capacity = iwl_read_targ_mem(priv, base);
2078 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2079 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2080 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2081
2082 if (capacity > logsize) {
2083 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2084 capacity, logsize);
2085 capacity = logsize;
2086 }
2087
2088 if (next_entry > logsize) {
2089 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2090 next_entry, logsize);
2091 next_entry = logsize;
2092 }
2093
2094 size = num_wraps ? capacity : next_entry;
2095
2096 /* bail out if nothing in log */
2097 if (size == 0) {
2098 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2099 return pos;
2100 }
2101
2102 /* enable/disable bt channel inhibition */
2103 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2104
2105 #ifdef CONFIG_IWLWIFI_DEBUG
2106 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2107 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2108 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2109 #else
2110 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2111 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2112 #endif
2113 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2114 size);
2115
2116 #ifdef CONFIG_IWLWIFI_DEBUG
2117 if (display) {
2118 if (full_log)
2119 bufsz = capacity * 48;
2120 else
2121 bufsz = size * 48;
2122 *buf = kmalloc(bufsz, GFP_KERNEL);
2123 if (!*buf)
2124 return -ENOMEM;
2125 }
2126 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2127 /*
2128 * if uCode has wrapped back to top of log,
2129 * start at the oldest entry,
2130 * i.e the next one that uCode would fill.
2131 */
2132 if (num_wraps)
2133 pos = iwl_print_event_log(priv, next_entry,
2134 capacity - next_entry, mode,
2135 pos, buf, bufsz);
2136 /* (then/else) start at top of log */
2137 pos = iwl_print_event_log(priv, 0,
2138 next_entry, mode, pos, buf, bufsz);
2139 } else
2140 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2141 next_entry, size, mode,
2142 pos, buf, bufsz);
2143 #else
2144 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2145 next_entry, size, mode,
2146 pos, buf, bufsz);
2147 #endif
2148 return pos;
2149 }
2150
2151 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2152 {
2153 struct iwl_ct_kill_config cmd;
2154 struct iwl_ct_kill_throttling_config adv_cmd;
2155 unsigned long flags;
2156 int ret = 0;
2157
2158 spin_lock_irqsave(&priv->lock, flags);
2159 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2160 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2161 spin_unlock_irqrestore(&priv->lock, flags);
2162 priv->thermal_throttle.ct_kill_toggle = false;
2163
2164 if (priv->cfg->base_params->support_ct_kill_exit) {
2165 adv_cmd.critical_temperature_enter =
2166 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2167 adv_cmd.critical_temperature_exit =
2168 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2169
2170 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2171 sizeof(adv_cmd), &adv_cmd);
2172 if (ret)
2173 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2174 else
2175 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2176 "succeeded, "
2177 "critical temperature enter is %d,"
2178 "exit is %d\n",
2179 priv->hw_params.ct_kill_threshold,
2180 priv->hw_params.ct_kill_exit_threshold);
2181 } else {
2182 cmd.critical_temperature_R =
2183 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2184
2185 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2186 sizeof(cmd), &cmd);
2187 if (ret)
2188 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2189 else
2190 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2191 "succeeded, "
2192 "critical temperature is %d\n",
2193 priv->hw_params.ct_kill_threshold);
2194 }
2195 }
2196
2197 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2198 {
2199 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2200 struct iwl_host_cmd cmd = {
2201 .id = CALIBRATION_CFG_CMD,
2202 .len = sizeof(struct iwl_calib_cfg_cmd),
2203 .data = &calib_cfg_cmd,
2204 };
2205
2206 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2207 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2208 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2209
2210 return iwl_send_cmd(priv, &cmd);
2211 }
2212
2213
2214 /**
2215 * iwl_alive_start - called after REPLY_ALIVE notification received
2216 * from protocol/runtime uCode (initialization uCode's
2217 * Alive gets handled by iwl_init_alive_start()).
2218 */
2219 static void iwl_alive_start(struct iwl_priv *priv)
2220 {
2221 int ret = 0;
2222 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2223
2224 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2225
2226 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2227 * This is a paranoid check, because we would not have gotten the
2228 * "runtime" alive if code weren't properly loaded. */
2229 if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2230 /* Runtime instruction load was bad;
2231 * take it all the way back down so we can try again */
2232 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2233 goto restart;
2234 }
2235
2236 ret = iwlagn_alive_notify(priv);
2237 if (ret) {
2238 IWL_WARN(priv,
2239 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2240 goto restart;
2241 }
2242
2243
2244 /* After the ALIVE response, we can send host commands to the uCode */
2245 set_bit(STATUS_ALIVE, &priv->status);
2246
2247 /* Enable watchdog to monitor the driver tx queues */
2248 iwl_setup_watchdog(priv);
2249
2250 if (iwl_is_rfkill(priv))
2251 return;
2252
2253 /* download priority table before any calibration request */
2254 if (priv->cfg->bt_params &&
2255 priv->cfg->bt_params->advanced_bt_coexist) {
2256 /* Configure Bluetooth device coexistence support */
2257 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2258 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2259 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2260 priv->cfg->ops->hcmd->send_bt_config(priv);
2261 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2262 iwlagn_send_prio_tbl(priv);
2263
2264 /* FIXME: w/a to force change uCode BT state machine */
2265 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2266 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2267 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2268 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2269 }
2270 if (priv->hw_params.calib_rt_cfg)
2271 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2272
2273 ieee80211_wake_queues(priv->hw);
2274
2275 priv->active_rate = IWL_RATES_MASK;
2276
2277 /* Configure Tx antenna selection based on H/W config */
2278 if (priv->cfg->ops->hcmd->set_tx_ant)
2279 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2280
2281 if (iwl_is_associated_ctx(ctx)) {
2282 struct iwl_rxon_cmd *active_rxon =
2283 (struct iwl_rxon_cmd *)&ctx->active;
2284 /* apply any changes in staging */
2285 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2286 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2287 } else {
2288 struct iwl_rxon_context *tmp;
2289 /* Initialize our rx_config data */
2290 for_each_context(priv, tmp)
2291 iwl_connection_init_rx_config(priv, tmp);
2292
2293 if (priv->cfg->ops->hcmd->set_rxon_chain)
2294 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2295 }
2296
2297 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2298 !priv->cfg->bt_params->advanced_bt_coexist)) {
2299 /*
2300 * default is 2-wire BT coexexistence support
2301 */
2302 priv->cfg->ops->hcmd->send_bt_config(priv);
2303 }
2304
2305 iwl_reset_run_time_calib(priv);
2306
2307 set_bit(STATUS_READY, &priv->status);
2308
2309 /* Configure the adapter for unassociated operation */
2310 iwlcore_commit_rxon(priv, ctx);
2311
2312 /* At this point, the NIC is initialized and operational */
2313 iwl_rf_kill_ct_config(priv);
2314
2315 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2316 wake_up_interruptible(&priv->wait_command_queue);
2317
2318 iwl_power_update_mode(priv, true);
2319 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2320
2321
2322 return;
2323
2324 restart:
2325 queue_work(priv->workqueue, &priv->restart);
2326 }
2327
2328 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2329
2330 static void __iwl_down(struct iwl_priv *priv)
2331 {
2332 unsigned long flags;
2333 int exit_pending;
2334
2335 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2336
2337 iwl_scan_cancel_timeout(priv, 200);
2338
2339 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2340
2341 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2342 * to prevent rearm timer */
2343 del_timer_sync(&priv->watchdog);
2344
2345 iwl_clear_ucode_stations(priv, NULL);
2346 iwl_dealloc_bcast_stations(priv);
2347 iwl_clear_driver_stations(priv);
2348
2349 /* reset BT coex data */
2350 priv->bt_status = 0;
2351 if (priv->cfg->bt_params)
2352 priv->bt_traffic_load =
2353 priv->cfg->bt_params->bt_init_traffic_load;
2354 else
2355 priv->bt_traffic_load = 0;
2356 priv->bt_full_concurrent = false;
2357 priv->bt_ci_compliance = 0;
2358
2359 /* Wipe out the EXIT_PENDING status bit if we are not actually
2360 * exiting the module */
2361 if (!exit_pending)
2362 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2363
2364 /* stop and reset the on-board processor */
2365 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2366
2367 /* tell the device to stop sending interrupts */
2368 spin_lock_irqsave(&priv->lock, flags);
2369 iwl_disable_interrupts(priv);
2370 spin_unlock_irqrestore(&priv->lock, flags);
2371 iwl_synchronize_irq(priv);
2372
2373 if (priv->mac80211_registered)
2374 ieee80211_stop_queues(priv->hw);
2375
2376 /* If we have not previously called iwl_init() then
2377 * clear all bits but the RF Kill bit and return */
2378 if (!iwl_is_init(priv)) {
2379 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2380 STATUS_RF_KILL_HW |
2381 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2382 STATUS_GEO_CONFIGURED |
2383 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2384 STATUS_EXIT_PENDING;
2385 goto exit;
2386 }
2387
2388 /* ...otherwise clear out all the status bits but the RF Kill
2389 * bit and continue taking the NIC down. */
2390 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2391 STATUS_RF_KILL_HW |
2392 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2393 STATUS_GEO_CONFIGURED |
2394 test_bit(STATUS_FW_ERROR, &priv->status) <<
2395 STATUS_FW_ERROR |
2396 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2397 STATUS_EXIT_PENDING;
2398
2399 /* device going down, Stop using ICT table */
2400 iwl_disable_ict(priv);
2401
2402 iwlagn_txq_ctx_stop(priv);
2403 iwlagn_rxq_stop(priv);
2404
2405 /* Power-down device's busmaster DMA clocks */
2406 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2407 udelay(5);
2408
2409 /* Make sure (redundant) we've released our request to stay awake */
2410 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2411
2412 /* Stop the device, and put it in low power state */
2413 iwl_apm_stop(priv);
2414
2415 exit:
2416 dev_kfree_skb(priv->beacon_skb);
2417 priv->beacon_skb = NULL;
2418
2419 /* clear out any free frames */
2420 iwl_clear_free_frames(priv);
2421 }
2422
2423 static void iwl_down(struct iwl_priv *priv)
2424 {
2425 mutex_lock(&priv->mutex);
2426 __iwl_down(priv);
2427 mutex_unlock(&priv->mutex);
2428
2429 iwl_cancel_deferred_work(priv);
2430 }
2431
2432 #define HW_READY_TIMEOUT (50)
2433
2434 static int iwl_set_hw_ready(struct iwl_priv *priv)
2435 {
2436 int ret = 0;
2437
2438 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2439 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2440
2441 /* See if we got it */
2442 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2443 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2444 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2445 HW_READY_TIMEOUT);
2446 if (ret != -ETIMEDOUT)
2447 priv->hw_ready = true;
2448 else
2449 priv->hw_ready = false;
2450
2451 IWL_DEBUG_INFO(priv, "hardware %s\n",
2452 (priv->hw_ready == 1) ? "ready" : "not ready");
2453 return ret;
2454 }
2455
2456 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2457 {
2458 int ret = 0;
2459
2460 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2461
2462 ret = iwl_set_hw_ready(priv);
2463 if (priv->hw_ready)
2464 return ret;
2465
2466 /* If HW is not ready, prepare the conditions to check again */
2467 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2468 CSR_HW_IF_CONFIG_REG_PREPARE);
2469
2470 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2471 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2472 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2473
2474 /* HW should be ready by now, check again. */
2475 if (ret != -ETIMEDOUT)
2476 iwl_set_hw_ready(priv);
2477
2478 return ret;
2479 }
2480
2481 #define MAX_HW_RESTARTS 5
2482
2483 static int __iwl_up(struct iwl_priv *priv)
2484 {
2485 struct iwl_rxon_context *ctx;
2486 int i;
2487 int ret;
2488
2489 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2490 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2491 return -EIO;
2492 }
2493
2494 for_each_context(priv, ctx) {
2495 ret = iwlagn_alloc_bcast_station(priv, ctx);
2496 if (ret) {
2497 iwl_dealloc_bcast_stations(priv);
2498 return ret;
2499 }
2500 }
2501
2502 iwl_prepare_card_hw(priv);
2503
2504 if (!priv->hw_ready) {
2505 IWL_WARN(priv, "Exit HW not ready\n");
2506 return -EIO;
2507 }
2508
2509 /* If platform's RF_KILL switch is NOT set to KILL */
2510 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2511 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2512 else
2513 set_bit(STATUS_RF_KILL_HW, &priv->status);
2514
2515 if (iwl_is_rfkill(priv)) {
2516 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2517
2518 iwl_enable_interrupts(priv);
2519 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2520 return 0;
2521 }
2522
2523 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2524
2525 ret = iwlagn_hw_nic_init(priv);
2526 if (ret) {
2527 IWL_ERR(priv, "Unable to init nic\n");
2528 return ret;
2529 }
2530
2531 /* make sure rfkill handshake bits are cleared */
2532 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2533 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2534 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2535
2536 /* clear (again), then enable host interrupts */
2537 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2538 iwl_enable_interrupts(priv);
2539
2540 /* really make sure rfkill handshake bits are cleared */
2541 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2542 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2543
2544 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2545
2546 /* load bootstrap state machine,
2547 * load bootstrap program into processor's memory,
2548 * prepare to load the "initialize" uCode */
2549 ret = iwlagn_load_ucode(priv);
2550
2551 if (ret) {
2552 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2553 ret);
2554 continue;
2555 }
2556
2557 /* start card; "initialize" will load runtime ucode */
2558 iwl_nic_start(priv);
2559
2560 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2561
2562 return 0;
2563 }
2564
2565 set_bit(STATUS_EXIT_PENDING, &priv->status);
2566 __iwl_down(priv);
2567 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2568
2569 /* tried to restart and config the device for as long as our
2570 * patience could withstand */
2571 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2572 return -EIO;
2573 }
2574
2575
2576 /*****************************************************************************
2577 *
2578 * Workqueue callbacks
2579 *
2580 *****************************************************************************/
2581
2582 static void iwl_bg_init_alive_start(struct work_struct *data)
2583 {
2584 struct iwl_priv *priv =
2585 container_of(data, struct iwl_priv, init_alive_start.work);
2586
2587 mutex_lock(&priv->mutex);
2588
2589 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2590 mutex_unlock(&priv->mutex);
2591 return;
2592 }
2593
2594 iwlagn_init_alive_start(priv);
2595 mutex_unlock(&priv->mutex);
2596 }
2597
2598 static void iwl_bg_alive_start(struct work_struct *data)
2599 {
2600 struct iwl_priv *priv =
2601 container_of(data, struct iwl_priv, alive_start.work);
2602
2603 mutex_lock(&priv->mutex);
2604 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2605 goto unlock;
2606
2607 /* enable dram interrupt */
2608 iwl_reset_ict(priv);
2609
2610 iwl_alive_start(priv);
2611 unlock:
2612 mutex_unlock(&priv->mutex);
2613 }
2614
2615 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2616 {
2617 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2618 run_time_calib_work);
2619
2620 mutex_lock(&priv->mutex);
2621
2622 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2623 test_bit(STATUS_SCANNING, &priv->status)) {
2624 mutex_unlock(&priv->mutex);
2625 return;
2626 }
2627
2628 if (priv->start_calib) {
2629 iwl_chain_noise_calibration(priv);
2630 iwl_sensitivity_calibration(priv);
2631 }
2632
2633 mutex_unlock(&priv->mutex);
2634 }
2635
2636 static void iwl_bg_restart(struct work_struct *data)
2637 {
2638 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2639
2640 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2641 return;
2642
2643 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2644 struct iwl_rxon_context *ctx;
2645 bool bt_full_concurrent;
2646 u8 bt_ci_compliance;
2647 u8 bt_load;
2648 u8 bt_status;
2649
2650 mutex_lock(&priv->mutex);
2651 for_each_context(priv, ctx)
2652 ctx->vif = NULL;
2653 priv->is_open = 0;
2654
2655 /*
2656 * __iwl_down() will clear the BT status variables,
2657 * which is correct, but when we restart we really
2658 * want to keep them so restore them afterwards.
2659 *
2660 * The restart process will later pick them up and
2661 * re-configure the hw when we reconfigure the BT
2662 * command.
2663 */
2664 bt_full_concurrent = priv->bt_full_concurrent;
2665 bt_ci_compliance = priv->bt_ci_compliance;
2666 bt_load = priv->bt_traffic_load;
2667 bt_status = priv->bt_status;
2668
2669 __iwl_down(priv);
2670
2671 priv->bt_full_concurrent = bt_full_concurrent;
2672 priv->bt_ci_compliance = bt_ci_compliance;
2673 priv->bt_traffic_load = bt_load;
2674 priv->bt_status = bt_status;
2675
2676 mutex_unlock(&priv->mutex);
2677 iwl_cancel_deferred_work(priv);
2678 ieee80211_restart_hw(priv->hw);
2679 } else {
2680 iwl_down(priv);
2681
2682 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2683 return;
2684
2685 mutex_lock(&priv->mutex);
2686 __iwl_up(priv);
2687 mutex_unlock(&priv->mutex);
2688 }
2689 }
2690
2691 static void iwl_bg_rx_replenish(struct work_struct *data)
2692 {
2693 struct iwl_priv *priv =
2694 container_of(data, struct iwl_priv, rx_replenish);
2695
2696 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2697 return;
2698
2699 mutex_lock(&priv->mutex);
2700 iwlagn_rx_replenish(priv);
2701 mutex_unlock(&priv->mutex);
2702 }
2703
2704 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2705 struct ieee80211_channel *chan,
2706 enum nl80211_channel_type channel_type,
2707 unsigned int wait)
2708 {
2709 struct iwl_priv *priv = hw->priv;
2710 int ret;
2711
2712 /* Not supported if we don't have PAN */
2713 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2714 ret = -EOPNOTSUPP;
2715 goto free;
2716 }
2717
2718 /* Not supported on pre-P2P firmware */
2719 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2720 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2721 ret = -EOPNOTSUPP;
2722 goto free;
2723 }
2724
2725 mutex_lock(&priv->mutex);
2726
2727 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2728 /*
2729 * If the PAN context is free, use the normal
2730 * way of doing remain-on-channel offload + TX.
2731 */
2732 ret = 1;
2733 goto out;
2734 }
2735
2736 /* TODO: queue up if scanning? */
2737 if (test_bit(STATUS_SCANNING, &priv->status) ||
2738 priv->_agn.offchan_tx_skb) {
2739 ret = -EBUSY;
2740 goto out;
2741 }
2742
2743 /*
2744 * max_scan_ie_len doesn't include the blank SSID or the header,
2745 * so need to add that again here.
2746 */
2747 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2748 ret = -ENOBUFS;
2749 goto out;
2750 }
2751
2752 priv->_agn.offchan_tx_skb = skb;
2753 priv->_agn.offchan_tx_timeout = wait;
2754 priv->_agn.offchan_tx_chan = chan;
2755
2756 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2757 IWL_SCAN_OFFCH_TX, chan->band);
2758 if (ret)
2759 priv->_agn.offchan_tx_skb = NULL;
2760 out:
2761 mutex_unlock(&priv->mutex);
2762 free:
2763 if (ret < 0)
2764 kfree_skb(skb);
2765
2766 return ret;
2767 }
2768
2769 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2770 {
2771 struct iwl_priv *priv = hw->priv;
2772 int ret;
2773
2774 mutex_lock(&priv->mutex);
2775
2776 if (!priv->_agn.offchan_tx_skb) {
2777 ret = -EINVAL;
2778 goto unlock;
2779 }
2780
2781 priv->_agn.offchan_tx_skb = NULL;
2782
2783 ret = iwl_scan_cancel_timeout(priv, 200);
2784 if (ret)
2785 ret = -EIO;
2786 unlock:
2787 mutex_unlock(&priv->mutex);
2788
2789 return ret;
2790 }
2791
2792 /*****************************************************************************
2793 *
2794 * mac80211 entry point functions
2795 *
2796 *****************************************************************************/
2797
2798 #define UCODE_READY_TIMEOUT (4 * HZ)
2799
2800 /*
2801 * Not a mac80211 entry point function, but it fits in with all the
2802 * other mac80211 functions grouped here.
2803 */
2804 static int iwl_mac_setup_register(struct iwl_priv *priv,
2805 struct iwlagn_ucode_capabilities *capa)
2806 {
2807 int ret;
2808 struct ieee80211_hw *hw = priv->hw;
2809 struct iwl_rxon_context *ctx;
2810
2811 hw->rate_control_algorithm = "iwl-agn-rs";
2812
2813 /* Tell mac80211 our characteristics */
2814 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2815 IEEE80211_HW_AMPDU_AGGREGATION |
2816 IEEE80211_HW_NEED_DTIM_PERIOD |
2817 IEEE80211_HW_SPECTRUM_MGMT |
2818 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2819
2820 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2821
2822 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2823 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2824
2825 if (priv->cfg->sku & IWL_SKU_N)
2826 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2827 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2828
2829 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2830 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2831
2832 hw->sta_data_size = sizeof(struct iwl_station_priv);
2833 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2834
2835 for_each_context(priv, ctx) {
2836 hw->wiphy->interface_modes |= ctx->interface_modes;
2837 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2838 }
2839
2840 hw->wiphy->max_remain_on_channel_duration = 1000;
2841
2842 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2843 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2844 WIPHY_FLAG_IBSS_RSN;
2845
2846 /*
2847 * For now, disable PS by default because it affects
2848 * RX performance significantly.
2849 */
2850 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2851
2852 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2853 /* we create the 802.11 header and a zero-length SSID element */
2854 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2855
2856 /* Default value; 4 EDCA QOS priorities */
2857 hw->queues = 4;
2858
2859 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2860
2861 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2862 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2863 &priv->bands[IEEE80211_BAND_2GHZ];
2864 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2865 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2866 &priv->bands[IEEE80211_BAND_5GHZ];
2867
2868 iwl_leds_init(priv);
2869
2870 ret = ieee80211_register_hw(priv->hw);
2871 if (ret) {
2872 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2873 return ret;
2874 }
2875 priv->mac80211_registered = 1;
2876
2877 return 0;
2878 }
2879
2880
2881 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2882 {
2883 struct iwl_priv *priv = hw->priv;
2884 int ret;
2885
2886 IWL_DEBUG_MAC80211(priv, "enter\n");
2887
2888 /* we should be verifying the device is ready to be opened */
2889 mutex_lock(&priv->mutex);
2890 ret = __iwl_up(priv);
2891 mutex_unlock(&priv->mutex);
2892
2893 if (ret)
2894 return ret;
2895
2896 if (iwl_is_rfkill(priv))
2897 goto out;
2898
2899 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2900
2901 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2902 * mac80211 will not be run successfully. */
2903 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2904 test_bit(STATUS_READY, &priv->status),
2905 UCODE_READY_TIMEOUT);
2906 if (!ret) {
2907 if (!test_bit(STATUS_READY, &priv->status)) {
2908 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2909 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2910 return -ETIMEDOUT;
2911 }
2912 }
2913
2914 iwlagn_led_enable(priv);
2915
2916 out:
2917 priv->is_open = 1;
2918 IWL_DEBUG_MAC80211(priv, "leave\n");
2919 return 0;
2920 }
2921
2922 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2923 {
2924 struct iwl_priv *priv = hw->priv;
2925
2926 IWL_DEBUG_MAC80211(priv, "enter\n");
2927
2928 if (!priv->is_open)
2929 return;
2930
2931 priv->is_open = 0;
2932
2933 iwl_down(priv);
2934
2935 flush_workqueue(priv->workqueue);
2936
2937 /* User space software may expect getting rfkill changes
2938 * even if interface is down */
2939 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2940 iwl_enable_rfkill_int(priv);
2941
2942 IWL_DEBUG_MAC80211(priv, "leave\n");
2943 }
2944
2945 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2946 {
2947 struct iwl_priv *priv = hw->priv;
2948
2949 IWL_DEBUG_MACDUMP(priv, "enter\n");
2950
2951 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2952 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2953
2954 if (iwlagn_tx_skb(priv, skb))
2955 dev_kfree_skb_any(skb);
2956
2957 IWL_DEBUG_MACDUMP(priv, "leave\n");
2958 }
2959
2960 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2961 struct ieee80211_vif *vif,
2962 struct ieee80211_key_conf *keyconf,
2963 struct ieee80211_sta *sta,
2964 u32 iv32, u16 *phase1key)
2965 {
2966 struct iwl_priv *priv = hw->priv;
2967 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2968
2969 IWL_DEBUG_MAC80211(priv, "enter\n");
2970
2971 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2972 iv32, phase1key);
2973
2974 IWL_DEBUG_MAC80211(priv, "leave\n");
2975 }
2976
2977 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2978 struct ieee80211_vif *vif,
2979 struct ieee80211_sta *sta,
2980 struct ieee80211_key_conf *key)
2981 {
2982 struct iwl_priv *priv = hw->priv;
2983 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2984 struct iwl_rxon_context *ctx = vif_priv->ctx;
2985 int ret;
2986 u8 sta_id;
2987 bool is_default_wep_key = false;
2988
2989 IWL_DEBUG_MAC80211(priv, "enter\n");
2990
2991 if (priv->cfg->mod_params->sw_crypto) {
2992 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2993 return -EOPNOTSUPP;
2994 }
2995
2996 /*
2997 * To support IBSS RSN, don't program group keys in IBSS, the
2998 * hardware will then not attempt to decrypt the frames.
2999 */
3000 if (vif->type == NL80211_IFTYPE_ADHOC &&
3001 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3002 return -EOPNOTSUPP;
3003
3004 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3005 if (sta_id == IWL_INVALID_STATION)
3006 return -EINVAL;
3007
3008 mutex_lock(&priv->mutex);
3009 iwl_scan_cancel_timeout(priv, 100);
3010
3011 /*
3012 * If we are getting WEP group key and we didn't receive any key mapping
3013 * so far, we are in legacy wep mode (group key only), otherwise we are
3014 * in 1X mode.
3015 * In legacy wep mode, we use another host command to the uCode.
3016 */
3017 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3018 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3019 !sta) {
3020 if (cmd == SET_KEY)
3021 is_default_wep_key = !ctx->key_mapping_keys;
3022 else
3023 is_default_wep_key =
3024 (key->hw_key_idx == HW_KEY_DEFAULT);
3025 }
3026
3027 switch (cmd) {
3028 case SET_KEY:
3029 if (is_default_wep_key)
3030 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3031 else
3032 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3033 key, sta_id);
3034
3035 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3036 break;
3037 case DISABLE_KEY:
3038 if (is_default_wep_key)
3039 ret = iwl_remove_default_wep_key(priv, ctx, key);
3040 else
3041 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3042
3043 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3044 break;
3045 default:
3046 ret = -EINVAL;
3047 }
3048
3049 mutex_unlock(&priv->mutex);
3050 IWL_DEBUG_MAC80211(priv, "leave\n");
3051
3052 return ret;
3053 }
3054
3055 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3056 struct ieee80211_vif *vif,
3057 enum ieee80211_ampdu_mlme_action action,
3058 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3059 u8 buf_size)
3060 {
3061 struct iwl_priv *priv = hw->priv;
3062 int ret = -EINVAL;
3063 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3064
3065 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3066 sta->addr, tid);
3067
3068 if (!(priv->cfg->sku & IWL_SKU_N))
3069 return -EACCES;
3070
3071 mutex_lock(&priv->mutex);
3072
3073 switch (action) {
3074 case IEEE80211_AMPDU_RX_START:
3075 IWL_DEBUG_HT(priv, "start Rx\n");
3076 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3077 break;
3078 case IEEE80211_AMPDU_RX_STOP:
3079 IWL_DEBUG_HT(priv, "stop Rx\n");
3080 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3081 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3082 ret = 0;
3083 break;
3084 case IEEE80211_AMPDU_TX_START:
3085 IWL_DEBUG_HT(priv, "start Tx\n");
3086 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3087 if (ret == 0) {
3088 priv->_agn.agg_tids_count++;
3089 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3090 priv->_agn.agg_tids_count);
3091 }
3092 break;
3093 case IEEE80211_AMPDU_TX_STOP:
3094 IWL_DEBUG_HT(priv, "stop Tx\n");
3095 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3096 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3097 priv->_agn.agg_tids_count--;
3098 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3099 priv->_agn.agg_tids_count);
3100 }
3101 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3102 ret = 0;
3103 if (priv->cfg->ht_params &&
3104 priv->cfg->ht_params->use_rts_for_aggregation) {
3105 struct iwl_station_priv *sta_priv =
3106 (void *) sta->drv_priv;
3107 /*
3108 * switch off RTS/CTS if it was previously enabled
3109 */
3110
3111 sta_priv->lq_sta.lq.general_params.flags &=
3112 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3113 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3114 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3115 }
3116 break;
3117 case IEEE80211_AMPDU_TX_OPERATIONAL:
3118 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3119
3120 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3121
3122 /*
3123 * If the limit is 0, then it wasn't initialised yet,
3124 * use the default. We can do that since we take the
3125 * minimum below, and we don't want to go above our
3126 * default due to hardware restrictions.
3127 */
3128 if (sta_priv->max_agg_bufsize == 0)
3129 sta_priv->max_agg_bufsize =
3130 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3131
3132 /*
3133 * Even though in theory the peer could have different
3134 * aggregation reorder buffer sizes for different sessions,
3135 * our ucode doesn't allow for that and has a global limit
3136 * for each station. Therefore, use the minimum of all the
3137 * aggregation sessions and our default value.
3138 */
3139 sta_priv->max_agg_bufsize =
3140 min(sta_priv->max_agg_bufsize, buf_size);
3141
3142 if (priv->cfg->ht_params &&
3143 priv->cfg->ht_params->use_rts_for_aggregation) {
3144 /*
3145 * switch to RTS/CTS if it is the prefer protection
3146 * method for HT traffic
3147 */
3148
3149 sta_priv->lq_sta.lq.general_params.flags |=
3150 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3151 }
3152
3153 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3154 sta_priv->max_agg_bufsize;
3155
3156 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3157 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3158 ret = 0;
3159 break;
3160 }
3161 mutex_unlock(&priv->mutex);
3162
3163 return ret;
3164 }
3165
3166 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3167 struct ieee80211_vif *vif,
3168 struct ieee80211_sta *sta)
3169 {
3170 struct iwl_priv *priv = hw->priv;
3171 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3172 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3173 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3174 int ret;
3175 u8 sta_id;
3176
3177 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3178 sta->addr);
3179 mutex_lock(&priv->mutex);
3180 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3181 sta->addr);
3182 sta_priv->common.sta_id = IWL_INVALID_STATION;
3183
3184 atomic_set(&sta_priv->pending_frames, 0);
3185 if (vif->type == NL80211_IFTYPE_AP)
3186 sta_priv->client = true;
3187
3188 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3189 is_ap, sta, &sta_id);
3190 if (ret) {
3191 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3192 sta->addr, ret);
3193 /* Should we return success if return code is EEXIST ? */
3194 mutex_unlock(&priv->mutex);
3195 return ret;
3196 }
3197
3198 sta_priv->common.sta_id = sta_id;
3199
3200 /* Initialize rate scaling */
3201 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3202 sta->addr);
3203 iwl_rs_rate_init(priv, sta, sta_id);
3204 mutex_unlock(&priv->mutex);
3205
3206 return 0;
3207 }
3208
3209 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3210 struct ieee80211_channel_switch *ch_switch)
3211 {
3212 struct iwl_priv *priv = hw->priv;
3213 const struct iwl_channel_info *ch_info;
3214 struct ieee80211_conf *conf = &hw->conf;
3215 struct ieee80211_channel *channel = ch_switch->channel;
3216 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3217 /*
3218 * MULTI-FIXME
3219 * When we add support for multiple interfaces, we need to
3220 * revisit this. The channel switch command in the device
3221 * only affects the BSS context, but what does that really
3222 * mean? And what if we get a CSA on the second interface?
3223 * This needs a lot of work.
3224 */
3225 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3226 u16 ch;
3227 unsigned long flags = 0;
3228
3229 IWL_DEBUG_MAC80211(priv, "enter\n");
3230
3231 mutex_lock(&priv->mutex);
3232
3233 if (iwl_is_rfkill(priv))
3234 goto out;
3235
3236 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3237 test_bit(STATUS_SCANNING, &priv->status))
3238 goto out;
3239
3240 if (!iwl_is_associated_ctx(ctx))
3241 goto out;
3242
3243 /* channel switch in progress */
3244 if (priv->switch_rxon.switch_in_progress == true)
3245 goto out;
3246
3247 if (priv->cfg->ops->lib->set_channel_switch) {
3248
3249 ch = channel->hw_value;
3250 if (le16_to_cpu(ctx->active.channel) != ch) {
3251 ch_info = iwl_get_channel_info(priv,
3252 channel->band,
3253 ch);
3254 if (!is_channel_valid(ch_info)) {
3255 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3256 goto out;
3257 }
3258 spin_lock_irqsave(&priv->lock, flags);
3259
3260 priv->current_ht_config.smps = conf->smps_mode;
3261
3262 /* Configure HT40 channels */
3263 ctx->ht.enabled = conf_is_ht(conf);
3264 if (ctx->ht.enabled) {
3265 if (conf_is_ht40_minus(conf)) {
3266 ctx->ht.extension_chan_offset =
3267 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3268 ctx->ht.is_40mhz = true;
3269 } else if (conf_is_ht40_plus(conf)) {
3270 ctx->ht.extension_chan_offset =
3271 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3272 ctx->ht.is_40mhz = true;
3273 } else {
3274 ctx->ht.extension_chan_offset =
3275 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3276 ctx->ht.is_40mhz = false;
3277 }
3278 } else
3279 ctx->ht.is_40mhz = false;
3280
3281 if ((le16_to_cpu(ctx->staging.channel) != ch))
3282 ctx->staging.flags = 0;
3283
3284 iwl_set_rxon_channel(priv, channel, ctx);
3285 iwl_set_rxon_ht(priv, ht_conf);
3286 iwl_set_flags_for_band(priv, ctx, channel->band,
3287 ctx->vif);
3288 spin_unlock_irqrestore(&priv->lock, flags);
3289
3290 iwl_set_rate(priv);
3291 /*
3292 * at this point, staging_rxon has the
3293 * configuration for channel switch
3294 */
3295 if (priv->cfg->ops->lib->set_channel_switch(priv,
3296 ch_switch))
3297 priv->switch_rxon.switch_in_progress = false;
3298 }
3299 }
3300 out:
3301 mutex_unlock(&priv->mutex);
3302 if (!priv->switch_rxon.switch_in_progress)
3303 ieee80211_chswitch_done(ctx->vif, false);
3304 IWL_DEBUG_MAC80211(priv, "leave\n");
3305 }
3306
3307 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3308 unsigned int changed_flags,
3309 unsigned int *total_flags,
3310 u64 multicast)
3311 {
3312 struct iwl_priv *priv = hw->priv;
3313 __le32 filter_or = 0, filter_nand = 0;
3314 struct iwl_rxon_context *ctx;
3315
3316 #define CHK(test, flag) do { \
3317 if (*total_flags & (test)) \
3318 filter_or |= (flag); \
3319 else \
3320 filter_nand |= (flag); \
3321 } while (0)
3322
3323 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3324 changed_flags, *total_flags);
3325
3326 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3327 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3328 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3329 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3330
3331 #undef CHK
3332
3333 mutex_lock(&priv->mutex);
3334
3335 for_each_context(priv, ctx) {
3336 ctx->staging.filter_flags &= ~filter_nand;
3337 ctx->staging.filter_flags |= filter_or;
3338
3339 /*
3340 * Not committing directly because hardware can perform a scan,
3341 * but we'll eventually commit the filter flags change anyway.
3342 */
3343 }
3344
3345 mutex_unlock(&priv->mutex);
3346
3347 /*
3348 * Receiving all multicast frames is always enabled by the
3349 * default flags setup in iwl_connection_init_rx_config()
3350 * since we currently do not support programming multicast
3351 * filters into the device.
3352 */
3353 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3354 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3355 }
3356
3357 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3358 {
3359 struct iwl_priv *priv = hw->priv;
3360
3361 mutex_lock(&priv->mutex);
3362 IWL_DEBUG_MAC80211(priv, "enter\n");
3363
3364 /* do not support "flush" */
3365 if (!priv->cfg->ops->lib->txfifo_flush)
3366 goto done;
3367
3368 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3369 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3370 goto done;
3371 }
3372 if (iwl_is_rfkill(priv)) {
3373 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3374 goto done;
3375 }
3376
3377 /*
3378 * mac80211 will not push any more frames for transmit
3379 * until the flush is completed
3380 */
3381 if (drop) {
3382 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3383 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3384 IWL_ERR(priv, "flush request fail\n");
3385 goto done;
3386 }
3387 }
3388 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3389 iwlagn_wait_tx_queue_empty(priv);
3390 done:
3391 mutex_unlock(&priv->mutex);
3392 IWL_DEBUG_MAC80211(priv, "leave\n");
3393 }
3394
3395 static void iwlagn_disable_roc(struct iwl_priv *priv)
3396 {
3397 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3398 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3399
3400 lockdep_assert_held(&priv->mutex);
3401
3402 if (!ctx->is_active)
3403 return;
3404
3405 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3406 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3407 iwl_set_rxon_channel(priv, chan, ctx);
3408 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3409
3410 priv->_agn.hw_roc_channel = NULL;
3411
3412 iwlcore_commit_rxon(priv, ctx);
3413
3414 ctx->is_active = false;
3415 }
3416
3417 static void iwlagn_bg_roc_done(struct work_struct *work)
3418 {
3419 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3420 _agn.hw_roc_work.work);
3421
3422 mutex_lock(&priv->mutex);
3423 ieee80211_remain_on_channel_expired(priv->hw);
3424 iwlagn_disable_roc(priv);
3425 mutex_unlock(&priv->mutex);
3426 }
3427
3428 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3429 struct ieee80211_channel *channel,
3430 enum nl80211_channel_type channel_type,
3431 int duration)
3432 {
3433 struct iwl_priv *priv = hw->priv;
3434 int err = 0;
3435
3436 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3437 return -EOPNOTSUPP;
3438
3439 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3440 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3441 return -EOPNOTSUPP;
3442
3443 mutex_lock(&priv->mutex);
3444
3445 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3446 test_bit(STATUS_SCAN_HW, &priv->status)) {
3447 err = -EBUSY;
3448 goto out;
3449 }
3450
3451 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3452 priv->_agn.hw_roc_channel = channel;
3453 priv->_agn.hw_roc_chantype = channel_type;
3454 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3455 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3456 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3457 msecs_to_jiffies(duration + 20));
3458
3459 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3460 ieee80211_ready_on_channel(priv->hw);
3461
3462 out:
3463 mutex_unlock(&priv->mutex);
3464
3465 return err;
3466 }
3467
3468 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3469 {
3470 struct iwl_priv *priv = hw->priv;
3471
3472 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3473 return -EOPNOTSUPP;
3474
3475 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3476
3477 mutex_lock(&priv->mutex);
3478 iwlagn_disable_roc(priv);
3479 mutex_unlock(&priv->mutex);
3480
3481 return 0;
3482 }
3483
3484 /*****************************************************************************
3485 *
3486 * driver setup and teardown
3487 *
3488 *****************************************************************************/
3489
3490 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3491 {
3492 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3493
3494 init_waitqueue_head(&priv->wait_command_queue);
3495
3496 INIT_WORK(&priv->restart, iwl_bg_restart);
3497 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3498 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3499 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3500 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3501 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3502 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3503 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3504 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3505 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3506
3507 iwl_setup_scan_deferred_work(priv);
3508
3509 if (priv->cfg->ops->lib->setup_deferred_work)
3510 priv->cfg->ops->lib->setup_deferred_work(priv);
3511
3512 init_timer(&priv->statistics_periodic);
3513 priv->statistics_periodic.data = (unsigned long)priv;
3514 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3515
3516 init_timer(&priv->ucode_trace);
3517 priv->ucode_trace.data = (unsigned long)priv;
3518 priv->ucode_trace.function = iwl_bg_ucode_trace;
3519
3520 init_timer(&priv->watchdog);
3521 priv->watchdog.data = (unsigned long)priv;
3522 priv->watchdog.function = iwl_bg_watchdog;
3523
3524 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3525 iwl_irq_tasklet, (unsigned long)priv);
3526 }
3527
3528 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3529 {
3530 if (priv->cfg->ops->lib->cancel_deferred_work)
3531 priv->cfg->ops->lib->cancel_deferred_work(priv);
3532
3533 cancel_delayed_work_sync(&priv->init_alive_start);
3534 cancel_delayed_work(&priv->alive_start);
3535 cancel_work_sync(&priv->run_time_calib_work);
3536 cancel_work_sync(&priv->beacon_update);
3537
3538 iwl_cancel_scan_deferred_work(priv);
3539
3540 cancel_work_sync(&priv->bt_full_concurrency);
3541 cancel_work_sync(&priv->bt_runtime_config);
3542
3543 del_timer_sync(&priv->statistics_periodic);
3544 del_timer_sync(&priv->ucode_trace);
3545 }
3546
3547 static void iwl_init_hw_rates(struct iwl_priv *priv,
3548 struct ieee80211_rate *rates)
3549 {
3550 int i;
3551
3552 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3553 rates[i].bitrate = iwl_rates[i].ieee * 5;
3554 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3555 rates[i].hw_value_short = i;
3556 rates[i].flags = 0;
3557 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3558 /*
3559 * If CCK != 1M then set short preamble rate flag.
3560 */
3561 rates[i].flags |=
3562 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3563 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3564 }
3565 }
3566 }
3567
3568 static int iwl_init_drv(struct iwl_priv *priv)
3569 {
3570 int ret;
3571
3572 spin_lock_init(&priv->sta_lock);
3573 spin_lock_init(&priv->hcmd_lock);
3574
3575 INIT_LIST_HEAD(&priv->free_frames);
3576
3577 mutex_init(&priv->mutex);
3578
3579 priv->ieee_channels = NULL;
3580 priv->ieee_rates = NULL;
3581 priv->band = IEEE80211_BAND_2GHZ;
3582
3583 priv->iw_mode = NL80211_IFTYPE_STATION;
3584 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3585 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3586 priv->_agn.agg_tids_count = 0;
3587
3588 /* initialize force reset */
3589 priv->force_reset[IWL_RF_RESET].reset_duration =
3590 IWL_DELAY_NEXT_FORCE_RF_RESET;
3591 priv->force_reset[IWL_FW_RESET].reset_duration =
3592 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3593
3594 priv->rx_statistics_jiffies = jiffies;
3595
3596 /* Choose which receivers/antennas to use */
3597 if (priv->cfg->ops->hcmd->set_rxon_chain)
3598 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3599 &priv->contexts[IWL_RXON_CTX_BSS]);
3600
3601 iwl_init_scan_params(priv);
3602
3603 /* init bt coex */
3604 if (priv->cfg->bt_params &&
3605 priv->cfg->bt_params->advanced_bt_coexist) {
3606 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3607 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3608 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3609 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3610 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3611 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3612 }
3613
3614 /* Set the tx_power_user_lmt to the lowest power level
3615 * this value will get overwritten by channel max power avg
3616 * from eeprom */
3617 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3618 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3619
3620 ret = iwl_init_channel_map(priv);
3621 if (ret) {
3622 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3623 goto err;
3624 }
3625
3626 ret = iwlcore_init_geos(priv);
3627 if (ret) {
3628 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3629 goto err_free_channel_map;
3630 }
3631 iwl_init_hw_rates(priv, priv->ieee_rates);
3632
3633 return 0;
3634
3635 err_free_channel_map:
3636 iwl_free_channel_map(priv);
3637 err:
3638 return ret;
3639 }
3640
3641 static void iwl_uninit_drv(struct iwl_priv *priv)
3642 {
3643 iwl_calib_free_results(priv);
3644 iwlcore_free_geos(priv);
3645 iwl_free_channel_map(priv);
3646 kfree(priv->scan_cmd);
3647 }
3648
3649 struct ieee80211_ops iwlagn_hw_ops = {
3650 .tx = iwlagn_mac_tx,
3651 .start = iwlagn_mac_start,
3652 .stop = iwlagn_mac_stop,
3653 .add_interface = iwl_mac_add_interface,
3654 .remove_interface = iwl_mac_remove_interface,
3655 .change_interface = iwl_mac_change_interface,
3656 .config = iwlagn_mac_config,
3657 .configure_filter = iwlagn_configure_filter,
3658 .set_key = iwlagn_mac_set_key,
3659 .update_tkip_key = iwlagn_mac_update_tkip_key,
3660 .conf_tx = iwl_mac_conf_tx,
3661 .bss_info_changed = iwlagn_bss_info_changed,
3662 .ampdu_action = iwlagn_mac_ampdu_action,
3663 .hw_scan = iwl_mac_hw_scan,
3664 .sta_notify = iwlagn_mac_sta_notify,
3665 .sta_add = iwlagn_mac_sta_add,
3666 .sta_remove = iwl_mac_sta_remove,
3667 .channel_switch = iwlagn_mac_channel_switch,
3668 .flush = iwlagn_mac_flush,
3669 .tx_last_beacon = iwl_mac_tx_last_beacon,
3670 .remain_on_channel = iwl_mac_remain_on_channel,
3671 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3672 .offchannel_tx = iwl_mac_offchannel_tx,
3673 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3674 };
3675
3676 static u32 iwl_hw_detect(struct iwl_priv *priv)
3677 {
3678 u8 rev_id;
3679
3680 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3681 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3682 return iwl_read32(priv, CSR_HW_REV);
3683 }
3684
3685 static int iwl_set_hw_params(struct iwl_priv *priv)
3686 {
3687 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3688 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3689 if (priv->cfg->mod_params->amsdu_size_8K)
3690 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3691 else
3692 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3693
3694 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3695
3696 if (priv->cfg->mod_params->disable_11n)
3697 priv->cfg->sku &= ~IWL_SKU_N;
3698
3699 /* Device-specific setup */
3700 return priv->cfg->ops->lib->set_hw_params(priv);
3701 }
3702
3703 static const u8 iwlagn_bss_ac_to_fifo[] = {
3704 IWL_TX_FIFO_VO,
3705 IWL_TX_FIFO_VI,
3706 IWL_TX_FIFO_BE,
3707 IWL_TX_FIFO_BK,
3708 };
3709
3710 static const u8 iwlagn_bss_ac_to_queue[] = {
3711 0, 1, 2, 3,
3712 };
3713
3714 static const u8 iwlagn_pan_ac_to_fifo[] = {
3715 IWL_TX_FIFO_VO_IPAN,
3716 IWL_TX_FIFO_VI_IPAN,
3717 IWL_TX_FIFO_BE_IPAN,
3718 IWL_TX_FIFO_BK_IPAN,
3719 };
3720
3721 static const u8 iwlagn_pan_ac_to_queue[] = {
3722 7, 6, 5, 4,
3723 };
3724
3725 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3726 {
3727 int err = 0, i;
3728 struct iwl_priv *priv;
3729 struct ieee80211_hw *hw;
3730 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3731 unsigned long flags;
3732 u16 pci_cmd, num_mac;
3733 u32 hw_rev;
3734
3735 /************************
3736 * 1. Allocating HW data
3737 ************************/
3738
3739 hw = iwl_alloc_all(cfg);
3740 if (!hw) {
3741 err = -ENOMEM;
3742 goto out;
3743 }
3744 priv = hw->priv;
3745 /* At this point both hw and priv are allocated. */
3746
3747 /*
3748 * The default context is always valid,
3749 * more may be discovered when firmware
3750 * is loaded.
3751 */
3752 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3753
3754 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3755 priv->contexts[i].ctxid = i;
3756
3757 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3758 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3759 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3760 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3761 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3762 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3763 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3764 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3765 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3766 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3767 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3768 BIT(NL80211_IFTYPE_ADHOC);
3769 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3770 BIT(NL80211_IFTYPE_STATION);
3771 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3772 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3773 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3774 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3775
3776 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3777 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3778 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3779 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3780 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3781 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3782 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3783 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3784 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3785 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3786 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3787 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3788 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3789 #ifdef CONFIG_IWL_P2P
3790 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3791 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3792 #endif
3793 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3794 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3795 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3796
3797 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3798
3799 SET_IEEE80211_DEV(hw, &pdev->dev);
3800
3801 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3802 priv->cfg = cfg;
3803 priv->pci_dev = pdev;
3804 priv->inta_mask = CSR_INI_SET_MASK;
3805
3806 /* is antenna coupling more than 35dB ? */
3807 priv->bt_ant_couple_ok =
3808 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3809 true : false;
3810
3811 /* enable/disable bt channel inhibition */
3812 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3813 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3814 (priv->bt_ch_announce) ? "On" : "Off");
3815
3816 if (iwl_alloc_traffic_mem(priv))
3817 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3818
3819 /**************************
3820 * 2. Initializing PCI bus
3821 **************************/
3822 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3823 PCIE_LINK_STATE_CLKPM);
3824
3825 if (pci_enable_device(pdev)) {
3826 err = -ENODEV;
3827 goto out_ieee80211_free_hw;
3828 }
3829
3830 pci_set_master(pdev);
3831
3832 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3833 if (!err)
3834 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3835 if (err) {
3836 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3837 if (!err)
3838 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3839 /* both attempts failed: */
3840 if (err) {
3841 IWL_WARN(priv, "No suitable DMA available.\n");
3842 goto out_pci_disable_device;
3843 }
3844 }
3845
3846 err = pci_request_regions(pdev, DRV_NAME);
3847 if (err)
3848 goto out_pci_disable_device;
3849
3850 pci_set_drvdata(pdev, priv);
3851
3852
3853 /***********************
3854 * 3. Read REV register
3855 ***********************/
3856 priv->hw_base = pci_iomap(pdev, 0, 0);
3857 if (!priv->hw_base) {
3858 err = -ENODEV;
3859 goto out_pci_release_regions;
3860 }
3861
3862 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3863 (unsigned long long) pci_resource_len(pdev, 0));
3864 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3865
3866 /* these spin locks will be used in apm_ops.init and EEPROM access
3867 * we should init now
3868 */
3869 spin_lock_init(&priv->reg_lock);
3870 spin_lock_init(&priv->lock);
3871
3872 /*
3873 * stop and reset the on-board processor just in case it is in a
3874 * strange state ... like being left stranded by a primary kernel
3875 * and this is now the kdump kernel trying to start up
3876 */
3877 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3878
3879 hw_rev = iwl_hw_detect(priv);
3880 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3881 priv->cfg->name, hw_rev);
3882
3883 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3884 * PCI Tx retries from interfering with C3 CPU state */
3885 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3886
3887 iwl_prepare_card_hw(priv);
3888 if (!priv->hw_ready) {
3889 IWL_WARN(priv, "Failed, HW not ready\n");
3890 goto out_iounmap;
3891 }
3892
3893 /*****************
3894 * 4. Read EEPROM
3895 *****************/
3896 /* Read the EEPROM */
3897 err = iwl_eeprom_init(priv, hw_rev);
3898 if (err) {
3899 IWL_ERR(priv, "Unable to init EEPROM\n");
3900 goto out_iounmap;
3901 }
3902 err = iwl_eeprom_check_version(priv);
3903 if (err)
3904 goto out_free_eeprom;
3905
3906 err = iwl_eeprom_check_sku(priv);
3907 if (err)
3908 goto out_free_eeprom;
3909
3910 /* extract MAC Address */
3911 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3912 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3913 priv->hw->wiphy->addresses = priv->addresses;
3914 priv->hw->wiphy->n_addresses = 1;
3915 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3916 if (num_mac > 1) {
3917 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3918 ETH_ALEN);
3919 priv->addresses[1].addr[5]++;
3920 priv->hw->wiphy->n_addresses++;
3921 }
3922
3923 /************************
3924 * 5. Setup HW constants
3925 ************************/
3926 if (iwl_set_hw_params(priv)) {
3927 IWL_ERR(priv, "failed to set hw parameters\n");
3928 goto out_free_eeprom;
3929 }
3930
3931 /*******************
3932 * 6. Setup priv
3933 *******************/
3934
3935 err = iwl_init_drv(priv);
3936 if (err)
3937 goto out_free_eeprom;
3938 /* At this point both hw and priv are initialized. */
3939
3940 /********************
3941 * 7. Setup services
3942 ********************/
3943 spin_lock_irqsave(&priv->lock, flags);
3944 iwl_disable_interrupts(priv);
3945 spin_unlock_irqrestore(&priv->lock, flags);
3946
3947 pci_enable_msi(priv->pci_dev);
3948
3949 iwl_alloc_isr_ict(priv);
3950
3951 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3952 IRQF_SHARED, DRV_NAME, priv);
3953 if (err) {
3954 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3955 goto out_disable_msi;
3956 }
3957
3958 iwl_setup_deferred_work(priv);
3959 iwl_setup_rx_handlers(priv);
3960
3961 /*********************************************
3962 * 8. Enable interrupts and read RFKILL state
3963 *********************************************/
3964
3965 /* enable rfkill interrupt: hw bug w/a */
3966 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3967 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3968 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3969 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3970 }
3971
3972 iwl_enable_rfkill_int(priv);
3973
3974 /* If platform's RF_KILL switch is NOT set to KILL */
3975 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3976 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3977 else
3978 set_bit(STATUS_RF_KILL_HW, &priv->status);
3979
3980 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3981 test_bit(STATUS_RF_KILL_HW, &priv->status));
3982
3983 iwl_power_initialize(priv);
3984 iwl_tt_initialize(priv);
3985
3986 init_completion(&priv->_agn.firmware_loading_complete);
3987
3988 err = iwl_request_firmware(priv, true);
3989 if (err)
3990 goto out_destroy_workqueue;
3991
3992 return 0;
3993
3994 out_destroy_workqueue:
3995 destroy_workqueue(priv->workqueue);
3996 priv->workqueue = NULL;
3997 free_irq(priv->pci_dev->irq, priv);
3998 iwl_free_isr_ict(priv);
3999 out_disable_msi:
4000 pci_disable_msi(priv->pci_dev);
4001 iwl_uninit_drv(priv);
4002 out_free_eeprom:
4003 iwl_eeprom_free(priv);
4004 out_iounmap:
4005 pci_iounmap(pdev, priv->hw_base);
4006 out_pci_release_regions:
4007 pci_set_drvdata(pdev, NULL);
4008 pci_release_regions(pdev);
4009 out_pci_disable_device:
4010 pci_disable_device(pdev);
4011 out_ieee80211_free_hw:
4012 iwl_free_traffic_mem(priv);
4013 ieee80211_free_hw(priv->hw);
4014 out:
4015 return err;
4016 }
4017
4018 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4019 {
4020 struct iwl_priv *priv = pci_get_drvdata(pdev);
4021 unsigned long flags;
4022
4023 if (!priv)
4024 return;
4025
4026 wait_for_completion(&priv->_agn.firmware_loading_complete);
4027
4028 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4029
4030 iwl_dbgfs_unregister(priv);
4031 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4032
4033 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4034 * to be called and iwl_down since we are removing the device
4035 * we need to set STATUS_EXIT_PENDING bit.
4036 */
4037 set_bit(STATUS_EXIT_PENDING, &priv->status);
4038
4039 iwl_leds_exit(priv);
4040
4041 if (priv->mac80211_registered) {
4042 ieee80211_unregister_hw(priv->hw);
4043 priv->mac80211_registered = 0;
4044 } else {
4045 iwl_down(priv);
4046 }
4047
4048 /*
4049 * Make sure device is reset to low power before unloading driver.
4050 * This may be redundant with iwl_down(), but there are paths to
4051 * run iwl_down() without calling apm_ops.stop(), and there are
4052 * paths to avoid running iwl_down() at all before leaving driver.
4053 * This (inexpensive) call *makes sure* device is reset.
4054 */
4055 iwl_apm_stop(priv);
4056
4057 iwl_tt_exit(priv);
4058
4059 /* make sure we flush any pending irq or
4060 * tasklet for the driver
4061 */
4062 spin_lock_irqsave(&priv->lock, flags);
4063 iwl_disable_interrupts(priv);
4064 spin_unlock_irqrestore(&priv->lock, flags);
4065
4066 iwl_synchronize_irq(priv);
4067
4068 iwl_dealloc_ucode_pci(priv);
4069
4070 if (priv->rxq.bd)
4071 iwlagn_rx_queue_free(priv, &priv->rxq);
4072 iwlagn_hw_txq_ctx_free(priv);
4073
4074 iwl_eeprom_free(priv);
4075
4076
4077 /*netif_stop_queue(dev); */
4078 flush_workqueue(priv->workqueue);
4079
4080 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4081 * priv->workqueue... so we can't take down the workqueue
4082 * until now... */
4083 destroy_workqueue(priv->workqueue);
4084 priv->workqueue = NULL;
4085 iwl_free_traffic_mem(priv);
4086
4087 free_irq(priv->pci_dev->irq, priv);
4088 pci_disable_msi(priv->pci_dev);
4089 pci_iounmap(pdev, priv->hw_base);
4090 pci_release_regions(pdev);
4091 pci_disable_device(pdev);
4092 pci_set_drvdata(pdev, NULL);
4093
4094 iwl_uninit_drv(priv);
4095
4096 iwl_free_isr_ict(priv);
4097
4098 dev_kfree_skb(priv->beacon_skb);
4099
4100 ieee80211_free_hw(priv->hw);
4101 }
4102
4103
4104 /*****************************************************************************
4105 *
4106 * driver and module entry point
4107 *
4108 *****************************************************************************/
4109
4110 /* Hardware specific file defines the PCI IDs table for that hardware module */
4111 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4112 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4113 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4114 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4115 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4116 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4117 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4118 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4119 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4120 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4121 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4122 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4123 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4124 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4125 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4126 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4127 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4128 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4129 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4130 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4131 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4132 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4133 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4134 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4135 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4136
4137 /* 5300 Series WiFi */
4138 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4139 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4140 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4141 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4142 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4143 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4144 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4145 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4146 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4147 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4148 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4149 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4150
4151 /* 5350 Series WiFi/WiMax */
4152 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4153 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4154 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4155
4156 /* 5150 Series Wifi/WiMax */
4157 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4158 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4159 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4160 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4161 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4162 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4163
4164 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4165 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4166 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4167 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4168
4169 /* 6x00 Series */
4170 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4171 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4172 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4173 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4174 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4175 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4176 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4177 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4178 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4179 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4180
4181 /* 6x05 Series */
4182 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4183 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4184 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4185 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4186 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4187 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4188 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4189
4190 /* 6x30 Series */
4191 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4192 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4193 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4194 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4195 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4196 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4197 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4198 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4199 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4200 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4201 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4202 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4203 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4204 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4205 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4206 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4207
4208 /* 6x50 WiFi/WiMax Series */
4209 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4210 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4211 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4212 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4213 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4214 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4215
4216 /* 6150 WiFi/WiMax Series */
4217 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4218 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4219 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4220 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4221 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4222 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4223
4224 /* 1000 Series WiFi */
4225 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4226 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4227 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4228 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4229 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4230 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4231 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4232 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4233 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4234 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4235 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4236 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4237
4238 /* 100 Series WiFi */
4239 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4240 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4241 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4242 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4243 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4244 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4245
4246 /* 130 Series WiFi */
4247 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4248 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4249 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4250 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4251 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4252 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4253
4254 /* 2x00 Series */
4255 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4256 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4257 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4258 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4259 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4260 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4261
4262 /* 2x30 Series */
4263 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4264 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4265 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4266 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4267 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4268 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4269
4270 /* 6x35 Series */
4271 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4272 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4273 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4274 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4275 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4276 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4277 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4278 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4279 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4280
4281 /* 200 Series */
4282 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4283 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4284 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4285 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4286 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4287 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4288
4289 /* 230 Series */
4290 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4291 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4292 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4293 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4294 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4295 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4296
4297 {0}
4298 };
4299 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4300
4301 static struct pci_driver iwl_driver = {
4302 .name = DRV_NAME,
4303 .id_table = iwl_hw_card_ids,
4304 .probe = iwl_pci_probe,
4305 .remove = __devexit_p(iwl_pci_remove),
4306 .driver.pm = IWL_PM_OPS,
4307 };
4308
4309 static int __init iwl_init(void)
4310 {
4311
4312 int ret;
4313 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4314 pr_info(DRV_COPYRIGHT "\n");
4315
4316 ret = iwlagn_rate_control_register();
4317 if (ret) {
4318 pr_err("Unable to register rate control algorithm: %d\n", ret);
4319 return ret;
4320 }
4321
4322 ret = pci_register_driver(&iwl_driver);
4323 if (ret) {
4324 pr_err("Unable to initialize PCI module\n");
4325 goto error_register;
4326 }
4327
4328 return ret;
4329
4330 error_register:
4331 iwlagn_rate_control_unregister();
4332 return ret;
4333 }
4334
4335 static void __exit iwl_exit(void)
4336 {
4337 pci_unregister_driver(&iwl_driver);
4338 iwlagn_rate_control_unregister();
4339 }
4340
4341 module_exit(iwl_exit);
4342 module_init(iwl_init);
4343
4344 #ifdef CONFIG_IWLWIFI_DEBUG
4345 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4346 MODULE_PARM_DESC(debug, "debug output mask");
4347 #endif
4348
4349 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4350 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4351 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4352 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4353 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4354 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4355 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4356 int, S_IRUGO);
4357 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4358 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4359 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4360
4361 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4362 S_IRUGO);
4363 MODULE_PARM_DESC(ucode_alternative,
4364 "specify ucode alternative to use from ucode file");
4365
4366 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4367 MODULE_PARM_DESC(antenna_coupling,
4368 "specify antenna coupling in dB (defualt: 0 dB)");
4369
4370 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4371 MODULE_PARM_DESC(bt_ch_inhibition,
4372 "Disable BT channel inhibition (default: enable)");
4373
4374 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4375 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4376
4377 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4378 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
Linux kernel - Deliverables
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