drivers/net/wireless/iwlwifi/iwl-csr.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*
  66  * CSR (control and status registers)
  67  *
  68  * CSR registers are mapped directly into PCI bus space, and are accessible
  69  * whenever platform supplies power to device, even when device is in
  70  * low power states due to driver-invoked device resets
  71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
  72  *
  73  * Use iwl_write32() and iwl_read32() family to access these registers;
  74  * these provide simple PCI bus access, without waking up the MAC.
  75  * Do not use iwl_write_direct32() family for these registers;
  76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
  77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
  78  * the CSR registers.
  79  *
  80  * NOTE:  Device does need to be awake in order to read this memory
  81  *        via CSR_EEPROM and CSR_OTP registers
  82  */
  83 #define CSR_BASE    (0x000)
  84
  85 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
  87 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  88 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  89 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  90 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  91 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  92 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  93
  94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
  95 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
  96
  97 /*
  98  * Hardware revision info
  99  * Bit fields:
 100  * 31-16:  Reserved
 101  *  15-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
 102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 103  *  1-0:  "Dash" (-) value, as in A-1, etc.
 104  */
 105 #define CSR_HW_REV              (CSR_BASE+0x028)
 106
 107 /*
 108  * EEPROM and OTP (one-time-programmable) memory reads
 109  *
 110  * NOTE:  Device must be awake, initialized via apm_ops.init(),
 111  *        in order to read.
 112  */
 113 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 114 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 115 #define CSR_OTP_GP_REG          (CSR_BASE+0x034)
 116
 117 #define CSR_GIO_REG             (CSR_BASE+0x03C)
 118 #define CSR_GP_UCODE_REG        (CSR_BASE+0x048)
 119 #define CSR_GP_DRIVER_REG       (CSR_BASE+0x050)
 120
 121 /*
 122  * UCODE-DRIVER GP (general purpose) mailbox registers.
 123  * SET/CLR registers set/clear bit(s) if "1" is written.
 124  */
 125 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 126 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 127 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 128 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 129
 130 #define CSR_LED_REG             (CSR_BASE+0x094)
 131 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
 132 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
 133
 134
 135 /* GIO Chicken Bits (PCI Express bus link power management) */
 136 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 137
 138 /* Analog phase-lock-loop configuration  */
 139 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 140
 141 /*
 142  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
 143  * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
 144  * See also CSR_HW_REV register.
 145  * Bit fields:
 146  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 147  *  1-0:  "Dash" (-) value, as in C-1, etc.
 148  */
 149 #define CSR_HW_REV_WA_REG               (CSR_BASE+0x22C)
 150
 151 #define CSR_DBG_HPET_MEM_REG            (CSR_BASE+0x240)
 152 #define CSR_DBG_LINK_PWR_MGMT_REG       (CSR_BASE+0x250)
 153
 154 /* Bits for CSR_HW_IF_CONFIG_REG */
 155 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH       (0x00000003)
 156 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP       (0x0000000C)
 157 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x000000C0)
 158 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 159 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 160 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE       (0x00000C00)
 161 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH       (0x00003000)
 162 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP       (0x0000C000)
 163
 164 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH       (0)
 165 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP       (2)
 166 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER      (6)
 167 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE       (10)
 168 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH       (12)
 169 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP       (14)
 170
 171 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A   (0x00080000)
 172 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
 173 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY      (0x00400000) /* PCI_OWN_SEM */
 174 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
 175 #define CSR_HW_IF_CONFIG_REG_PREPARE              (0x08000000) /* WAKE_ME */
 176
 177 #define CSR_INT_PERIODIC_DIS                    (0x00) /* disable periodic int*/
 178 #define CSR_INT_PERIODIC_ENA                    (0xFF) /* 255*32 usec ~ 8 msec*/
 179
 180 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 181  * acknowledged (reset) by host writing "1" to flagged bits. */
 182 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 183 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 184 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28) /* Rx periodic */
 185 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 186 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 187 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 188 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 189 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 190 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
 191 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 192 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 193
 194 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 195                                  CSR_INT_BIT_HW_ERR  | \
 196                                  CSR_INT_BIT_FH_TX   | \
 197                                  CSR_INT_BIT_SW_ERR  | \
 198                                  CSR_INT_BIT_RF_KILL | \
 199                                  CSR_INT_BIT_SW_RX   | \
 200                                  CSR_INT_BIT_WAKEUP  | \
 201                                  CSR_INT_BIT_ALIVE)
 202
 203 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 204 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 205 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 206 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 207 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 208 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 209 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 210
 211 #define CSR_FH_INT_RX_MASK      (CSR_FH_INT_BIT_HI_PRIOR | \
 212                                 CSR_FH_INT_BIT_RX_CHNL1 | \
 213                                 CSR_FH_INT_BIT_RX_CHNL0)
 214
 215 #define CSR_FH_INT_TX_MASK      (CSR_FH_INT_BIT_TX_CHNL1 | \
 216                                 CSR_FH_INT_BIT_TX_CHNL0)
 217
 218 /* GPIO */
 219 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 220 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 221 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 222
 223 /* RESET */
 224 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 225 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 226 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 227 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 228 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 229 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
 230
 231 /*
 232  * GP (general purpose) CONTROL REGISTER
 233  * Bit fields:
 234  *    27:  HW_RF_KILL_SW
 235  *         Indicates state of (platform's) hardware RF-Kill switch
 236  * 26-24:  POWER_SAVE_TYPE
 237  *         Indicates current power-saving mode:
 238  *         000 -- No power saving
 239  *         001 -- MAC power-down
 240  *         010 -- PHY (radio) power-down
 241  *         011 -- Error
 242  *   9-6:  SYS_CONFIG
 243  *         Indicates current system configuration, reflecting pins on chip
 244  *         as forced high/low by device circuit board.
 245  *     4:  GOING_TO_SLEEP
 246  *         Indicates MAC is entering a power-saving sleep power-down.
 247  *         Not a good time to access device-internal resources.
 248  *     3:  MAC_ACCESS_REQ
 249  *         Host sets this to request and maintain MAC wakeup, to allow host
 250  *         access to device-internal resources.  Host must wait for
 251  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
 252  *         device registers.
 253  *     2:  INIT_DONE
 254  *         Host sets this to put device into fully operational D0 power mode.
 255  *         Host resets this after SW_RESET to put device into low power mode.
 256  *     0:  MAC_CLOCK_READY
 257  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
 258  *         Internal resources are accessible.
 259  *         NOTE:  This does not indicate that the processor is actually running.
 260  *         NOTE:  This does not indicate that device has completed
 261  *                init or post-power-down restore of internal SRAM memory.
 262  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 263  *                SRAM is restored and uCode is in normal operation mode.
 264  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 265  *                do not need to save/restore it.
 266  *         NOTE:  After device reset, this bit remains "0" until host sets
 267  *                INIT_DONE
 268  */
 269 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 270 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 271 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 272 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 273
 274 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 275
 276 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 277 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 278 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 279
 280
 281 /* HW REV */
 282 #define CSR_HW_REV_DASH(_val)          (((_val) & 0x0000003) >> 0)
 283 #define CSR_HW_REV_STEP(_val)          (((_val) & 0x000000C) >> 2)
 284
 285 #define CSR_HW_REV_TYPE_MSK            (0x000FFF0)
 286 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 287 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 288 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 289 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 290 #define CSR_HW_REV_TYPE_1000           (0x0000060)
 291 #define CSR_HW_REV_TYPE_6x00           (0x0000070)
 292 #define CSR_HW_REV_TYPE_6x50           (0x0000080)
 293 #define CSR_HW_REV_TYPE_6150           (0x0000084)
 294 #define CSR_HW_REV_TYPE_6x05           (0x00000B0)
 295 #define CSR_HW_REV_TYPE_6x30           CSR_HW_REV_TYPE_6x05
 296 #define CSR_HW_REV_TYPE_6x35           CSR_HW_REV_TYPE_6x05
 297 #define CSR_HW_REV_TYPE_2x30           (0x00000C0)
 298 #define CSR_HW_REV_TYPE_2x00           (0x0000100)
 299 #define CSR_HW_REV_TYPE_105            (0x0000110)
 300 #define CSR_HW_REV_TYPE_135            (0x0000120)
 301 #define CSR_HW_REV_TYPE_NONE           (0x00001F0)
 302
 303 /* EEPROM REG */
 304 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 305 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 306 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 307 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 308
 309 /* EEPROM GP */
 310 #define CSR_EEPROM_GP_VALID_MSK         (0x00000007) /* signature */
 311 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 312 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP    (0x00000000)
 313 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP          (0x00000001)
 314 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K         (0x00000002)
 315 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K         (0x00000004)
 316
 317 /* One-time-programmable memory general purpose reg */
 318 #define CSR_OTP_GP_REG_DEVICE_SELECT    (0x00010000) /* 0 - EEPROM, 1 - OTP */
 319 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE  (0x00020000) /* 0 - absolute, 1 - relative */
 320 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
 321 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
 322
 323 /* GP REG */
 324 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
 325 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
 326 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
 327 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
 328 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
 329
 330
 331 /* CSR GIO */
 332 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 333
 334 /*
 335  * UCODE-DRIVER GP (general purpose) mailbox register 1
 336  * Host driver and uCode write and/or read this register to communicate with
 337  * each other.
 338  * Bit fields:
 339  *     4:  UCODE_DISABLE
 340  *         Host sets this to request permanent halt of uCode, same as
 341  *         sending CARD_STATE command with "halt" bit set.
 342  *     3:  CT_KILL_EXIT
 343  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
 344  *         device temperature is low enough to continue normal operation.
 345  *     2:  CMD_BLOCKED
 346  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
 347  *         to release uCode to clear all Tx and command queues, enter
 348  *         unassociated mode, and power down.
 349  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
 350  *     1:  SW_BIT_RFKILL
 351  *         Host sets this when issuing CARD_STATE command to request
 352  *         device sleep.
 353  *     0:  MAC_SLEEP
 354  *         uCode sets this when preparing a power-saving power-down.
 355  *         uCode resets this when power-up is complete and SRAM is sane.
 356  *         NOTE:  device saves internal SRAM data to host when powering down,
 357  *                and must restore this data after powering back up.
 358  *                MAC_SLEEP is the best indication that restore is complete.
 359  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 360  *                do not need to save/restore it.
 361  */
 362 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 363 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 364 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 365 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 366 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE       (0x00000020)
 367
 368 /* GP Driver */
 369 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK         (0x00000003)
 370 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB     (0x00000000)
 371 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB     (0x00000001)
 372 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA     (0x00000002)
 373 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6        (0x00000004)
 374 #define CSR_GP_DRIVER_REG_BIT_6050_1x2              (0x00000008)
 375
 376 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER        (0x00000080)
 377
 378 /* GIO Chicken Bits (PCI Express bus link power management) */
 379 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 380 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 381
 382 /* LED */
 383 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 384 #define CSR_LED_REG_TRUN_ON (0x78)
 385 #define CSR_LED_REG_TRUN_OFF (0x38)
 386
 387 /* ANA_PLL */
 388 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 389
 390 /* HPET MEM debug */
 391 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 392
 393 /* DRAM INT TABLE */
 394 #define CSR_DRAM_INT_TBL_ENABLE         (1 << 31)
 395 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
 396
 397 /*
 398  * HBUS (Host-side Bus)
 399  *
 400  * HBUS registers are mapped directly into PCI bus space, but are used
 401  * to indirectly access device's internal memory or registers that
 402  * may be powered-down.
 403  *
 404  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
 405  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
 406  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
 407  * internal resources.
 408  *
 409  * Do not use iwl_write32()/iwl_read32() family to access these registers;
 410  * these provide only simple PCI bus access, without waking up the MAC.
 411  */
 412 #define HBUS_BASE       (0x400)
 413
 414 /*
 415  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 416  * structures, error log, event log, verifying uCode load).
 417  * First write to address register, then read from or write to data register
 418  * to complete the job.  Once the address register is set up, accesses to
 419  * data registers auto-increment the address by one dword.
 420  * Bit usage for address registers (read or write):
 421  *  0-31:  memory address within device
 422  */
 423 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 424 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 425 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 426 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 427
 428 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
 429 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 430 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 431
 432 /*
 433  * Registers for accessing device's internal peripheral registers
 434  * (e.g. SCD, BSM, etc.).  First write to address register,
 435  * then read from or write to data register to complete the job.
 436  * Bit usage for address registers (read or write):
 437  *  0-15:  register address (offset) within device
 438  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 439  */
 440 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 441 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 442 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 443 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 444
 445 /* Used to enable DBGM */
 446 #define HBUS_TARG_TEST_REG      (HBUS_BASE+0x05c)
 447
 448 /*
 449  * Per-Tx-queue write pointer (index, really!)
 450  * Indicates index to next TFD that driver will fill (1 past latest filled).
 451  * Bit usage:
 452  *  0-7:  queue write index
 453  * 11-8:  queue selector
 454  */
 455 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 456
 457 /**********************************************************
 458  * CSR values
 459  **********************************************************/
 460  /*
 461  * host interrupt timeout value
 462  * used with setting interrupt coalescing timer
 463  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
 464  *
 465  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
 466  * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
 467  */
 468 #define IWL_HOST_INT_TIMEOUT_MAX        (0xFF)
 469 #define IWL_HOST_INT_TIMEOUT_DEF        (0x40)
 470 #define IWL_HOST_INT_TIMEOUT_MIN        (0x0)
 471 #define IWL_HOST_INT_CALIB_TIMEOUT_MAX  (0xFF)
 472 #define IWL_HOST_INT_CALIB_TIMEOUT_DEF  (0x10)
 473 #define IWL_HOST_INT_CALIB_TIMEOUT_MIN  (0x0)
 474
 475 #endif /* !__iwl_csr_h__ */