drivers/net/wireless/iwlwifi/iwl-csr.h

   1 /******************************************************************************
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   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
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   8  * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
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  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
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  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
  34  * All rights reserved.
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  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
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  40  *  * Redistributions of source code must retain the above copyright
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  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
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  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*=== CSR (control and status registers) ===*/
  66 #define CSR_BASE    (0x000)
  67
  68 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  69 #define CSR_INT_COALESCING     (CSR_BASE+0x004) /* accum ints, 32-usec units */
  70 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  71 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  72 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  73 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  74 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  75 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  76
  77 /*
  78  * Hardware revision info
  79  * Bit fields:
  80  * 31-8:  Reserved
  81  *  7-4:  Type of device:  0x0 = 4965, 0xd = 3945
  82  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
  83  *  1-0:  "Dash" value, as in A-1, etc.
  84  *
  85  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
  86  */
  87 #define CSR_HW_REV              (CSR_BASE+0x028)
  88
  89 /* EEPROM reads */
  90 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
  91 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
  92 #define CSR_OTP_GP_REG          (CSR_BASE+0x034)
  93 #define CSR_GIO_REG             (CSR_BASE+0x03C)
  94 #define CSR_GP_UCODE            (CSR_BASE+0x044)
  95 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
  96 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
  97 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
  98 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
  99 #define CSR_LED_REG             (CSR_BASE+0x094)
 100 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
 101 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 102
 103 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
 104 /* Analog phase-lock-loop configuration  */
 105 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 106 /*
 107  * Indicates hardware rev, to determine CCK backoff for txpower calculation.
 108  * Bit fields:
 109  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 110  */
 111 #define CSR_HW_REV_WA_REG       (CSR_BASE+0x22C)
 112 #define CSR_DBG_HPET_MEM_REG    (CSR_BASE+0x240)
 113
 114 /* Bits for CSR_HW_IF_CONFIG_REG */
 115 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R       (0x00000010)
 116 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 117 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 118 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 119
 120 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
 121 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
 122 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 123 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 124 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 125 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 126
 127 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A           (0x00080000)
 128 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM         (0x00200000)
 129 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY              (0x00400000)
 130 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE       (0x02000000)
 131 #define CSR_HW_IF_CONFIG_REG_PREPARE                    (0x08000000)
 132
 133 #define CSR_INT_PERIODIC_DIS                    (0x00)
 134 #define CSR_INT_PERIODIC_ENA                    (0xFF)
 135
 136 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 137  * acknowledged (reset) by host writing "1" to flagged bits. */
 138 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 139 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 140 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28) /* Rx periodic */
 141 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 142 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 143 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 144 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 145 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 146 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
 147 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 148 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 149
 150 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 151                                  CSR_INT_BIT_HW_ERR  | \
 152                                  CSR_INT_BIT_FH_TX   | \
 153                                  CSR_INT_BIT_SW_ERR  | \
 154                                  CSR_INT_BIT_RF_KILL | \
 155                                  CSR_INT_BIT_SW_RX   | \
 156                                  CSR_INT_BIT_WAKEUP  | \
 157                                  CSR_INT_BIT_ALIVE)
 158
 159 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 160 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 161 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 162 #define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
 163 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 164 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 165 #define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
 166 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 167 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 168
 169 #define CSR39_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 170                                  CSR39_FH_INT_BIT_RX_CHNL2 | \
 171                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 172                                  CSR_FH_INT_BIT_RX_CHNL0)
 173
 174
 175 #define CSR39_FH_INT_TX_MASK    (CSR39_FH_INT_BIT_TX_CHNL6 | \
 176                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 177                                  CSR_FH_INT_BIT_TX_CHNL0)
 178
 179 #define CSR49_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 180                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 181                                  CSR_FH_INT_BIT_RX_CHNL0)
 182
 183 #define CSR49_FH_INT_TX_MASK    (CSR_FH_INT_BIT_TX_CHNL1 | \
 184                                  CSR_FH_INT_BIT_TX_CHNL0)
 185
 186 /* GPIO */
 187 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 188 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 189 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 190
 191 /* RESET */
 192 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 193 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 194 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 195 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 196 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 197
 198 /* GP (general purpose) CONTROL */
 199 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 200 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 201 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 202 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 203
 204 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 205
 206 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 207 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 208 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 209
 210
 211 /* HW REV */
 212 #define CSR_HW_REV_TYPE_MSK            (0x00000F0)
 213 #define CSR_HW_REV_TYPE_3945           (0x00000D0)
 214 #define CSR_HW_REV_TYPE_4965           (0x0000000)
 215 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 216 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 217 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 218 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 219 #define CSR_HW_REV_TYPE_1000           (0x0000060)
 220 #define CSR_HW_REV_TYPE_6x00           (0x0000070)
 221 #define CSR_HW_REV_TYPE_6x50           (0x0000080)
 222 #define CSR_HW_REV_TYPE_NONE           (0x00000F0)
 223
 224 /* EEPROM REG */
 225 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 226 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 227 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 228 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 229
 230 /* EEPROM GP */
 231 #define CSR_EEPROM_GP_VALID_MSK         (0x00000007)
 232 #define CSR_EEPROM_GP_BAD_SIGNATURE     (0x00000000)
 233 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 234 #define CSR_OTP_GP_REG_DEVICE_SELECT    (0x00010000) /* 0 - EEPROM, 1 - OTP */
 235 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE  (0x00020000) /* 0 - absolute, 1 - relative */
 236 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
 237 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
 238
 239 /* CSR GIO */
 240 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 241
 242 /* UCODE DRV GP */
 243 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 244 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 245 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 246 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 247
 248 /* GI Chicken Bits */
 249 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 250 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 251
 252 /* LED */
 253 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 254 #define CSR_LED_REG_TRUN_ON (0x78)
 255 #define CSR_LED_REG_TRUN_OFF (0x38)
 256
 257 /* ANA_PLL */
 258 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
 259 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 260
 261 /* HPET MEM debug */
 262 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 263
 264 /* DRAM INT TABLE */
 265 #define CSR_DRAM_INT_TBL_ENABLE         (1 << 31)
 266 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
 267
 268 /*=== HBUS (Host-side Bus) ===*/
 269 #define HBUS_BASE       (0x400)
 270 /*
 271  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 272  * structures, error log, event log, verifying uCode load).
 273  * First write to address register, then read from or write to data register
 274  * to complete the job.  Once the address register is set up, accesses to
 275  * data registers auto-increment the address by one dword.
 276  * Bit usage for address registers (read or write):
 277  *  0-31:  memory address within device
 278  */
 279 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 280 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 281 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 282 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 283
 284 /*
 285  * Registers for accessing device's internal peripheral registers
 286  * (e.g. SCD, BSM, etc.).  First write to address register,
 287  * then read from or write to data register to complete the job.
 288  * Bit usage for address registers (read or write):
 289  *  0-15:  register address (offset) within device
 290  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 291  */
 292 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 293 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 294 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 295 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 296
 297 /*
 298  * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
 299  * Indicates index to next TFD that driver will fill (1 past latest filled).
 300  * Bit usage:
 301  *  0-7:  queue write index
 302  * 11-8:  queue selector
 303  */
 304 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 305 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 306
 307 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 308
 309
 310 #endif /* !__iwl_csr_h__ */