1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
69 #include <net/mac80211.h>
71 #include "iwl-commands.h"
74 #include "iwl-debug.h"
75 #include "iwl-eeprom.h"
78 /************************** EEPROM BANDS ****************************
80 * The iwl_eeprom_band definitions below provide the mapping from the
81 * EEPROM contents to the specific channel number supported for each
84 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
85 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
86 * The specific geography and calibration information for that channel
87 * is contained in the eeprom map itself.
89 * During init, we copy the eeprom information and channel map
90 * information into priv->channel_info_24/52 and priv->channel_map_24/52
92 * channel_map_24/52 provides the index in the channel_info array for a
93 * given channel. We have to have two separate maps as there is channel
94 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * A value of 0xff stored in the channel_map indicates that the channel
98 * is not supported by the hardware at all.
100 * A value of 0xfe in the channel_map indicates that the channel is not
101 * valid for Tx with the current hardware. This means that
102 * while the system can tune and receive on a given channel, it may not
103 * be able to associate or transmit any frames on that
104 * channel. There is no corresponding channel information for that
107 *********************************************************************/
110 const u8 iwl_eeprom_band_1
[14] = {
111 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
115 static const u8 iwl_eeprom_band_2
[] = { /* 4915-5080MHz */
116 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119 static const u8 iwl_eeprom_band_3
[] = { /* 5170-5320MHz */
120 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123 static const u8 iwl_eeprom_band_4
[] = { /* 5500-5700MHz */
124 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127 static const u8 iwl_eeprom_band_5
[] = { /* 5725-5825MHz */
128 145, 149, 153, 157, 161, 165
131 static const u8 iwl_eeprom_band_6
[] = { /* 2.4 ht40 channel */
135 static const u8 iwl_eeprom_band_7
[] = { /* 5.2 ht40 channel */
136 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
140 * struct iwl_txpwr_section: eeprom section information
141 * @offset: indirect address into eeprom image
142 * @count: number of "struct iwl_eeprom_enhanced_txpwr" in this section
143 * @band: band type for the section
144 * @is_common - true: common section, false: channel section
145 * @is_cck - true: cck section, false: not cck section
146 * @is_ht_40 - true: all channel in the section are HT40 channel,
147 * false: legacy or HT 20 MHz
148 * ignore if it is common section
149 * @iwl_eeprom_section_channel: channel array in the section,
150 * ignore if common section
152 struct iwl_txpwr_section
{
155 enum ieee80211_band band
;
159 u8 iwl_eeprom_section_channel
[EEPROM_MAX_TXPOWER_SECTION_ELEMENTS
];
163 * section 1 - 3 are regulatory tx power apply to all channels based on
164 * modulation: CCK, OFDM
165 * Band: 2.4GHz, 5.2GHz
166 * section 4 - 10 are regulatory tx power apply to specified channels
168 * 1L - Channel 1 Legacy
170 * (1,+1) - Channel 1 HT40 "_above_"
172 * Section 1: all CCK channels
173 * Section 2: all 2.4 GHz OFDM (Legacy, HT and HT40) channels
174 * Section 3: all 5.2 GHz OFDM (Legacy, HT and HT40) channels
175 * Section 4: 2.4 GHz 20MHz channels: 1L, 1HT, 2L, 2HT, 10L, 10HT, 11L, 11HT
176 * Section 5: 2.4 GHz 40MHz channels: (1,+1) (2,+1) (6,+1) (7,+1) (9,+1)
177 * Section 6: 5.2 GHz 20MHz channels: 36L, 64L, 100L, 36HT, 64HT, 100HT
178 * Section 7: 5.2 GHz 40MHz channels: (36,+1) (60,+1) (100,+1)
179 * Section 8: 2.4 GHz channel: 13L, 13HT
180 * Section 9: 2.4 GHz channel: 140L, 140HT
181 * Section 10: 2.4 GHz 40MHz channels: (132,+1) (44,+1)
184 static const struct iwl_txpwr_section enhinfo
[] = {
185 { EEPROM_LB_CCK_20_COMMON
, 1, IEEE80211_BAND_2GHZ
, true, true, false },
186 { EEPROM_LB_OFDM_COMMON
, 3, IEEE80211_BAND_2GHZ
, true, false, false },
187 { EEPROM_HB_OFDM_COMMON
, 3, IEEE80211_BAND_5GHZ
, true, false, false },
188 { EEPROM_LB_OFDM_20_BAND
, 8, IEEE80211_BAND_2GHZ
,
190 {1, 1, 2, 2, 10, 10, 11, 11 } },
191 { EEPROM_LB_OFDM_HT40_BAND
, 5, IEEE80211_BAND_2GHZ
,
194 { EEPROM_HB_OFDM_20_BAND
, 6, IEEE80211_BAND_5GHZ
,
196 { 36, 64, 100, 36, 64, 100 } },
197 { EEPROM_HB_OFDM_HT40_BAND
, 3, IEEE80211_BAND_5GHZ
,
200 { EEPROM_LB_OFDM_20_CHANNEL_13
, 2, IEEE80211_BAND_2GHZ
,
203 { EEPROM_HB_OFDM_20_CHANNEL_140
, 2, IEEE80211_BAND_5GHZ
,
206 { EEPROM_HB_OFDM_HT40_BAND_1
, 2, IEEE80211_BAND_5GHZ
,
211 /******************************************************************************
213 * EEPROM related functions
215 ******************************************************************************/
217 static int iwl_eeprom_verify_signature(struct iwl_priv
*priv
)
219 u32 gp
= iwl_read32(priv
, CSR_EEPROM_GP
) & CSR_EEPROM_GP_VALID_MSK
;
222 IWL_DEBUG_INFO(priv
, "EEPROM signature=0x%08x\n", gp
);
224 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP
:
225 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_OTP
) {
226 IWL_ERR(priv
, "EEPROM with bad signature: 0x%08x\n",
231 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K
:
232 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K
:
233 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_EEPROM
) {
234 IWL_ERR(priv
, "OTP with bad signature: 0x%08x\n", gp
);
238 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP
:
240 IWL_ERR(priv
, "bad EEPROM/OTP signature, type=%s, "
241 "EEPROM_GP=0x%08x\n",
242 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
243 ? "OTP" : "EEPROM", gp
);
250 static void iwl_set_otp_access(struct iwl_priv
*priv
, enum iwl_access_mode mode
)
254 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
255 if (mode
== IWL_OTP_ACCESS_ABSOLUTE
)
256 iwl_clear_bit(priv
, CSR_OTP_GP_REG
,
257 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
259 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
260 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
263 static int iwlcore_get_nvm_type(struct iwl_priv
*priv
)
268 /* OTP only valid for CP/PP and after */
269 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
270 case CSR_HW_REV_TYPE_NONE
:
271 IWL_ERR(priv
, "Unknown hardware type\n");
273 case CSR_HW_REV_TYPE_3945
:
274 case CSR_HW_REV_TYPE_4965
:
275 case CSR_HW_REV_TYPE_5300
:
276 case CSR_HW_REV_TYPE_5350
:
277 case CSR_HW_REV_TYPE_5100
:
278 case CSR_HW_REV_TYPE_5150
:
279 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
282 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
283 if (otpgp
& CSR_OTP_GP_REG_DEVICE_SELECT
)
284 nvm_type
= NVM_DEVICE_TYPE_OTP
;
286 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
293 * The device's EEPROM semaphore prevents conflicts between driver and uCode
294 * when accessing the EEPROM; each access is a series of pulses to/from the
295 * EEPROM chip, not a single event, so even reads could conflict if they
296 * weren't arbitrated by the semaphore.
298 int iwlcore_eeprom_acquire_semaphore(struct iwl_priv
*priv
)
303 for (count
= 0; count
< EEPROM_SEM_RETRY_LIMIT
; count
++) {
304 /* Request semaphore */
305 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
306 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
);
308 /* See if we got it */
309 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
310 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
,
311 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
,
314 IWL_DEBUG_IO(priv
, "Acquired semaphore after %d tries.\n",
322 EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore
);
324 void iwlcore_eeprom_release_semaphore(struct iwl_priv
*priv
)
326 iwl_clear_bit(priv
, CSR_HW_IF_CONFIG_REG
,
327 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
);
330 EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore
);
332 const u8
*iwlcore_eeprom_query_addr(const struct iwl_priv
*priv
, size_t offset
)
334 BUG_ON(offset
>= priv
->cfg
->base_params
->eeprom_size
);
335 return &priv
->eeprom
[offset
];
337 EXPORT_SYMBOL(iwlcore_eeprom_query_addr
);
339 static int iwl_init_otp_access(struct iwl_priv
*priv
)
343 /* Enable 40MHz radio clock */
344 _iwl_write32(priv
, CSR_GP_CNTRL
,
345 _iwl_read32(priv
, CSR_GP_CNTRL
) |
346 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
348 /* wait for clock to be ready */
349 ret
= iwl_poll_bit(priv
, CSR_GP_CNTRL
,
350 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
351 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
354 IWL_ERR(priv
, "Time out access OTP\n");
356 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
,
357 APMG_PS_CTRL_VAL_RESET_REQ
);
359 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
,
360 APMG_PS_CTRL_VAL_RESET_REQ
);
363 * CSR auto clock gate disable bit -
364 * this is only applicable for HW with OTP shadow RAM
366 if (priv
->cfg
->base_params
->shadow_ram_support
)
367 iwl_set_bit(priv
, CSR_DBG_LINK_PWR_MGMT_REG
,
368 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
373 static int iwl_read_otp_word(struct iwl_priv
*priv
, u16 addr
, __le16
*eeprom_data
)
379 _iwl_write32(priv
, CSR_EEPROM_REG
,
380 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
381 ret
= iwl_poll_bit(priv
, CSR_EEPROM_REG
,
382 CSR_EEPROM_REG_READ_VALID_MSK
,
383 CSR_EEPROM_REG_READ_VALID_MSK
,
384 IWL_EEPROM_ACCESS_TIMEOUT
);
386 IWL_ERR(priv
, "Time out reading OTP[%d]\n", addr
);
389 r
= _iwl_read_direct32(priv
, CSR_EEPROM_REG
);
390 /* check for ECC errors: */
391 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
392 if (otpgp
& CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
) {
393 /* stop in this case */
394 /* set the uncorrectable OTP ECC bit for acknowledgement */
395 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
396 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
397 IWL_ERR(priv
, "Uncorrectable OTP ECC error, abort OTP read\n");
400 if (otpgp
& CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
) {
401 /* continue in this case */
402 /* set the correctable OTP ECC bit for acknowledgement */
403 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
404 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
);
405 IWL_ERR(priv
, "Correctable OTP ECC error, continue read\n");
407 *eeprom_data
= cpu_to_le16(r
>> 16);
412 * iwl_is_otp_empty: check for empty OTP
414 static bool iwl_is_otp_empty(struct iwl_priv
*priv
)
416 u16 next_link_addr
= 0;
418 bool is_empty
= false;
420 /* locate the beginning of OTP link list */
421 if (!iwl_read_otp_word(priv
, next_link_addr
, &link_value
)) {
423 IWL_ERR(priv
, "OTP is empty\n");
427 IWL_ERR(priv
, "Unable to read first block of OTP list.\n");
436 * iwl_find_otp_image: find EEPROM image in OTP
437 * finding the OTP block that contains the EEPROM image.
438 * the last valid block on the link list (the block _before_ the last block)
439 * is the block we should read and used to configure the device.
440 * If all the available OTP blocks are full, the last block will be the block
441 * we should read and used to configure the device.
442 * only perform this operation if shadow RAM is disabled
444 static int iwl_find_otp_image(struct iwl_priv
*priv
,
447 u16 next_link_addr
= 0, valid_addr
;
448 __le16 link_value
= 0;
451 /* set addressing mode to absolute to traverse the link list */
452 iwl_set_otp_access(priv
, IWL_OTP_ACCESS_ABSOLUTE
);
454 /* checking for empty OTP or error */
455 if (iwl_is_otp_empty(priv
))
459 * start traverse link list
460 * until reach the max number of OTP blocks
461 * different devices have different number of OTP blocks
464 /* save current valid block address
465 * check for more block on the link list
467 valid_addr
= next_link_addr
;
468 next_link_addr
= le16_to_cpu(link_value
) * sizeof(u16
);
469 IWL_DEBUG_INFO(priv
, "OTP blocks %d addr 0x%x\n",
470 usedblocks
, next_link_addr
);
471 if (iwl_read_otp_word(priv
, next_link_addr
, &link_value
))
475 * reach the end of link list, return success and
476 * set address point to the starting address
479 *validblockaddr
= valid_addr
;
480 /* skip first 2 bytes (link list pointer) */
481 *validblockaddr
+= 2;
484 /* more in the link list, continue */
486 } while (usedblocks
<= priv
->cfg
->base_params
->max_ll_items
);
488 /* OTP has no valid blocks */
489 IWL_DEBUG_INFO(priv
, "OTP has no valid blocks\n");
494 * iwl_eeprom_init - read EEPROM contents
496 * Load the EEPROM contents from adapter into priv->eeprom
498 * NOTE: This routine uses the non-debug IO access functions.
500 int iwl_eeprom_init(struct iwl_priv
*priv
)
503 u32 gp
= iwl_read32(priv
, CSR_EEPROM_GP
);
507 u16 validblockaddr
= 0;
510 priv
->nvm_device_type
= iwlcore_get_nvm_type(priv
);
511 if (priv
->nvm_device_type
== -ENOENT
)
513 /* allocate eeprom */
514 sz
= priv
->cfg
->base_params
->eeprom_size
;
515 IWL_DEBUG_INFO(priv
, "NVM size = %d\n", sz
);
516 priv
->eeprom
= kzalloc(sz
, GFP_KERNEL
);
521 e
= (__le16
*)priv
->eeprom
;
523 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
525 ret
= iwl_eeprom_verify_signature(priv
);
527 IWL_ERR(priv
, "EEPROM not found, EEPROM_GP=0x%08x\n", gp
);
532 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
533 ret
= priv
->cfg
->ops
->lib
->eeprom_ops
.acquire_semaphore(priv
);
535 IWL_ERR(priv
, "Failed to acquire EEPROM semaphore.\n");
540 if (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
) {
542 ret
= iwl_init_otp_access(priv
);
544 IWL_ERR(priv
, "Failed to initialize OTP access.\n");
548 _iwl_write32(priv
, CSR_EEPROM_GP
,
549 iwl_read32(priv
, CSR_EEPROM_GP
) &
550 ~CSR_EEPROM_GP_IF_OWNER_MSK
);
552 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
553 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
|
554 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
555 /* traversing the linked list if no shadow ram supported */
556 if (!priv
->cfg
->base_params
->shadow_ram_support
) {
557 if (iwl_find_otp_image(priv
, &validblockaddr
)) {
562 for (addr
= validblockaddr
; addr
< validblockaddr
+ sz
;
563 addr
+= sizeof(u16
)) {
566 ret
= iwl_read_otp_word(priv
, addr
, &eeprom_data
);
569 e
[cache_addr
/ 2] = eeprom_data
;
570 cache_addr
+= sizeof(u16
);
573 /* eeprom is an array of 16bit values */
574 for (addr
= 0; addr
< sz
; addr
+= sizeof(u16
)) {
577 _iwl_write32(priv
, CSR_EEPROM_REG
,
578 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
580 ret
= iwl_poll_bit(priv
, CSR_EEPROM_REG
,
581 CSR_EEPROM_REG_READ_VALID_MSK
,
582 CSR_EEPROM_REG_READ_VALID_MSK
,
583 IWL_EEPROM_ACCESS_TIMEOUT
);
585 IWL_ERR(priv
, "Time out reading EEPROM[%d]\n", addr
);
588 r
= _iwl_read_direct32(priv
, CSR_EEPROM_REG
);
589 e
[addr
/ 2] = cpu_to_le16(r
>> 16);
593 IWL_DEBUG_INFO(priv
, "NVM Type: %s, version: 0x%x\n",
594 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
596 iwl_eeprom_query16(priv
, EEPROM_VERSION
));
600 priv
->cfg
->ops
->lib
->eeprom_ops
.release_semaphore(priv
);
604 iwl_eeprom_free(priv
);
605 /* Reset chip to save power until we load uCode during "up". */
610 EXPORT_SYMBOL(iwl_eeprom_init
);
612 void iwl_eeprom_free(struct iwl_priv
*priv
)
617 EXPORT_SYMBOL(iwl_eeprom_free
);
619 int iwl_eeprom_check_version(struct iwl_priv
*priv
)
624 eeprom_ver
= iwl_eeprom_query16(priv
, EEPROM_VERSION
);
625 calib_ver
= priv
->cfg
->ops
->lib
->eeprom_ops
.calib_version(priv
);
627 if (eeprom_ver
< priv
->cfg
->eeprom_ver
||
628 calib_ver
< priv
->cfg
->eeprom_calib_ver
)
631 IWL_INFO(priv
, "device EEPROM VER=0x%x, CALIB=0x%x\n",
632 eeprom_ver
, calib_ver
);
636 IWL_ERR(priv
, "Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
637 eeprom_ver
, priv
->cfg
->eeprom_ver
,
638 calib_ver
, priv
->cfg
->eeprom_calib_ver
);
642 EXPORT_SYMBOL(iwl_eeprom_check_version
);
644 const u8
*iwl_eeprom_query_addr(const struct iwl_priv
*priv
, size_t offset
)
646 return priv
->cfg
->ops
->lib
->eeprom_ops
.query_addr(priv
, offset
);
648 EXPORT_SYMBOL(iwl_eeprom_query_addr
);
650 u16
iwl_eeprom_query16(const struct iwl_priv
*priv
, size_t offset
)
654 return (u16
)priv
->eeprom
[offset
] | ((u16
)priv
->eeprom
[offset
+ 1] << 8);
656 EXPORT_SYMBOL(iwl_eeprom_query16
);
658 void iwl_eeprom_get_mac(const struct iwl_priv
*priv
, u8
*mac
)
660 const u8
*addr
= priv
->cfg
->ops
->lib
->eeprom_ops
.query_addr(priv
,
662 memcpy(mac
, addr
, ETH_ALEN
);
664 EXPORT_SYMBOL(iwl_eeprom_get_mac
);
666 static void iwl_init_band_reference(const struct iwl_priv
*priv
,
667 int eep_band
, int *eeprom_ch_count
,
668 const struct iwl_eeprom_channel
**eeprom_ch_info
,
669 const u8
**eeprom_ch_index
)
671 u32 offset
= priv
->cfg
->ops
->lib
->
672 eeprom_ops
.regulatory_bands
[eep_band
- 1];
674 case 1: /* 2.4GHz band */
675 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_1
);
676 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
677 iwl_eeprom_query_addr(priv
, offset
);
678 *eeprom_ch_index
= iwl_eeprom_band_1
;
680 case 2: /* 4.9GHz band */
681 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_2
);
682 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
683 iwl_eeprom_query_addr(priv
, offset
);
684 *eeprom_ch_index
= iwl_eeprom_band_2
;
686 case 3: /* 5.2GHz band */
687 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_3
);
688 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
689 iwl_eeprom_query_addr(priv
, offset
);
690 *eeprom_ch_index
= iwl_eeprom_band_3
;
692 case 4: /* 5.5GHz band */
693 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_4
);
694 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
695 iwl_eeprom_query_addr(priv
, offset
);
696 *eeprom_ch_index
= iwl_eeprom_band_4
;
698 case 5: /* 5.7GHz band */
699 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_5
);
700 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
701 iwl_eeprom_query_addr(priv
, offset
);
702 *eeprom_ch_index
= iwl_eeprom_band_5
;
704 case 6: /* 2.4GHz ht40 channels */
705 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_6
);
706 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
707 iwl_eeprom_query_addr(priv
, offset
);
708 *eeprom_ch_index
= iwl_eeprom_band_6
;
710 case 7: /* 5 GHz ht40 channels */
711 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_7
);
712 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
713 iwl_eeprom_query_addr(priv
, offset
);
714 *eeprom_ch_index
= iwl_eeprom_band_7
;
722 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
726 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
728 * Does not set up a command, or touch hardware.
730 static int iwl_mod_ht40_chan_info(struct iwl_priv
*priv
,
731 enum ieee80211_band band
, u16 channel
,
732 const struct iwl_eeprom_channel
*eeprom_ch
,
733 u8 clear_ht40_extension_channel
)
735 struct iwl_channel_info
*ch_info
;
737 ch_info
= (struct iwl_channel_info
*)
738 iwl_get_channel_info(priv
, band
, channel
);
740 if (!is_channel_valid(ch_info
))
743 IWL_DEBUG_INFO(priv
, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
744 " Ad-Hoc %ssupported\n",
746 is_channel_a_band(ch_info
) ?
748 CHECK_AND_PRINT(IBSS
),
749 CHECK_AND_PRINT(ACTIVE
),
750 CHECK_AND_PRINT(RADAR
),
751 CHECK_AND_PRINT(WIDE
),
752 CHECK_AND_PRINT(DFS
),
754 eeprom_ch
->max_power_avg
,
755 ((eeprom_ch
->flags
& EEPROM_CHANNEL_IBSS
)
756 && !(eeprom_ch
->flags
& EEPROM_CHANNEL_RADAR
)) ?
759 ch_info
->ht40_eeprom
= *eeprom_ch
;
760 ch_info
->ht40_max_power_avg
= eeprom_ch
->max_power_avg
;
761 ch_info
->ht40_flags
= eeprom_ch
->flags
;
762 if (eeprom_ch
->flags
& EEPROM_CHANNEL_VALID
)
763 ch_info
->ht40_extension_channel
&= ~clear_ht40_extension_channel
;
769 * iwl_get_max_txpower_avg - get the highest tx power from all chains.
770 * find the highest tx power from all chains for the channel
772 static s8
iwl_get_max_txpower_avg(struct iwl_priv
*priv
,
773 struct iwl_eeprom_enhanced_txpwr
*enhanced_txpower
,
774 int element
, s8
*max_txpower_in_half_dbm
)
776 s8 max_txpower_avg
= 0; /* (dBm) */
778 IWL_DEBUG_INFO(priv
, "%d - "
779 "chain_a: %d dB chain_b: %d dB "
780 "chain_c: %d dB mimo2: %d dB mimo3: %d dB\n",
782 enhanced_txpower
[element
].chain_a_max
>> 1,
783 enhanced_txpower
[element
].chain_b_max
>> 1,
784 enhanced_txpower
[element
].chain_c_max
>> 1,
785 enhanced_txpower
[element
].mimo2_max
>> 1,
786 enhanced_txpower
[element
].mimo3_max
>> 1);
787 /* Take the highest tx power from any valid chains */
788 if ((priv
->cfg
->valid_tx_ant
& ANT_A
) &&
789 (enhanced_txpower
[element
].chain_a_max
> max_txpower_avg
))
790 max_txpower_avg
= enhanced_txpower
[element
].chain_a_max
;
791 if ((priv
->cfg
->valid_tx_ant
& ANT_B
) &&
792 (enhanced_txpower
[element
].chain_b_max
> max_txpower_avg
))
793 max_txpower_avg
= enhanced_txpower
[element
].chain_b_max
;
794 if ((priv
->cfg
->valid_tx_ant
& ANT_C
) &&
795 (enhanced_txpower
[element
].chain_c_max
> max_txpower_avg
))
796 max_txpower_avg
= enhanced_txpower
[element
].chain_c_max
;
797 if (((priv
->cfg
->valid_tx_ant
== ANT_AB
) |
798 (priv
->cfg
->valid_tx_ant
== ANT_BC
) |
799 (priv
->cfg
->valid_tx_ant
== ANT_AC
)) &&
800 (enhanced_txpower
[element
].mimo2_max
> max_txpower_avg
))
801 max_txpower_avg
= enhanced_txpower
[element
].mimo2_max
;
802 if ((priv
->cfg
->valid_tx_ant
== ANT_ABC
) &&
803 (enhanced_txpower
[element
].mimo3_max
> max_txpower_avg
))
804 max_txpower_avg
= enhanced_txpower
[element
].mimo3_max
;
807 * max. tx power in EEPROM is in 1/2 dBm format
808 * convert from 1/2 dBm to dBm (round-up convert)
809 * but we also do not want to loss 1/2 dBm resolution which
810 * will impact performance
812 *max_txpower_in_half_dbm
= max_txpower_avg
;
813 return (max_txpower_avg
& 0x01) + (max_txpower_avg
>> 1);
817 * iwl_update_common_txpower: update channel tx power
818 * update tx power per band based on EEPROM enhanced tx power info.
820 static s8
iwl_update_common_txpower(struct iwl_priv
*priv
,
821 struct iwl_eeprom_enhanced_txpwr
*enhanced_txpower
,
822 int section
, int element
, s8
*max_txpower_in_half_dbm
)
824 struct iwl_channel_info
*ch_info
;
826 bool is_ht40
= false;
827 s8 max_txpower_avg
; /* (dBm) */
829 /* it is common section, contain all type (Legacy, HT and HT40)
830 * based on the element in the section to determine
833 if (element
== EEPROM_TXPOWER_COMMON_HT40_INDEX
)
836 iwl_get_max_txpower_avg(priv
, enhanced_txpower
,
837 element
, max_txpower_in_half_dbm
);
839 ch_info
= priv
->channel_info
;
841 for (ch
= 0; ch
< priv
->channel_count
; ch
++) {
842 /* find matching band and update tx power if needed */
843 if ((ch_info
->band
== enhinfo
[section
].band
) &&
844 (ch_info
->max_power_avg
< max_txpower_avg
) &&
846 /* Update regulatory-based run-time data */
847 ch_info
->max_power_avg
= ch_info
->curr_txpow
=
849 ch_info
->scan_power
= max_txpower_avg
;
851 if ((ch_info
->band
== enhinfo
[section
].band
) && is_ht40
&&
852 (ch_info
->ht40_max_power_avg
< max_txpower_avg
)) {
853 /* Update regulatory-based run-time data */
854 ch_info
->ht40_max_power_avg
= max_txpower_avg
;
858 return max_txpower_avg
;
862 * iwl_update_channel_txpower: update channel tx power
863 * update channel tx power based on EEPROM enhanced tx power info.
865 static s8
iwl_update_channel_txpower(struct iwl_priv
*priv
,
866 struct iwl_eeprom_enhanced_txpwr
*enhanced_txpower
,
867 int section
, int element
, s8
*max_txpower_in_half_dbm
)
869 struct iwl_channel_info
*ch_info
;
872 s8 max_txpower_avg
; /* (dBm) */
874 channel
= enhinfo
[section
].iwl_eeprom_section_channel
[element
];
876 iwl_get_max_txpower_avg(priv
, enhanced_txpower
,
877 element
, max_txpower_in_half_dbm
);
879 ch_info
= priv
->channel_info
;
880 for (ch
= 0; ch
< priv
->channel_count
; ch
++) {
881 /* find matching channel and update tx power if needed */
882 if (ch_info
->channel
== channel
) {
883 if ((ch_info
->max_power_avg
< max_txpower_avg
) &&
884 (!enhinfo
[section
].is_ht40
)) {
885 /* Update regulatory-based run-time data */
886 ch_info
->max_power_avg
= max_txpower_avg
;
887 ch_info
->curr_txpow
= max_txpower_avg
;
888 ch_info
->scan_power
= max_txpower_avg
;
890 if ((enhinfo
[section
].is_ht40
) &&
891 (ch_info
->ht40_max_power_avg
< max_txpower_avg
)) {
892 /* Update regulatory-based run-time data */
893 ch_info
->ht40_max_power_avg
= max_txpower_avg
;
899 return max_txpower_avg
;
903 * iwlcore_eeprom_enhanced_txpower: process enhanced tx power info
905 void iwlcore_eeprom_enhanced_txpower(struct iwl_priv
*priv
)
907 int eeprom_section_count
= 0;
908 int section
, element
;
909 struct iwl_eeprom_enhanced_txpwr
*enhanced_txpower
;
911 s8 max_txpower_avg
; /* (dBm) */
912 s8 max_txpower_in_half_dbm
; /* (half-dBm) */
914 /* Loop through all the sections
915 * adjust bands and channel's max tx power
916 * Set the tx_power_user_lmt to the highest power
917 * supported by any channels and chains
919 for (section
= 0; section
< ARRAY_SIZE(enhinfo
); section
++) {
920 eeprom_section_count
= enhinfo
[section
].count
;
921 offset
= enhinfo
[section
].offset
;
922 enhanced_txpower
= (struct iwl_eeprom_enhanced_txpwr
*)
923 iwl_eeprom_query_addr(priv
, offset
);
926 * check for valid entry -
927 * different version of EEPROM might contain different set
928 * of enhanced tx power table
929 * always check for valid entry before process
932 if (!enhanced_txpower
->common
|| enhanced_txpower
->reserved
)
935 for (element
= 0; element
< eeprom_section_count
; element
++) {
936 if (enhinfo
[section
].is_common
)
938 iwl_update_common_txpower(priv
,
939 enhanced_txpower
, section
,
941 &max_txpower_in_half_dbm
);
944 iwl_update_channel_txpower(priv
,
945 enhanced_txpower
, section
,
947 &max_txpower_in_half_dbm
);
949 /* Update the tx_power_user_lmt to the highest power
950 * supported by any channel */
951 if (max_txpower_avg
> priv
->tx_power_user_lmt
)
952 priv
->tx_power_user_lmt
= max_txpower_avg
;
955 * Update the tx_power_lmt_in_half_dbm to
956 * the highest power supported by any channel
958 if (max_txpower_in_half_dbm
>
959 priv
->tx_power_lmt_in_half_dbm
)
960 priv
->tx_power_lmt_in_half_dbm
=
961 max_txpower_in_half_dbm
;
965 EXPORT_SYMBOL(iwlcore_eeprom_enhanced_txpower
);
967 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
971 * iwl_init_channel_map - Set up driver's info for all possible channels
973 int iwl_init_channel_map(struct iwl_priv
*priv
)
975 int eeprom_ch_count
= 0;
976 const u8
*eeprom_ch_index
= NULL
;
977 const struct iwl_eeprom_channel
*eeprom_ch_info
= NULL
;
979 struct iwl_channel_info
*ch_info
;
981 if (priv
->channel_count
) {
982 IWL_DEBUG_INFO(priv
, "Channel map already initialized.\n");
986 IWL_DEBUG_INFO(priv
, "Initializing regulatory info from EEPROM\n");
988 priv
->channel_count
=
989 ARRAY_SIZE(iwl_eeprom_band_1
) +
990 ARRAY_SIZE(iwl_eeprom_band_2
) +
991 ARRAY_SIZE(iwl_eeprom_band_3
) +
992 ARRAY_SIZE(iwl_eeprom_band_4
) +
993 ARRAY_SIZE(iwl_eeprom_band_5
);
995 IWL_DEBUG_INFO(priv
, "Parsing data for %d channels.\n", priv
->channel_count
);
997 priv
->channel_info
= kzalloc(sizeof(struct iwl_channel_info
) *
998 priv
->channel_count
, GFP_KERNEL
);
999 if (!priv
->channel_info
) {
1000 IWL_ERR(priv
, "Could not allocate channel_info\n");
1001 priv
->channel_count
= 0;
1005 ch_info
= priv
->channel_info
;
1007 /* Loop through the 5 EEPROM bands adding them in order to the
1008 * channel map we maintain (that contains additional information than
1009 * what just in the EEPROM) */
1010 for (band
= 1; band
<= 5; band
++) {
1012 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
1013 &eeprom_ch_info
, &eeprom_ch_index
);
1015 /* Loop through each band adding each of the channels */
1016 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
1017 ch_info
->channel
= eeprom_ch_index
[ch
];
1018 ch_info
->band
= (band
== 1) ? IEEE80211_BAND_2GHZ
:
1019 IEEE80211_BAND_5GHZ
;
1021 /* permanently store EEPROM's channel regulatory flags
1022 * and max power in channel info database. */
1023 ch_info
->eeprom
= eeprom_ch_info
[ch
];
1025 /* Copy the run-time flags so they are there even on
1026 * invalid channels */
1027 ch_info
->flags
= eeprom_ch_info
[ch
].flags
;
1028 /* First write that ht40 is not enabled, and then enable
1030 ch_info
->ht40_extension_channel
=
1031 IEEE80211_CHAN_NO_HT40
;
1033 if (!(is_channel_valid(ch_info
))) {
1034 IWL_DEBUG_INFO(priv
, "Ch. %d Flags %x [%sGHz] - "
1038 is_channel_a_band(ch_info
) ?
1044 /* Initialize regulatory-based run-time data */
1045 ch_info
->max_power_avg
= ch_info
->curr_txpow
=
1046 eeprom_ch_info
[ch
].max_power_avg
;
1047 ch_info
->scan_power
= eeprom_ch_info
[ch
].max_power_avg
;
1048 ch_info
->min_power
= 0;
1050 IWL_DEBUG_INFO(priv
, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
1051 " Ad-Hoc %ssupported\n",
1053 is_channel_a_band(ch_info
) ?
1055 CHECK_AND_PRINT_I(VALID
),
1056 CHECK_AND_PRINT_I(IBSS
),
1057 CHECK_AND_PRINT_I(ACTIVE
),
1058 CHECK_AND_PRINT_I(RADAR
),
1059 CHECK_AND_PRINT_I(WIDE
),
1060 CHECK_AND_PRINT_I(DFS
),
1061 eeprom_ch_info
[ch
].flags
,
1062 eeprom_ch_info
[ch
].max_power_avg
,
1063 ((eeprom_ch_info
[ch
].
1064 flags
& EEPROM_CHANNEL_IBSS
)
1065 && !(eeprom_ch_info
[ch
].
1066 flags
& EEPROM_CHANNEL_RADAR
))
1069 /* Set the tx_power_user_lmt to the highest power
1070 * supported by any channel */
1071 if (eeprom_ch_info
[ch
].max_power_avg
>
1072 priv
->tx_power_user_lmt
)
1073 priv
->tx_power_user_lmt
=
1074 eeprom_ch_info
[ch
].max_power_avg
;
1080 /* Check if we do have HT40 channels */
1081 if (priv
->cfg
->ops
->lib
->eeprom_ops
.regulatory_bands
[5] ==
1082 EEPROM_REGULATORY_BAND_NO_HT40
&&
1083 priv
->cfg
->ops
->lib
->eeprom_ops
.regulatory_bands
[6] ==
1084 EEPROM_REGULATORY_BAND_NO_HT40
)
1087 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1088 for (band
= 6; band
<= 7; band
++) {
1089 enum ieee80211_band ieeeband
;
1091 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
1092 &eeprom_ch_info
, &eeprom_ch_index
);
1094 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1096 (band
== 6) ? IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
1098 /* Loop through each band adding each of the channels */
1099 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
1100 /* Set up driver's info for lower half */
1101 iwl_mod_ht40_chan_info(priv
, ieeeband
,
1102 eeprom_ch_index
[ch
],
1103 &eeprom_ch_info
[ch
],
1104 IEEE80211_CHAN_NO_HT40PLUS
);
1106 /* Set up driver's info for upper half */
1107 iwl_mod_ht40_chan_info(priv
, ieeeband
,
1108 eeprom_ch_index
[ch
] + 4,
1109 &eeprom_ch_info
[ch
],
1110 IEEE80211_CHAN_NO_HT40MINUS
);
1114 /* for newer device (6000 series and up)
1115 * EEPROM contain enhanced tx power information
1116 * driver need to process addition information
1117 * to determine the max channel tx power limits
1119 if (priv
->cfg
->ops
->lib
->eeprom_ops
.update_enhanced_txpower
)
1120 priv
->cfg
->ops
->lib
->eeprom_ops
.update_enhanced_txpower(priv
);
1124 EXPORT_SYMBOL(iwl_init_channel_map
);
1127 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
1129 void iwl_free_channel_map(struct iwl_priv
*priv
)
1131 kfree(priv
->channel_info
);
1132 priv
->channel_count
= 0;
1134 EXPORT_SYMBOL(iwl_free_channel_map
);
1137 * iwl_get_channel_info - Find driver's private channel info
1139 * Based on band and channel number.
1141 const struct iwl_channel_info
*iwl_get_channel_info(const struct iwl_priv
*priv
,
1142 enum ieee80211_band band
, u16 channel
)
1147 case IEEE80211_BAND_5GHZ
:
1148 for (i
= 14; i
< priv
->channel_count
; i
++) {
1149 if (priv
->channel_info
[i
].channel
== channel
)
1150 return &priv
->channel_info
[i
];
1153 case IEEE80211_BAND_2GHZ
:
1154 if (channel
>= 1 && channel
<= 14)
1155 return &priv
->channel_info
[channel
- 1];
1163 EXPORT_SYMBOL(iwl_get_channel_info
);