1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
69 #include <net/mac80211.h>
72 #include "iwl-debug.h"
74 #include "iwl-eeprom.h"
78 /************************** EEPROM BANDS ****************************
80 * The iwl_eeprom_band definitions below provide the mapping from the
81 * EEPROM contents to the specific channel number supported for each
84 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
85 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
86 * The specific geography and calibration information for that channel
87 * is contained in the eeprom map itself.
89 * During init, we copy the eeprom information and channel map
90 * information into priv->channel_info_24/52 and priv->channel_map_24/52
92 * channel_map_24/52 provides the index in the channel_info array for a
93 * given channel. We have to have two separate maps as there is channel
94 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * A value of 0xff stored in the channel_map indicates that the channel
98 * is not supported by the hardware at all.
100 * A value of 0xfe in the channel_map indicates that the channel is not
101 * valid for Tx with the current hardware. This means that
102 * while the system can tune and receive on a given channel, it may not
103 * be able to associate or transmit any frames on that
104 * channel. There is no corresponding channel information for that
107 *********************************************************************/
110 const u8 iwl_eeprom_band_1
[14] = {
111 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
115 static const u8 iwl_eeprom_band_2
[] = { /* 4915-5080MHz */
116 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119 static const u8 iwl_eeprom_band_3
[] = { /* 5170-5320MHz */
120 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123 static const u8 iwl_eeprom_band_4
[] = { /* 5500-5700MHz */
124 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127 static const u8 iwl_eeprom_band_5
[] = { /* 5725-5825MHz */
128 145, 149, 153, 157, 161, 165
131 static const u8 iwl_eeprom_band_6
[] = { /* 2.4 ht40 channel */
135 static const u8 iwl_eeprom_band_7
[] = { /* 5.2 ht40 channel */
136 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
139 /******************************************************************************
141 * generic NVM functions
143 ******************************************************************************/
146 * The device's EEPROM semaphore prevents conflicts between driver and uCode
147 * when accessing the EEPROM; each access is a series of pulses to/from the
148 * EEPROM chip, not a single event, so even reads could conflict if they
149 * weren't arbitrated by the semaphore.
152 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
153 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
155 static int iwl_eeprom_acquire_semaphore(struct iwl_trans
*trans
)
160 for (count
= 0; count
< EEPROM_SEM_RETRY_LIMIT
; count
++) {
161 /* Request semaphore */
162 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
163 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
);
165 /* See if we got it */
166 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
167 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
,
168 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
,
171 IWL_DEBUG_EEPROM(trans
,
172 "Acquired semaphore after %d tries.\n",
181 static void iwl_eeprom_release_semaphore(struct iwl_trans
*trans
)
183 iwl_clear_bit(trans
, CSR_HW_IF_CONFIG_REG
,
184 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM
);
188 static int iwl_eeprom_verify_signature(struct iwl_priv
*priv
)
190 u32 gp
= iwl_read32(priv
->trans
, CSR_EEPROM_GP
) &
191 CSR_EEPROM_GP_VALID_MSK
;
194 IWL_DEBUG_EEPROM(priv
, "EEPROM signature=0x%08x\n", gp
);
196 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP
:
197 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_OTP
) {
198 IWL_ERR(priv
, "EEPROM with bad signature: 0x%08x\n",
203 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K
:
204 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K
:
205 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_EEPROM
) {
206 IWL_ERR(priv
, "OTP with bad signature: 0x%08x\n", gp
);
210 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP
:
212 IWL_ERR(priv
, "bad EEPROM/OTP signature, type=%s, "
213 "EEPROM_GP=0x%08x\n",
214 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
215 ? "OTP" : "EEPROM", gp
);
222 u16
iwl_eeprom_query16(struct iwl_priv
*priv
, size_t offset
)
226 return (u16
)priv
->eeprom
[offset
] | ((u16
)priv
->eeprom
[offset
+ 1] << 8);
229 int iwl_eeprom_check_version(struct iwl_priv
*priv
)
234 eeprom_ver
= iwl_eeprom_query16(priv
, EEPROM_VERSION
);
235 calib_ver
= iwl_eeprom_calib_version(priv
);
237 if (eeprom_ver
< priv
->cfg
->eeprom_ver
||
238 calib_ver
< priv
->cfg
->eeprom_calib_ver
)
241 IWL_INFO(priv
, "device EEPROM VER=0x%x, CALIB=0x%x\n",
242 eeprom_ver
, calib_ver
);
246 IWL_ERR(priv
, "Unsupported (too old) EEPROM VER=0x%x < 0x%x "
247 "CALIB=0x%x < 0x%x\n",
248 eeprom_ver
, priv
->cfg
->eeprom_ver
,
249 calib_ver
, priv
->cfg
->eeprom_calib_ver
);
254 int iwl_eeprom_init_hw_params(struct iwl_priv
*priv
)
258 priv
->hw_params
.sku
= iwl_eeprom_query16(priv
, EEPROM_SKU_CAP
);
259 if (priv
->hw_params
.sku
& EEPROM_SKU_CAP_11N_ENABLE
&&
260 !priv
->cfg
->ht_params
) {
261 IWL_ERR(priv
, "Invalid 11n configuration\n");
265 if (!priv
->hw_params
.sku
) {
266 IWL_ERR(priv
, "Invalid device sku\n");
270 IWL_INFO(priv
, "Device SKU: 0x%X\n", priv
->hw_params
.sku
);
272 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
274 priv
->hw_params
.valid_tx_ant
= EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg
);
275 priv
->hw_params
.valid_rx_ant
= EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg
);
277 /* check overrides (some devices have wrong EEPROM) */
278 if (priv
->cfg
->valid_tx_ant
)
279 priv
->hw_params
.valid_tx_ant
= priv
->cfg
->valid_tx_ant
;
280 if (priv
->cfg
->valid_rx_ant
)
281 priv
->hw_params
.valid_rx_ant
= priv
->cfg
->valid_rx_ant
;
283 if (!priv
->hw_params
.valid_tx_ant
|| !priv
->hw_params
.valid_rx_ant
) {
284 IWL_ERR(priv
, "Invalid chain (0x%X, 0x%X)\n",
285 priv
->hw_params
.valid_tx_ant
,
286 priv
->hw_params
.valid_rx_ant
);
290 IWL_INFO(priv
, "Valid Tx ant: 0x%X, Valid Rx ant: 0x%X\n",
291 priv
->hw_params
.valid_tx_ant
, priv
->hw_params
.valid_rx_ant
);
296 u16
iwl_eeprom_calib_version(struct iwl_priv
*priv
)
298 struct iwl_eeprom_calib_hdr
*hdr
;
300 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
305 static u32
eeprom_indirect_address(struct iwl_priv
*priv
, u32 address
)
309 if ((address
& INDIRECT_ADDRESS
) == 0)
312 switch (address
& INDIRECT_TYPE_MSK
) {
314 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_HOST
);
316 case INDIRECT_GENERAL
:
317 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_GENERAL
);
319 case INDIRECT_REGULATORY
:
320 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_REGULATORY
);
322 case INDIRECT_TXP_LIMIT
:
323 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_TXP_LIMIT
);
325 case INDIRECT_TXP_LIMIT_SIZE
:
326 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_TXP_LIMIT_SIZE
);
328 case INDIRECT_CALIBRATION
:
329 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_CALIBRATION
);
331 case INDIRECT_PROCESS_ADJST
:
332 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_PROCESS_ADJST
);
334 case INDIRECT_OTHERS
:
335 offset
= iwl_eeprom_query16(priv
, EEPROM_LINK_OTHERS
);
338 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
339 address
& INDIRECT_TYPE_MSK
);
343 /* translate the offset from words to byte */
344 return (address
& ADDRESS_MSK
) + (offset
<< 1);
347 const u8
*iwl_eeprom_query_addr(struct iwl_priv
*priv
, size_t offset
)
349 u32 address
= eeprom_indirect_address(priv
, offset
);
350 BUG_ON(address
>= priv
->cfg
->base_params
->eeprom_size
);
351 return &priv
->eeprom
[address
];
354 void iwl_eeprom_get_mac(struct iwl_priv
*priv
, u8
*mac
)
356 const u8
*addr
= iwl_eeprom_query_addr(priv
,
358 memcpy(mac
, addr
, ETH_ALEN
);
361 /******************************************************************************
363 * OTP related functions
365 ******************************************************************************/
367 static void iwl_set_otp_access(struct iwl_trans
*trans
,
368 enum iwl_access_mode mode
)
370 iwl_read32(trans
, CSR_OTP_GP_REG
);
372 if (mode
== IWL_OTP_ACCESS_ABSOLUTE
)
373 iwl_clear_bit(trans
, CSR_OTP_GP_REG
,
374 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
376 iwl_set_bit(trans
, CSR_OTP_GP_REG
,
377 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
380 static int iwl_get_nvm_type(struct iwl_trans
*trans
, u32 hw_rev
)
385 /* OTP only valid for CP/PP and after */
386 switch (hw_rev
& CSR_HW_REV_TYPE_MSK
) {
387 case CSR_HW_REV_TYPE_NONE
:
388 IWL_ERR(trans
, "Unknown hardware type\n");
390 case CSR_HW_REV_TYPE_5300
:
391 case CSR_HW_REV_TYPE_5350
:
392 case CSR_HW_REV_TYPE_5100
:
393 case CSR_HW_REV_TYPE_5150
:
394 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
397 otpgp
= iwl_read32(trans
, CSR_OTP_GP_REG
);
398 if (otpgp
& CSR_OTP_GP_REG_DEVICE_SELECT
)
399 nvm_type
= NVM_DEVICE_TYPE_OTP
;
401 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
407 static int iwl_init_otp_access(struct iwl_trans
*trans
)
411 /* Enable 40MHz radio clock */
412 iwl_write32(trans
, CSR_GP_CNTRL
,
413 iwl_read32(trans
, CSR_GP_CNTRL
) |
414 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
416 /* wait for clock to be ready */
417 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
418 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
419 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
422 IWL_ERR(trans
, "Time out access OTP\n");
424 iwl_set_bits_prph(trans
, APMG_PS_CTRL_REG
,
425 APMG_PS_CTRL_VAL_RESET_REQ
);
427 iwl_clear_bits_prph(trans
, APMG_PS_CTRL_REG
,
428 APMG_PS_CTRL_VAL_RESET_REQ
);
431 * CSR auto clock gate disable bit -
432 * this is only applicable for HW with OTP shadow RAM
434 if (trans
->cfg
->base_params
->shadow_ram_support
)
435 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
436 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
441 static int iwl_read_otp_word(struct iwl_trans
*trans
, u16 addr
,
448 iwl_write32(trans
, CSR_EEPROM_REG
,
449 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
450 ret
= iwl_poll_bit(trans
, CSR_EEPROM_REG
,
451 CSR_EEPROM_REG_READ_VALID_MSK
,
452 CSR_EEPROM_REG_READ_VALID_MSK
,
453 IWL_EEPROM_ACCESS_TIMEOUT
);
455 IWL_ERR(trans
, "Time out reading OTP[%d]\n", addr
);
458 r
= iwl_read32(trans
, CSR_EEPROM_REG
);
459 /* check for ECC errors: */
460 otpgp
= iwl_read32(trans
, CSR_OTP_GP_REG
);
461 if (otpgp
& CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
) {
462 /* stop in this case */
463 /* set the uncorrectable OTP ECC bit for acknowledgement */
464 iwl_set_bit(trans
, CSR_OTP_GP_REG
,
465 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
466 IWL_ERR(trans
, "Uncorrectable OTP ECC error, abort OTP read\n");
469 if (otpgp
& CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
) {
470 /* continue in this case */
471 /* set the correctable OTP ECC bit for acknowledgement */
472 iwl_set_bit(trans
, CSR_OTP_GP_REG
,
473 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
);
474 IWL_ERR(trans
, "Correctable OTP ECC error, continue read\n");
476 *eeprom_data
= cpu_to_le16(r
>> 16);
481 * iwl_is_otp_empty: check for empty OTP
483 static bool iwl_is_otp_empty(struct iwl_trans
*trans
)
485 u16 next_link_addr
= 0;
487 bool is_empty
= false;
489 /* locate the beginning of OTP link list */
490 if (!iwl_read_otp_word(trans
, next_link_addr
, &link_value
)) {
492 IWL_ERR(trans
, "OTP is empty\n");
496 IWL_ERR(trans
, "Unable to read first block of OTP list.\n");
505 * iwl_find_otp_image: find EEPROM image in OTP
506 * finding the OTP block that contains the EEPROM image.
507 * the last valid block on the link list (the block _before_ the last block)
508 * is the block we should read and used to configure the device.
509 * If all the available OTP blocks are full, the last block will be the block
510 * we should read and used to configure the device.
511 * only perform this operation if shadow RAM is disabled
513 static int iwl_find_otp_image(struct iwl_trans
*trans
,
516 u16 next_link_addr
= 0, valid_addr
;
517 __le16 link_value
= 0;
520 /* set addressing mode to absolute to traverse the link list */
521 iwl_set_otp_access(trans
, IWL_OTP_ACCESS_ABSOLUTE
);
523 /* checking for empty OTP or error */
524 if (iwl_is_otp_empty(trans
))
528 * start traverse link list
529 * until reach the max number of OTP blocks
530 * different devices have different number of OTP blocks
533 /* save current valid block address
534 * check for more block on the link list
536 valid_addr
= next_link_addr
;
537 next_link_addr
= le16_to_cpu(link_value
) * sizeof(u16
);
538 IWL_DEBUG_EEPROM(trans
, "OTP blocks %d addr 0x%x\n",
539 usedblocks
, next_link_addr
);
540 if (iwl_read_otp_word(trans
, next_link_addr
, &link_value
))
544 * reach the end of link list, return success and
545 * set address point to the starting address
548 *validblockaddr
= valid_addr
;
549 /* skip first 2 bytes (link list pointer) */
550 *validblockaddr
+= 2;
553 /* more in the link list, continue */
555 } while (usedblocks
<= trans
->cfg
->base_params
->max_ll_items
);
557 /* OTP has no valid blocks */
558 IWL_DEBUG_EEPROM(trans
, "OTP has no valid blocks\n");
562 /******************************************************************************
564 * Tx Power related functions
566 ******************************************************************************/
568 * iwl_get_max_txpower_avg - get the highest tx power from all chains.
569 * find the highest tx power from all chains for the channel
571 static s8
iwl_get_max_txpower_avg(struct iwl_priv
*priv
,
572 struct iwl_eeprom_enhanced_txpwr
*enhanced_txpower
,
573 int element
, s8
*max_txpower_in_half_dbm
)
575 s8 max_txpower_avg
= 0; /* (dBm) */
577 /* Take the highest tx power from any valid chains */
578 if ((priv
->hw_params
.valid_tx_ant
& ANT_A
) &&
579 (enhanced_txpower
[element
].chain_a_max
> max_txpower_avg
))
580 max_txpower_avg
= enhanced_txpower
[element
].chain_a_max
;
581 if ((priv
->hw_params
.valid_tx_ant
& ANT_B
) &&
582 (enhanced_txpower
[element
].chain_b_max
> max_txpower_avg
))
583 max_txpower_avg
= enhanced_txpower
[element
].chain_b_max
;
584 if ((priv
->hw_params
.valid_tx_ant
& ANT_C
) &&
585 (enhanced_txpower
[element
].chain_c_max
> max_txpower_avg
))
586 max_txpower_avg
= enhanced_txpower
[element
].chain_c_max
;
587 if (((priv
->hw_params
.valid_tx_ant
== ANT_AB
) |
588 (priv
->hw_params
.valid_tx_ant
== ANT_BC
) |
589 (priv
->hw_params
.valid_tx_ant
== ANT_AC
)) &&
590 (enhanced_txpower
[element
].mimo2_max
> max_txpower_avg
))
591 max_txpower_avg
= enhanced_txpower
[element
].mimo2_max
;
592 if ((priv
->hw_params
.valid_tx_ant
== ANT_ABC
) &&
593 (enhanced_txpower
[element
].mimo3_max
> max_txpower_avg
))
594 max_txpower_avg
= enhanced_txpower
[element
].mimo3_max
;
597 * max. tx power in EEPROM is in 1/2 dBm format
598 * convert from 1/2 dBm to dBm (round-up convert)
599 * but we also do not want to loss 1/2 dBm resolution which
600 * will impact performance
602 *max_txpower_in_half_dbm
= max_txpower_avg
;
603 return (max_txpower_avg
& 0x01) + (max_txpower_avg
>> 1);
607 iwl_eeprom_enh_txp_read_element(struct iwl_priv
*priv
,
608 struct iwl_eeprom_enhanced_txpwr
*txp
,
612 bool is_ht40
= txp
->flags
& IWL_EEPROM_ENH_TXP_FL_40MHZ
;
613 enum ieee80211_band band
;
615 band
= txp
->flags
& IWL_EEPROM_ENH_TXP_FL_BAND_52G
?
616 IEEE80211_BAND_5GHZ
: IEEE80211_BAND_2GHZ
;
618 for (ch_idx
= 0; ch_idx
< priv
->channel_count
; ch_idx
++) {
619 struct iwl_channel_info
*ch_info
= &priv
->channel_info
[ch_idx
];
621 /* update matching channel or from common data only */
622 if (txp
->channel
!= 0 && ch_info
->channel
!= txp
->channel
)
625 /* update matching band only */
626 if (band
!= ch_info
->band
)
629 if (ch_info
->max_power_avg
< max_txpower_avg
&& !is_ht40
) {
630 ch_info
->max_power_avg
= max_txpower_avg
;
631 ch_info
->curr_txpow
= max_txpower_avg
;
632 ch_info
->scan_power
= max_txpower_avg
;
635 if (is_ht40
&& ch_info
->ht40_max_power_avg
< max_txpower_avg
)
636 ch_info
->ht40_max_power_avg
= max_txpower_avg
;
640 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
641 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
642 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
644 #define TXP_CHECK_AND_PRINT(x) ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) \
647 static void iwl_eeprom_enhanced_txpower(struct iwl_priv
*priv
)
649 struct iwl_eeprom_enhanced_txpwr
*txp_array
, *txp
;
652 s8 max_txp_avg
, max_txp_avg_halfdbm
;
654 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr
) != 8);
656 /* the length is in 16-bit words, but we want entries */
657 txp_len
= (__le16
*) iwl_eeprom_query_addr(priv
, EEPROM_TXP_SZ_OFFS
);
658 entries
= le16_to_cpup(txp_len
) * 2 / EEPROM_TXP_ENTRY_LEN
;
660 txp_array
= (void *) iwl_eeprom_query_addr(priv
, EEPROM_TXP_OFFS
);
662 for (idx
= 0; idx
< entries
; idx
++) {
663 txp
= &txp_array
[idx
];
664 /* skip invalid entries */
665 if (!(txp
->flags
& IWL_EEPROM_ENH_TXP_FL_VALID
))
668 IWL_DEBUG_EEPROM(priv
, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
669 (txp
->channel
&& (txp
->flags
&
670 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE
)) ?
671 "Common " : (txp
->channel
) ?
672 "Channel" : "Common",
674 TXP_CHECK_AND_PRINT(VALID
),
675 TXP_CHECK_AND_PRINT(BAND_52G
),
676 TXP_CHECK_AND_PRINT(OFDM
),
677 TXP_CHECK_AND_PRINT(40MHZ
),
678 TXP_CHECK_AND_PRINT(HT_AP
),
679 TXP_CHECK_AND_PRINT(RES1
),
680 TXP_CHECK_AND_PRINT(RES2
),
681 TXP_CHECK_AND_PRINT(COMMON_TYPE
),
683 IWL_DEBUG_EEPROM(priv
, "\t\t chain_A: 0x%02x "
684 "chain_B: 0X%02x chain_C: 0X%02x\n",
685 txp
->chain_a_max
, txp
->chain_b_max
,
687 IWL_DEBUG_EEPROM(priv
, "\t\t MIMO2: 0x%02x "
688 "MIMO3: 0x%02x High 20_on_40: 0x%02x "
689 "Low 20_on_40: 0x%02x\n",
690 txp
->mimo2_max
, txp
->mimo3_max
,
691 ((txp
->delta_20_in_40
& 0xf0) >> 4),
692 (txp
->delta_20_in_40
& 0x0f));
694 max_txp_avg
= iwl_get_max_txpower_avg(priv
, txp_array
, idx
,
695 &max_txp_avg_halfdbm
);
698 * Update the user limit values values to the highest
699 * power supported by any channel
701 if (max_txp_avg
> priv
->tx_power_user_lmt
)
702 priv
->tx_power_user_lmt
= max_txp_avg
;
703 if (max_txp_avg_halfdbm
> priv
->tx_power_lmt_in_half_dbm
)
704 priv
->tx_power_lmt_in_half_dbm
= max_txp_avg_halfdbm
;
706 iwl_eeprom_enh_txp_read_element(priv
, txp
, max_txp_avg
);
711 * iwl_eeprom_init - read EEPROM contents
713 * Load the EEPROM contents from adapter into priv->eeprom
715 * NOTE: This routine uses the non-debug IO access functions.
717 int iwl_eeprom_init(struct iwl_priv
*priv
, u32 hw_rev
)
720 u32 gp
= iwl_read32(priv
->trans
, CSR_EEPROM_GP
);
724 u16 validblockaddr
= 0;
727 priv
->nvm_device_type
= iwl_get_nvm_type(priv
->trans
, hw_rev
);
728 if (priv
->nvm_device_type
== -ENOENT
)
730 /* allocate eeprom */
731 sz
= priv
->cfg
->base_params
->eeprom_size
;
732 IWL_DEBUG_EEPROM(priv
, "NVM size = %d\n", sz
);
733 priv
->eeprom
= kzalloc(sz
, GFP_KERNEL
);
738 e
= (__le16
*)priv
->eeprom
;
740 ret
= iwl_eeprom_verify_signature(priv
);
742 IWL_ERR(priv
, "EEPROM not found, EEPROM_GP=0x%08x\n", gp
);
747 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
748 ret
= iwl_eeprom_acquire_semaphore(priv
->trans
);
750 IWL_ERR(priv
, "Failed to acquire EEPROM semaphore.\n");
755 if (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
) {
757 ret
= iwl_init_otp_access(priv
->trans
);
759 IWL_ERR(priv
, "Failed to initialize OTP access.\n");
763 iwl_write32(priv
->trans
, CSR_EEPROM_GP
,
764 iwl_read32(priv
->trans
, CSR_EEPROM_GP
) &
765 ~CSR_EEPROM_GP_IF_OWNER_MSK
);
767 iwl_set_bit(priv
->trans
, CSR_OTP_GP_REG
,
768 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
|
769 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
770 /* traversing the linked list if no shadow ram supported */
771 if (!priv
->cfg
->base_params
->shadow_ram_support
) {
772 if (iwl_find_otp_image(priv
->trans
, &validblockaddr
)) {
777 for (addr
= validblockaddr
; addr
< validblockaddr
+ sz
;
778 addr
+= sizeof(u16
)) {
781 ret
= iwl_read_otp_word(priv
->trans
, addr
,
785 e
[cache_addr
/ 2] = eeprom_data
;
786 cache_addr
+= sizeof(u16
);
789 /* eeprom is an array of 16bit values */
790 for (addr
= 0; addr
< sz
; addr
+= sizeof(u16
)) {
793 iwl_write32(priv
->trans
, CSR_EEPROM_REG
,
794 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
796 ret
= iwl_poll_bit(priv
->trans
, CSR_EEPROM_REG
,
797 CSR_EEPROM_REG_READ_VALID_MSK
,
798 CSR_EEPROM_REG_READ_VALID_MSK
,
799 IWL_EEPROM_ACCESS_TIMEOUT
);
802 "Time out reading EEPROM[%d]\n", addr
);
805 r
= iwl_read32(priv
->trans
, CSR_EEPROM_REG
);
806 e
[addr
/ 2] = cpu_to_le16(r
>> 16);
810 IWL_DEBUG_EEPROM(priv
, "NVM Type: %s, version: 0x%x\n",
811 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
813 iwl_eeprom_query16(priv
, EEPROM_VERSION
));
817 iwl_eeprom_release_semaphore(priv
->trans
);
821 iwl_eeprom_free(priv
);
826 void iwl_eeprom_free(struct iwl_priv
*priv
)
832 static void iwl_init_band_reference(struct iwl_priv
*priv
,
833 int eep_band
, int *eeprom_ch_count
,
834 const struct iwl_eeprom_channel
**eeprom_ch_info
,
835 const u8
**eeprom_ch_index
)
837 u32 offset
= priv
->lib
->
838 eeprom_ops
.regulatory_bands
[eep_band
- 1];
840 case 1: /* 2.4GHz band */
841 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_1
);
842 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
843 iwl_eeprom_query_addr(priv
, offset
);
844 *eeprom_ch_index
= iwl_eeprom_band_1
;
846 case 2: /* 4.9GHz band */
847 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_2
);
848 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
849 iwl_eeprom_query_addr(priv
, offset
);
850 *eeprom_ch_index
= iwl_eeprom_band_2
;
852 case 3: /* 5.2GHz band */
853 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_3
);
854 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
855 iwl_eeprom_query_addr(priv
, offset
);
856 *eeprom_ch_index
= iwl_eeprom_band_3
;
858 case 4: /* 5.5GHz band */
859 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_4
);
860 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
861 iwl_eeprom_query_addr(priv
, offset
);
862 *eeprom_ch_index
= iwl_eeprom_band_4
;
864 case 5: /* 5.7GHz band */
865 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_5
);
866 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
867 iwl_eeprom_query_addr(priv
, offset
);
868 *eeprom_ch_index
= iwl_eeprom_band_5
;
870 case 6: /* 2.4GHz ht40 channels */
871 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_6
);
872 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
873 iwl_eeprom_query_addr(priv
, offset
);
874 *eeprom_ch_index
= iwl_eeprom_band_6
;
876 case 7: /* 5 GHz ht40 channels */
877 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_7
);
878 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
879 iwl_eeprom_query_addr(priv
, offset
);
880 *eeprom_ch_index
= iwl_eeprom_band_7
;
888 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
891 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
893 * Does not set up a command, or touch hardware.
895 static int iwl_mod_ht40_chan_info(struct iwl_priv
*priv
,
896 enum ieee80211_band band
, u16 channel
,
897 const struct iwl_eeprom_channel
*eeprom_ch
,
898 u8 clear_ht40_extension_channel
)
900 struct iwl_channel_info
*ch_info
;
902 ch_info
= (struct iwl_channel_info
*)
903 iwl_get_channel_info(priv
, band
, channel
);
905 if (!is_channel_valid(ch_info
))
908 IWL_DEBUG_EEPROM(priv
, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
909 " Ad-Hoc %ssupported\n",
911 is_channel_a_band(ch_info
) ?
913 CHECK_AND_PRINT(IBSS
),
914 CHECK_AND_PRINT(ACTIVE
),
915 CHECK_AND_PRINT(RADAR
),
916 CHECK_AND_PRINT(WIDE
),
917 CHECK_AND_PRINT(DFS
),
919 eeprom_ch
->max_power_avg
,
920 ((eeprom_ch
->flags
& EEPROM_CHANNEL_IBSS
)
921 && !(eeprom_ch
->flags
& EEPROM_CHANNEL_RADAR
)) ?
924 ch_info
->ht40_eeprom
= *eeprom_ch
;
925 ch_info
->ht40_max_power_avg
= eeprom_ch
->max_power_avg
;
926 ch_info
->ht40_flags
= eeprom_ch
->flags
;
927 if (eeprom_ch
->flags
& EEPROM_CHANNEL_VALID
)
928 ch_info
->ht40_extension_channel
&= ~clear_ht40_extension_channel
;
933 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
937 * iwl_init_channel_map - Set up driver's info for all possible channels
939 int iwl_init_channel_map(struct iwl_priv
*priv
)
941 int eeprom_ch_count
= 0;
942 const u8
*eeprom_ch_index
= NULL
;
943 const struct iwl_eeprom_channel
*eeprom_ch_info
= NULL
;
945 struct iwl_channel_info
*ch_info
;
947 if (priv
->channel_count
) {
948 IWL_DEBUG_EEPROM(priv
, "Channel map already initialized.\n");
952 IWL_DEBUG_EEPROM(priv
, "Initializing regulatory info from EEPROM\n");
954 priv
->channel_count
=
955 ARRAY_SIZE(iwl_eeprom_band_1
) +
956 ARRAY_SIZE(iwl_eeprom_band_2
) +
957 ARRAY_SIZE(iwl_eeprom_band_3
) +
958 ARRAY_SIZE(iwl_eeprom_band_4
) +
959 ARRAY_SIZE(iwl_eeprom_band_5
);
961 IWL_DEBUG_EEPROM(priv
, "Parsing data for %d channels.\n",
962 priv
->channel_count
);
964 priv
->channel_info
= kcalloc(priv
->channel_count
,
965 sizeof(struct iwl_channel_info
),
967 if (!priv
->channel_info
) {
968 IWL_ERR(priv
, "Could not allocate channel_info\n");
969 priv
->channel_count
= 0;
973 ch_info
= priv
->channel_info
;
975 /* Loop through the 5 EEPROM bands adding them in order to the
976 * channel map we maintain (that contains additional information than
977 * what just in the EEPROM) */
978 for (band
= 1; band
<= 5; band
++) {
980 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
981 &eeprom_ch_info
, &eeprom_ch_index
);
983 /* Loop through each band adding each of the channels */
984 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
985 ch_info
->channel
= eeprom_ch_index
[ch
];
986 ch_info
->band
= (band
== 1) ? IEEE80211_BAND_2GHZ
:
989 /* permanently store EEPROM's channel regulatory flags
990 * and max power in channel info database. */
991 ch_info
->eeprom
= eeprom_ch_info
[ch
];
993 /* Copy the run-time flags so they are there even on
994 * invalid channels */
995 ch_info
->flags
= eeprom_ch_info
[ch
].flags
;
996 /* First write that ht40 is not enabled, and then enable
998 ch_info
->ht40_extension_channel
=
999 IEEE80211_CHAN_NO_HT40
;
1001 if (!(is_channel_valid(ch_info
))) {
1002 IWL_DEBUG_EEPROM(priv
,
1003 "Ch. %d Flags %x [%sGHz] - "
1007 is_channel_a_band(ch_info
) ?
1013 /* Initialize regulatory-based run-time data */
1014 ch_info
->max_power_avg
= ch_info
->curr_txpow
=
1015 eeprom_ch_info
[ch
].max_power_avg
;
1016 ch_info
->scan_power
= eeprom_ch_info
[ch
].max_power_avg
;
1017 ch_info
->min_power
= 0;
1019 IWL_DEBUG_EEPROM(priv
, "Ch. %d [%sGHz] "
1020 "%s%s%s%s%s%s(0x%02x %ddBm):"
1021 " Ad-Hoc %ssupported\n",
1023 is_channel_a_band(ch_info
) ?
1025 CHECK_AND_PRINT_I(VALID
),
1026 CHECK_AND_PRINT_I(IBSS
),
1027 CHECK_AND_PRINT_I(ACTIVE
),
1028 CHECK_AND_PRINT_I(RADAR
),
1029 CHECK_AND_PRINT_I(WIDE
),
1030 CHECK_AND_PRINT_I(DFS
),
1031 eeprom_ch_info
[ch
].flags
,
1032 eeprom_ch_info
[ch
].max_power_avg
,
1033 ((eeprom_ch_info
[ch
].
1034 flags
& EEPROM_CHANNEL_IBSS
)
1035 && !(eeprom_ch_info
[ch
].
1036 flags
& EEPROM_CHANNEL_RADAR
))
1043 /* Check if we do have HT40 channels */
1044 if (priv
->lib
->eeprom_ops
.regulatory_bands
[5] ==
1045 EEPROM_REGULATORY_BAND_NO_HT40
&&
1046 priv
->lib
->eeprom_ops
.regulatory_bands
[6] ==
1047 EEPROM_REGULATORY_BAND_NO_HT40
)
1050 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1051 for (band
= 6; band
<= 7; band
++) {
1052 enum ieee80211_band ieeeband
;
1054 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
1055 &eeprom_ch_info
, &eeprom_ch_index
);
1057 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1059 (band
== 6) ? IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
1061 /* Loop through each band adding each of the channels */
1062 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
1063 /* Set up driver's info for lower half */
1064 iwl_mod_ht40_chan_info(priv
, ieeeband
,
1065 eeprom_ch_index
[ch
],
1066 &eeprom_ch_info
[ch
],
1067 IEEE80211_CHAN_NO_HT40PLUS
);
1069 /* Set up driver's info for upper half */
1070 iwl_mod_ht40_chan_info(priv
, ieeeband
,
1071 eeprom_ch_index
[ch
] + 4,
1072 &eeprom_ch_info
[ch
],
1073 IEEE80211_CHAN_NO_HT40MINUS
);
1077 /* for newer device (6000 series and up)
1078 * EEPROM contain enhanced tx power information
1079 * driver need to process addition information
1080 * to determine the max channel tx power limits
1082 if (priv
->lib
->eeprom_ops
.enhanced_txpower
)
1083 iwl_eeprom_enhanced_txpower(priv
);
1089 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
1091 void iwl_free_channel_map(struct iwl_priv
*priv
)
1093 kfree(priv
->channel_info
);
1094 priv
->channel_count
= 0;
1098 * iwl_get_channel_info - Find driver's private channel info
1100 * Based on band and channel number.
1102 const struct iwl_channel_info
*iwl_get_channel_info(const struct iwl_priv
*priv
,
1103 enum ieee80211_band band
, u16 channel
)
1108 case IEEE80211_BAND_5GHZ
:
1109 for (i
= 14; i
< priv
->channel_count
; i
++) {
1110 if (priv
->channel_info
[i
].channel
== channel
)
1111 return &priv
->channel_info
[i
];
1114 case IEEE80211_BAND_2GHZ
:
1115 if (channel
>= 1 && channel
<= 14)
1116 return &priv
->channel_info
[channel
- 1];
1125 void iwl_rf_config(struct iwl_priv
*priv
)
1129 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
1131 /* write radio config values to register */
1132 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) <= EEPROM_RF_CONFIG_TYPE_MAX
) {
1133 iwl_set_bit(priv
->trans
, CSR_HW_IF_CONFIG_REG
,
1134 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
1135 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
1136 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
1137 IWL_INFO(priv
, "Radio type=0x%x-0x%x-0x%x\n",
1138 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
),
1139 EEPROM_RF_CFG_STEP_MSK(radio_cfg
),
1140 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
1144 /* set CSR_HW_CONFIG_REG for uCode use */
1145 iwl_set_bit(priv
->trans
, CSR_HW_IF_CONFIG_REG
,
1146 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
1147 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);