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net: compare_ether_addr[_64bits]() has no ordering
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-rx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 #include "iwl-prph.h"
34 #include "iwl-io.h"
35 #include "iwl-trans-pcie-int.h"
36 #include "iwl-op-mode.h"
37
38 #ifdef CONFIG_IWLWIFI_IDI
39 #include "iwl-amfh.h"
40 #endif
41
42 /******************************************************************************
43 *
44 * RX path functions
45 *
46 ******************************************************************************/
47
48 /*
49 * Rx theory of operation
50 *
51 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
52 * each of which point to Receive Buffers to be filled by the NIC. These get
53 * used not only for Rx frames, but for any command response or notification
54 * from the NIC. The driver and NIC manage the Rx buffers by means
55 * of indexes into the circular buffer.
56 *
57 * Rx Queue Indexes
58 * The host/firmware share two index registers for managing the Rx buffers.
59 *
60 * The READ index maps to the first position that the firmware may be writing
61 * to -- the driver can read up to (but not including) this position and get
62 * good data.
63 * The READ index is managed by the firmware once the card is enabled.
64 *
65 * The WRITE index maps to the last position the driver has read from -- the
66 * position preceding WRITE is the last slot the firmware can place a packet.
67 *
68 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
69 * WRITE = READ.
70 *
71 * During initialization, the host sets up the READ queue position to the first
72 * INDEX position, and WRITE to the last (READ - 1 wrapped)
73 *
74 * When the firmware places a packet in a buffer, it will advance the READ index
75 * and fire the RX interrupt. The driver can then query the READ index and
76 * process as many packets as possible, moving the WRITE index forward as it
77 * resets the Rx queue buffers with new memory.
78 *
79 * The management in the driver is as follows:
80 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
81 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
82 * to replenish the iwl->rxq->rx_free.
83 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
84 * iwl->rxq is replenished and the READ INDEX is updated (updating the
85 * 'processed' and 'read' driver indexes as well)
86 * + A received packet is processed and handed to the kernel network stack,
87 * detached from the iwl->rxq. The driver 'processed' index is updated.
88 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
89 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
90 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
91 * were enough free buffers and RX_STALLED is set it is cleared.
92 *
93 *
94 * Driver sequence:
95 *
96 * iwl_rx_queue_alloc() Allocates rx_free
97 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
98 * iwl_rx_queue_restock
99 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
100 * queue, updates firmware pointers, and updates
101 * the WRITE index. If insufficient rx_free buffers
102 * are available, schedules iwl_rx_replenish
103 *
104 * -- enable interrupts --
105 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
106 * READ INDEX, detaching the SKB from the pool.
107 * Moves the packet buffer from queue to rx_used.
108 * Calls iwl_rx_queue_restock to refill any empty
109 * slots.
110 * ...
111 *
112 */
113
114 /**
115 * iwl_rx_queue_space - Return number of free slots available in queue.
116 */
117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
118 {
119 int s = q->read - q->write;
120 if (s <= 0)
121 s += RX_QUEUE_SIZE;
122 /* keep some buffer to not confuse full and empty queue */
123 s -= 2;
124 if (s < 0)
125 s = 0;
126 return s;
127 }
128
129 /**
130 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
131 */
132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
133 struct iwl_rx_queue *q)
134 {
135 unsigned long flags;
136 u32 reg;
137
138 spin_lock_irqsave(&q->lock, flags);
139
140 if (q->need_update == 0)
141 goto exit_unlock;
142
143 if (cfg(trans)->base_params->shadow_reg_enable) {
144 /* shadow register enabled */
145 /* Device expects a multiple of 8 */
146 q->write_actual = (q->write & ~0x7);
147 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
148 } else {
149 /* If power-saving is in use, make sure device is awake */
150 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
151 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
152
153 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
154 IWL_DEBUG_INFO(trans,
155 "Rx queue requesting wakeup,"
156 " GP1 = 0x%x\n", reg);
157 iwl_set_bit(trans, CSR_GP_CNTRL,
158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
159 goto exit_unlock;
160 }
161
162 q->write_actual = (q->write & ~0x7);
163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
164 q->write_actual);
165
166 /* Else device is assumed to be awake */
167 } else {
168 /* Device expects a multiple of 8 */
169 q->write_actual = (q->write & ~0x7);
170 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
171 q->write_actual);
172 }
173 }
174 q->need_update = 0;
175
176 exit_unlock:
177 spin_unlock_irqrestore(&q->lock, flags);
178 }
179
180 /**
181 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
182 */
183 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
184 {
185 return cpu_to_le32((u32)(dma_addr >> 8));
186 }
187
188 /**
189 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
190 *
191 * If there are slots in the RX queue that need to be restocked,
192 * and we have free pre-allocated buffers, fill the ranks as much
193 * as we can, pulling from rx_free.
194 *
195 * This moves the 'write' index forward to catch up with 'processed', and
196 * also updates the memory address in the firmware to reference the new
197 * target buffer.
198 */
199 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
200 {
201 struct iwl_trans_pcie *trans_pcie =
202 IWL_TRANS_GET_PCIE_TRANS(trans);
203
204 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
205 struct list_head *element;
206 struct iwl_rx_mem_buffer *rxb;
207 unsigned long flags;
208
209 spin_lock_irqsave(&rxq->lock, flags);
210 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
211 /* The overwritten rxb must be a used one */
212 rxb = rxq->queue[rxq->write];
213 BUG_ON(rxb && rxb->page);
214
215 /* Get next free Rx buffer, remove from free list */
216 element = rxq->rx_free.next;
217 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
218 list_del(element);
219
220 /* Point to Rx buffer via next RBD in circular buffer */
221 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
222 rxq->queue[rxq->write] = rxb;
223 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
224 rxq->free_count--;
225 }
226 spin_unlock_irqrestore(&rxq->lock, flags);
227 /* If the pre-allocated buffer pool is dropping low, schedule to
228 * refill it */
229 if (rxq->free_count <= RX_LOW_WATERMARK)
230 schedule_work(&trans_pcie->rx_replenish);
231
232
233 /* If we've added more space for the firmware to place data, tell it.
234 * Increment device's write pointer in multiples of 8. */
235 if (rxq->write_actual != (rxq->write & ~0x7)) {
236 spin_lock_irqsave(&rxq->lock, flags);
237 rxq->need_update = 1;
238 spin_unlock_irqrestore(&rxq->lock, flags);
239 iwl_rx_queue_update_write_ptr(trans, rxq);
240 }
241 }
242
243 /**
244 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
245 *
246 * When moving to rx_free an SKB is allocated for the slot.
247 *
248 * Also restock the Rx queue via iwl_rx_queue_restock.
249 * This is called as a scheduled work item (except for during initialization)
250 */
251 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
252 {
253 struct iwl_trans_pcie *trans_pcie =
254 IWL_TRANS_GET_PCIE_TRANS(trans);
255
256 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
257 struct list_head *element;
258 struct iwl_rx_mem_buffer *rxb;
259 struct page *page;
260 unsigned long flags;
261 gfp_t gfp_mask = priority;
262
263 while (1) {
264 spin_lock_irqsave(&rxq->lock, flags);
265 if (list_empty(&rxq->rx_used)) {
266 spin_unlock_irqrestore(&rxq->lock, flags);
267 return;
268 }
269 spin_unlock_irqrestore(&rxq->lock, flags);
270
271 if (rxq->free_count > RX_LOW_WATERMARK)
272 gfp_mask |= __GFP_NOWARN;
273
274 if (hw_params(trans).rx_page_order > 0)
275 gfp_mask |= __GFP_COMP;
276
277 /* Alloc a new receive buffer */
278 page = alloc_pages(gfp_mask,
279 hw_params(trans).rx_page_order);
280 if (!page) {
281 if (net_ratelimit())
282 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
283 "order: %d\n",
284 hw_params(trans).rx_page_order);
285
286 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
287 net_ratelimit())
288 IWL_CRIT(trans, "Failed to alloc_pages with %s."
289 "Only %u free buffers remaining.\n",
290 priority == GFP_ATOMIC ?
291 "GFP_ATOMIC" : "GFP_KERNEL",
292 rxq->free_count);
293 /* We don't reschedule replenish work here -- we will
294 * call the restock method and if it still needs
295 * more buffers it will schedule replenish */
296 return;
297 }
298
299 spin_lock_irqsave(&rxq->lock, flags);
300
301 if (list_empty(&rxq->rx_used)) {
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 __free_pages(page, hw_params(trans).rx_page_order);
304 return;
305 }
306 element = rxq->rx_used.next;
307 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
308 list_del(element);
309
310 spin_unlock_irqrestore(&rxq->lock, flags);
311
312 BUG_ON(rxb->page);
313 rxb->page = page;
314 /* Get physical address of the RB */
315 rxb->page_dma = dma_map_page(trans->dev, page, 0,
316 PAGE_SIZE << hw_params(trans).rx_page_order,
317 DMA_FROM_DEVICE);
318 /* dma address must be no more than 36 bits */
319 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
320 /* and also 256 byte aligned! */
321 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
322
323 spin_lock_irqsave(&rxq->lock, flags);
324
325 list_add_tail(&rxb->list, &rxq->rx_free);
326 rxq->free_count++;
327
328 spin_unlock_irqrestore(&rxq->lock, flags);
329 }
330 }
331
332 void iwlagn_rx_replenish(struct iwl_trans *trans)
333 {
334 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
335 unsigned long flags;
336
337 iwlagn_rx_allocate(trans, GFP_KERNEL);
338
339 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
340 iwlagn_rx_queue_restock(trans);
341 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
342 }
343
344 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
345 {
346 iwlagn_rx_allocate(trans, GFP_ATOMIC);
347
348 iwlagn_rx_queue_restock(trans);
349 }
350
351 void iwl_bg_rx_replenish(struct work_struct *data)
352 {
353 struct iwl_trans_pcie *trans_pcie =
354 container_of(data, struct iwl_trans_pcie, rx_replenish);
355
356 iwlagn_rx_replenish(trans_pcie->trans);
357 }
358
359 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
360 struct iwl_rx_mem_buffer *rxb)
361 {
362 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
363 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
364 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
365 struct iwl_device_cmd *cmd;
366 unsigned long flags;
367 int len, err;
368 u16 sequence;
369 struct iwl_rx_cmd_buffer rxcb;
370 struct iwl_rx_packet *pkt;
371 bool reclaim;
372 int index, cmd_index;
373
374 if (WARN_ON(!rxb))
375 return;
376
377 rxcb.truesize = PAGE_SIZE << hw_params(trans).rx_page_order;
378 dma_unmap_page(trans->dev, rxb->page_dma,
379 rxcb.truesize,
380 DMA_FROM_DEVICE);
381
382 rxcb._page = rxb->page;
383 pkt = rxb_addr(&rxcb);
384
385 IWL_DEBUG_RX(trans, "%s, 0x%02x\n",
386 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
387
388
389 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
390 len += sizeof(u32); /* account for status word */
391 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
392
393 /* Reclaim a command buffer only if this packet is a response
394 * to a (driver-originated) command.
395 * If the packet (e.g. Rx frame) originated from uCode,
396 * there is no command buffer to reclaim.
397 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
398 * but apparently a few don't get set; catch them here. */
399 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
400 if (reclaim) {
401 int i;
402
403 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
404 if (trans_pcie->no_reclaim_cmds[i] == pkt->hdr.cmd) {
405 reclaim = false;
406 break;
407 }
408 }
409 }
410
411 sequence = le16_to_cpu(pkt->hdr.sequence);
412 index = SEQ_TO_INDEX(sequence);
413 cmd_index = get_cmd_index(&txq->q, index);
414
415 if (reclaim)
416 cmd = txq->cmd[cmd_index];
417 else
418 cmd = NULL;
419
420 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
421
422 /*
423 * XXX: After here, we should always check rxcb._page
424 * against NULL before touching it or its virtual
425 * memory (pkt). Because some rx_handler might have
426 * already taken or freed the pages.
427 */
428
429 if (reclaim) {
430 /* Invoke any callbacks, transfer the buffer to caller,
431 * and fire off the (possibly) blocking
432 * iwl_trans_send_cmd()
433 * as we reclaim the driver command queue */
434 if (rxcb._page)
435 iwl_tx_cmd_complete(trans, &rxcb, err);
436 else
437 IWL_WARN(trans, "Claim null rxb?\n");
438 }
439
440 /* page was stolen from us */
441 if (rxcb._page == NULL)
442 rxb->page = NULL;
443
444 /* Reuse the page if possible. For notification packets and
445 * SKBs that fail to Rx correctly, add them back into the
446 * rx_free list for reuse later. */
447 spin_lock_irqsave(&rxq->lock, flags);
448 if (rxb->page != NULL) {
449 rxb->page_dma =
450 dma_map_page(trans->dev, rxb->page, 0,
451 PAGE_SIZE << hw_params(trans).rx_page_order,
452 DMA_FROM_DEVICE);
453 list_add_tail(&rxb->list, &rxq->rx_free);
454 rxq->free_count++;
455 } else
456 list_add_tail(&rxb->list, &rxq->rx_used);
457 spin_unlock_irqrestore(&rxq->lock, flags);
458 }
459
460 /**
461 * iwl_rx_handle - Main entry function for receiving responses from uCode
462 *
463 * Uses the priv->rx_handlers callback function array to invoke
464 * the appropriate handlers, including command responses,
465 * frame-received notifications, and other notifications.
466 */
467 static void iwl_rx_handle(struct iwl_trans *trans)
468 {
469 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
470 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
471 u32 r, i;
472 u8 fill_rx = 0;
473 u32 count = 8;
474 int total_empty;
475
476 /* uCode's read index (stored in shared DRAM) indicates the last Rx
477 * buffer that the driver may process (last buffer filled by ucode). */
478 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
479 i = rxq->read;
480
481 /* Rx interrupt, but nothing sent from uCode */
482 if (i == r)
483 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
484
485 /* calculate total frames need to be restock after handling RX */
486 total_empty = r - rxq->write_actual;
487 if (total_empty < 0)
488 total_empty += RX_QUEUE_SIZE;
489
490 if (total_empty > (RX_QUEUE_SIZE / 2))
491 fill_rx = 1;
492
493 while (i != r) {
494 struct iwl_rx_mem_buffer *rxb;
495
496 rxb = rxq->queue[i];
497 rxq->queue[i] = NULL;
498
499 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
500
501 iwl_rx_handle_rxbuf(trans, rxb);
502
503 i = (i + 1) & RX_QUEUE_MASK;
504 /* If there are a lot of unused frames,
505 * restock the Rx queue so ucode wont assert. */
506 if (fill_rx) {
507 count++;
508 if (count >= 8) {
509 rxq->read = i;
510 iwlagn_rx_replenish_now(trans);
511 count = 0;
512 }
513 }
514 }
515
516 /* Backtrack one entry */
517 rxq->read = i;
518 if (fill_rx)
519 iwlagn_rx_replenish_now(trans);
520 else
521 iwlagn_rx_queue_restock(trans);
522 }
523
524 static const char * const desc_lookup_text[] = {
525 "OK",
526 "FAIL",
527 "BAD_PARAM",
528 "BAD_CHECKSUM",
529 "NMI_INTERRUPT_WDG",
530 "SYSASSERT",
531 "FATAL_ERROR",
532 "BAD_COMMAND",
533 "HW_ERROR_TUNE_LOCK",
534 "HW_ERROR_TEMPERATURE",
535 "ILLEGAL_CHAN_FREQ",
536 "VCC_NOT_STABLE",
537 "FH_ERROR",
538 "NMI_INTERRUPT_HOST",
539 "NMI_INTERRUPT_ACTION_PT",
540 "NMI_INTERRUPT_UNKNOWN",
541 "UCODE_VERSION_MISMATCH",
542 "HW_ERROR_ABS_LOCK",
543 "HW_ERROR_CAL_LOCK_FAIL",
544 "NMI_INTERRUPT_INST_ACTION_PT",
545 "NMI_INTERRUPT_DATA_ACTION_PT",
546 "NMI_TRM_HW_ER",
547 "NMI_INTERRUPT_TRM",
548 "NMI_INTERRUPT_BREAK_POINT",
549 "DEBUG_0",
550 "DEBUG_1",
551 "DEBUG_2",
552 "DEBUG_3",
553 };
554
555 static struct { char *name; u8 num; } advanced_lookup[] = {
556 { "NMI_INTERRUPT_WDG", 0x34 },
557 { "SYSASSERT", 0x35 },
558 { "UCODE_VERSION_MISMATCH", 0x37 },
559 { "BAD_COMMAND", 0x38 },
560 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
561 { "FATAL_ERROR", 0x3D },
562 { "NMI_TRM_HW_ERR", 0x46 },
563 { "NMI_INTERRUPT_TRM", 0x4C },
564 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
565 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
566 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
567 { "NMI_INTERRUPT_HOST", 0x66 },
568 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
569 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
570 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
571 { "ADVANCED_SYSASSERT", 0 },
572 };
573
574 static const char *desc_lookup(u32 num)
575 {
576 int i;
577 int max = ARRAY_SIZE(desc_lookup_text);
578
579 if (num < max)
580 return desc_lookup_text[num];
581
582 max = ARRAY_SIZE(advanced_lookup) - 1;
583 for (i = 0; i < max; i++) {
584 if (advanced_lookup[i].num == num)
585 break;
586 }
587 return advanced_lookup[i].name;
588 }
589
590 #define ERROR_START_OFFSET (1 * sizeof(u32))
591 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
592
593 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
594 {
595 u32 base;
596 struct iwl_error_event_table table;
597 struct iwl_trans_pcie *trans_pcie =
598 IWL_TRANS_GET_PCIE_TRANS(trans);
599
600 base = trans->shrd->device_pointers.error_event_table;
601 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
602 if (!base)
603 base = trans->shrd->fw->init_errlog_ptr;
604 } else {
605 if (!base)
606 base = trans->shrd->fw->inst_errlog_ptr;
607 }
608
609 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
610 IWL_ERR(trans,
611 "Not valid error log pointer 0x%08X for %s uCode\n",
612 base,
613 (trans->shrd->ucode_type == IWL_UCODE_INIT)
614 ? "Init" : "RT");
615 return;
616 }
617
618 iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
619
620 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
621 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
622 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
623 trans->shrd->status, table.valid);
624 }
625
626 trans_pcie->isr_stats.err_code = table.error_id;
627
628 trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
629 table.data1, table.data2, table.line,
630 table.blink1, table.blink2, table.ilink1,
631 table.ilink2, table.bcon_time, table.gp1,
632 table.gp2, table.gp3, table.ucode_ver,
633 table.hw_ver, table.brd_ver);
634 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
635 desc_lookup(table.error_id));
636 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
637 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
638 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
639 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
640 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
641 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
642 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
643 IWL_ERR(trans, "0x%08X | line\n", table.line);
644 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
645 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
646 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
647 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
648 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
649 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
650 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
651 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
652 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
653 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
654
655 IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
656 IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
657 IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
658 IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
659 IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
660 IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
661 IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
662 IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
663 IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
664 IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
665 IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
666 IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
667 IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
668 IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
669 }
670
671 /**
672 * iwl_irq_handle_error - called for HW or SW error interrupt from card
673 */
674 static void iwl_irq_handle_error(struct iwl_trans *trans)
675 {
676 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
677 if (cfg(trans)->internal_wimax_coex &&
678 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
679 APMS_CLK_VAL_MRB_FUNC_MODE) ||
680 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
681 APMG_PS_CTRL_VAL_RESET_REQ))) {
682 /*
683 * Keep the restart process from trying to send host
684 * commands by clearing the ready bit.
685 */
686 clear_bit(STATUS_READY, &trans->shrd->status);
687 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
688 wake_up(&trans->wait_command_queue);
689 IWL_ERR(trans, "RF is used by WiMAX\n");
690 return;
691 }
692
693 IWL_ERR(trans, "Loaded firmware version: %s\n",
694 trans->shrd->fw->fw_version);
695
696 iwl_dump_nic_error_log(trans);
697 iwl_dump_csr(trans);
698 iwl_dump_fh(trans, NULL, false);
699 iwl_dump_nic_event_log(trans, false, NULL, false);
700
701 iwl_op_mode_nic_error(trans->op_mode);
702 }
703
704 #define EVENT_START_OFFSET (4 * sizeof(u32))
705
706 /**
707 * iwl_print_event_log - Dump error event log to syslog
708 *
709 */
710 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
711 u32 num_events, u32 mode,
712 int pos, char **buf, size_t bufsz)
713 {
714 u32 i;
715 u32 base; /* SRAM byte address of event log header */
716 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
717 u32 ptr; /* SRAM byte address of log data */
718 u32 ev, time, data; /* event log data */
719 unsigned long reg_flags;
720
721 if (num_events == 0)
722 return pos;
723
724 base = trans->shrd->device_pointers.log_event_table;
725 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
726 if (!base)
727 base = trans->shrd->fw->init_evtlog_ptr;
728 } else {
729 if (!base)
730 base = trans->shrd->fw->inst_evtlog_ptr;
731 }
732
733 if (mode == 0)
734 event_size = 2 * sizeof(u32);
735 else
736 event_size = 3 * sizeof(u32);
737
738 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
739
740 /* Make sure device is powered up for SRAM reads */
741 spin_lock_irqsave(&trans->reg_lock, reg_flags);
742 if (unlikely(!iwl_grab_nic_access(trans)))
743 goto out_unlock;
744
745 /* Set starting address; reads will auto-increment */
746 iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
747
748 /* "time" is actually "data" for mode 0 (no timestamp).
749 * place event id # at far right for easier visual parsing. */
750 for (i = 0; i < num_events; i++) {
751 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
752 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
753 if (mode == 0) {
754 /* data, ev */
755 if (bufsz) {
756 pos += scnprintf(*buf + pos, bufsz - pos,
757 "EVT_LOG:0x%08x:%04u\n",
758 time, ev);
759 } else {
760 trace_iwlwifi_dev_ucode_event(trans->dev, 0,
761 time, ev);
762 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
763 time, ev);
764 }
765 } else {
766 data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
767 if (bufsz) {
768 pos += scnprintf(*buf + pos, bufsz - pos,
769 "EVT_LOGT:%010u:0x%08x:%04u\n",
770 time, data, ev);
771 } else {
772 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
773 time, data, ev);
774 trace_iwlwifi_dev_ucode_event(trans->dev, time,
775 data, ev);
776 }
777 }
778 }
779
780 /* Allow device to power down */
781 iwl_release_nic_access(trans);
782 out_unlock:
783 spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
784 return pos;
785 }
786
787 /**
788 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
789 */
790 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
791 u32 num_wraps, u32 next_entry,
792 u32 size, u32 mode,
793 int pos, char **buf, size_t bufsz)
794 {
795 /*
796 * display the newest DEFAULT_LOG_ENTRIES entries
797 * i.e the entries just before the next ont that uCode would fill.
798 */
799 if (num_wraps) {
800 if (next_entry < size) {
801 pos = iwl_print_event_log(trans,
802 capacity - (size - next_entry),
803 size - next_entry, mode,
804 pos, buf, bufsz);
805 pos = iwl_print_event_log(trans, 0,
806 next_entry, mode,
807 pos, buf, bufsz);
808 } else
809 pos = iwl_print_event_log(trans, next_entry - size,
810 size, mode, pos, buf, bufsz);
811 } else {
812 if (next_entry < size) {
813 pos = iwl_print_event_log(trans, 0, next_entry,
814 mode, pos, buf, bufsz);
815 } else {
816 pos = iwl_print_event_log(trans, next_entry - size,
817 size, mode, pos, buf, bufsz);
818 }
819 }
820 return pos;
821 }
822
823 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
824
825 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
826 char **buf, bool display)
827 {
828 u32 base; /* SRAM byte address of event log header */
829 u32 capacity; /* event log capacity in # entries */
830 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
831 u32 num_wraps; /* # times uCode wrapped to top of log */
832 u32 next_entry; /* index of next entry to be written by uCode */
833 u32 size; /* # entries that we'll print */
834 u32 logsize;
835 int pos = 0;
836 size_t bufsz = 0;
837
838 base = trans->shrd->device_pointers.log_event_table;
839 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
840 logsize = trans->shrd->fw->init_evtlog_size;
841 if (!base)
842 base = trans->shrd->fw->init_evtlog_ptr;
843 } else {
844 logsize = trans->shrd->fw->inst_evtlog_size;
845 if (!base)
846 base = trans->shrd->fw->inst_evtlog_ptr;
847 }
848
849 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
850 IWL_ERR(trans,
851 "Invalid event log pointer 0x%08X for %s uCode\n",
852 base,
853 (trans->shrd->ucode_type == IWL_UCODE_INIT)
854 ? "Init" : "RT");
855 return -EINVAL;
856 }
857
858 /* event log header */
859 capacity = iwl_read_targ_mem(trans, base);
860 mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
861 num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
862 next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
863
864 if (capacity > logsize) {
865 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
866 "entries\n", capacity, logsize);
867 capacity = logsize;
868 }
869
870 if (next_entry > logsize) {
871 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
872 next_entry, logsize);
873 next_entry = logsize;
874 }
875
876 size = num_wraps ? capacity : next_entry;
877
878 /* bail out if nothing in log */
879 if (size == 0) {
880 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
881 return pos;
882 }
883
884 #ifdef CONFIG_IWLWIFI_DEBUG
885 if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
886 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
887 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
888 #else
889 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
890 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
891 #endif
892 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
893 size);
894
895 #ifdef CONFIG_IWLWIFI_DEBUG
896 if (display) {
897 if (full_log)
898 bufsz = capacity * 48;
899 else
900 bufsz = size * 48;
901 *buf = kmalloc(bufsz, GFP_KERNEL);
902 if (!*buf)
903 return -ENOMEM;
904 }
905 if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
906 /*
907 * if uCode has wrapped back to top of log,
908 * start at the oldest entry,
909 * i.e the next one that uCode would fill.
910 */
911 if (num_wraps)
912 pos = iwl_print_event_log(trans, next_entry,
913 capacity - next_entry, mode,
914 pos, buf, bufsz);
915 /* (then/else) start at top of log */
916 pos = iwl_print_event_log(trans, 0,
917 next_entry, mode, pos, buf, bufsz);
918 } else
919 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
920 next_entry, size, mode,
921 pos, buf, bufsz);
922 #else
923 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
924 next_entry, size, mode,
925 pos, buf, bufsz);
926 #endif
927 return pos;
928 }
929
930 /* tasklet for iwlagn interrupt */
931 void iwl_irq_tasklet(struct iwl_trans *trans)
932 {
933 u32 inta = 0;
934 u32 handled = 0;
935 unsigned long flags;
936 u32 i;
937 #ifdef CONFIG_IWLWIFI_DEBUG
938 u32 inta_mask;
939 #endif
940
941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
942 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
943
944
945 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
946
947 /* Ack/clear/reset pending uCode interrupts.
948 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
949 */
950 /* There is a hardware bug in the interrupt mask function that some
951 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
952 * they are disabled in the CSR_INT_MASK register. Furthermore the
953 * ICT interrupt handling mechanism has another bug that might cause
954 * these unmasked interrupts fail to be detected. We workaround the
955 * hardware bugs here by ACKing all the possible interrupts so that
956 * interrupt coalescing can still be achieved.
957 */
958 iwl_write32(trans, CSR_INT,
959 trans_pcie->inta | ~trans_pcie->inta_mask);
960
961 inta = trans_pcie->inta;
962
963 #ifdef CONFIG_IWLWIFI_DEBUG
964 if (iwl_have_debug_level(IWL_DL_ISR)) {
965 /* just for debug */
966 inta_mask = iwl_read32(trans, CSR_INT_MASK);
967 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
968 inta, inta_mask);
969 }
970 #endif
971
972 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
973 trans_pcie->inta = 0;
974
975 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
976
977 /* Now service all interrupt bits discovered above. */
978 if (inta & CSR_INT_BIT_HW_ERR) {
979 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
980
981 /* Tell the device to stop sending interrupts */
982 iwl_disable_interrupts(trans);
983
984 isr_stats->hw++;
985 iwl_irq_handle_error(trans);
986
987 handled |= CSR_INT_BIT_HW_ERR;
988
989 return;
990 }
991
992 #ifdef CONFIG_IWLWIFI_DEBUG
993 if (iwl_have_debug_level(IWL_DL_ISR)) {
994 /* NIC fires this, but we don't use it, redundant with WAKEUP */
995 if (inta & CSR_INT_BIT_SCD) {
996 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
997 "the frame/frames.\n");
998 isr_stats->sch++;
999 }
1000
1001 /* Alive notification via Rx interrupt will do the real work */
1002 if (inta & CSR_INT_BIT_ALIVE) {
1003 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1004 isr_stats->alive++;
1005 }
1006 }
1007 #endif
1008 /* Safely ignore these bits for debug checks below */
1009 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1010
1011 /* HW RF KILL switch toggled */
1012 if (inta & CSR_INT_BIT_RF_KILL) {
1013 bool hw_rfkill;
1014
1015 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1016 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1017 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1018 hw_rfkill ? "disable radio" : "enable radio");
1019
1020 isr_stats->rfkill++;
1021
1022 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1023
1024 handled |= CSR_INT_BIT_RF_KILL;
1025 }
1026
1027 /* Chip got too hot and stopped itself */
1028 if (inta & CSR_INT_BIT_CT_KILL) {
1029 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1030 isr_stats->ctkill++;
1031 handled |= CSR_INT_BIT_CT_KILL;
1032 }
1033
1034 /* Error detected by uCode */
1035 if (inta & CSR_INT_BIT_SW_ERR) {
1036 IWL_ERR(trans, "Microcode SW error detected. "
1037 " Restarting 0x%X.\n", inta);
1038 isr_stats->sw++;
1039 iwl_irq_handle_error(trans);
1040 handled |= CSR_INT_BIT_SW_ERR;
1041 }
1042
1043 /* uCode wakes up after power-down sleep */
1044 if (inta & CSR_INT_BIT_WAKEUP) {
1045 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1046 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1047 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++)
1048 iwl_txq_update_write_ptr(trans,
1049 &trans_pcie->txq[i]);
1050
1051 isr_stats->wakeup++;
1052
1053 handled |= CSR_INT_BIT_WAKEUP;
1054 }
1055
1056 /* All uCode command responses, including Tx command responses,
1057 * Rx "responses" (frame-received notification), and other
1058 * notifications from uCode come through here*/
1059 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1060 CSR_INT_BIT_RX_PERIODIC)) {
1061 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1062 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1063 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1064 iwl_write32(trans, CSR_FH_INT_STATUS,
1065 CSR_FH_INT_RX_MASK);
1066 }
1067 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1068 handled |= CSR_INT_BIT_RX_PERIODIC;
1069 iwl_write32(trans,
1070 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1071 }
1072 /* Sending RX interrupt require many steps to be done in the
1073 * the device:
1074 * 1- write interrupt to current index in ICT table.
1075 * 2- dma RX frame.
1076 * 3- update RX shared data to indicate last write index.
1077 * 4- send interrupt.
1078 * This could lead to RX race, driver could receive RX interrupt
1079 * but the shared data changes does not reflect this;
1080 * periodic interrupt will detect any dangling Rx activity.
1081 */
1082
1083 /* Disable periodic interrupt; we use it as just a one-shot. */
1084 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1085 CSR_INT_PERIODIC_DIS);
1086 #ifdef CONFIG_IWLWIFI_IDI
1087 iwl_amfh_rx_handler();
1088 #else
1089 iwl_rx_handle(trans);
1090 #endif
1091 /*
1092 * Enable periodic interrupt in 8 msec only if we received
1093 * real RX interrupt (instead of just periodic int), to catch
1094 * any dangling Rx interrupt. If it was just the periodic
1095 * interrupt, there was no dangling Rx activity, and no need
1096 * to extend the periodic interrupt; one-shot is enough.
1097 */
1098 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1099 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1100 CSR_INT_PERIODIC_ENA);
1101
1102 isr_stats->rx++;
1103 }
1104
1105 /* This "Tx" DMA channel is used only for loading uCode */
1106 if (inta & CSR_INT_BIT_FH_TX) {
1107 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1108 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1109 isr_stats->tx++;
1110 handled |= CSR_INT_BIT_FH_TX;
1111 /* Wake up uCode load routine, now that load is complete */
1112 trans_pcie->ucode_write_complete = true;
1113 wake_up(&trans_pcie->ucode_write_waitq);
1114 }
1115
1116 if (inta & ~handled) {
1117 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1118 isr_stats->unhandled++;
1119 }
1120
1121 if (inta & ~(trans_pcie->inta_mask)) {
1122 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1123 inta & ~trans_pcie->inta_mask);
1124 }
1125
1126 /* Re-enable all interrupts */
1127 /* only Re-enable if disabled by irq */
1128 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1129 iwl_enable_interrupts(trans);
1130 /* Re-enable RF_KILL if it occurred */
1131 else if (handled & CSR_INT_BIT_RF_KILL)
1132 iwl_enable_rfkill_int(trans);
1133 }
1134
1135 /******************************************************************************
1136 *
1137 * ICT functions
1138 *
1139 ******************************************************************************/
1140
1141 /* a device (PCI-E) page is 4096 bytes long */
1142 #define ICT_SHIFT 12
1143 #define ICT_SIZE (1 << ICT_SHIFT)
1144 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1145
1146 /* Free dram table */
1147 void iwl_free_isr_ict(struct iwl_trans *trans)
1148 {
1149 struct iwl_trans_pcie *trans_pcie =
1150 IWL_TRANS_GET_PCIE_TRANS(trans);
1151
1152 if (trans_pcie->ict_tbl) {
1153 dma_free_coherent(trans->dev, ICT_SIZE,
1154 trans_pcie->ict_tbl,
1155 trans_pcie->ict_tbl_dma);
1156 trans_pcie->ict_tbl = NULL;
1157 trans_pcie->ict_tbl_dma = 0;
1158 }
1159 }
1160
1161
1162 /*
1163 * allocate dram shared table, it is an aligned memory
1164 * block of ICT_SIZE.
1165 * also reset all data related to ICT table interrupt.
1166 */
1167 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1168 {
1169 struct iwl_trans_pcie *trans_pcie =
1170 IWL_TRANS_GET_PCIE_TRANS(trans);
1171
1172 trans_pcie->ict_tbl =
1173 dma_alloc_coherent(trans->dev, ICT_SIZE,
1174 &trans_pcie->ict_tbl_dma,
1175 GFP_KERNEL);
1176 if (!trans_pcie->ict_tbl)
1177 return -ENOMEM;
1178
1179 /* just an API sanity check ... it is guaranteed to be aligned */
1180 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1181 iwl_free_isr_ict(trans);
1182 return -EINVAL;
1183 }
1184
1185 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1186 (unsigned long long)trans_pcie->ict_tbl_dma);
1187
1188 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1189
1190 /* reset table and index to all 0 */
1191 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1192 trans_pcie->ict_index = 0;
1193
1194 /* add periodic RX interrupt */
1195 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1196 return 0;
1197 }
1198
1199 /* Device is going up inform it about using ICT interrupt table,
1200 * also we need to tell the driver to start using ICT interrupt.
1201 */
1202 void iwl_reset_ict(struct iwl_trans *trans)
1203 {
1204 u32 val;
1205 unsigned long flags;
1206 struct iwl_trans_pcie *trans_pcie =
1207 IWL_TRANS_GET_PCIE_TRANS(trans);
1208
1209 if (!trans_pcie->ict_tbl)
1210 return;
1211
1212 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1213 iwl_disable_interrupts(trans);
1214
1215 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1216
1217 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1218
1219 val |= CSR_DRAM_INT_TBL_ENABLE;
1220 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1221
1222 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1223
1224 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1225 trans_pcie->use_ict = true;
1226 trans_pcie->ict_index = 0;
1227 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1228 iwl_enable_interrupts(trans);
1229 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1230 }
1231
1232 /* Device is going down disable ict interrupt usage */
1233 void iwl_disable_ict(struct iwl_trans *trans)
1234 {
1235 struct iwl_trans_pcie *trans_pcie =
1236 IWL_TRANS_GET_PCIE_TRANS(trans);
1237
1238 unsigned long flags;
1239
1240 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1241 trans_pcie->use_ict = false;
1242 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1243 }
1244
1245 static irqreturn_t iwl_isr(int irq, void *data)
1246 {
1247 struct iwl_trans *trans = data;
1248 struct iwl_trans_pcie *trans_pcie;
1249 u32 inta, inta_mask;
1250 unsigned long flags;
1251 #ifdef CONFIG_IWLWIFI_DEBUG
1252 u32 inta_fh;
1253 #endif
1254 if (!trans)
1255 return IRQ_NONE;
1256
1257 trace_iwlwifi_dev_irq(trans->dev);
1258
1259 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1260
1261 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1262
1263 /* Disable (but don't clear!) interrupts here to avoid
1264 * back-to-back ISRs and sporadic interrupts from our NIC.
1265 * If we have something to service, the tasklet will re-enable ints.
1266 * If we *don't* have something, we'll re-enable before leaving here. */
1267 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1268 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1269
1270 /* Discover which interrupts are active/pending */
1271 inta = iwl_read32(trans, CSR_INT);
1272
1273 /* Ignore interrupt if there's nothing in NIC to service.
1274 * This may be due to IRQ shared with another device,
1275 * or due to sporadic interrupts thrown from our NIC. */
1276 if (!inta) {
1277 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1278 goto none;
1279 }
1280
1281 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1282 /* Hardware disappeared. It might have already raised
1283 * an interrupt */
1284 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1285 goto unplugged;
1286 }
1287
1288 #ifdef CONFIG_IWLWIFI_DEBUG
1289 if (iwl_have_debug_level(IWL_DL_ISR)) {
1290 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1291 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1292 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1293 }
1294 #endif
1295
1296 trans_pcie->inta |= inta;
1297 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1298 if (likely(inta))
1299 tasklet_schedule(&trans_pcie->irq_tasklet);
1300 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1301 !trans_pcie->inta)
1302 iwl_enable_interrupts(trans);
1303
1304 unplugged:
1305 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1306 return IRQ_HANDLED;
1307
1308 none:
1309 /* re-enable interrupts here since we don't have anything to service. */
1310 /* only Re-enable if disabled by irq and no schedules tasklet. */
1311 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1312 !trans_pcie->inta)
1313 iwl_enable_interrupts(trans);
1314
1315 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1316 return IRQ_NONE;
1317 }
1318
1319 /* interrupt handler using ict table, with this interrupt driver will
1320 * stop using INTA register to get device's interrupt, reading this register
1321 * is expensive, device will write interrupts in ICT dram table, increment
1322 * index then will fire interrupt to driver, driver will OR all ICT table
1323 * entries from current index up to table entry with 0 value. the result is
1324 * the interrupt we need to service, driver will set the entries back to 0 and
1325 * set index.
1326 */
1327 irqreturn_t iwl_isr_ict(int irq, void *data)
1328 {
1329 struct iwl_trans *trans = data;
1330 struct iwl_trans_pcie *trans_pcie;
1331 u32 inta, inta_mask;
1332 u32 val = 0;
1333 u32 read;
1334 unsigned long flags;
1335
1336 if (!trans)
1337 return IRQ_NONE;
1338
1339 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1340
1341 /* dram interrupt table not set yet,
1342 * use legacy interrupt.
1343 */
1344 if (!trans_pcie->use_ict)
1345 return iwl_isr(irq, data);
1346
1347 trace_iwlwifi_dev_irq(trans->dev);
1348
1349 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1350
1351 /* Disable (but don't clear!) interrupts here to avoid
1352 * back-to-back ISRs and sporadic interrupts from our NIC.
1353 * If we have something to service, the tasklet will re-enable ints.
1354 * If we *don't* have something, we'll re-enable before leaving here.
1355 */
1356 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1357 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1358
1359
1360 /* Ignore interrupt if there's nothing in NIC to service.
1361 * This may be due to IRQ shared with another device,
1362 * or due to sporadic interrupts thrown from our NIC. */
1363 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1364 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1365 if (!read) {
1366 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1367 goto none;
1368 }
1369
1370 /*
1371 * Collect all entries up to the first 0, starting from ict_index;
1372 * note we already read at ict_index.
1373 */
1374 do {
1375 val |= read;
1376 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1377 trans_pcie->ict_index, read);
1378 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1379 trans_pcie->ict_index =
1380 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1381
1382 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1383 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1384 read);
1385 } while (read);
1386
1387 /* We should not get this value, just ignore it. */
1388 if (val == 0xffffffff)
1389 val = 0;
1390
1391 /*
1392 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1393 * (bit 15 before shifting it to 31) to clear when using interrupt
1394 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1395 * so we use them to decide on the real state of the Rx bit.
1396 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1397 */
1398 if (val & 0xC0000)
1399 val |= 0x8000;
1400
1401 inta = (0xff & val) | ((0xff00 & val) << 16);
1402 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1403 inta, inta_mask, val);
1404
1405 inta &= trans_pcie->inta_mask;
1406 trans_pcie->inta |= inta;
1407
1408 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1409 if (likely(inta))
1410 tasklet_schedule(&trans_pcie->irq_tasklet);
1411 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1412 !trans_pcie->inta) {
1413 /* Allow interrupt if was disabled by this handler and
1414 * no tasklet was schedules, We should not enable interrupt,
1415 * tasklet will enable it.
1416 */
1417 iwl_enable_interrupts(trans);
1418 }
1419
1420 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1421 return IRQ_HANDLED;
1422
1423 none:
1424 /* re-enable interrupts here since we don't have anything to service.
1425 * only Re-enable if disabled by irq.
1426 */
1427 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1428 !trans_pcie->inta)
1429 iwl_enable_interrupts(trans);
1430
1431 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1432 return IRQ_NONE;
1433 }
Linux kernel - Deliverables
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