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iwlwifi: remove a few dereferences to iwl_priv from the tansport
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-rx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 /*TODO: Remove include to iwl-core.h*/
34 #include "iwl-core.h"
35 #include "iwl-io.h"
36 #include "iwl-trans-pcie-int.h"
37 #include "iwl-wifi.h"
38 #include "iwl-op-mode.h"
39
40 #ifdef CONFIG_IWLWIFI_IDI
41 #include "iwl-amfh.h"
42 #endif
43
44 /******************************************************************************
45 *
46 * RX path functions
47 *
48 ******************************************************************************/
49
50 /*
51 * Rx theory of operation
52 *
53 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
54 * each of which point to Receive Buffers to be filled by the NIC. These get
55 * used not only for Rx frames, but for any command response or notification
56 * from the NIC. The driver and NIC manage the Rx buffers by means
57 * of indexes into the circular buffer.
58 *
59 * Rx Queue Indexes
60 * The host/firmware share two index registers for managing the Rx buffers.
61 *
62 * The READ index maps to the first position that the firmware may be writing
63 * to -- the driver can read up to (but not including) this position and get
64 * good data.
65 * The READ index is managed by the firmware once the card is enabled.
66 *
67 * The WRITE index maps to the last position the driver has read from -- the
68 * position preceding WRITE is the last slot the firmware can place a packet.
69 *
70 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
71 * WRITE = READ.
72 *
73 * During initialization, the host sets up the READ queue position to the first
74 * INDEX position, and WRITE to the last (READ - 1 wrapped)
75 *
76 * When the firmware places a packet in a buffer, it will advance the READ index
77 * and fire the RX interrupt. The driver can then query the READ index and
78 * process as many packets as possible, moving the WRITE index forward as it
79 * resets the Rx queue buffers with new memory.
80 *
81 * The management in the driver is as follows:
82 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
83 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
84 * to replenish the iwl->rxq->rx_free.
85 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
86 * iwl->rxq is replenished and the READ INDEX is updated (updating the
87 * 'processed' and 'read' driver indexes as well)
88 * + A received packet is processed and handed to the kernel network stack,
89 * detached from the iwl->rxq. The driver 'processed' index is updated.
90 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
91 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
92 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
93 * were enough free buffers and RX_STALLED is set it is cleared.
94 *
95 *
96 * Driver sequence:
97 *
98 * iwl_rx_queue_alloc() Allocates rx_free
99 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
100 * iwl_rx_queue_restock
101 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
102 * queue, updates firmware pointers, and updates
103 * the WRITE index. If insufficient rx_free buffers
104 * are available, schedules iwl_rx_replenish
105 *
106 * -- enable interrupts --
107 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
108 * READ INDEX, detaching the SKB from the pool.
109 * Moves the packet buffer from queue to rx_used.
110 * Calls iwl_rx_queue_restock to refill any empty
111 * slots.
112 * ...
113 *
114 */
115
116 /**
117 * iwl_rx_queue_space - Return number of free slots available in queue.
118 */
119 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
120 {
121 int s = q->read - q->write;
122 if (s <= 0)
123 s += RX_QUEUE_SIZE;
124 /* keep some buffer to not confuse full and empty queue */
125 s -= 2;
126 if (s < 0)
127 s = 0;
128 return s;
129 }
130
131 /**
132 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
133 */
134 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
135 struct iwl_rx_queue *q)
136 {
137 unsigned long flags;
138 u32 reg;
139
140 spin_lock_irqsave(&q->lock, flags);
141
142 if (q->need_update == 0)
143 goto exit_unlock;
144
145 if (hw_params(trans).shadow_reg_enable) {
146 /* shadow register enabled */
147 /* Device expects a multiple of 8 */
148 q->write_actual = (q->write & ~0x7);
149 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
150 } else {
151 /* If power-saving is in use, make sure device is awake */
152 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
153 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
154
155 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
156 IWL_DEBUG_INFO(trans,
157 "Rx queue requesting wakeup,"
158 " GP1 = 0x%x\n", reg);
159 iwl_set_bit(trans, CSR_GP_CNTRL,
160 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
161 goto exit_unlock;
162 }
163
164 q->write_actual = (q->write & ~0x7);
165 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
166 q->write_actual);
167
168 /* Else device is assumed to be awake */
169 } else {
170 /* Device expects a multiple of 8 */
171 q->write_actual = (q->write & ~0x7);
172 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
173 q->write_actual);
174 }
175 }
176 q->need_update = 0;
177
178 exit_unlock:
179 spin_unlock_irqrestore(&q->lock, flags);
180 }
181
182 /**
183 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
184 */
185 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
186 {
187 return cpu_to_le32((u32)(dma_addr >> 8));
188 }
189
190 /**
191 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
192 *
193 * If there are slots in the RX queue that need to be restocked,
194 * and we have free pre-allocated buffers, fill the ranks as much
195 * as we can, pulling from rx_free.
196 *
197 * This moves the 'write' index forward to catch up with 'processed', and
198 * also updates the memory address in the firmware to reference the new
199 * target buffer.
200 */
201 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
202 {
203 struct iwl_trans_pcie *trans_pcie =
204 IWL_TRANS_GET_PCIE_TRANS(trans);
205
206 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
207 struct list_head *element;
208 struct iwl_rx_mem_buffer *rxb;
209 unsigned long flags;
210
211 spin_lock_irqsave(&rxq->lock, flags);
212 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
213 /* The overwritten rxb must be a used one */
214 rxb = rxq->queue[rxq->write];
215 BUG_ON(rxb && rxb->page);
216
217 /* Get next free Rx buffer, remove from free list */
218 element = rxq->rx_free.next;
219 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
220 list_del(element);
221
222 /* Point to Rx buffer via next RBD in circular buffer */
223 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
224 rxq->queue[rxq->write] = rxb;
225 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
226 rxq->free_count--;
227 }
228 spin_unlock_irqrestore(&rxq->lock, flags);
229 /* If the pre-allocated buffer pool is dropping low, schedule to
230 * refill it */
231 if (rxq->free_count <= RX_LOW_WATERMARK)
232 schedule_work(&trans_pcie->rx_replenish);
233
234
235 /* If we've added more space for the firmware to place data, tell it.
236 * Increment device's write pointer in multiples of 8. */
237 if (rxq->write_actual != (rxq->write & ~0x7)) {
238 spin_lock_irqsave(&rxq->lock, flags);
239 rxq->need_update = 1;
240 spin_unlock_irqrestore(&rxq->lock, flags);
241 iwl_rx_queue_update_write_ptr(trans, rxq);
242 }
243 }
244
245 /**
246 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
247 *
248 * When moving to rx_free an SKB is allocated for the slot.
249 *
250 * Also restock the Rx queue via iwl_rx_queue_restock.
251 * This is called as a scheduled work item (except for during initialization)
252 */
253 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
254 {
255 struct iwl_trans_pcie *trans_pcie =
256 IWL_TRANS_GET_PCIE_TRANS(trans);
257
258 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
259 struct list_head *element;
260 struct iwl_rx_mem_buffer *rxb;
261 struct page *page;
262 unsigned long flags;
263 gfp_t gfp_mask = priority;
264
265 while (1) {
266 spin_lock_irqsave(&rxq->lock, flags);
267 if (list_empty(&rxq->rx_used)) {
268 spin_unlock_irqrestore(&rxq->lock, flags);
269 return;
270 }
271 spin_unlock_irqrestore(&rxq->lock, flags);
272
273 if (rxq->free_count > RX_LOW_WATERMARK)
274 gfp_mask |= __GFP_NOWARN;
275
276 if (hw_params(trans).rx_page_order > 0)
277 gfp_mask |= __GFP_COMP;
278
279 /* Alloc a new receive buffer */
280 page = alloc_pages(gfp_mask,
281 hw_params(trans).rx_page_order);
282 if (!page) {
283 if (net_ratelimit())
284 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
285 "order: %d\n",
286 hw_params(trans).rx_page_order);
287
288 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
289 net_ratelimit())
290 IWL_CRIT(trans, "Failed to alloc_pages with %s."
291 "Only %u free buffers remaining.\n",
292 priority == GFP_ATOMIC ?
293 "GFP_ATOMIC" : "GFP_KERNEL",
294 rxq->free_count);
295 /* We don't reschedule replenish work here -- we will
296 * call the restock method and if it still needs
297 * more buffers it will schedule replenish */
298 return;
299 }
300
301 spin_lock_irqsave(&rxq->lock, flags);
302
303 if (list_empty(&rxq->rx_used)) {
304 spin_unlock_irqrestore(&rxq->lock, flags);
305 __free_pages(page, hw_params(trans).rx_page_order);
306 return;
307 }
308 element = rxq->rx_used.next;
309 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
310 list_del(element);
311
312 spin_unlock_irqrestore(&rxq->lock, flags);
313
314 BUG_ON(rxb->page);
315 rxb->page = page;
316 /* Get physical address of the RB */
317 rxb->page_dma = dma_map_page(trans->dev, page, 0,
318 PAGE_SIZE << hw_params(trans).rx_page_order,
319 DMA_FROM_DEVICE);
320 /* dma address must be no more than 36 bits */
321 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
322 /* and also 256 byte aligned! */
323 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
324
325 spin_lock_irqsave(&rxq->lock, flags);
326
327 list_add_tail(&rxb->list, &rxq->rx_free);
328 rxq->free_count++;
329
330 spin_unlock_irqrestore(&rxq->lock, flags);
331 }
332 }
333
334 void iwlagn_rx_replenish(struct iwl_trans *trans)
335 {
336 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
337 unsigned long flags;
338
339 iwlagn_rx_allocate(trans, GFP_KERNEL);
340
341 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
342 iwlagn_rx_queue_restock(trans);
343 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
344 }
345
346 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
347 {
348 iwlagn_rx_allocate(trans, GFP_ATOMIC);
349
350 iwlagn_rx_queue_restock(trans);
351 }
352
353 void iwl_bg_rx_replenish(struct work_struct *data)
354 {
355 struct iwl_trans_pcie *trans_pcie =
356 container_of(data, struct iwl_trans_pcie, rx_replenish);
357
358 iwlagn_rx_replenish(trans_pcie->trans);
359 }
360
361 /**
362 * iwl_rx_handle - Main entry function for receiving responses from uCode
363 *
364 * Uses the priv->rx_handlers callback function array to invoke
365 * the appropriate handlers, including command responses,
366 * frame-received notifications, and other notifications.
367 */
368 static void iwl_rx_handle(struct iwl_trans *trans)
369 {
370 struct iwl_rx_mem_buffer *rxb;
371 struct iwl_rx_packet *pkt;
372 struct iwl_trans_pcie *trans_pcie =
373 IWL_TRANS_GET_PCIE_TRANS(trans);
374 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
375 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
376 struct iwl_device_cmd *cmd;
377 u32 r, i;
378 int reclaim;
379 unsigned long flags;
380 u8 fill_rx = 0;
381 u32 count = 8;
382 int total_empty;
383 int index, cmd_index;
384
385 /* uCode's read index (stored in shared DRAM) indicates the last Rx
386 * buffer that the driver may process (last buffer filled by ucode). */
387 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
388 i = rxq->read;
389
390 /* Rx interrupt, but nothing sent from uCode */
391 if (i == r)
392 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
393
394 /* calculate total frames need to be restock after handling RX */
395 total_empty = r - rxq->write_actual;
396 if (total_empty < 0)
397 total_empty += RX_QUEUE_SIZE;
398
399 if (total_empty > (RX_QUEUE_SIZE / 2))
400 fill_rx = 1;
401
402 while (i != r) {
403 int len, err;
404 u16 sequence;
405
406 rxb = rxq->queue[i];
407
408 /* If an RXB doesn't have a Rx queue slot associated with it,
409 * then a bug has been introduced in the queue refilling
410 * routines -- catch it here */
411 if (WARN_ON(rxb == NULL)) {
412 i = (i + 1) & RX_QUEUE_MASK;
413 continue;
414 }
415
416 rxq->queue[i] = NULL;
417
418 dma_unmap_page(trans->dev, rxb->page_dma,
419 PAGE_SIZE << hw_params(trans).rx_page_order,
420 DMA_FROM_DEVICE);
421 pkt = rxb_addr(rxb);
422
423 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
424 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
425
426 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
427 len += sizeof(u32); /* account for status word */
428 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
429
430 /* Reclaim a command buffer only if this packet is a response
431 * to a (driver-originated) command.
432 * If the packet (e.g. Rx frame) originated from uCode,
433 * there is no command buffer to reclaim.
434 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
435 * but apparently a few don't get set; catch them here. */
436 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
437 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
438 (pkt->hdr.cmd != REPLY_RX) &&
439 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
440 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
441 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
442 (pkt->hdr.cmd != REPLY_TX);
443
444 sequence = le16_to_cpu(pkt->hdr.sequence);
445 index = SEQ_TO_INDEX(sequence);
446 cmd_index = get_cmd_index(&txq->q, index);
447
448 if (reclaim)
449 cmd = txq->cmd[cmd_index];
450 else
451 cmd = NULL;
452
453 /* warn if this is cmd response / notification and the uCode
454 * didn't set the SEQ_RX_FRAME for a frame that is
455 * uCode-originated
456 * If you saw this code after the second half of 2012, then
457 * please remove it
458 */
459 WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
460 (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
461 "reclaim is false, SEQ_RX_FRAME unset: %s\n",
462 get_cmd_string(pkt->hdr.cmd));
463
464 err = iwl_op_mode_rx(trans->op_mode, rxb, cmd);
465
466 /*
467 * XXX: After here, we should always check rxb->page
468 * against NULL before touching it or its virtual
469 * memory (pkt). Because some rx_handler might have
470 * already taken or freed the pages.
471 */
472
473 if (reclaim) {
474 /* Invoke any callbacks, transfer the buffer to caller,
475 * and fire off the (possibly) blocking
476 * iwl_trans_send_cmd()
477 * as we reclaim the driver command queue */
478 if (rxb->page)
479 iwl_tx_cmd_complete(trans, rxb, err);
480 else
481 IWL_WARN(trans, "Claim null rxb?\n");
482 }
483
484 /* Reuse the page if possible. For notification packets and
485 * SKBs that fail to Rx correctly, add them back into the
486 * rx_free list for reuse later. */
487 spin_lock_irqsave(&rxq->lock, flags);
488 if (rxb->page != NULL) {
489 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
490 0, PAGE_SIZE <<
491 hw_params(trans).rx_page_order,
492 DMA_FROM_DEVICE);
493 list_add_tail(&rxb->list, &rxq->rx_free);
494 rxq->free_count++;
495 } else
496 list_add_tail(&rxb->list, &rxq->rx_used);
497
498 spin_unlock_irqrestore(&rxq->lock, flags);
499
500 i = (i + 1) & RX_QUEUE_MASK;
501 /* If there are a lot of unused frames,
502 * restock the Rx queue so ucode wont assert. */
503 if (fill_rx) {
504 count++;
505 if (count >= 8) {
506 rxq->read = i;
507 iwlagn_rx_replenish_now(trans);
508 count = 0;
509 }
510 }
511 }
512
513 /* Backtrack one entry */
514 rxq->read = i;
515 if (fill_rx)
516 iwlagn_rx_replenish_now(trans);
517 else
518 iwlagn_rx_queue_restock(trans);
519 }
520
521 static const char * const desc_lookup_text[] = {
522 "OK",
523 "FAIL",
524 "BAD_PARAM",
525 "BAD_CHECKSUM",
526 "NMI_INTERRUPT_WDG",
527 "SYSASSERT",
528 "FATAL_ERROR",
529 "BAD_COMMAND",
530 "HW_ERROR_TUNE_LOCK",
531 "HW_ERROR_TEMPERATURE",
532 "ILLEGAL_CHAN_FREQ",
533 "VCC_NOT_STABLE",
534 "FH_ERROR",
535 "NMI_INTERRUPT_HOST",
536 "NMI_INTERRUPT_ACTION_PT",
537 "NMI_INTERRUPT_UNKNOWN",
538 "UCODE_VERSION_MISMATCH",
539 "HW_ERROR_ABS_LOCK",
540 "HW_ERROR_CAL_LOCK_FAIL",
541 "NMI_INTERRUPT_INST_ACTION_PT",
542 "NMI_INTERRUPT_DATA_ACTION_PT",
543 "NMI_TRM_HW_ER",
544 "NMI_INTERRUPT_TRM",
545 "NMI_INTERRUPT_BREAK_POINT",
546 "DEBUG_0",
547 "DEBUG_1",
548 "DEBUG_2",
549 "DEBUG_3",
550 };
551
552 static struct { char *name; u8 num; } advanced_lookup[] = {
553 { "NMI_INTERRUPT_WDG", 0x34 },
554 { "SYSASSERT", 0x35 },
555 { "UCODE_VERSION_MISMATCH", 0x37 },
556 { "BAD_COMMAND", 0x38 },
557 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
558 { "FATAL_ERROR", 0x3D },
559 { "NMI_TRM_HW_ERR", 0x46 },
560 { "NMI_INTERRUPT_TRM", 0x4C },
561 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
562 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
563 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
564 { "NMI_INTERRUPT_HOST", 0x66 },
565 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
566 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
567 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
568 { "ADVANCED_SYSASSERT", 0 },
569 };
570
571 static const char *desc_lookup(u32 num)
572 {
573 int i;
574 int max = ARRAY_SIZE(desc_lookup_text);
575
576 if (num < max)
577 return desc_lookup_text[num];
578
579 max = ARRAY_SIZE(advanced_lookup) - 1;
580 for (i = 0; i < max; i++) {
581 if (advanced_lookup[i].num == num)
582 break;
583 }
584 return advanced_lookup[i].name;
585 }
586
587 #define ERROR_START_OFFSET (1 * sizeof(u32))
588 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
589
590 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
591 {
592 u32 base;
593 struct iwl_error_event_table table;
594 struct iwl_nic *nic = nic(trans);
595 struct iwl_trans_pcie *trans_pcie =
596 IWL_TRANS_GET_PCIE_TRANS(trans);
597
598 base = trans->shrd->device_pointers.error_event_table;
599 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
600 if (!base)
601 base = nic->init_errlog_ptr;
602 } else {
603 if (!base)
604 base = nic->inst_errlog_ptr;
605 }
606
607 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
608 IWL_ERR(trans,
609 "Not valid error log pointer 0x%08X for %s uCode\n",
610 base,
611 (trans->shrd->ucode_type == IWL_UCODE_INIT)
612 ? "Init" : "RT");
613 return;
614 }
615
616 iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
617
618 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
619 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
620 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
621 trans->shrd->status, table.valid);
622 }
623
624 trans_pcie->isr_stats.err_code = table.error_id;
625
626 trace_iwlwifi_dev_ucode_error(priv(nic), table.error_id, table.tsf_low,
627 table.data1, table.data2, table.line,
628 table.blink1, table.blink2, table.ilink1,
629 table.ilink2, table.bcon_time, table.gp1,
630 table.gp2, table.gp3, table.ucode_ver,
631 table.hw_ver, table.brd_ver);
632 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
633 desc_lookup(table.error_id));
634 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
635 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
636 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
637 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
638 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
639 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
640 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
641 IWL_ERR(trans, "0x%08X | line\n", table.line);
642 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
643 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
644 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
645 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
646 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
647 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
648 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
649 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
650 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
651 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
652
653 IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
654 IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
655 IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
656 IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
657 IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
658 IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
659 IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
660 IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
661 IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
662 IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
663 IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
664 IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
665 IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
666 IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
667 }
668
669 /**
670 * iwl_irq_handle_error - called for HW or SW error interrupt from card
671 */
672 static void iwl_irq_handle_error(struct iwl_trans *trans)
673 {
674 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
675 if (cfg(trans)->internal_wimax_coex &&
676 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
677 APMS_CLK_VAL_MRB_FUNC_MODE) ||
678 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
679 APMG_PS_CTRL_VAL_RESET_REQ))) {
680 /*
681 * Keep the restart process from trying to send host
682 * commands by clearing the ready bit.
683 */
684 clear_bit(STATUS_READY, &trans->shrd->status);
685 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
686 wake_up(&trans->shrd->wait_command_queue);
687 IWL_ERR(trans, "RF is used by WiMAX\n");
688 return;
689 }
690
691 IWL_ERR(trans, "Loaded firmware version: %s\n",
692 nic(trans)->fw.fw_version);
693
694 iwl_dump_nic_error_log(trans);
695 iwl_dump_csr(trans);
696 iwl_dump_fh(trans, NULL, false);
697 iwl_dump_nic_event_log(trans, false, NULL, false);
698 #ifdef CONFIG_IWLWIFI_DEBUG
699 if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
700 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
701 #endif
702
703 iwl_op_mode_nic_error(trans->op_mode);
704 }
705
706 #define EVENT_START_OFFSET (4 * sizeof(u32))
707
708 /**
709 * iwl_print_event_log - Dump error event log to syslog
710 *
711 */
712 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
713 u32 num_events, u32 mode,
714 int pos, char **buf, size_t bufsz)
715 {
716 u32 i;
717 u32 base; /* SRAM byte address of event log header */
718 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
719 u32 ptr; /* SRAM byte address of log data */
720 u32 ev, time, data; /* event log data */
721 unsigned long reg_flags;
722 struct iwl_nic *nic = nic(trans);
723
724 if (num_events == 0)
725 return pos;
726
727 base = trans->shrd->device_pointers.log_event_table;
728 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
729 if (!base)
730 base = nic->init_evtlog_ptr;
731 } else {
732 if (!base)
733 base = nic->inst_evtlog_ptr;
734 }
735
736 if (mode == 0)
737 event_size = 2 * sizeof(u32);
738 else
739 event_size = 3 * sizeof(u32);
740
741 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
742
743 /* Make sure device is powered up for SRAM reads */
744 spin_lock_irqsave(&trans->reg_lock, reg_flags);
745 iwl_grab_nic_access(trans);
746
747 /* Set starting address; reads will auto-increment */
748 iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
749 rmb();
750
751 /* "time" is actually "data" for mode 0 (no timestamp).
752 * place event id # at far right for easier visual parsing. */
753 for (i = 0; i < num_events; i++) {
754 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
755 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
756 if (mode == 0) {
757 /* data, ev */
758 if (bufsz) {
759 pos += scnprintf(*buf + pos, bufsz - pos,
760 "EVT_LOG:0x%08x:%04u\n",
761 time, ev);
762 } else {
763 trace_iwlwifi_dev_ucode_event(priv(trans), 0,
764 time, ev);
765 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
766 time, ev);
767 }
768 } else {
769 data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
770 if (bufsz) {
771 pos += scnprintf(*buf + pos, bufsz - pos,
772 "EVT_LOGT:%010u:0x%08x:%04u\n",
773 time, data, ev);
774 } else {
775 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
776 time, data, ev);
777 trace_iwlwifi_dev_ucode_event(priv(trans), time,
778 data, ev);
779 }
780 }
781 }
782
783 /* Allow device to power down */
784 iwl_release_nic_access(trans);
785 spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
786 return pos;
787 }
788
789 /**
790 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
791 */
792 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
793 u32 num_wraps, u32 next_entry,
794 u32 size, u32 mode,
795 int pos, char **buf, size_t bufsz)
796 {
797 /*
798 * display the newest DEFAULT_LOG_ENTRIES entries
799 * i.e the entries just before the next ont that uCode would fill.
800 */
801 if (num_wraps) {
802 if (next_entry < size) {
803 pos = iwl_print_event_log(trans,
804 capacity - (size - next_entry),
805 size - next_entry, mode,
806 pos, buf, bufsz);
807 pos = iwl_print_event_log(trans, 0,
808 next_entry, mode,
809 pos, buf, bufsz);
810 } else
811 pos = iwl_print_event_log(trans, next_entry - size,
812 size, mode, pos, buf, bufsz);
813 } else {
814 if (next_entry < size) {
815 pos = iwl_print_event_log(trans, 0, next_entry,
816 mode, pos, buf, bufsz);
817 } else {
818 pos = iwl_print_event_log(trans, next_entry - size,
819 size, mode, pos, buf, bufsz);
820 }
821 }
822 return pos;
823 }
824
825 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
826
827 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
828 char **buf, bool display)
829 {
830 u32 base; /* SRAM byte address of event log header */
831 u32 capacity; /* event log capacity in # entries */
832 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
833 u32 num_wraps; /* # times uCode wrapped to top of log */
834 u32 next_entry; /* index of next entry to be written by uCode */
835 u32 size; /* # entries that we'll print */
836 u32 logsize;
837 int pos = 0;
838 size_t bufsz = 0;
839 struct iwl_nic *nic = nic(trans);
840
841 base = trans->shrd->device_pointers.log_event_table;
842 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
843 logsize = nic->init_evtlog_size;
844 if (!base)
845 base = nic->init_evtlog_ptr;
846 } else {
847 logsize = nic->inst_evtlog_size;
848 if (!base)
849 base = nic->inst_evtlog_ptr;
850 }
851
852 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
853 IWL_ERR(trans,
854 "Invalid event log pointer 0x%08X for %s uCode\n",
855 base,
856 (trans->shrd->ucode_type == IWL_UCODE_INIT)
857 ? "Init" : "RT");
858 return -EINVAL;
859 }
860
861 /* event log header */
862 capacity = iwl_read_targ_mem(trans, base);
863 mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
864 num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
865 next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
866
867 if (capacity > logsize) {
868 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
869 "entries\n", capacity, logsize);
870 capacity = logsize;
871 }
872
873 if (next_entry > logsize) {
874 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
875 next_entry, logsize);
876 next_entry = logsize;
877 }
878
879 size = num_wraps ? capacity : next_entry;
880
881 /* bail out if nothing in log */
882 if (size == 0) {
883 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
884 return pos;
885 }
886
887 #ifdef CONFIG_IWLWIFI_DEBUG
888 if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
889 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
890 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
891 #else
892 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
893 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
894 #endif
895 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
896 size);
897
898 #ifdef CONFIG_IWLWIFI_DEBUG
899 if (display) {
900 if (full_log)
901 bufsz = capacity * 48;
902 else
903 bufsz = size * 48;
904 *buf = kmalloc(bufsz, GFP_KERNEL);
905 if (!*buf)
906 return -ENOMEM;
907 }
908 if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
909 /*
910 * if uCode has wrapped back to top of log,
911 * start at the oldest entry,
912 * i.e the next one that uCode would fill.
913 */
914 if (num_wraps)
915 pos = iwl_print_event_log(trans, next_entry,
916 capacity - next_entry, mode,
917 pos, buf, bufsz);
918 /* (then/else) start at top of log */
919 pos = iwl_print_event_log(trans, 0,
920 next_entry, mode, pos, buf, bufsz);
921 } else
922 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
923 next_entry, size, mode,
924 pos, buf, bufsz);
925 #else
926 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
927 next_entry, size, mode,
928 pos, buf, bufsz);
929 #endif
930 return pos;
931 }
932
933 /* tasklet for iwlagn interrupt */
934 void iwl_irq_tasklet(struct iwl_trans *trans)
935 {
936 u32 inta = 0;
937 u32 handled = 0;
938 unsigned long flags;
939 u32 i;
940 #ifdef CONFIG_IWLWIFI_DEBUG
941 u32 inta_mask;
942 #endif
943
944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
945 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
946
947
948 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
949
950 /* Ack/clear/reset pending uCode interrupts.
951 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
952 */
953 /* There is a hardware bug in the interrupt mask function that some
954 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
955 * they are disabled in the CSR_INT_MASK register. Furthermore the
956 * ICT interrupt handling mechanism has another bug that might cause
957 * these unmasked interrupts fail to be detected. We workaround the
958 * hardware bugs here by ACKing all the possible interrupts so that
959 * interrupt coalescing can still be achieved.
960 */
961 iwl_write32(trans, CSR_INT,
962 trans_pcie->inta | ~trans_pcie->inta_mask);
963
964 inta = trans_pcie->inta;
965
966 #ifdef CONFIG_IWLWIFI_DEBUG
967 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
968 /* just for debug */
969 inta_mask = iwl_read32(trans, CSR_INT_MASK);
970 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
971 inta, inta_mask);
972 }
973 #endif
974
975 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
976 trans_pcie->inta = 0;
977
978 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
979
980 /* Now service all interrupt bits discovered above. */
981 if (inta & CSR_INT_BIT_HW_ERR) {
982 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
983
984 /* Tell the device to stop sending interrupts */
985 iwl_disable_interrupts(trans);
986
987 isr_stats->hw++;
988 iwl_irq_handle_error(trans);
989
990 handled |= CSR_INT_BIT_HW_ERR;
991
992 return;
993 }
994
995 #ifdef CONFIG_IWLWIFI_DEBUG
996 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
997 /* NIC fires this, but we don't use it, redundant with WAKEUP */
998 if (inta & CSR_INT_BIT_SCD) {
999 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1000 "the frame/frames.\n");
1001 isr_stats->sch++;
1002 }
1003
1004 /* Alive notification via Rx interrupt will do the real work */
1005 if (inta & CSR_INT_BIT_ALIVE) {
1006 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1007 isr_stats->alive++;
1008 }
1009 }
1010 #endif
1011 /* Safely ignore these bits for debug checks below */
1012 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1013
1014 /* HW RF KILL switch toggled */
1015 if (inta & CSR_INT_BIT_RF_KILL) {
1016 int hw_rf_kill = 0;
1017 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1018 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1019 hw_rf_kill = 1;
1020
1021 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1022 hw_rf_kill ? "disable radio" : "enable radio");
1023
1024 isr_stats->rfkill++;
1025
1026 /* driver only loads ucode once setting the interface up.
1027 * the driver allows loading the ucode even if the radio
1028 * is killed. Hence update the killswitch state here. The
1029 * rfkill handler will care about restarting if needed.
1030 */
1031 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1032 if (hw_rf_kill)
1033 set_bit(STATUS_RF_KILL_HW,
1034 &trans->shrd->status);
1035 else
1036 clear_bit(STATUS_RF_KILL_HW,
1037 &trans->shrd->status);
1038 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rf_kill);
1039 }
1040
1041 handled |= CSR_INT_BIT_RF_KILL;
1042 }
1043
1044 /* Chip got too hot and stopped itself */
1045 if (inta & CSR_INT_BIT_CT_KILL) {
1046 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1047 isr_stats->ctkill++;
1048 handled |= CSR_INT_BIT_CT_KILL;
1049 }
1050
1051 /* Error detected by uCode */
1052 if (inta & CSR_INT_BIT_SW_ERR) {
1053 IWL_ERR(trans, "Microcode SW error detected. "
1054 " Restarting 0x%X.\n", inta);
1055 isr_stats->sw++;
1056 iwl_irq_handle_error(trans);
1057 handled |= CSR_INT_BIT_SW_ERR;
1058 }
1059
1060 /* uCode wakes up after power-down sleep */
1061 if (inta & CSR_INT_BIT_WAKEUP) {
1062 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1063 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1064 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1065 iwl_txq_update_write_ptr(trans,
1066 &trans_pcie->txq[i]);
1067
1068 isr_stats->wakeup++;
1069
1070 handled |= CSR_INT_BIT_WAKEUP;
1071 }
1072
1073 /* All uCode command responses, including Tx command responses,
1074 * Rx "responses" (frame-received notification), and other
1075 * notifications from uCode come through here*/
1076 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1077 CSR_INT_BIT_RX_PERIODIC)) {
1078 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1079 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1080 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1081 iwl_write32(trans, CSR_FH_INT_STATUS,
1082 CSR_FH_INT_RX_MASK);
1083 }
1084 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1085 handled |= CSR_INT_BIT_RX_PERIODIC;
1086 iwl_write32(trans,
1087 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1088 }
1089 /* Sending RX interrupt require many steps to be done in the
1090 * the device:
1091 * 1- write interrupt to current index in ICT table.
1092 * 2- dma RX frame.
1093 * 3- update RX shared data to indicate last write index.
1094 * 4- send interrupt.
1095 * This could lead to RX race, driver could receive RX interrupt
1096 * but the shared data changes does not reflect this;
1097 * periodic interrupt will detect any dangling Rx activity.
1098 */
1099
1100 /* Disable periodic interrupt; we use it as just a one-shot. */
1101 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1102 CSR_INT_PERIODIC_DIS);
1103 #ifdef CONFIG_IWLWIFI_IDI
1104 iwl_amfh_rx_handler();
1105 #else
1106 iwl_rx_handle(trans);
1107 #endif
1108 /*
1109 * Enable periodic interrupt in 8 msec only if we received
1110 * real RX interrupt (instead of just periodic int), to catch
1111 * any dangling Rx interrupt. If it was just the periodic
1112 * interrupt, there was no dangling Rx activity, and no need
1113 * to extend the periodic interrupt; one-shot is enough.
1114 */
1115 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1116 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1117 CSR_INT_PERIODIC_ENA);
1118
1119 isr_stats->rx++;
1120 }
1121
1122 /* This "Tx" DMA channel is used only for loading uCode */
1123 if (inta & CSR_INT_BIT_FH_TX) {
1124 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1125 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1126 isr_stats->tx++;
1127 handled |= CSR_INT_BIT_FH_TX;
1128 /* Wake up uCode load routine, now that load is complete */
1129 trans->ucode_write_complete = 1;
1130 wake_up(&trans->shrd->wait_command_queue);
1131 }
1132
1133 if (inta & ~handled) {
1134 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1135 isr_stats->unhandled++;
1136 }
1137
1138 if (inta & ~(trans_pcie->inta_mask)) {
1139 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1140 inta & ~trans_pcie->inta_mask);
1141 }
1142
1143 /* Re-enable all interrupts */
1144 /* only Re-enable if disabled by irq */
1145 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1146 iwl_enable_interrupts(trans);
1147 /* Re-enable RF_KILL if it occurred */
1148 else if (handled & CSR_INT_BIT_RF_KILL) {
1149 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1150 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1151 }
1152 }
1153
1154 /******************************************************************************
1155 *
1156 * ICT functions
1157 *
1158 ******************************************************************************/
1159
1160 /* a device (PCI-E) page is 4096 bytes long */
1161 #define ICT_SHIFT 12
1162 #define ICT_SIZE (1 << ICT_SHIFT)
1163 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1164
1165 /* Free dram table */
1166 void iwl_free_isr_ict(struct iwl_trans *trans)
1167 {
1168 struct iwl_trans_pcie *trans_pcie =
1169 IWL_TRANS_GET_PCIE_TRANS(trans);
1170
1171 if (trans_pcie->ict_tbl) {
1172 dma_free_coherent(trans->dev, ICT_SIZE,
1173 trans_pcie->ict_tbl,
1174 trans_pcie->ict_tbl_dma);
1175 trans_pcie->ict_tbl = NULL;
1176 trans_pcie->ict_tbl_dma = 0;
1177 }
1178 }
1179
1180
1181 /*
1182 * allocate dram shared table, it is an aligned memory
1183 * block of ICT_SIZE.
1184 * also reset all data related to ICT table interrupt.
1185 */
1186 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1187 {
1188 struct iwl_trans_pcie *trans_pcie =
1189 IWL_TRANS_GET_PCIE_TRANS(trans);
1190
1191 trans_pcie->ict_tbl =
1192 dma_alloc_coherent(trans->dev, ICT_SIZE,
1193 &trans_pcie->ict_tbl_dma,
1194 GFP_KERNEL);
1195 if (!trans_pcie->ict_tbl)
1196 return -ENOMEM;
1197
1198 /* just an API sanity check ... it is guaranteed to be aligned */
1199 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1200 iwl_free_isr_ict(trans);
1201 return -EINVAL;
1202 }
1203
1204 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1205 (unsigned long long)trans_pcie->ict_tbl_dma);
1206
1207 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1208
1209 /* reset table and index to all 0 */
1210 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1211 trans_pcie->ict_index = 0;
1212
1213 /* add periodic RX interrupt */
1214 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1215 return 0;
1216 }
1217
1218 /* Device is going up inform it about using ICT interrupt table,
1219 * also we need to tell the driver to start using ICT interrupt.
1220 */
1221 void iwl_reset_ict(struct iwl_trans *trans)
1222 {
1223 u32 val;
1224 unsigned long flags;
1225 struct iwl_trans_pcie *trans_pcie =
1226 IWL_TRANS_GET_PCIE_TRANS(trans);
1227
1228 if (!trans_pcie->ict_tbl)
1229 return;
1230
1231 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1232 iwl_disable_interrupts(trans);
1233
1234 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1235
1236 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1237
1238 val |= CSR_DRAM_INT_TBL_ENABLE;
1239 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1240
1241 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1242
1243 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1244 trans_pcie->use_ict = true;
1245 trans_pcie->ict_index = 0;
1246 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1247 iwl_enable_interrupts(trans);
1248 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1249 }
1250
1251 /* Device is going down disable ict interrupt usage */
1252 void iwl_disable_ict(struct iwl_trans *trans)
1253 {
1254 struct iwl_trans_pcie *trans_pcie =
1255 IWL_TRANS_GET_PCIE_TRANS(trans);
1256
1257 unsigned long flags;
1258
1259 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1260 trans_pcie->use_ict = false;
1261 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1262 }
1263
1264 static irqreturn_t iwl_isr(int irq, void *data)
1265 {
1266 struct iwl_trans *trans = data;
1267 struct iwl_trans_pcie *trans_pcie;
1268 u32 inta, inta_mask;
1269 unsigned long flags;
1270 #ifdef CONFIG_IWLWIFI_DEBUG
1271 u32 inta_fh;
1272 #endif
1273 if (!trans)
1274 return IRQ_NONE;
1275
1276 trace_iwlwifi_dev_irq(priv(trans));
1277
1278 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1279
1280 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1281
1282 /* Disable (but don't clear!) interrupts here to avoid
1283 * back-to-back ISRs and sporadic interrupts from our NIC.
1284 * If we have something to service, the tasklet will re-enable ints.
1285 * If we *don't* have something, we'll re-enable before leaving here. */
1286 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1287 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1288
1289 /* Discover which interrupts are active/pending */
1290 inta = iwl_read32(trans, CSR_INT);
1291
1292 /* Ignore interrupt if there's nothing in NIC to service.
1293 * This may be due to IRQ shared with another device,
1294 * or due to sporadic interrupts thrown from our NIC. */
1295 if (!inta) {
1296 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1297 goto none;
1298 }
1299
1300 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1301 /* Hardware disappeared. It might have already raised
1302 * an interrupt */
1303 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1304 goto unplugged;
1305 }
1306
1307 #ifdef CONFIG_IWLWIFI_DEBUG
1308 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1309 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1310 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1311 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1312 }
1313 #endif
1314
1315 trans_pcie->inta |= inta;
1316 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1317 if (likely(inta))
1318 tasklet_schedule(&trans_pcie->irq_tasklet);
1319 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1320 !trans_pcie->inta)
1321 iwl_enable_interrupts(trans);
1322
1323 unplugged:
1324 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1325 return IRQ_HANDLED;
1326
1327 none:
1328 /* re-enable interrupts here since we don't have anything to service. */
1329 /* only Re-enable if disabled by irq and no schedules tasklet. */
1330 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1331 !trans_pcie->inta)
1332 iwl_enable_interrupts(trans);
1333
1334 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1335 return IRQ_NONE;
1336 }
1337
1338 /* interrupt handler using ict table, with this interrupt driver will
1339 * stop using INTA register to get device's interrupt, reading this register
1340 * is expensive, device will write interrupts in ICT dram table, increment
1341 * index then will fire interrupt to driver, driver will OR all ICT table
1342 * entries from current index up to table entry with 0 value. the result is
1343 * the interrupt we need to service, driver will set the entries back to 0 and
1344 * set index.
1345 */
1346 irqreturn_t iwl_isr_ict(int irq, void *data)
1347 {
1348 struct iwl_trans *trans = data;
1349 struct iwl_trans_pcie *trans_pcie;
1350 u32 inta, inta_mask;
1351 u32 val = 0;
1352 u32 read;
1353 unsigned long flags;
1354
1355 if (!trans)
1356 return IRQ_NONE;
1357
1358 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359
1360 /* dram interrupt table not set yet,
1361 * use legacy interrupt.
1362 */
1363 if (!trans_pcie->use_ict)
1364 return iwl_isr(irq, data);
1365
1366 trace_iwlwifi_dev_irq(priv(trans));
1367
1368 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1369
1370 /* Disable (but don't clear!) interrupts here to avoid
1371 * back-to-back ISRs and sporadic interrupts from our NIC.
1372 * If we have something to service, the tasklet will re-enable ints.
1373 * If we *don't* have something, we'll re-enable before leaving here.
1374 */
1375 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1376 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1377
1378
1379 /* Ignore interrupt if there's nothing in NIC to service.
1380 * This may be due to IRQ shared with another device,
1381 * or due to sporadic interrupts thrown from our NIC. */
1382 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1383 trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read);
1384 if (!read) {
1385 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1386 goto none;
1387 }
1388
1389 /*
1390 * Collect all entries up to the first 0, starting from ict_index;
1391 * note we already read at ict_index.
1392 */
1393 do {
1394 val |= read;
1395 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1396 trans_pcie->ict_index, read);
1397 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1398 trans_pcie->ict_index =
1399 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1400
1401 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1402 trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index,
1403 read);
1404 } while (read);
1405
1406 /* We should not get this value, just ignore it. */
1407 if (val == 0xffffffff)
1408 val = 0;
1409
1410 /*
1411 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1412 * (bit 15 before shifting it to 31) to clear when using interrupt
1413 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1414 * so we use them to decide on the real state of the Rx bit.
1415 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1416 */
1417 if (val & 0xC0000)
1418 val |= 0x8000;
1419
1420 inta = (0xff & val) | ((0xff00 & val) << 16);
1421 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1422 inta, inta_mask, val);
1423
1424 inta &= trans_pcie->inta_mask;
1425 trans_pcie->inta |= inta;
1426
1427 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1428 if (likely(inta))
1429 tasklet_schedule(&trans_pcie->irq_tasklet);
1430 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1431 !trans_pcie->inta) {
1432 /* Allow interrupt if was disabled by this handler and
1433 * no tasklet was schedules, We should not enable interrupt,
1434 * tasklet will enable it.
1435 */
1436 iwl_enable_interrupts(trans);
1437 }
1438
1439 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1440 return IRQ_HANDLED;
1441
1442 none:
1443 /* re-enable interrupts here since we don't have anything to service.
1444 * only Re-enable if disabled by irq.
1445 */
1446 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1447 !trans_pcie->inta)
1448 iwl_enable_interrupts(trans);
1449
1450 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1451 return IRQ_NONE;
1452 }
Linux kernel - Deliverables
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