1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 /* TODO: remove include to iwl-dev.h */
35 #include "iwl-debug.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-helpers.h"
41 #include "iwl-trans-pcie-int.h"
43 #define IWL_TX_CRC_SIZE 4
44 #define IWL_TX_DELIMITER_SIZE 4
47 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
50 struct iwl_tx_queue
*txq
,
53 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
54 struct iwl_trans_pcie
*trans_pcie
=
55 IWL_TRANS_GET_PCIE_TRANS(trans
);
56 int write_ptr
= txq
->q
.write_ptr
;
57 int txq_id
= txq
->q
.id
;
60 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
63 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
65 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
67 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
68 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
70 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
78 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
82 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
84 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
86 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
88 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
92 * iwl_txq_update_write_ptr - Send new write index to hardware
94 void iwl_txq_update_write_ptr(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
)
97 int txq_id
= txq
->q
.id
;
99 if (txq
->need_update
== 0)
102 if (hw_params(trans
).shadow_reg_enable
) {
103 /* shadow register enabled */
104 iwl_write32(bus(trans
), HBUS_TARG_WRPTR
,
105 txq
->q
.write_ptr
| (txq_id
<< 8));
107 /* if we're trying to save power */
108 if (test_bit(STATUS_POWER_PMI
, &trans
->shrd
->status
)) {
109 /* wake up nic if it's powered down ...
110 * uCode will wake up, and interrupt us again, so next
111 * time we'll skip this part. */
112 reg
= iwl_read32(bus(trans
), CSR_UCODE_DRV_GP1
);
114 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
115 IWL_DEBUG_INFO(trans
,
116 "Tx queue %d requesting wakeup,"
117 " GP1 = 0x%x\n", txq_id
, reg
);
118 iwl_set_bit(bus(trans
), CSR_GP_CNTRL
,
119 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
123 iwl_write_direct32(bus(trans
), HBUS_TARG_WRPTR
,
124 txq
->q
.write_ptr
| (txq_id
<< 8));
127 * else not in power-save mode,
128 * uCode will never sleep when we're
129 * trying to tx (during RFKILL, we're not trying to tx).
132 iwl_write32(bus(trans
), HBUS_TARG_WRPTR
,
133 txq
->q
.write_ptr
| (txq_id
<< 8));
135 txq
->need_update
= 0;
138 static inline dma_addr_t
iwl_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
140 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
142 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
143 if (sizeof(dma_addr_t
) > sizeof(u32
))
145 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
150 static inline u16
iwl_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
152 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
154 return le16_to_cpu(tb
->hi_n_len
) >> 4;
157 static inline void iwl_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
158 dma_addr_t addr
, u16 len
)
160 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
161 u16 hi_n_len
= len
<< 4;
163 put_unaligned_le32(addr
, &tb
->lo
);
164 if (sizeof(dma_addr_t
) > sizeof(u32
))
165 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
167 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
169 tfd
->num_tbs
= idx
+ 1;
172 static inline u8
iwl_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
174 return tfd
->num_tbs
& 0x1f;
177 static void iwlagn_unmap_tfd(struct iwl_trans
*trans
, struct iwl_cmd_meta
*meta
,
178 struct iwl_tfd
*tfd
, enum dma_data_direction dma_dir
)
183 /* Sanity check on number of chunks */
184 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
186 if (num_tbs
>= IWL_NUM_OF_TBS
) {
187 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
188 /* @todo issue fatal error, it is quite serious situation */
194 dma_unmap_single(bus(trans
)->dev
,
195 dma_unmap_addr(meta
, mapping
),
196 dma_unmap_len(meta
, len
),
199 /* Unmap chunks, if any. */
200 for (i
= 1; i
< num_tbs
; i
++)
201 dma_unmap_single(bus(trans
)->dev
, iwl_tfd_tb_get_addr(tfd
, i
),
202 iwl_tfd_tb_get_len(tfd
, i
), dma_dir
);
206 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
207 * @trans - transport private data
209 * @index - the index of the TFD to be freed
210 *@dma_dir - the direction of the DMA mapping
212 * Does NOT advance any TFD circular buffer read/write indexes
213 * Does NOT free the TFD itself (which is within circular buffer)
215 void iwlagn_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
216 int index
, enum dma_data_direction dma_dir
)
218 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
220 iwlagn_unmap_tfd(trans
, &txq
->meta
[index
], &tfd_tmp
[index
], dma_dir
);
226 skb
= txq
->skbs
[index
];
228 /* Can be called from irqs-disabled context
229 * If skb is not NULL, it means that the whole queue is being
230 * freed and that the queue is not empty - free the skb
233 iwl_free_skb(priv(trans
), skb
);
234 txq
->skbs
[index
] = NULL
;
239 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans
*trans
,
240 struct iwl_tx_queue
*txq
,
241 dma_addr_t addr
, u16 len
,
245 struct iwl_tfd
*tfd
, *tfd_tmp
;
250 tfd
= &tfd_tmp
[q
->write_ptr
];
253 memset(tfd
, 0, sizeof(*tfd
));
255 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
257 /* Each TFD can point to a maximum 20 Tx buffers */
258 if (num_tbs
>= IWL_NUM_OF_TBS
) {
259 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
264 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
267 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
268 IWL_ERR(trans
, "Unaligned address = %llx\n",
269 (unsigned long long)addr
);
271 iwl_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
276 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
279 * Theory of operation
281 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
282 * of buffer descriptors, each of which points to one or more data buffers for
283 * the device to read from or fill. Driver and device exchange status of each
284 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
285 * entries in each circular buffer, to protect against confusing empty and full
288 * The device reads or writes the data in the queues via the device's several
289 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
291 * For Tx queue, there are low mark and high mark limits. If, after queuing
292 * the packet for Tx, free space become < low mark, Tx queue stopped. When
293 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
296 ***************************************************/
298 int iwl_queue_space(const struct iwl_queue
*q
)
300 int s
= q
->read_ptr
- q
->write_ptr
;
302 if (q
->read_ptr
> q
->write_ptr
)
307 /* keep some reserve to not confuse empty and full situations */
315 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
317 int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
320 q
->n_window
= slots_num
;
323 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
324 * and iwl_queue_dec_wrap are broken. */
325 if (WARN_ON(!is_power_of_2(count
)))
328 /* slots_num must be power-of-two size, otherwise
329 * get_cmd_index is broken. */
330 if (WARN_ON(!is_power_of_2(slots_num
)))
333 q
->low_mark
= q
->n_window
/ 4;
337 q
->high_mark
= q
->n_window
/ 8;
338 if (q
->high_mark
< 2)
341 q
->write_ptr
= q
->read_ptr
= 0;
346 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
347 struct iwl_tx_queue
*txq
)
349 struct iwl_trans_pcie
*trans_pcie
=
350 IWL_TRANS_GET_PCIE_TRANS(trans
);
351 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
352 int txq_id
= txq
->q
.id
;
353 int read_ptr
= txq
->q
.read_ptr
;
357 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
359 if (txq_id
!= trans
->shrd
->cmd_queue
)
360 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
362 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
363 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
365 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
367 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
370 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans
*trans
, u16 ra_tid
,
377 struct iwl_trans_pcie
*trans_pcie
=
378 IWL_TRANS_GET_PCIE_TRANS(trans
);
380 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
382 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
383 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
385 tbl_dw
= iwl_read_targ_mem(bus(trans
), tbl_dw_addr
);
388 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
390 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
392 iwl_write_targ_mem(bus(trans
), tbl_dw_addr
, tbl_dw
);
397 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans
*trans
, u16 txq_id
)
399 /* Simply stop the queue, but don't change any configuration;
400 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
401 iwl_write_prph(bus(trans
),
402 SCD_QUEUE_STATUS_BITS(txq_id
),
403 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
404 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
407 void iwl_trans_set_wr_ptrs(struct iwl_trans
*trans
,
408 int txq_id
, u32 index
)
410 iwl_write_direct32(bus(trans
), HBUS_TARG_WRPTR
,
411 (index
& 0xff) | (txq_id
<< 8));
412 iwl_write_prph(bus(trans
), SCD_QUEUE_RDPTR(txq_id
), index
);
415 void iwl_trans_tx_queue_set_status(struct iwl_trans
*trans
,
416 struct iwl_tx_queue
*txq
,
417 int tx_fifo_id
, int scd_retry
)
419 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
420 int txq_id
= txq
->q
.id
;
422 test_bit(txq_id
, &trans_pcie
->txq_ctx_active_msk
) ? 1 : 0;
424 iwl_write_prph(bus(trans
), SCD_QUEUE_STATUS_BITS(txq_id
),
425 (active
<< SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
426 (tx_fifo_id
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
427 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
428 SCD_QUEUE_STTS_REG_MSK
);
430 txq
->sched_retry
= scd_retry
;
432 IWL_DEBUG_INFO(trans
, "%s %s Queue %d on FIFO %d\n",
433 active
? "Activate" : "Deactivate",
434 scd_retry
? "BA" : "AC/CMD", txq_id
, tx_fifo_id
);
437 static inline int get_fifo_from_tid(struct iwl_trans_pcie
*trans_pcie
,
440 const u8
*ac_to_fifo
= trans_pcie
->ac_to_fifo
[ctx
];
441 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
442 return ac_to_fifo
[tid_to_ac
[tid
]];
444 /* no support for TIDs 8-15 yet */
448 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans
*trans
,
449 enum iwl_rxon_context_id ctx
, int sta_id
,
450 int tid
, int frame_limit
)
452 int tx_fifo
, txq_id
, ssn_idx
;
455 struct iwl_tid_data
*tid_data
;
457 struct iwl_trans_pcie
*trans_pcie
=
458 IWL_TRANS_GET_PCIE_TRANS(trans
);
460 if (WARN_ON(sta_id
== IWL_INVALID_STATION
))
462 if (WARN_ON(tid
>= IWL_MAX_TID_COUNT
))
465 tx_fifo
= get_fifo_from_tid(trans_pcie
, ctx
, tid
);
466 if (WARN_ON(tx_fifo
< 0)) {
467 IWL_ERR(trans
, "txq_agg_setup, bad fifo: %d\n", tx_fifo
);
471 spin_lock_irqsave(&trans
->shrd
->sta_lock
, flags
);
472 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
473 ssn_idx
= SEQ_TO_SN(tid_data
->seq_number
);
474 txq_id
= tid_data
->agg
.txq_id
;
475 spin_unlock_irqrestore(&trans
->shrd
->sta_lock
, flags
);
477 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
479 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
481 /* Stop this Tx queue before configuring it */
482 iwlagn_tx_queue_stop_scheduler(trans
, txq_id
);
484 /* Map receiver-address / traffic-ID to this queue */
485 iwlagn_tx_queue_set_q2ratid(trans
, ra_tid
, txq_id
);
487 /* Set this queue as a chain-building queue */
488 iwl_set_bits_prph(bus(trans
), SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
490 /* enable aggregations for the queue */
491 iwl_set_bits_prph(bus(trans
), SCD_AGGR_SEL
, (1<<txq_id
));
493 /* Place first TFD at index corresponding to start sequence number.
494 * Assumes that ssn_idx is valid (!= 0xFFF) */
495 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
496 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
497 iwl_trans_set_wr_ptrs(trans
, txq_id
, ssn_idx
);
499 /* Set up Tx window size and frame limit for this queue */
500 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
501 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
504 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
505 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
507 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
508 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
510 iwl_set_bits_prph(bus(trans
), SCD_INTERRUPT_MASK
, (1 << txq_id
));
512 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
513 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[txq_id
],
516 trans_pcie
->txq
[txq_id
].sta_id
= sta_id
;
517 trans_pcie
->txq
[txq_id
].tid
= tid
;
519 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
523 * Find first available (lowest unused) Tx Queue, mark it "active".
524 * Called only when finding queue for aggregation.
525 * Should never return anything < 7, because they should already
526 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
528 static int iwlagn_txq_ctx_activate_free(struct iwl_trans
*trans
)
530 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
533 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
534 if (!test_and_set_bit(txq_id
,
535 &trans_pcie
->txq_ctx_active_msk
))
540 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans
*trans
,
541 enum iwl_rxon_context_id ctx
, int sta_id
,
544 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
545 struct iwl_tid_data
*tid_data
;
549 txq_id
= iwlagn_txq_ctx_activate_free(trans
);
551 IWL_ERR(trans
, "No free aggregation queue available\n");
555 spin_lock_irqsave(&trans
->shrd
->sta_lock
, flags
);
556 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
557 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
558 tid_data
->agg
.txq_id
= txq_id
;
559 iwl_set_swq_id(&trans_pcie
->txq
[txq_id
], get_ac_from_tid(tid
), txq_id
);
561 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
562 if (tid_data
->tfds_in_queue
== 0) {
563 IWL_DEBUG_HT(trans
, "HW queue is empty\n");
564 tid_data
->agg
.state
= IWL_AGG_ON
;
565 iwl_start_tx_ba_trans_ready(priv(trans
), ctx
, sta_id
, tid
);
567 IWL_DEBUG_HT(trans
, "HW queue is NOT empty: %d packets in HW"
568 "queue\n", tid_data
->tfds_in_queue
);
569 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
571 spin_unlock_irqrestore(&trans
->shrd
->sta_lock
, flags
);
576 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans
*trans
, int txq_id
)
578 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
579 iwlagn_tx_queue_stop_scheduler(trans
, txq_id
);
581 iwl_clear_bits_prph(bus(trans
), SCD_AGGR_SEL
, (1 << txq_id
));
583 trans_pcie
->txq
[txq_id
].q
.read_ptr
= 0;
584 trans_pcie
->txq
[txq_id
].q
.write_ptr
= 0;
585 /* supposes that ssn_idx is valid (!= 0xFFF) */
586 iwl_trans_set_wr_ptrs(trans
, txq_id
, 0);
588 iwl_clear_bits_prph(bus(trans
), SCD_INTERRUPT_MASK
, (1 << txq_id
));
589 iwl_txq_ctx_deactivate(trans_pcie
, txq_id
);
590 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[txq_id
], 0, 0);
593 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans
*trans
,
594 enum iwl_rxon_context_id ctx
, int sta_id
,
597 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
599 int read_ptr
, write_ptr
;
600 struct iwl_tid_data
*tid_data
;
603 spin_lock_irqsave(&trans
->shrd
->sta_lock
, flags
);
605 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
606 txq_id
= tid_data
->agg
.txq_id
;
608 if ((IWLAGN_FIRST_AMPDU_QUEUE
> txq_id
) ||
609 (IWLAGN_FIRST_AMPDU_QUEUE
+
610 hw_params(trans
).num_ampdu_queues
<= txq_id
)) {
612 "queue number out of range: %d, must be %d to %d\n",
613 txq_id
, IWLAGN_FIRST_AMPDU_QUEUE
,
614 IWLAGN_FIRST_AMPDU_QUEUE
+
615 hw_params(trans
).num_ampdu_queues
- 1);
616 spin_unlock_irqrestore(&trans
->shrd
->sta_lock
, flags
);
620 switch (trans
->shrd
->tid_data
[sta_id
][tid
].agg
.state
) {
621 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
623 * This can happen if the peer stops aggregation
624 * again before we've had a chance to drain the
625 * queue we selected previously, i.e. before the
626 * session was really started completely.
628 IWL_DEBUG_HT(trans
, "AGG stop before setup done\n");
633 IWL_WARN(trans
, "Stopping AGG while state not ON"
637 write_ptr
= trans_pcie
->txq
[txq_id
].q
.write_ptr
;
638 read_ptr
= trans_pcie
->txq
[txq_id
].q
.read_ptr
;
640 /* The queue is not empty */
641 if (write_ptr
!= read_ptr
) {
642 IWL_DEBUG_HT(trans
, "Stopping a non empty AGG HW QUEUE\n");
643 trans
->shrd
->tid_data
[sta_id
][tid
].agg
.state
=
644 IWL_EMPTYING_HW_QUEUE_DELBA
;
645 spin_unlock_irqrestore(&trans
->shrd
->sta_lock
, flags
);
649 IWL_DEBUG_HT(trans
, "HW queue is empty\n");
651 trans
->shrd
->tid_data
[sta_id
][tid
].agg
.state
= IWL_AGG_OFF
;
653 /* do not restore/save irqs */
654 spin_unlock(&trans
->shrd
->sta_lock
);
655 spin_lock(&trans
->shrd
->lock
);
657 iwl_trans_pcie_txq_agg_disable(trans
, txq_id
);
659 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
661 iwl_stop_tx_ba_trans_ready(priv(trans
), ctx
, sta_id
, tid
);
666 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
669 * iwl_enqueue_hcmd - enqueue a uCode command
670 * @priv: device private data point
671 * @cmd: a point to the ucode command structure
673 * The function returns < 0 values to indicate the operation is
674 * failed. On success, it turns the index (> 0) of command in the
677 static int iwl_enqueue_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
679 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
680 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[trans
->shrd
->cmd_queue
];
681 struct iwl_queue
*q
= &txq
->q
;
682 struct iwl_device_cmd
*out_cmd
;
683 struct iwl_cmd_meta
*out_meta
;
684 dma_addr_t phys_addr
;
687 u16 copy_size
, cmd_size
;
688 bool is_ct_kill
= false;
689 bool had_nocopy
= false;
692 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
693 const void *trace_bufs
[IWL_MAX_CMD_TFDS
+ 1] = {};
694 int trace_lens
[IWL_MAX_CMD_TFDS
+ 1] = {};
698 if (test_bit(STATUS_FW_ERROR
, &trans
->shrd
->status
)) {
699 IWL_WARN(trans
, "fw recovery, no hcmd send\n");
703 if ((trans
->shrd
->ucode_owner
== IWL_OWNERSHIP_TM
) &&
704 !(cmd
->flags
& CMD_ON_DEMAND
)) {
705 IWL_DEBUG_HC(trans
, "tm own the uCode, no regular hcmd send\n");
709 copy_size
= sizeof(out_cmd
->hdr
);
710 cmd_size
= sizeof(out_cmd
->hdr
);
712 /* need one for the header if the first is NOCOPY */
713 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
> IWL_NUM_OF_TBS
- 1);
715 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
718 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
721 /* NOCOPY must not be followed by normal! */
722 if (WARN_ON(had_nocopy
))
724 copy_size
+= cmd
->len
[i
];
726 cmd_size
+= cmd
->len
[i
];
730 * If any of the command structures end up being larger than
731 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
732 * allocated into separate TFDs, then we will need to
733 * increase the size of the buffers.
735 if (WARN_ON(copy_size
> TFD_MAX_PAYLOAD_SIZE
))
738 if (iwl_is_rfkill(trans
->shrd
) || iwl_is_ctkill(trans
->shrd
)) {
739 IWL_WARN(trans
, "Not sending command - %s KILL\n",
740 iwl_is_rfkill(trans
->shrd
) ? "RF" : "CT");
744 spin_lock_irqsave(&trans
->hcmd_lock
, flags
);
746 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
747 spin_unlock_irqrestore(&trans
->hcmd_lock
, flags
);
749 IWL_ERR(trans
, "No space in command queue\n");
750 is_ct_kill
= iwl_check_for_ct_kill(priv(trans
));
752 IWL_ERR(trans
, "Restarting adapter queue is full\n");
753 iwlagn_fw_error(priv(trans
), false);
758 idx
= get_cmd_index(q
, q
->write_ptr
);
759 out_cmd
= txq
->cmd
[idx
];
760 out_meta
= &txq
->meta
[idx
];
762 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
763 if (cmd
->flags
& CMD_WANT_SKB
)
764 out_meta
->source
= cmd
;
765 if (cmd
->flags
& CMD_ASYNC
)
766 out_meta
->callback
= cmd
->callback
;
768 /* set up the header */
770 out_cmd
->hdr
.cmd
= cmd
->id
;
771 out_cmd
->hdr
.flags
= 0;
772 out_cmd
->hdr
.sequence
=
773 cpu_to_le16(QUEUE_TO_SEQ(trans
->shrd
->cmd_queue
) |
774 INDEX_TO_SEQ(q
->write_ptr
));
776 /* and copy the data that needs to be copied */
778 cmd_dest
= &out_cmd
->cmd
.payload
[0];
779 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
782 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
)
784 memcpy(cmd_dest
, cmd
->data
[i
], cmd
->len
[i
]);
785 cmd_dest
+= cmd
->len
[i
];
788 IWL_DEBUG_HC(trans
, "Sending command %s (#%x), seq: 0x%04X, "
789 "%d bytes at %d[%d]:%d\n",
790 get_cmd_string(out_cmd
->hdr
.cmd
),
792 le16_to_cpu(out_cmd
->hdr
.sequence
), cmd_size
,
793 q
->write_ptr
, idx
, trans
->shrd
->cmd_queue
);
795 phys_addr
= dma_map_single(bus(trans
)->dev
, &out_cmd
->hdr
, copy_size
,
797 if (unlikely(dma_mapping_error(bus(trans
)->dev
, phys_addr
))) {
802 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
803 dma_unmap_len_set(out_meta
, len
, copy_size
);
805 iwlagn_txq_attach_buf_to_tfd(trans
, txq
,
806 phys_addr
, copy_size
, 1);
807 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
808 trace_bufs
[0] = &out_cmd
->hdr
;
809 trace_lens
[0] = copy_size
;
813 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
816 if (!(cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
))
818 phys_addr
= dma_map_single(bus(trans
)->dev
,
819 (void *)cmd
->data
[i
],
820 cmd
->len
[i
], DMA_BIDIRECTIONAL
);
821 if (dma_mapping_error(bus(trans
)->dev
, phys_addr
)) {
822 iwlagn_unmap_tfd(trans
, out_meta
,
823 &txq
->tfds
[q
->write_ptr
],
829 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
831 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
832 trace_bufs
[trace_idx
] = cmd
->data
[i
];
833 trace_lens
[trace_idx
] = cmd
->len
[i
];
838 out_meta
->flags
= cmd
->flags
;
840 txq
->need_update
= 1;
842 /* check that tracing gets all possible blocks */
843 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
+ 1 != 3);
844 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
845 trace_iwlwifi_dev_hcmd(priv(trans
), cmd
->flags
,
846 trace_bufs
[0], trace_lens
[0],
847 trace_bufs
[1], trace_lens
[1],
848 trace_bufs
[2], trace_lens
[2]);
851 /* Increment and update queue's write index */
852 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
853 iwl_txq_update_write_ptr(trans
, txq
);
856 spin_unlock_irqrestore(&trans
->hcmd_lock
, flags
);
861 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
863 * When FW advances 'R' index, all entries between old and new 'R' index
864 * need to be reclaimed. As result, some free space forms. If there is
865 * enough free space (> low mark), wake the stack that feeds us.
867 static void iwl_hcmd_queue_reclaim(struct iwl_trans
*trans
, int txq_id
,
870 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
871 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
872 struct iwl_queue
*q
= &txq
->q
;
875 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
876 IWL_ERR(trans
, "%s: Read index for DMA queue txq id (%d), "
877 "index %d is out of range [0-%d] %d %d.\n", __func__
,
878 txq_id
, idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
882 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
883 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
886 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n", idx
,
887 q
->write_ptr
, q
->read_ptr
);
888 iwlagn_fw_error(priv(trans
), false);
895 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
896 * @rxb: Rx buffer to reclaim
898 * If an Rx buffer has an async callback associated with it the callback
899 * will be executed. The attached skb (if present) will only be freed
900 * if the callback returns 1
902 void iwl_tx_cmd_complete(struct iwl_trans
*trans
, struct iwl_rx_mem_buffer
*rxb
)
904 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
905 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
906 int txq_id
= SEQ_TO_QUEUE(sequence
);
907 int index
= SEQ_TO_INDEX(sequence
);
909 struct iwl_device_cmd
*cmd
;
910 struct iwl_cmd_meta
*meta
;
911 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
912 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[trans
->shrd
->cmd_queue
];
915 /* If a Tx command is being handled and it isn't in the actual
916 * command queue then there a command routing bug has been introduced
917 * in the queue management code. */
918 if (WARN(txq_id
!= trans
->shrd
->cmd_queue
,
919 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
920 txq_id
, trans
->shrd
->cmd_queue
, sequence
,
921 trans_pcie
->txq
[trans
->shrd
->cmd_queue
].q
.read_ptr
,
922 trans_pcie
->txq
[trans
->shrd
->cmd_queue
].q
.write_ptr
)) {
923 iwl_print_hex_error(trans
, pkt
, 32);
927 cmd_index
= get_cmd_index(&txq
->q
, index
);
928 cmd
= txq
->cmd
[cmd_index
];
929 meta
= &txq
->meta
[cmd_index
];
931 iwlagn_unmap_tfd(trans
, meta
, &txq
->tfds
[index
],
934 /* Input error checking is done when commands are added to queue. */
935 if (meta
->flags
& CMD_WANT_SKB
) {
936 meta
->source
->reply_page
= (unsigned long)rxb_addr(rxb
);
938 } else if (meta
->callback
)
939 meta
->callback(trans
->shrd
, cmd
, pkt
);
941 spin_lock_irqsave(&trans
->hcmd_lock
, flags
);
943 iwl_hcmd_queue_reclaim(trans
, txq_id
, index
);
945 if (!(meta
->flags
& CMD_ASYNC
)) {
946 clear_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
);
947 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
948 get_cmd_string(cmd
->hdr
.cmd
));
949 wake_up(&trans
->shrd
->wait_command_queue
);
954 spin_unlock_irqrestore(&trans
->hcmd_lock
, flags
);
957 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
959 static void iwl_generic_cmd_callback(struct iwl_shared
*shrd
,
960 struct iwl_device_cmd
*cmd
,
961 struct iwl_rx_packet
*pkt
)
963 if (pkt
->hdr
.flags
& IWL_CMD_FAILED_MSK
) {
964 IWL_ERR(shrd
->trans
, "Bad return from %s (0x%08X)\n",
965 get_cmd_string(cmd
->hdr
.cmd
), pkt
->hdr
.flags
);
969 #ifdef CONFIG_IWLWIFI_DEBUG
970 switch (cmd
->hdr
.cmd
) {
971 case REPLY_TX_LINK_QUALITY_CMD
:
972 case SENSITIVITY_CMD
:
973 IWL_DEBUG_HC_DUMP(shrd
->trans
, "back from %s (0x%08X)\n",
974 get_cmd_string(cmd
->hdr
.cmd
), pkt
->hdr
.flags
);
977 IWL_DEBUG_HC(shrd
->trans
, "back from %s (0x%08X)\n",
978 get_cmd_string(cmd
->hdr
.cmd
), pkt
->hdr
.flags
);
983 static int iwl_send_cmd_async(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
987 /* An asynchronous command can not expect an SKB to be set. */
988 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
991 /* Assign a generic callback if one is not provided */
993 cmd
->callback
= iwl_generic_cmd_callback
;
995 if (test_bit(STATUS_EXIT_PENDING
, &trans
->shrd
->status
))
998 ret
= iwl_enqueue_hcmd(trans
, cmd
);
1000 IWL_ERR(trans
, "Error sending %s: enqueue_hcmd failed: %d\n",
1001 get_cmd_string(cmd
->id
), ret
);
1007 static int iwl_send_cmd_sync(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1009 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1013 lockdep_assert_held(&trans
->shrd
->mutex
);
1015 /* A synchronous command can not have a callback set. */
1016 if (WARN_ON(cmd
->callback
))
1019 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1020 get_cmd_string(cmd
->id
));
1022 set_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
);
1023 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1024 get_cmd_string(cmd
->id
));
1026 cmd_idx
= iwl_enqueue_hcmd(trans
, cmd
);
1029 clear_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
);
1030 IWL_ERR(trans
, "Error sending %s: enqueue_hcmd failed: %d\n",
1031 get_cmd_string(cmd
->id
), ret
);
1035 ret
= wait_event_timeout(trans
->shrd
->wait_command_queue
,
1036 !test_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
),
1037 HOST_COMPLETE_TIMEOUT
);
1039 if (test_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
)) {
1041 "Error sending %s: time out after %dms.\n",
1042 get_cmd_string(cmd
->id
),
1043 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1045 clear_bit(STATUS_HCMD_ACTIVE
, &trans
->shrd
->status
);
1046 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command"
1047 "%s\n", get_cmd_string(cmd
->id
));
1053 if (test_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
)) {
1054 IWL_ERR(trans
, "Command %s aborted: RF KILL Switch\n",
1055 get_cmd_string(cmd
->id
));
1059 if (test_bit(STATUS_FW_ERROR
, &trans
->shrd
->status
)) {
1060 IWL_ERR(trans
, "Command %s failed: FW Error\n",
1061 get_cmd_string(cmd
->id
));
1065 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->reply_page
) {
1066 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1067 get_cmd_string(cmd
->id
));
1075 if (cmd
->flags
& CMD_WANT_SKB
) {
1077 * Cancel the CMD_WANT_SKB flag for the cmd in the
1078 * TX cmd queue. Otherwise in case the cmd comes
1079 * in later, it will possibly set an invalid
1080 * address (cmd->meta.source).
1082 trans_pcie
->txq
[trans
->shrd
->cmd_queue
].meta
[cmd_idx
].flags
&=
1086 if (cmd
->reply_page
) {
1087 iwl_free_pages(trans
->shrd
, cmd
->reply_page
);
1088 cmd
->reply_page
= 0;
1094 int iwl_trans_pcie_send_cmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1096 if (cmd
->flags
& CMD_ASYNC
)
1097 return iwl_send_cmd_async(trans
, cmd
);
1099 return iwl_send_cmd_sync(trans
, cmd
);
1102 /* Frees buffers until index _not_ inclusive */
1103 int iwl_tx_queue_reclaim(struct iwl_trans
*trans
, int txq_id
, int index
,
1104 struct sk_buff_head
*skbs
)
1106 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1107 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1108 struct iwl_queue
*q
= &txq
->q
;
1112 /* This function is not meant to release cmd queue*/
1113 if (WARN_ON(txq_id
== trans
->shrd
->cmd_queue
))
1116 /*Since we free until index _not_ inclusive, the one before index is
1117 * the last we will free. This one must be used */
1118 last_to_free
= iwl_queue_dec_wrap(index
, q
->n_bd
);
1120 if ((index
>= q
->n_bd
) ||
1121 (iwl_queue_used(q
, last_to_free
) == 0)) {
1122 IWL_ERR(trans
, "%s: Read index for DMA queue txq id (%d), "
1123 "last_to_free %d is out of range [0-%d] %d %d.\n",
1124 __func__
, txq_id
, last_to_free
, q
->n_bd
,
1125 q
->write_ptr
, q
->read_ptr
);
1129 IWL_DEBUG_TX_REPLY(trans
, "reclaim: [%d, %d, %d]\n", txq_id
,
1130 q
->read_ptr
, index
);
1132 if (WARN_ON(!skb_queue_empty(skbs
)))
1136 q
->read_ptr
!= index
;
1137 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1139 if (WARN_ON_ONCE(txq
->skbs
[txq
->q
.read_ptr
] == NULL
))
1142 __skb_queue_tail(skbs
, txq
->skbs
[txq
->q
.read_ptr
]);
1144 txq
->skbs
[txq
->q
.read_ptr
] = NULL
;
1146 iwlagn_txq_inval_byte_cnt_tbl(trans
, txq
);
1148 iwlagn_txq_free_tfd(trans
, txq
, txq
->q
.read_ptr
, DMA_TO_DEVICE
);