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iwlwifi: pass response packet directly
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-tx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-agn-hw.h"
38 #include "iwl-op-mode.h"
39 #include "iwl-trans-pcie-int.h"
40
41 #define IWL_TX_CRC_SIZE 4
42 #define IWL_TX_DELIMITER_SIZE 4
43
44 /**
45 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
46 */
47 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
48 struct iwl_tx_queue *txq,
49 u16 byte_cnt)
50 {
51 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
52 struct iwl_trans_pcie *trans_pcie =
53 IWL_TRANS_GET_PCIE_TRANS(trans);
54 int write_ptr = txq->q.write_ptr;
55 int txq_id = txq->q.id;
56 u8 sec_ctl = 0;
57 u8 sta_id = 0;
58 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
59 __le16 bc_ent;
60 struct iwl_tx_cmd *tx_cmd =
61 (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload;
62
63 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
64
65 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
66
67 sta_id = tx_cmd->sta_id;
68 sec_ctl = tx_cmd->sec_ctl;
69
70 switch (sec_ctl & TX_CMD_SEC_MSK) {
71 case TX_CMD_SEC_CCM:
72 len += CCMP_MIC_LEN;
73 break;
74 case TX_CMD_SEC_TKIP:
75 len += TKIP_ICV_LEN;
76 break;
77 case TX_CMD_SEC_WEP:
78 len += WEP_IV_LEN + WEP_ICV_LEN;
79 break;
80 }
81
82 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
83
84 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
85
86 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
87 scd_bc_tbl[txq_id].
88 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
89 }
90
91 /**
92 * iwl_txq_update_write_ptr - Send new write index to hardware
93 */
94 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
95 {
96 u32 reg = 0;
97 int txq_id = txq->q.id;
98
99 if (txq->need_update == 0)
100 return;
101
102 if (hw_params(trans).shadow_reg_enable) {
103 /* shadow register enabled */
104 iwl_write32(trans, HBUS_TARG_WRPTR,
105 txq->q.write_ptr | (txq_id << 8));
106 } else {
107 /* if we're trying to save power */
108 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
109 /* wake up nic if it's powered down ...
110 * uCode will wake up, and interrupt us again, so next
111 * time we'll skip this part. */
112 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
113
114 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
115 IWL_DEBUG_INFO(trans,
116 "Tx queue %d requesting wakeup,"
117 " GP1 = 0x%x\n", txq_id, reg);
118 iwl_set_bit(trans, CSR_GP_CNTRL,
119 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
120 return;
121 }
122
123 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
124 txq->q.write_ptr | (txq_id << 8));
125
126 /*
127 * else not in power-save mode,
128 * uCode will never sleep when we're
129 * trying to tx (during RFKILL, we're not trying to tx).
130 */
131 } else
132 iwl_write32(trans, HBUS_TARG_WRPTR,
133 txq->q.write_ptr | (txq_id << 8));
134 }
135 txq->need_update = 0;
136 }
137
138 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
139 {
140 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
141
142 dma_addr_t addr = get_unaligned_le32(&tb->lo);
143 if (sizeof(dma_addr_t) > sizeof(u32))
144 addr |=
145 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
146
147 return addr;
148 }
149
150 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
151 {
152 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
153
154 return le16_to_cpu(tb->hi_n_len) >> 4;
155 }
156
157 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
158 dma_addr_t addr, u16 len)
159 {
160 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
161 u16 hi_n_len = len << 4;
162
163 put_unaligned_le32(addr, &tb->lo);
164 if (sizeof(dma_addr_t) > sizeof(u32))
165 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
166
167 tb->hi_n_len = cpu_to_le16(hi_n_len);
168
169 tfd->num_tbs = idx + 1;
170 }
171
172 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
173 {
174 return tfd->num_tbs & 0x1f;
175 }
176
177 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
178 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
179 {
180 int i;
181 int num_tbs;
182
183 /* Sanity check on number of chunks */
184 num_tbs = iwl_tfd_get_num_tbs(tfd);
185
186 if (num_tbs >= IWL_NUM_OF_TBS) {
187 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
188 /* @todo issue fatal error, it is quite serious situation */
189 return;
190 }
191
192 /* Unmap tx_cmd */
193 if (num_tbs)
194 dma_unmap_single(trans->dev,
195 dma_unmap_addr(meta, mapping),
196 dma_unmap_len(meta, len),
197 DMA_BIDIRECTIONAL);
198
199 /* Unmap chunks, if any. */
200 for (i = 1; i < num_tbs; i++)
201 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
202 iwl_tfd_tb_get_len(tfd, i), dma_dir);
203 }
204
205 /**
206 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
207 * @trans - transport private data
208 * @txq - tx queue
209 * @index - the index of the TFD to be freed
210 *@dma_dir - the direction of the DMA mapping
211 *
212 * Does NOT advance any TFD circular buffer read/write indexes
213 * Does NOT free the TFD itself (which is within circular buffer)
214 */
215 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
216 int index, enum dma_data_direction dma_dir)
217 {
218 struct iwl_tfd *tfd_tmp = txq->tfds;
219
220 lockdep_assert_held(&txq->lock);
221
222 iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir);
223
224 /* free SKB */
225 if (txq->skbs) {
226 struct sk_buff *skb;
227
228 skb = txq->skbs[index];
229
230 /* Can be called from irqs-disabled context
231 * If skb is not NULL, it means that the whole queue is being
232 * freed and that the queue is not empty - free the skb
233 */
234 if (skb) {
235 iwl_op_mode_free_skb(trans->op_mode, skb);
236 txq->skbs[index] = NULL;
237 }
238 }
239 }
240
241 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
242 struct iwl_tx_queue *txq,
243 dma_addr_t addr, u16 len,
244 u8 reset)
245 {
246 struct iwl_queue *q;
247 struct iwl_tfd *tfd, *tfd_tmp;
248 u32 num_tbs;
249
250 q = &txq->q;
251 tfd_tmp = txq->tfds;
252 tfd = &tfd_tmp[q->write_ptr];
253
254 if (reset)
255 memset(tfd, 0, sizeof(*tfd));
256
257 num_tbs = iwl_tfd_get_num_tbs(tfd);
258
259 /* Each TFD can point to a maximum 20 Tx buffers */
260 if (num_tbs >= IWL_NUM_OF_TBS) {
261 IWL_ERR(trans, "Error can not send more than %d chunks\n",
262 IWL_NUM_OF_TBS);
263 return -EINVAL;
264 }
265
266 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
267 return -EINVAL;
268
269 if (unlikely(addr & ~IWL_TX_DMA_MASK))
270 IWL_ERR(trans, "Unaligned address = %llx\n",
271 (unsigned long long)addr);
272
273 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
274
275 return 0;
276 }
277
278 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
279 * DMA services
280 *
281 * Theory of operation
282 *
283 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
284 * of buffer descriptors, each of which points to one or more data buffers for
285 * the device to read from or fill. Driver and device exchange status of each
286 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
287 * entries in each circular buffer, to protect against confusing empty and full
288 * queue states.
289 *
290 * The device reads or writes the data in the queues via the device's several
291 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
292 *
293 * For Tx queue, there are low mark and high mark limits. If, after queuing
294 * the packet for Tx, free space become < low mark, Tx queue stopped. When
295 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
296 * Tx queue resumed.
297 *
298 ***************************************************/
299
300 int iwl_queue_space(const struct iwl_queue *q)
301 {
302 int s = q->read_ptr - q->write_ptr;
303
304 if (q->read_ptr > q->write_ptr)
305 s -= q->n_bd;
306
307 if (s <= 0)
308 s += q->n_window;
309 /* keep some reserve to not confuse empty and full situations */
310 s -= 2;
311 if (s < 0)
312 s = 0;
313 return s;
314 }
315
316 /**
317 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
318 */
319 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
320 {
321 q->n_bd = count;
322 q->n_window = slots_num;
323 q->id = id;
324
325 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
326 * and iwl_queue_dec_wrap are broken. */
327 if (WARN_ON(!is_power_of_2(count)))
328 return -EINVAL;
329
330 /* slots_num must be power-of-two size, otherwise
331 * get_cmd_index is broken. */
332 if (WARN_ON(!is_power_of_2(slots_num)))
333 return -EINVAL;
334
335 q->low_mark = q->n_window / 4;
336 if (q->low_mark < 4)
337 q->low_mark = 4;
338
339 q->high_mark = q->n_window / 8;
340 if (q->high_mark < 2)
341 q->high_mark = 2;
342
343 q->write_ptr = q->read_ptr = 0;
344
345 return 0;
346 }
347
348 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
349 struct iwl_tx_queue *txq)
350 {
351 struct iwl_trans_pcie *trans_pcie =
352 IWL_TRANS_GET_PCIE_TRANS(trans);
353 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
354 int txq_id = txq->q.id;
355 int read_ptr = txq->q.read_ptr;
356 u8 sta_id = 0;
357 __le16 bc_ent;
358 struct iwl_tx_cmd *tx_cmd =
359 (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload;
360
361 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
362
363 if (txq_id != trans->shrd->cmd_queue)
364 sta_id = tx_cmd->sta_id;
365
366 bc_ent = cpu_to_le16(1 | (sta_id << 12));
367 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
368
369 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
370 scd_bc_tbl[txq_id].
371 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
372 }
373
374 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
375 u16 txq_id)
376 {
377 u32 tbl_dw_addr;
378 u32 tbl_dw;
379 u16 scd_q2ratid;
380
381 struct iwl_trans_pcie *trans_pcie =
382 IWL_TRANS_GET_PCIE_TRANS(trans);
383
384 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
385
386 tbl_dw_addr = trans_pcie->scd_base_addr +
387 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
388
389 tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
390
391 if (txq_id & 0x1)
392 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
393 else
394 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
395
396 iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
397
398 return 0;
399 }
400
401 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
402 {
403 /* Simply stop the queue, but don't change any configuration;
404 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
405 iwl_write_prph(trans,
406 SCD_QUEUE_STATUS_BITS(txq_id),
407 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
408 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
409 }
410
411 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
412 int txq_id, u32 index)
413 {
414 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff);
415 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
416 (index & 0xff) | (txq_id << 8));
417 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
418 }
419
420 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
421 struct iwl_tx_queue *txq,
422 int tx_fifo_id, int scd_retry)
423 {
424 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
425 int txq_id = txq->q.id;
426 int active =
427 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
428
429 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
430 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
431 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
432 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
433 SCD_QUEUE_STTS_REG_MSK);
434
435 txq->sched_retry = scd_retry;
436
437 if (active)
438 IWL_DEBUG_TX_QUEUES(trans, "Activate %s Queue %d on FIFO %d\n",
439 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
440 else
441 IWL_DEBUG_TX_QUEUES(trans, "Deactivate %s Queue %d\n",
442 scd_retry ? "BA" : "AC/CMD", txq_id);
443 }
444
445 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
446 u8 ctx, u16 tid)
447 {
448 const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
449 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
450 return ac_to_fifo[tid_to_ac[tid]];
451
452 /* no support for TIDs 8-15 yet */
453 return -EINVAL;
454 }
455
456 static inline bool is_agg_txqid_valid(struct iwl_trans *trans, int txq_id)
457 {
458 if (txq_id < IWLAGN_FIRST_AMPDU_QUEUE)
459 return false;
460 return txq_id < (IWLAGN_FIRST_AMPDU_QUEUE +
461 hw_params(trans).num_ampdu_queues);
462 }
463
464 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
465 enum iwl_rxon_context_id ctx, int sta_id,
466 int tid, int frame_limit, u16 ssn)
467 {
468 int tx_fifo, txq_id;
469 u16 ra_tid;
470 unsigned long flags;
471
472 struct iwl_trans_pcie *trans_pcie =
473 IWL_TRANS_GET_PCIE_TRANS(trans);
474
475 if (WARN_ON(sta_id == IWL_INVALID_STATION))
476 return;
477 if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
478 return;
479
480 tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
481 if (WARN_ON(tx_fifo < 0)) {
482 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
483 return;
484 }
485
486 txq_id = trans_pcie->agg_txq[sta_id][tid];
487 if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) {
488 IWL_ERR(trans,
489 "queue number out of range: %d, must be %d to %d\n",
490 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
491 IWLAGN_FIRST_AMPDU_QUEUE +
492 hw_params(trans).num_ampdu_queues - 1);
493 return;
494 }
495
496 ra_tid = BUILD_RAxTID(sta_id, tid);
497
498 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
499
500 /* Stop this Tx queue before configuring it */
501 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
502
503 /* Map receiver-address / traffic-ID to this queue */
504 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
505
506 /* Set this queue as a chain-building queue */
507 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id));
508
509 /* enable aggregations for the queue */
510 iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id));
511
512 /* Place first TFD at index corresponding to start sequence number.
513 * Assumes that ssn_idx is valid (!= 0xFFF) */
514 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
515 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
516 iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
517
518 /* Set up Tx window size and frame limit for this queue */
519 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
520 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
521 sizeof(u32),
522 ((frame_limit <<
523 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
524 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
525 ((frame_limit <<
526 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
527 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
528
529 iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
530
531 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
532 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
533 tx_fifo, 1);
534
535 trans_pcie->txq[txq_id].sta_id = sta_id;
536 trans_pcie->txq[txq_id].tid = tid;
537
538 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
539 }
540
541 /*
542 * Find first available (lowest unused) Tx Queue, mark it "active".
543 * Called only when finding queue for aggregation.
544 * Should never return anything < 7, because they should already
545 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
546 */
547 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
548 {
549 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
550 int txq_id;
551
552 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
553 if (!test_and_set_bit(txq_id,
554 &trans_pcie->txq_ctx_active_msk))
555 return txq_id;
556 return -1;
557 }
558
559 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
560 int sta_id, int tid)
561 {
562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
563 int txq_id;
564
565 txq_id = iwlagn_txq_ctx_activate_free(trans);
566 if (txq_id == -1) {
567 IWL_ERR(trans, "No free aggregation queue available\n");
568 return -ENXIO;
569 }
570
571 trans_pcie->agg_txq[sta_id][tid] = txq_id;
572 iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
573
574 return 0;
575 }
576
577 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid)
578 {
579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
580 u8 txq_id = trans_pcie->agg_txq[sta_id][tid];
581
582 if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) {
583 IWL_ERR(trans,
584 "queue number out of range: %d, must be %d to %d\n",
585 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
586 IWLAGN_FIRST_AMPDU_QUEUE +
587 hw_params(trans).num_ampdu_queues - 1);
588 return -EINVAL;
589 }
590
591 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
592
593 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id));
594
595 trans_pcie->agg_txq[sta_id][tid] = 0;
596 trans_pcie->txq[txq_id].q.read_ptr = 0;
597 trans_pcie->txq[txq_id].q.write_ptr = 0;
598 /* supposes that ssn_idx is valid (!= 0xFFF) */
599 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
600
601 iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
602 iwl_txq_ctx_deactivate(trans_pcie, txq_id);
603 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
604 return 0;
605 }
606
607 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
608
609 /**
610 * iwl_enqueue_hcmd - enqueue a uCode command
611 * @priv: device private data point
612 * @cmd: a point to the ucode command structure
613 *
614 * The function returns < 0 values to indicate the operation is
615 * failed. On success, it turns the index (> 0) of command in the
616 * command queue.
617 */
618 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
619 {
620 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
621 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
622 struct iwl_queue *q = &txq->q;
623 struct iwl_device_cmd *out_cmd;
624 struct iwl_cmd_meta *out_meta;
625 dma_addr_t phys_addr;
626 u32 idx;
627 u16 copy_size, cmd_size;
628 bool is_ct_kill = false;
629 bool had_nocopy = false;
630 int i;
631 u8 *cmd_dest;
632 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
633 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
634 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
635 int trace_idx;
636 #endif
637
638 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
639 IWL_WARN(trans, "fw recovery, no hcmd send\n");
640 return -EIO;
641 }
642
643 if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
644 !(cmd->flags & CMD_ON_DEMAND)) {
645 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
646 return -EIO;
647 }
648
649 copy_size = sizeof(out_cmd->hdr);
650 cmd_size = sizeof(out_cmd->hdr);
651
652 /* need one for the header if the first is NOCOPY */
653 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
654
655 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
656 if (!cmd->len[i])
657 continue;
658 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
659 had_nocopy = true;
660 } else {
661 /* NOCOPY must not be followed by normal! */
662 if (WARN_ON(had_nocopy))
663 return -EINVAL;
664 copy_size += cmd->len[i];
665 }
666 cmd_size += cmd->len[i];
667 }
668
669 /*
670 * If any of the command structures end up being larger than
671 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
672 * allocated into separate TFDs, then we will need to
673 * increase the size of the buffers.
674 */
675 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
676 return -EINVAL;
677
678 if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
679 IWL_WARN(trans, "Not sending command - %s KILL\n",
680 iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
681 return -EIO;
682 }
683
684 spin_lock_bh(&txq->lock);
685
686 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
687 spin_unlock_bh(&txq->lock);
688
689 IWL_ERR(trans, "No space in command queue\n");
690 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
691 if (!is_ct_kill) {
692 IWL_ERR(trans, "Restarting adapter queue is full\n");
693 iwl_op_mode_nic_error(trans->op_mode);
694 }
695 return -ENOSPC;
696 }
697
698 idx = get_cmd_index(q, q->write_ptr);
699 out_cmd = txq->cmd[idx];
700 out_meta = &txq->meta[idx];
701
702 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
703 if (cmd->flags & CMD_WANT_SKB)
704 out_meta->source = cmd;
705
706 /* set up the header */
707
708 out_cmd->hdr.cmd = cmd->id;
709 out_cmd->hdr.flags = 0;
710 out_cmd->hdr.sequence =
711 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
712 INDEX_TO_SEQ(q->write_ptr));
713
714 /* and copy the data that needs to be copied */
715
716 cmd_dest = out_cmd->payload;
717 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
718 if (!cmd->len[i])
719 continue;
720 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
721 break;
722 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
723 cmd_dest += cmd->len[i];
724 }
725
726 IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
727 "%d bytes at %d[%d]:%d\n",
728 get_cmd_string(out_cmd->hdr.cmd),
729 out_cmd->hdr.cmd,
730 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
731 q->write_ptr, idx, trans->shrd->cmd_queue);
732
733 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
734 DMA_BIDIRECTIONAL);
735 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
736 idx = -ENOMEM;
737 goto out;
738 }
739
740 dma_unmap_addr_set(out_meta, mapping, phys_addr);
741 dma_unmap_len_set(out_meta, len, copy_size);
742
743 iwlagn_txq_attach_buf_to_tfd(trans, txq,
744 phys_addr, copy_size, 1);
745 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
746 trace_bufs[0] = &out_cmd->hdr;
747 trace_lens[0] = copy_size;
748 trace_idx = 1;
749 #endif
750
751 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
752 if (!cmd->len[i])
753 continue;
754 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
755 continue;
756 phys_addr = dma_map_single(trans->dev,
757 (void *)cmd->data[i],
758 cmd->len[i], DMA_BIDIRECTIONAL);
759 if (dma_mapping_error(trans->dev, phys_addr)) {
760 iwlagn_unmap_tfd(trans, out_meta,
761 &txq->tfds[q->write_ptr],
762 DMA_BIDIRECTIONAL);
763 idx = -ENOMEM;
764 goto out;
765 }
766
767 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
768 cmd->len[i], 0);
769 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
770 trace_bufs[trace_idx] = cmd->data[i];
771 trace_lens[trace_idx] = cmd->len[i];
772 trace_idx++;
773 #endif
774 }
775
776 out_meta->flags = cmd->flags;
777
778 txq->need_update = 1;
779
780 /* check that tracing gets all possible blocks */
781 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
782 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
783 trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
784 trace_bufs[0], trace_lens[0],
785 trace_bufs[1], trace_lens[1],
786 trace_bufs[2], trace_lens[2]);
787 #endif
788
789 /* Increment and update queue's write index */
790 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
791 iwl_txq_update_write_ptr(trans, txq);
792
793 out:
794 spin_unlock_bh(&txq->lock);
795 return idx;
796 }
797
798 /**
799 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
800 *
801 * When FW advances 'R' index, all entries between old and new 'R' index
802 * need to be reclaimed. As result, some free space forms. If there is
803 * enough free space (> low mark), wake the stack that feeds us.
804 */
805 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
806 int idx)
807 {
808 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
809 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
810 struct iwl_queue *q = &txq->q;
811 int nfreed = 0;
812
813 lockdep_assert_held(&txq->lock);
814
815 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
816 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
817 "index %d is out of range [0-%d] %d %d.\n", __func__,
818 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
819 return;
820 }
821
822 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
823 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
824
825 if (nfreed++ > 0) {
826 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
827 q->write_ptr, q->read_ptr);
828 iwl_op_mode_nic_error(trans->op_mode);
829 }
830
831 }
832 }
833
834 /**
835 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
836 * @rxb: Rx buffer to reclaim
837 * @handler_status: return value of the handler of the command
838 * (put in setup_rx_handlers)
839 *
840 * If an Rx buffer has an async callback associated with it the callback
841 * will be executed. The attached skb (if present) will only be freed
842 * if the callback returns 1
843 */
844 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb,
845 int handler_status)
846 {
847 struct iwl_rx_packet *pkt = rxb_addr(rxb);
848 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
849 int txq_id = SEQ_TO_QUEUE(sequence);
850 int index = SEQ_TO_INDEX(sequence);
851 int cmd_index;
852 struct iwl_device_cmd *cmd;
853 struct iwl_cmd_meta *meta;
854 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
855 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
856
857 /* If a Tx command is being handled and it isn't in the actual
858 * command queue then there a command routing bug has been introduced
859 * in the queue management code. */
860 if (WARN(txq_id != trans->shrd->cmd_queue,
861 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
862 txq_id, trans->shrd->cmd_queue, sequence,
863 trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
864 trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
865 iwl_print_hex_error(trans, pkt, 32);
866 return;
867 }
868
869 spin_lock(&txq->lock);
870
871 cmd_index = get_cmd_index(&txq->q, index);
872 cmd = txq->cmd[cmd_index];
873 meta = &txq->meta[cmd_index];
874
875 txq->time_stamp = jiffies;
876
877 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
878 DMA_BIDIRECTIONAL);
879
880 /* Input error checking is done when commands are added to queue. */
881 if (meta->flags & CMD_WANT_SKB) {
882 struct page *p = rxb->page;
883
884 rxb->page = NULL;
885 meta->source->resp_pkt = pkt;
886 meta->source->_rx_page_addr = (unsigned long)page_address(p);
887 meta->source->_rx_page_order = hw_params(trans).rx_page_order;
888 meta->source->handler_status = handler_status;
889 }
890
891 iwl_hcmd_queue_reclaim(trans, txq_id, index);
892
893 if (!(meta->flags & CMD_ASYNC)) {
894 if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
895 IWL_WARN(trans,
896 "HCMD_ACTIVE already clear for command %s\n",
897 get_cmd_string(cmd->hdr.cmd));
898 }
899 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
900 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
901 get_cmd_string(cmd->hdr.cmd));
902 wake_up(&trans->shrd->wait_command_queue);
903 }
904
905 meta->flags = 0;
906
907 spin_unlock(&txq->lock);
908 }
909
910 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
911
912 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
913 {
914 int ret;
915
916 /* An asynchronous command can not expect an SKB to be set. */
917 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
918 return -EINVAL;
919
920
921 ret = iwl_enqueue_hcmd(trans, cmd);
922 if (ret < 0) {
923 IWL_DEBUG_QUIET_RFKILL(trans,
924 "Error sending %s: enqueue_hcmd failed: %d\n",
925 get_cmd_string(cmd->id), ret);
926 return ret;
927 }
928 return 0;
929 }
930
931 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
932 {
933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
934 int cmd_idx;
935 int ret;
936
937 lockdep_assert_held(&trans->shrd->mutex);
938
939 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
940 get_cmd_string(cmd->id));
941
942 if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
943 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
944 get_cmd_string(cmd->id));
945 return -ECANCELED;
946 }
947 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
948 IWL_ERR(trans, "Command %s failed: FW Error\n",
949 get_cmd_string(cmd->id));
950 return -EIO;
951 }
952 set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
953 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
954 get_cmd_string(cmd->id));
955
956 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
957 if (cmd_idx < 0) {
958 ret = cmd_idx;
959 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
960 IWL_DEBUG_QUIET_RFKILL(trans,
961 "Error sending %s: enqueue_hcmd failed: %d\n",
962 get_cmd_string(cmd->id), ret);
963 return ret;
964 }
965
966 ret = wait_event_timeout(trans->shrd->wait_command_queue,
967 !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
968 HOST_COMPLETE_TIMEOUT);
969 if (!ret) {
970 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
971 struct iwl_tx_queue *txq =
972 &trans_pcie->txq[trans->shrd->cmd_queue];
973 struct iwl_queue *q = &txq->q;
974
975 IWL_DEBUG_QUIET_RFKILL(trans,
976 "Error sending %s: time out after %dms.\n",
977 get_cmd_string(cmd->id),
978 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
979
980 IWL_DEBUG_QUIET_RFKILL(trans,
981 "Current CMD queue read_ptr %d write_ptr %d\n",
982 q->read_ptr, q->write_ptr);
983
984 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
985 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
986 "%s\n", get_cmd_string(cmd->id));
987 ret = -ETIMEDOUT;
988 goto cancel;
989 }
990 }
991
992 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
993 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
994 get_cmd_string(cmd->id));
995 ret = -EIO;
996 goto cancel;
997 }
998
999 return 0;
1000
1001 cancel:
1002 if (cmd->flags & CMD_WANT_SKB) {
1003 /*
1004 * Cancel the CMD_WANT_SKB flag for the cmd in the
1005 * TX cmd queue. Otherwise in case the cmd comes
1006 * in later, it will possibly set an invalid
1007 * address (cmd->meta.source).
1008 */
1009 trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1010 ~CMD_WANT_SKB;
1011 }
1012
1013 if (cmd->resp_pkt) {
1014 iwl_free_resp(cmd);
1015 cmd->resp_pkt = NULL;
1016 }
1017
1018 return ret;
1019 }
1020
1021 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1022 {
1023 if (cmd->flags & CMD_ASYNC)
1024 return iwl_send_cmd_async(trans, cmd);
1025
1026 return iwl_send_cmd_sync(trans, cmd);
1027 }
1028
1029 /* Frees buffers until index _not_ inclusive */
1030 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1031 struct sk_buff_head *skbs)
1032 {
1033 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1034 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1035 struct iwl_queue *q = &txq->q;
1036 int last_to_free;
1037 int freed = 0;
1038
1039 /* This function is not meant to release cmd queue*/
1040 if (WARN_ON(txq_id == trans->shrd->cmd_queue))
1041 return 0;
1042
1043 lockdep_assert_held(&txq->lock);
1044
1045 /*Since we free until index _not_ inclusive, the one before index is
1046 * the last we will free. This one must be used */
1047 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1048
1049 if ((index >= q->n_bd) ||
1050 (iwl_queue_used(q, last_to_free) == 0)) {
1051 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1052 "last_to_free %d is out of range [0-%d] %d %d.\n",
1053 __func__, txq_id, last_to_free, q->n_bd,
1054 q->write_ptr, q->read_ptr);
1055 return 0;
1056 }
1057
1058 if (WARN_ON(!skb_queue_empty(skbs)))
1059 return 0;
1060
1061 for (;
1062 q->read_ptr != index;
1063 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1064
1065 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1066 continue;
1067
1068 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1069
1070 txq->skbs[txq->q.read_ptr] = NULL;
1071
1072 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1073
1074 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE);
1075 freed++;
1076 }
1077 return freed;
1078 }
Linux kernel - Deliverables
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