drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/slab.h>
  31 #include <linux/sched.h>
  32
  33 #include "iwl-debug.h"
  34 #include "iwl-csr.h"
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "iwl-agn-hw.h"
  38 #include "iwl-op-mode.h"
  39 #include "iwl-trans-pcie-int.h"
  40
  41 #define IWL_TX_CRC_SIZE 4
  42 #define IWL_TX_DELIMITER_SIZE 4
  43
  44 /**
  45  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  46  */
  47 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  48                                            struct iwl_tx_queue *txq,
  49                                            u16 byte_cnt)
  50 {
  51         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
  52         struct iwl_trans_pcie *trans_pcie =
  53                 IWL_TRANS_GET_PCIE_TRANS(trans);
  54         int write_ptr = txq->q.write_ptr;
  55         int txq_id = txq->q.id;
  56         u8 sec_ctl = 0;
  57         u8 sta_id = 0;
  58         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  59         __le16 bc_ent;
  60         struct iwl_tx_cmd *tx_cmd =
  61                 (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload;
  62
  63         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
  64
  65         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  66
  67         sta_id = tx_cmd->sta_id;
  68         sec_ctl = tx_cmd->sec_ctl;
  69
  70         switch (sec_ctl & TX_CMD_SEC_MSK) {
  71         case TX_CMD_SEC_CCM:
  72                 len += CCMP_MIC_LEN;
  73                 break;
  74         case TX_CMD_SEC_TKIP:
  75                 len += TKIP_ICV_LEN;
  76                 break;
  77         case TX_CMD_SEC_WEP:
  78                 len += WEP_IV_LEN + WEP_ICV_LEN;
  79                 break;
  80         }
  81
  82         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
  83
  84         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  85
  86         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  87                 scd_bc_tbl[txq_id].
  88                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  89 }
  90
  91 /**
  92  * iwl_txq_update_write_ptr - Send new write index to hardware
  93  */
  94 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
  95 {
  96         u32 reg = 0;
  97         int txq_id = txq->q.id;
  98
  99         if (txq->need_update == 0)
 100                 return;
 101
 102         if (cfg(trans)->base_params->shadow_reg_enable) {
 103                 /* shadow register enabled */
 104                 iwl_write32(trans, HBUS_TARG_WRPTR,
 105                             txq->q.write_ptr | (txq_id << 8));
 106         } else {
 107                 struct iwl_trans_pcie *trans_pcie =
 108                         IWL_TRANS_GET_PCIE_TRANS(trans);
 109                 /* if we're trying to save power */
 110                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 111                         /* wake up nic if it's powered down ...
 112                          * uCode will wake up, and interrupt us again, so next
 113                          * time we'll skip this part. */
 114                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 115
 116                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 117                                 IWL_DEBUG_INFO(trans,
 118                                         "Tx queue %d requesting wakeup,"
 119                                         " GP1 = 0x%x\n", txq_id, reg);
 120                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 121                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 122                                 return;
 123                         }
 124
 125                         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
 126                                      txq->q.write_ptr | (txq_id << 8));
 127
 128                 /*
 129                  * else not in power-save mode,
 130                  * uCode will never sleep when we're
 131                  * trying to tx (during RFKILL, we're not trying to tx).
 132                  */
 133                 } else
 134                         iwl_write32(trans, HBUS_TARG_WRPTR,
 135                                     txq->q.write_ptr | (txq_id << 8));
 136         }
 137         txq->need_update = 0;
 138 }
 139
 140 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 141 {
 142         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 143
 144         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 145         if (sizeof(dma_addr_t) > sizeof(u32))
 146                 addr |=
 147                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 148
 149         return addr;
 150 }
 151
 152 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 153 {
 154         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 155
 156         return le16_to_cpu(tb->hi_n_len) >> 4;
 157 }
 158
 159 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 160                                   dma_addr_t addr, u16 len)
 161 {
 162         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 163         u16 hi_n_len = len << 4;
 164
 165         put_unaligned_le32(addr, &tb->lo);
 166         if (sizeof(dma_addr_t) > sizeof(u32))
 167                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 168
 169         tb->hi_n_len = cpu_to_le16(hi_n_len);
 170
 171         tfd->num_tbs = idx + 1;
 172 }
 173
 174 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 175 {
 176         return tfd->num_tbs & 0x1f;
 177 }
 178
 179 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
 180                      struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
 181 {
 182         int i;
 183         int num_tbs;
 184
 185         /* Sanity check on number of chunks */
 186         num_tbs = iwl_tfd_get_num_tbs(tfd);
 187
 188         if (num_tbs >= IWL_NUM_OF_TBS) {
 189                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 190                 /* @todo issue fatal error, it is quite serious situation */
 191                 return;
 192         }
 193
 194         /* Unmap tx_cmd */
 195         if (num_tbs)
 196                 dma_unmap_single(trans->dev,
 197                                 dma_unmap_addr(meta, mapping),
 198                                 dma_unmap_len(meta, len),
 199                                 DMA_BIDIRECTIONAL);
 200
 201         /* Unmap chunks, if any. */
 202         for (i = 1; i < num_tbs; i++)
 203                 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
 204                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
 205 }
 206
 207 /**
 208  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 209  * @trans - transport private data
 210  * @txq - tx queue
 211  * @index - the index of the TFD to be freed
 212  *@dma_dir - the direction of the DMA mapping
 213  *
 214  * Does NOT advance any TFD circular buffer read/write indexes
 215  * Does NOT free the TFD itself (which is within circular buffer)
 216  */
 217 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 218         int index, enum dma_data_direction dma_dir)
 219 {
 220         struct iwl_tfd *tfd_tmp = txq->tfds;
 221
 222         lockdep_assert_held(&txq->lock);
 223
 224         iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir);
 225
 226         /* free SKB */
 227         if (txq->skbs) {
 228                 struct sk_buff *skb;
 229
 230                 skb = txq->skbs[index];
 231
 232                 /* Can be called from irqs-disabled context
 233                  * If skb is not NULL, it means that the whole queue is being
 234                  * freed and that the queue is not empty - free the skb
 235                  */
 236                 if (skb) {
 237                         iwl_op_mode_free_skb(trans->op_mode, skb);
 238                         txq->skbs[index] = NULL;
 239                 }
 240         }
 241 }
 242
 243 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 244                                  struct iwl_tx_queue *txq,
 245                                  dma_addr_t addr, u16 len,
 246                                  u8 reset)
 247 {
 248         struct iwl_queue *q;
 249         struct iwl_tfd *tfd, *tfd_tmp;
 250         u32 num_tbs;
 251
 252         q = &txq->q;
 253         tfd_tmp = txq->tfds;
 254         tfd = &tfd_tmp[q->write_ptr];
 255
 256         if (reset)
 257                 memset(tfd, 0, sizeof(*tfd));
 258
 259         num_tbs = iwl_tfd_get_num_tbs(tfd);
 260
 261         /* Each TFD can point to a maximum 20 Tx buffers */
 262         if (num_tbs >= IWL_NUM_OF_TBS) {
 263                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 264                           IWL_NUM_OF_TBS);
 265                 return -EINVAL;
 266         }
 267
 268         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 269                 return -EINVAL;
 270
 271         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 272                 IWL_ERR(trans, "Unaligned address = %llx\n",
 273                           (unsigned long long)addr);
 274
 275         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 276
 277         return 0;
 278 }
 279
 280 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 281  * DMA services
 282  *
 283  * Theory of operation
 284  *
 285  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 286  * of buffer descriptors, each of which points to one or more data buffers for
 287  * the device to read from or fill.  Driver and device exchange status of each
 288  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 289  * entries in each circular buffer, to protect against confusing empty and full
 290  * queue states.
 291  *
 292  * The device reads or writes the data in the queues via the device's several
 293  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 294  *
 295  * For Tx queue, there are low mark and high mark limits. If, after queuing
 296  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 297  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 298  * Tx queue resumed.
 299  *
 300  ***************************************************/
 301
 302 int iwl_queue_space(const struct iwl_queue *q)
 303 {
 304         int s = q->read_ptr - q->write_ptr;
 305
 306         if (q->read_ptr > q->write_ptr)
 307                 s -= q->n_bd;
 308
 309         if (s <= 0)
 310                 s += q->n_window;
 311         /* keep some reserve to not confuse empty and full situations */
 312         s -= 2;
 313         if (s < 0)
 314                 s = 0;
 315         return s;
 316 }
 317
 318 /**
 319  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 320  */
 321 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
 322 {
 323         q->n_bd = count;
 324         q->n_window = slots_num;
 325         q->id = id;
 326
 327         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
 328          * and iwl_queue_dec_wrap are broken. */
 329         if (WARN_ON(!is_power_of_2(count)))
 330                 return -EINVAL;
 331
 332         /* slots_num must be power-of-two size, otherwise
 333          * get_cmd_index is broken. */
 334         if (WARN_ON(!is_power_of_2(slots_num)))
 335                 return -EINVAL;
 336
 337         q->low_mark = q->n_window / 4;
 338         if (q->low_mark < 4)
 339                 q->low_mark = 4;
 340
 341         q->high_mark = q->n_window / 8;
 342         if (q->high_mark < 2)
 343                 q->high_mark = 2;
 344
 345         q->write_ptr = q->read_ptr = 0;
 346
 347         return 0;
 348 }
 349
 350 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 351                                           struct iwl_tx_queue *txq)
 352 {
 353         struct iwl_trans_pcie *trans_pcie =
 354                 IWL_TRANS_GET_PCIE_TRANS(trans);
 355         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 356         int txq_id = txq->q.id;
 357         int read_ptr = txq->q.read_ptr;
 358         u8 sta_id = 0;
 359         __le16 bc_ent;
 360         struct iwl_tx_cmd *tx_cmd =
 361                 (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload;
 362
 363         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 364
 365         if (txq_id != trans_pcie->cmd_queue)
 366                 sta_id = tx_cmd->sta_id;
 367
 368         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 369         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 370
 371         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 372                 scd_bc_tbl[txq_id].
 373                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 374 }
 375
 376 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
 377                                         u16 txq_id)
 378 {
 379         u32 tbl_dw_addr;
 380         u32 tbl_dw;
 381         u16 scd_q2ratid;
 382
 383         struct iwl_trans_pcie *trans_pcie =
 384                 IWL_TRANS_GET_PCIE_TRANS(trans);
 385
 386         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 387
 388         tbl_dw_addr = trans_pcie->scd_base_addr +
 389                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 390
 391         tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
 392
 393         if (txq_id & 0x1)
 394                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 395         else
 396                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 397
 398         iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
 399
 400         return 0;
 401 }
 402
 403 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 404 {
 405         /* Simply stop the queue, but don't change any configuration;
 406          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 407         iwl_write_prph(trans,
 408                 SCD_QUEUE_STATUS_BITS(txq_id),
 409                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 410                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 411 }
 412
 413 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
 414                                 int txq_id, u32 index)
 415 {
 416         IWL_DEBUG_TX_QUEUES(trans, "Q %d  WrPtr: %d\n", txq_id, index & 0xff);
 417         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
 418                         (index & 0xff) | (txq_id << 8));
 419         iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
 420 }
 421
 422 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
 423                                    struct iwl_tx_queue *txq,
 424                                    int tx_fifo_id, bool active)
 425 {
 426         int txq_id = txq->q.id;
 427
 428         iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
 429                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 430                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
 431                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
 432                         SCD_QUEUE_STTS_REG_MSK);
 433
 434         if (active)
 435                 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n",
 436                                     txq_id, tx_fifo_id);
 437         else
 438                 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
 439 }
 440
 441 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo,
 442                                  int sta_id, int tid, int frame_limit, u16 ssn)
 443 {
 444         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 445         unsigned long flags;
 446         u16 ra_tid = BUILD_RAxTID(sta_id, tid);
 447
 448         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
 449                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
 450
 451         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 452
 453         /* Stop this Tx queue before configuring it */
 454         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 455
 456         /* Map receiver-address / traffic-ID to this queue */
 457         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 458
 459         /* Set this queue as a chain-building queue */
 460         iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
 461
 462         /* enable aggregations for the queue */
 463         iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 464
 465         /* Place first TFD at index corresponding to start sequence number.
 466          * Assumes that ssn_idx is valid (!= 0xFFF) */
 467         trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
 468         trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
 469         iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
 470
 471         /* Set up Tx window size and frame limit for this queue */
 472         iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
 473                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
 474                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 475                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 476                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 477                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 478
 479         iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
 480
 481         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 482         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 483                                       fifo, true);
 484
 485         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 486 }
 487
 488 void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id)
 489 {
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
 493                 WARN_ONCE(1, "queue %d not used", txq_id);
 494                 return;
 495         }
 496
 497         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 498
 499         iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 500
 501         trans_pcie->txq[txq_id].q.read_ptr = 0;
 502         trans_pcie->txq[txq_id].q.write_ptr = 0;
 503         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
 504
 505         iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id));
 506
 507         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 508                                       0, false);
 509 }
 510
 511 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
 512
 513 /**
 514  * iwl_enqueue_hcmd - enqueue a uCode command
 515  * @priv: device private data point
 516  * @cmd: a point to the ucode command structure
 517  *
 518  * The function returns < 0 values to indicate the operation is
 519  * failed. On success, it turns the index (> 0) of command in the
 520  * command queue.
 521  */
 522 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 523 {
 524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 525         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 526         struct iwl_queue *q = &txq->q;
 527         struct iwl_device_cmd *out_cmd;
 528         struct iwl_cmd_meta *out_meta;
 529         dma_addr_t phys_addr;
 530         u32 idx;
 531         u16 copy_size, cmd_size;
 532         bool had_nocopy = false;
 533         int i;
 534         u8 *cmd_dest;
 535 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 536         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
 537         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
 538         int trace_idx;
 539 #endif
 540
 541         copy_size = sizeof(out_cmd->hdr);
 542         cmd_size = sizeof(out_cmd->hdr);
 543
 544         /* need one for the header if the first is NOCOPY */
 545         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
 546
 547         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 548                 if (!cmd->len[i])
 549                         continue;
 550                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
 551                         had_nocopy = true;
 552                 } else {
 553                         /* NOCOPY must not be followed by normal! */
 554                         if (WARN_ON(had_nocopy))
 555                                 return -EINVAL;
 556                         copy_size += cmd->len[i];
 557                 }
 558                 cmd_size += cmd->len[i];
 559         }
 560
 561         /*
 562          * If any of the command structures end up being larger than
 563          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
 564          * allocated into separate TFDs, then we will need to
 565          * increase the size of the buffers.
 566          */
 567         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
 568                 return -EINVAL;
 569
 570         spin_lock_bh(&txq->lock);
 571
 572         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
 573                 spin_unlock_bh(&txq->lock);
 574
 575                 IWL_ERR(trans, "No space in command queue\n");
 576                 iwl_op_mode_cmd_queue_full(trans->op_mode);
 577                 return -ENOSPC;
 578         }
 579
 580         idx = get_cmd_index(q, q->write_ptr);
 581         out_cmd = txq->cmd[idx];
 582         out_meta = &txq->meta[idx];
 583
 584         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
 585         if (cmd->flags & CMD_WANT_SKB)
 586                 out_meta->source = cmd;
 587
 588         /* set up the header */
 589
 590         out_cmd->hdr.cmd = cmd->id;
 591         out_cmd->hdr.flags = 0;
 592         out_cmd->hdr.sequence =
 593                 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
 594                                          INDEX_TO_SEQ(q->write_ptr));
 595
 596         /* and copy the data that needs to be copied */
 597
 598         cmd_dest = out_cmd->payload;
 599         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 600                 if (!cmd->len[i])
 601                         continue;
 602                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
 603                         break;
 604                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
 605                 cmd_dest += cmd->len[i];
 606         }
 607
 608         IWL_DEBUG_HC(trans,
 609                 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
 610                 trans_pcie_get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
 611                 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
 612                 q->write_ptr, idx, trans_pcie->cmd_queue);
 613
 614         phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
 615                                 DMA_BIDIRECTIONAL);
 616         if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
 617                 idx = -ENOMEM;
 618                 goto out;
 619         }
 620
 621         dma_unmap_addr_set(out_meta, mapping, phys_addr);
 622         dma_unmap_len_set(out_meta, len, copy_size);
 623
 624         iwlagn_txq_attach_buf_to_tfd(trans, txq,
 625                                         phys_addr, copy_size, 1);
 626 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 627         trace_bufs[0] = &out_cmd->hdr;
 628         trace_lens[0] = copy_size;
 629         trace_idx = 1;
 630 #endif
 631
 632         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 633                 if (!cmd->len[i])
 634                         continue;
 635                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
 636                         continue;
 637                 phys_addr = dma_map_single(trans->dev,
 638                                            (void *)cmd->data[i],
 639                                            cmd->len[i], DMA_BIDIRECTIONAL);
 640                 if (dma_mapping_error(trans->dev, phys_addr)) {
 641                         iwlagn_unmap_tfd(trans, out_meta,
 642                                          &txq->tfds[q->write_ptr],
 643                                          DMA_BIDIRECTIONAL);
 644                         idx = -ENOMEM;
 645                         goto out;
 646                 }
 647
 648                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
 649                                              cmd->len[i], 0);
 650 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 651                 trace_bufs[trace_idx] = cmd->data[i];
 652                 trace_lens[trace_idx] = cmd->len[i];
 653                 trace_idx++;
 654 #endif
 655         }
 656
 657         out_meta->flags = cmd->flags;
 658
 659         txq->need_update = 1;
 660
 661         /* check that tracing gets all possible blocks */
 662         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
 663 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 664         trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags,
 665                                trace_bufs[0], trace_lens[0],
 666                                trace_bufs[1], trace_lens[1],
 667                                trace_bufs[2], trace_lens[2]);
 668 #endif
 669
 670         /* start timer if queue currently empty */
 671         if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
 672                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
 673
 674         /* Increment and update queue's write index */
 675         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
 676         iwl_txq_update_write_ptr(trans, txq);
 677
 678  out:
 679         spin_unlock_bh(&txq->lock);
 680         return idx;
 681 }
 682
 683 static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie,
 684                                       struct iwl_tx_queue *txq)
 685 {
 686         if (!trans_pcie->wd_timeout)
 687                 return;
 688
 689         /*
 690          * if empty delete timer, otherwise move timer forward
 691          * since we're making progress on this queue
 692          */
 693         if (txq->q.read_ptr == txq->q.write_ptr)
 694                 del_timer(&txq->stuck_timer);
 695         else
 696                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
 697 }
 698
 699 /**
 700  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 701  *
 702  * When FW advances 'R' index, all entries between old and new 'R' index
 703  * need to be reclaimed. As result, some free space forms.  If there is
 704  * enough free space (> low mark), wake the stack that feeds us.
 705  */
 706 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
 707                                    int idx)
 708 {
 709         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 710         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 711         struct iwl_queue *q = &txq->q;
 712         int nfreed = 0;
 713
 714         lockdep_assert_held(&txq->lock);
 715
 716         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
 717                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
 718                           "index %d is out of range [0-%d] %d %d.\n", __func__,
 719                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
 720                 return;
 721         }
 722
 723         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
 724              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 725
 726                 if (nfreed++ > 0) {
 727                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
 728                                         q->write_ptr, q->read_ptr);
 729                         iwl_op_mode_nic_error(trans->op_mode);
 730                 }
 731
 732         }
 733
 734         iwl_queue_progress(trans_pcie, txq);
 735 }
 736
 737 /**
 738  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 739  * @rxb: Rx buffer to reclaim
 740  * @handler_status: return value of the handler of the command
 741  *      (put in setup_rx_handlers)
 742  *
 743  * If an Rx buffer has an async callback associated with it the callback
 744  * will be executed.  The attached skb (if present) will only be freed
 745  * if the callback returns 1
 746  */
 747 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb,
 748                          int handler_status)
 749 {
 750         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 751         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 752         int txq_id = SEQ_TO_QUEUE(sequence);
 753         int index = SEQ_TO_INDEX(sequence);
 754         int cmd_index;
 755         struct iwl_device_cmd *cmd;
 756         struct iwl_cmd_meta *meta;
 757         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 758         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 759
 760         /* If a Tx command is being handled and it isn't in the actual
 761          * command queue then there a command routing bug has been introduced
 762          * in the queue management code. */
 763         if (WARN(txq_id != trans_pcie->cmd_queue,
 764                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
 765                   txq_id, trans_pcie->cmd_queue, sequence,
 766                   trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
 767                   trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
 768                 iwl_print_hex_error(trans, pkt, 32);
 769                 return;
 770         }
 771
 772         spin_lock(&txq->lock);
 773
 774         cmd_index = get_cmd_index(&txq->q, index);
 775         cmd = txq->cmd[cmd_index];
 776         meta = &txq->meta[cmd_index];
 777
 778         iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
 779                          DMA_BIDIRECTIONAL);
 780
 781         /* Input error checking is done when commands are added to queue. */
 782         if (meta->flags & CMD_WANT_SKB) {
 783                 struct page *p = rxb_steal_page(rxb);
 784
 785                 meta->source->resp_pkt = pkt;
 786                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
 787                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
 788                 meta->source->handler_status = handler_status;
 789         }
 790
 791         iwl_hcmd_queue_reclaim(trans, txq_id, index);
 792
 793         if (!(meta->flags & CMD_ASYNC)) {
 794                 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
 795                         IWL_WARN(trans,
 796                                  "HCMD_ACTIVE already clear for command %s\n",
 797                                  trans_pcie_get_cmd_string(trans_pcie,
 798                                                            cmd->hdr.cmd));
 799                 }
 800                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 801                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
 802                                trans_pcie_get_cmd_string(trans_pcie,
 803                                                          cmd->hdr.cmd));
 804                 wake_up(&trans->wait_command_queue);
 805         }
 806
 807         meta->flags = 0;
 808
 809         spin_unlock(&txq->lock);
 810 }
 811
 812 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
 813
 814 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 815 {
 816         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 817         int ret;
 818
 819         /* An asynchronous command can not expect an SKB to be set. */
 820         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
 821                 return -EINVAL;
 822
 823
 824         ret = iwl_enqueue_hcmd(trans, cmd);
 825         if (ret < 0) {
 826                 IWL_ERR(trans,
 827                         "Error sending %s: enqueue_hcmd failed: %d\n",
 828                         trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
 829                 return ret;
 830         }
 831         return 0;
 832 }
 833
 834 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 835 {
 836         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 837         int cmd_idx;
 838         int ret;
 839
 840         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
 841                        trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 842
 843         if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
 844                                      &trans_pcie->status))) {
 845                 IWL_ERR(trans, "Command %s: a command is already active!\n",
 846                         trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 847                 return -EIO;
 848         }
 849
 850         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
 851                        trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 852
 853         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
 854         if (cmd_idx < 0) {
 855                 ret = cmd_idx;
 856                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 857                 IWL_ERR(trans,
 858                         "Error sending %s: enqueue_hcmd failed: %d\n",
 859                         trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
 860                 return ret;
 861         }
 862
 863         ret = wait_event_timeout(trans->wait_command_queue,
 864                         !test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status),
 865                         HOST_COMPLETE_TIMEOUT);
 866         if (!ret) {
 867                 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
 868                         struct iwl_tx_queue *txq =
 869                                 &trans_pcie->txq[trans_pcie->cmd_queue];
 870                         struct iwl_queue *q = &txq->q;
 871
 872                         IWL_ERR(trans,
 873                                 "Error sending %s: time out after %dms.\n",
 874                                 trans_pcie_get_cmd_string(trans_pcie, cmd->id),
 875                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
 876
 877                         IWL_ERR(trans,
 878                                 "Current CMD queue read_ptr %d write_ptr %d\n",
 879                                 q->read_ptr, q->write_ptr);
 880
 881                         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 882                         IWL_DEBUG_INFO(trans,
 883                                        "Clearing HCMD_ACTIVE for command %s\n",
 884                                        trans_pcie_get_cmd_string(trans_pcie,
 885                                                                  cmd->id));
 886                         ret = -ETIMEDOUT;
 887                         goto cancel;
 888                 }
 889         }
 890
 891         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
 892                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
 893                         trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 894                 ret = -EIO;
 895                 goto cancel;
 896         }
 897
 898         return 0;
 899
 900 cancel:
 901         if (cmd->flags & CMD_WANT_SKB) {
 902                 /*
 903                  * Cancel the CMD_WANT_SKB flag for the cmd in the
 904                  * TX cmd queue. Otherwise in case the cmd comes
 905                  * in later, it will possibly set an invalid
 906                  * address (cmd->meta.source).
 907                  */
 908                 trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &=
 909                                                         ~CMD_WANT_SKB;
 910         }
 911
 912         if (cmd->resp_pkt) {
 913                 iwl_free_resp(cmd);
 914                 cmd->resp_pkt = NULL;
 915         }
 916
 917         return ret;
 918 }
 919
 920 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 921 {
 922         if (cmd->flags & CMD_ASYNC)
 923                 return iwl_send_cmd_async(trans, cmd);
 924
 925         return iwl_send_cmd_sync(trans, cmd);
 926 }
 927
 928 /* Frees buffers until index _not_ inclusive */
 929 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
 930                          struct sk_buff_head *skbs)
 931 {
 932         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 933         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 934         struct iwl_queue *q = &txq->q;
 935         int last_to_free;
 936         int freed = 0;
 937
 938         /* This function is not meant to release cmd queue*/
 939         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
 940                 return 0;
 941
 942         lockdep_assert_held(&txq->lock);
 943
 944         /*Since we free until index _not_ inclusive, the one before index is
 945          * the last we will free. This one must be used */
 946         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
 947
 948         if ((index >= q->n_bd) ||
 949            (iwl_queue_used(q, last_to_free) == 0)) {
 950                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
 951                           "last_to_free %d is out of range [0-%d] %d %d.\n",
 952                           __func__, txq_id, last_to_free, q->n_bd,
 953                           q->write_ptr, q->read_ptr);
 954                 return 0;
 955         }
 956
 957         if (WARN_ON(!skb_queue_empty(skbs)))
 958                 return 0;
 959
 960         for (;
 961              q->read_ptr != index;
 962              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 963
 964                 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
 965                         continue;
 966
 967                 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
 968
 969                 txq->skbs[txq->q.read_ptr] = NULL;
 970
 971                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
 972
 973                 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE);
 974                 freed++;
 975         }
 976
 977         iwl_queue_progress(trans_pcie, txq);
 978
 979         return freed;
 980 }