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iwlwifi: add debugging to shadow registers and fix typo
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-trans-pcie-int.h"
74 #include "iwl-csr.h"
75 #include "iwl-prph.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78 /* FIXME: need to abstract out TX command (once we know what it looks like) */
79 #include "iwl-commands.h"
80
81 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
82 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
83 (~(1<<(trans_pcie)->cmd_queue)))
84
85 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
86 {
87 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
88 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
89 struct device *dev = trans->dev;
90
91 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
92
93 spin_lock_init(&rxq->lock);
94
95 if (WARN_ON(rxq->bd || rxq->rb_stts))
96 return -EINVAL;
97
98 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
99 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
100 &rxq->bd_dma, GFP_KERNEL);
101 if (!rxq->bd)
102 goto err_bd;
103
104 /*Allocate the driver's pointer to receive buffer status */
105 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
106 &rxq->rb_stts_dma, GFP_KERNEL);
107 if (!rxq->rb_stts)
108 goto err_rb_stts;
109
110 return 0;
111
112 err_rb_stts:
113 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
114 rxq->bd, rxq->bd_dma);
115 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
116 rxq->bd = NULL;
117 err_bd:
118 return -ENOMEM;
119 }
120
121 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
122 {
123 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
124 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
125 int i;
126
127 /* Fill the rx_used queue with _all_ of the Rx buffers */
128 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
129 /* In the reset function, these buffers may have been allocated
130 * to an SKB, so we need to unmap and free potential storage */
131 if (rxq->pool[i].page != NULL) {
132 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
133 PAGE_SIZE << trans_pcie->rx_page_order,
134 DMA_FROM_DEVICE);
135 __free_pages(rxq->pool[i].page,
136 trans_pcie->rx_page_order);
137 rxq->pool[i].page = NULL;
138 }
139 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
140 }
141 }
142
143 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
144 struct iwl_rx_queue *rxq)
145 {
146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
147 u32 rb_size;
148 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
149 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
150
151 if (trans_pcie->rx_buf_size_8k)
152 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
153 else
154 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
155
156 /* Stop Rx DMA */
157 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
158
159 /* Reset driver's Rx queue write index */
160 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
161
162 /* Tell device where to find RBD circular buffer in DRAM */
163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
164 (u32)(rxq->bd_dma >> 8));
165
166 /* Tell device where in DRAM to update its Rx status */
167 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
168 rxq->rb_stts_dma >> 4);
169
170 /* Enable Rx DMA
171 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
172 * the credit mechanism in 5000 HW RX FIFO
173 * Direct rx interrupts to hosts
174 * Rx buffer size 4 or 8k
175 * RB timeout 0x10
176 * 256 RBDs
177 */
178 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
179 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
180 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
181 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
182 rb_size|
183 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
184 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
185
186 /* Set interrupt coalescing timer to default (2048 usecs) */
187 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
188 }
189
190 static int iwl_rx_init(struct iwl_trans *trans)
191 {
192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
193 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
194
195 int i, err;
196 unsigned long flags;
197
198 if (!rxq->bd) {
199 err = iwl_trans_rx_alloc(trans);
200 if (err)
201 return err;
202 }
203
204 spin_lock_irqsave(&rxq->lock, flags);
205 INIT_LIST_HEAD(&rxq->rx_free);
206 INIT_LIST_HEAD(&rxq->rx_used);
207
208 iwl_trans_rxq_free_rx_bufs(trans);
209
210 for (i = 0; i < RX_QUEUE_SIZE; i++)
211 rxq->queue[i] = NULL;
212
213 /* Set us so that we have processed and used all buffers, but have
214 * not restocked the Rx queue with fresh buffers */
215 rxq->read = rxq->write = 0;
216 rxq->write_actual = 0;
217 rxq->free_count = 0;
218 spin_unlock_irqrestore(&rxq->lock, flags);
219
220 iwlagn_rx_replenish(trans);
221
222 iwl_trans_rx_hw_init(trans, rxq);
223
224 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
225 rxq->need_update = 1;
226 iwl_rx_queue_update_write_ptr(trans, rxq);
227 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
228
229 return 0;
230 }
231
232 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
233 {
234 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
235 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
236 unsigned long flags;
237
238 /*if rxq->bd is NULL, it means that nothing has been allocated,
239 * exit now */
240 if (!rxq->bd) {
241 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
242 return;
243 }
244
245 spin_lock_irqsave(&rxq->lock, flags);
246 iwl_trans_rxq_free_rx_bufs(trans);
247 spin_unlock_irqrestore(&rxq->lock, flags);
248
249 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
250 rxq->bd, rxq->bd_dma);
251 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
252 rxq->bd = NULL;
253
254 if (rxq->rb_stts)
255 dma_free_coherent(trans->dev,
256 sizeof(struct iwl_rb_status),
257 rxq->rb_stts, rxq->rb_stts_dma);
258 else
259 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
260 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
261 rxq->rb_stts = NULL;
262 }
263
264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
265 {
266
267 /* stop Rx DMA */
268 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
269 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
270 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
271 }
272
273 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
274 struct iwl_dma_ptr *ptr, size_t size)
275 {
276 if (WARN_ON(ptr->addr))
277 return -EINVAL;
278
279 ptr->addr = dma_alloc_coherent(trans->dev, size,
280 &ptr->dma, GFP_KERNEL);
281 if (!ptr->addr)
282 return -ENOMEM;
283 ptr->size = size;
284 return 0;
285 }
286
287 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
288 struct iwl_dma_ptr *ptr)
289 {
290 if (unlikely(!ptr->addr))
291 return;
292
293 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
294 memset(ptr, 0, sizeof(*ptr));
295 }
296
297 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
298 {
299 struct iwl_tx_queue *txq = (void *)data;
300 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
301 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
302
303 spin_lock(&txq->lock);
304 /* check if triggered erroneously */
305 if (txq->q.read_ptr == txq->q.write_ptr) {
306 spin_unlock(&txq->lock);
307 return;
308 }
309 spin_unlock(&txq->lock);
310
311
312 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
313 jiffies_to_msecs(trans_pcie->wd_timeout));
314 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
315 txq->q.read_ptr, txq->q.write_ptr);
316 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
317 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
318 & (TFD_QUEUE_SIZE_MAX - 1),
319 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
320
321 iwl_op_mode_nic_error(trans->op_mode);
322 }
323
324 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
325 struct iwl_tx_queue *txq, int slots_num,
326 u32 txq_id)
327 {
328 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
329 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
330 int i;
331
332 if (WARN_ON(txq->entries || txq->tfds))
333 return -EINVAL;
334
335 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
336 (unsigned long)txq);
337 txq->trans_pcie = trans_pcie;
338
339 txq->q.n_window = slots_num;
340
341 txq->entries = kcalloc(slots_num,
342 sizeof(struct iwl_pcie_tx_queue_entry),
343 GFP_KERNEL);
344
345 if (!txq->entries)
346 goto error;
347
348 if (txq_id == trans_pcie->cmd_queue)
349 for (i = 0; i < slots_num; i++) {
350 txq->entries[i].cmd =
351 kmalloc(sizeof(struct iwl_device_cmd),
352 GFP_KERNEL);
353 if (!txq->entries[i].cmd)
354 goto error;
355 }
356
357 /* Circular buffer of transmit frame descriptors (TFDs),
358 * shared with device */
359 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
360 &txq->q.dma_addr, GFP_KERNEL);
361 if (!txq->tfds) {
362 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
363 goto error;
364 }
365 txq->q.id = txq_id;
366
367 return 0;
368 error:
369 if (txq->entries && txq_id == trans_pcie->cmd_queue)
370 for (i = 0; i < slots_num; i++)
371 kfree(txq->entries[i].cmd);
372 kfree(txq->entries);
373 txq->entries = NULL;
374
375 return -ENOMEM;
376
377 }
378
379 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
380 int slots_num, u32 txq_id)
381 {
382 int ret;
383
384 txq->need_update = 0;
385
386 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
387 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
388 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
389
390 /* Initialize queue's high/low-water marks, and head/tail indexes */
391 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
392 txq_id);
393 if (ret)
394 return ret;
395
396 spin_lock_init(&txq->lock);
397
398 /*
399 * Tell nic where to find circular buffer of Tx Frame Descriptors for
400 * given Tx queue, and enable the DMA channel used for that queue.
401 * Circular buffer (TFD queue in DRAM) physical base address */
402 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
403 txq->q.dma_addr >> 8);
404
405 return 0;
406 }
407
408 /**
409 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
410 */
411 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
412 {
413 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
414 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
415 struct iwl_queue *q = &txq->q;
416 enum dma_data_direction dma_dir;
417
418 if (!q->n_bd)
419 return;
420
421 /* In the command queue, all the TBs are mapped as BIDI
422 * so unmap them as such.
423 */
424 if (txq_id == trans_pcie->cmd_queue)
425 dma_dir = DMA_BIDIRECTIONAL;
426 else
427 dma_dir = DMA_TO_DEVICE;
428
429 spin_lock_bh(&txq->lock);
430 while (q->write_ptr != q->read_ptr) {
431 iwl_txq_free_tfd(trans, txq, dma_dir);
432 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
433 }
434 spin_unlock_bh(&txq->lock);
435 }
436
437 /**
438 * iwl_tx_queue_free - Deallocate DMA queue.
439 * @txq: Transmit queue to deallocate.
440 *
441 * Empty queue by removing and destroying all BD's.
442 * Free all buffers.
443 * 0-fill, but do not free "txq" descriptor structure.
444 */
445 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
446 {
447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
448 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
449 struct device *dev = trans->dev;
450 int i;
451
452 if (WARN_ON(!txq))
453 return;
454
455 iwl_tx_queue_unmap(trans, txq_id);
456
457 /* De-alloc array of command/tx buffers */
458
459 if (txq_id == trans_pcie->cmd_queue)
460 for (i = 0; i < txq->q.n_window; i++)
461 kfree(txq->entries[i].cmd);
462
463 /* De-alloc circular buffer of TFDs */
464 if (txq->q.n_bd) {
465 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
466 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
467 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
468 }
469
470 kfree(txq->entries);
471 txq->entries = NULL;
472
473 del_timer_sync(&txq->stuck_timer);
474
475 /* 0-fill queue descriptor structure */
476 memset(txq, 0, sizeof(*txq));
477 }
478
479 /**
480 * iwl_trans_tx_free - Free TXQ Context
481 *
482 * Destroy all TX DMA queues and structures
483 */
484 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
485 {
486 int txq_id;
487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
488
489 /* Tx queues */
490 if (trans_pcie->txq) {
491 for (txq_id = 0;
492 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
493 iwl_tx_queue_free(trans, txq_id);
494 }
495
496 kfree(trans_pcie->txq);
497 trans_pcie->txq = NULL;
498
499 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
500
501 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
502 }
503
504 /**
505 * iwl_trans_tx_alloc - allocate TX context
506 * Allocate all Tx DMA structures and initialize them
507 *
508 * @param priv
509 * @return error code
510 */
511 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
512 {
513 int ret;
514 int txq_id, slots_num;
515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
516
517 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
518 sizeof(struct iwlagn_scd_bc_tbl);
519
520 /*It is not allowed to alloc twice, so warn when this happens.
521 * We cannot rely on the previous allocation, so free and fail */
522 if (WARN_ON(trans_pcie->txq)) {
523 ret = -EINVAL;
524 goto error;
525 }
526
527 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
528 scd_bc_tbls_size);
529 if (ret) {
530 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
531 goto error;
532 }
533
534 /* Alloc keep-warm buffer */
535 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
536 if (ret) {
537 IWL_ERR(trans, "Keep Warm allocation failed\n");
538 goto error;
539 }
540
541 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
542 sizeof(struct iwl_tx_queue), GFP_KERNEL);
543 if (!trans_pcie->txq) {
544 IWL_ERR(trans, "Not enough memory for txq\n");
545 ret = ENOMEM;
546 goto error;
547 }
548
549 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
550 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
551 txq_id++) {
552 slots_num = (txq_id == trans_pcie->cmd_queue) ?
553 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
554 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
555 slots_num, txq_id);
556 if (ret) {
557 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
558 goto error;
559 }
560 }
561
562 return 0;
563
564 error:
565 iwl_trans_pcie_tx_free(trans);
566
567 return ret;
568 }
569 static int iwl_tx_init(struct iwl_trans *trans)
570 {
571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
572 int ret;
573 int txq_id, slots_num;
574 unsigned long flags;
575 bool alloc = false;
576
577 if (!trans_pcie->txq) {
578 ret = iwl_trans_tx_alloc(trans);
579 if (ret)
580 goto error;
581 alloc = true;
582 }
583
584 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
585
586 /* Turn off all Tx DMA fifos */
587 iwl_write_prph(trans, SCD_TXFACT, 0);
588
589 /* Tell NIC where to find the "keep warm" buffer */
590 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
591 trans_pcie->kw.dma >> 4);
592
593 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
594
595 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
596 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
597 txq_id++) {
598 slots_num = (txq_id == trans_pcie->cmd_queue) ?
599 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
600 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
601 slots_num, txq_id);
602 if (ret) {
603 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
604 goto error;
605 }
606 }
607
608 return 0;
609 error:
610 /*Upon error, free only if we allocated something */
611 if (alloc)
612 iwl_trans_pcie_tx_free(trans);
613 return ret;
614 }
615
616 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
617 {
618 /*
619 * (for documentation purposes)
620 * to set power to V_AUX, do:
621
622 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
623 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
624 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
625 ~APMG_PS_CTRL_MSK_PWR_SRC);
626 */
627
628 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
629 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
630 ~APMG_PS_CTRL_MSK_PWR_SRC);
631 }
632
633 /* PCI registers */
634 #define PCI_CFG_RETRY_TIMEOUT 0x041
635 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
636 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
637
638 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
639 {
640 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
641 int pos;
642 u16 pci_lnk_ctl;
643
644 struct pci_dev *pci_dev = trans_pcie->pci_dev;
645
646 pos = pci_pcie_cap(pci_dev);
647 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
648 return pci_lnk_ctl;
649 }
650
651 static void iwl_apm_config(struct iwl_trans *trans)
652 {
653 /*
654 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
655 * Check if BIOS (or OS) enabled L1-ASPM on this device.
656 * If so (likely), disable L0S, so device moves directly L0->L1;
657 * costs negligible amount of power savings.
658 * If not (unlikely), enable L0S, so there is at least some
659 * power savings, even without L1.
660 */
661 u16 lctl = iwl_pciexp_link_ctrl(trans);
662
663 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
664 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
665 /* L1-ASPM enabled; disable(!) L0S */
666 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
667 dev_printk(KERN_INFO, trans->dev,
668 "L1 Enabled; Disabling L0S\n");
669 } else {
670 /* L1-ASPM disabled; enable(!) L0S */
671 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
672 dev_printk(KERN_INFO, trans->dev,
673 "L1 Disabled; Enabling L0S\n");
674 }
675 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
676 }
677
678 /*
679 * Start up NIC's basic functionality after it has been reset
680 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
681 * NOTE: This does not load uCode nor start the embedded processor
682 */
683 static int iwl_apm_init(struct iwl_trans *trans)
684 {
685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
686 int ret = 0;
687 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
688
689 /*
690 * Use "set_bit" below rather than "write", to preserve any hardware
691 * bits already set by default after reset.
692 */
693
694 /* Disable L0S exit timer (platform NMI Work/Around) */
695 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
696 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
697
698 /*
699 * Disable L0s without affecting L1;
700 * don't wait for ICH L0s (ICH bug W/A)
701 */
702 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
703 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
704
705 /* Set FH wait threshold to maximum (HW error during stress W/A) */
706 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
707
708 /*
709 * Enable HAP INTA (interrupt from management bus) to
710 * wake device's PCI Express link L1a -> L0s
711 */
712 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
713 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
714
715 iwl_apm_config(trans);
716
717 /* Configure analog phase-lock-loop before activating to D0A */
718 if (trans->cfg->base_params->pll_cfg_val)
719 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
720 trans->cfg->base_params->pll_cfg_val);
721
722 /*
723 * Set "initialization complete" bit to move adapter from
724 * D0U* --> D0A* (powered-up active) state.
725 */
726 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
727
728 /*
729 * Wait for clock stabilization; once stabilized, access to
730 * device-internal resources is supported, e.g. iwl_write_prph()
731 * and accesses to uCode SRAM.
732 */
733 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
734 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
735 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
736 if (ret < 0) {
737 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
738 goto out;
739 }
740
741 /*
742 * Enable DMA clock and wait for it to stabilize.
743 *
744 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
745 * do not disable clocks. This preserves any hardware bits already
746 * set by default in "CLK_CTRL_REG" after reset.
747 */
748 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
749 udelay(20);
750
751 /* Disable L1-Active */
752 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
753 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
754
755 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
756
757 out:
758 return ret;
759 }
760
761 static int iwl_apm_stop_master(struct iwl_trans *trans)
762 {
763 int ret = 0;
764
765 /* stop device's busmaster DMA activity */
766 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
767
768 ret = iwl_poll_bit(trans, CSR_RESET,
769 CSR_RESET_REG_FLAG_MASTER_DISABLED,
770 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
771 if (ret)
772 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
773
774 IWL_DEBUG_INFO(trans, "stop master\n");
775
776 return ret;
777 }
778
779 static void iwl_apm_stop(struct iwl_trans *trans)
780 {
781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
782 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
783
784 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
785
786 /* Stop device's DMA activity */
787 iwl_apm_stop_master(trans);
788
789 /* Reset the entire device */
790 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
791
792 udelay(10);
793
794 /*
795 * Clear "initialization complete" bit to move adapter from
796 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
797 */
798 iwl_clear_bit(trans, CSR_GP_CNTRL,
799 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
800 }
801
802 static int iwl_nic_init(struct iwl_trans *trans)
803 {
804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
805 unsigned long flags;
806
807 /* nic_init */
808 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
809 iwl_apm_init(trans);
810
811 /* Set interrupt coalescing calibration timer to default (512 usecs) */
812 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
813
814 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
815
816 iwl_set_pwr_vmain(trans);
817
818 iwl_op_mode_nic_config(trans->op_mode);
819
820 #ifndef CONFIG_IWLWIFI_IDI
821 /* Allocate the RX queue, or reset if it is already allocated */
822 iwl_rx_init(trans);
823 #endif
824
825 /* Allocate or reset and init all Tx and Command queues */
826 if (iwl_tx_init(trans))
827 return -ENOMEM;
828
829 if (trans->cfg->base_params->shadow_reg_enable) {
830 /* enable shadow regs in HW */
831 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
832 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
833 }
834
835 return 0;
836 }
837
838 #define HW_READY_TIMEOUT (50)
839
840 /* Note: returns poll_bit return value, which is >= 0 if success */
841 static int iwl_set_hw_ready(struct iwl_trans *trans)
842 {
843 int ret;
844
845 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
846 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
847
848 /* See if we got it */
849 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
850 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
851 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
852 HW_READY_TIMEOUT);
853
854 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
855 return ret;
856 }
857
858 /* Note: returns standard 0/-ERROR code */
859 static int iwl_prepare_card_hw(struct iwl_trans *trans)
860 {
861 int ret;
862
863 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
864
865 ret = iwl_set_hw_ready(trans);
866 /* If the card is ready, exit 0 */
867 if (ret >= 0)
868 return 0;
869
870 /* If HW is not ready, prepare the conditions to check again */
871 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
872 CSR_HW_IF_CONFIG_REG_PREPARE);
873
874 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
875 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
876 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
877
878 if (ret < 0)
879 return ret;
880
881 /* HW should be ready by now, check again. */
882 ret = iwl_set_hw_ready(trans);
883 if (ret >= 0)
884 return 0;
885 return ret;
886 }
887
888 /*
889 * ucode
890 */
891 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
892 const struct fw_desc *section)
893 {
894 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
895 dma_addr_t phy_addr = section->p_addr;
896 u32 byte_cnt = section->len;
897 u32 dst_addr = section->offset;
898 int ret;
899
900 trans_pcie->ucode_write_complete = false;
901
902 iwl_write_direct32(trans,
903 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
904 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
905
906 iwl_write_direct32(trans,
907 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
908 dst_addr);
909
910 iwl_write_direct32(trans,
911 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
912 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
913
914 iwl_write_direct32(trans,
915 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
916 (iwl_get_dma_hi_addr(phy_addr)
917 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
918
919 iwl_write_direct32(trans,
920 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
921 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
922 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
923 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
924
925 iwl_write_direct32(trans,
926 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
927 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
928 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
929 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
930
931 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
932 section_num);
933 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
934 trans_pcie->ucode_write_complete, 5 * HZ);
935 if (!ret) {
936 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
937 section_num);
938 return -ETIMEDOUT;
939 }
940
941 return 0;
942 }
943
944 static int iwl_load_given_ucode(struct iwl_trans *trans,
945 const struct fw_img *image)
946 {
947 int ret = 0;
948 int i;
949
950 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
951 if (!image->sec[i].p_addr)
952 break;
953
954 ret = iwl_load_section(trans, i, &image->sec[i]);
955 if (ret)
956 return ret;
957 }
958
959 /* Remove all resets to allow NIC to operate */
960 iwl_write32(trans, CSR_RESET, 0);
961
962 return 0;
963 }
964
965 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
966 const struct fw_img *fw)
967 {
968 int ret;
969 bool hw_rfkill;
970
971 /* This may fail if AMT took ownership of the device */
972 if (iwl_prepare_card_hw(trans)) {
973 IWL_WARN(trans, "Exit HW not ready\n");
974 return -EIO;
975 }
976
977 iwl_enable_rfkill_int(trans);
978
979 /* If platform's RF_KILL switch is NOT set to KILL */
980 hw_rfkill = iwl_is_rfkill_set(trans);
981 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
982 if (hw_rfkill)
983 return -ERFKILL;
984
985 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
986
987 ret = iwl_nic_init(trans);
988 if (ret) {
989 IWL_ERR(trans, "Unable to init nic\n");
990 return ret;
991 }
992
993 /* make sure rfkill handshake bits are cleared */
994 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
995 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
996 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
997
998 /* clear (again), then enable host interrupts */
999 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1000 iwl_enable_interrupts(trans);
1001
1002 /* really make sure rfkill handshake bits are cleared */
1003 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1004 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1005
1006 /* Load the given image to the HW */
1007 return iwl_load_given_ucode(trans, fw);
1008 }
1009
1010 /*
1011 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1012 * must be called under the irq lock and with MAC access
1013 */
1014 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1015 {
1016 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1017 IWL_TRANS_GET_PCIE_TRANS(trans);
1018
1019 lockdep_assert_held(&trans_pcie->irq_lock);
1020
1021 iwl_write_prph(trans, SCD_TXFACT, mask);
1022 }
1023
1024 static void iwl_tx_start(struct iwl_trans *trans)
1025 {
1026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1027 u32 a;
1028 unsigned long flags;
1029 int i, chan;
1030 u32 reg_val;
1031
1032 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1033
1034 trans_pcie->scd_base_addr =
1035 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1036 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1037 /* reset conext data memory */
1038 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1039 a += 4)
1040 iwl_write_targ_mem(trans, a, 0);
1041 /* reset tx status memory */
1042 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1043 a += 4)
1044 iwl_write_targ_mem(trans, a, 0);
1045 for (; a < trans_pcie->scd_base_addr +
1046 SCD_TRANS_TBL_OFFSET_QUEUE(
1047 trans->cfg->base_params->num_of_queues);
1048 a += 4)
1049 iwl_write_targ_mem(trans, a, 0);
1050
1051 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1052 trans_pcie->scd_bc_tbls.dma >> 10);
1053
1054 /* Enable DMA channel */
1055 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1056 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1057 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1058 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1059
1060 /* Update FH chicken bits */
1061 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1062 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1063 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1064
1065 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1066 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1067 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1068
1069 /* initiate the queues */
1070 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1071 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1072 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1073 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1074 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1075 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1076 SCD_CONTEXT_QUEUE_OFFSET(i) +
1077 sizeof(u32),
1078 ((SCD_WIN_SIZE <<
1079 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1080 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1081 ((SCD_FRAME_LIMIT <<
1082 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1083 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1084 }
1085
1086 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1087 IWL_MASK(0, trans->cfg->base_params->num_of_queues));
1088
1089 /* Activate all Tx DMA/FIFO channels */
1090 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1091
1092 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1093
1094 /* make sure all queue are not stopped/used */
1095 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1096 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1097
1098 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1099 int fifo = trans_pcie->setup_q_to_fifo[i];
1100
1101 set_bit(i, trans_pcie->queue_used);
1102
1103 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1104 fifo, true);
1105 }
1106
1107 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1108
1109 /* Enable L1-Active */
1110 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1111 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1112 }
1113
1114 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1115 {
1116 iwl_reset_ict(trans);
1117 iwl_tx_start(trans);
1118 }
1119
1120 /**
1121 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1122 */
1123 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1124 {
1125 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1126 int ch, txq_id, ret;
1127 unsigned long flags;
1128
1129 /* Turn off all Tx DMA fifos */
1130 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1131
1132 iwl_trans_txq_set_sched(trans, 0);
1133
1134 /* Stop each Tx DMA channel, and wait for it to be idle */
1135 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1136 iwl_write_direct32(trans,
1137 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1138 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1139 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1140 if (ret < 0)
1141 IWL_ERR(trans,
1142 "Failing on timeout while stopping DMA channel %d [0x%08x]",
1143 ch,
1144 iwl_read_direct32(trans,
1145 FH_TSSR_TX_STATUS_REG));
1146 }
1147 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1148
1149 if (!trans_pcie->txq) {
1150 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1151 return 0;
1152 }
1153
1154 /* Unmap DMA from host system and free skb's */
1155 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1156 txq_id++)
1157 iwl_tx_queue_unmap(trans, txq_id);
1158
1159 return 0;
1160 }
1161
1162 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1163 {
1164 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1165 unsigned long flags;
1166
1167 /* tell the device to stop sending interrupts */
1168 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1169 iwl_disable_interrupts(trans);
1170 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1171
1172 /* device going down, Stop using ICT table */
1173 iwl_disable_ict(trans);
1174
1175 /*
1176 * If a HW restart happens during firmware loading,
1177 * then the firmware loading might call this function
1178 * and later it might be called again due to the
1179 * restart. So don't process again if the device is
1180 * already dead.
1181 */
1182 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1183 iwl_trans_tx_stop(trans);
1184 #ifndef CONFIG_IWLWIFI_IDI
1185 iwl_trans_rx_stop(trans);
1186 #endif
1187 /* Power-down device's busmaster DMA clocks */
1188 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1189 APMG_CLK_VAL_DMA_CLK_RQT);
1190 udelay(5);
1191 }
1192
1193 /* Make sure (redundant) we've released our request to stay awake */
1194 iwl_clear_bit(trans, CSR_GP_CNTRL,
1195 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1196
1197 /* Stop the device, and put it in low power state */
1198 iwl_apm_stop(trans);
1199
1200 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1201 * Clean again the interrupt here
1202 */
1203 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1204 iwl_disable_interrupts(trans);
1205 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1206
1207 iwl_enable_rfkill_int(trans);
1208
1209 /* wait to make sure we flush pending tasklet*/
1210 synchronize_irq(trans_pcie->irq);
1211 tasklet_kill(&trans_pcie->irq_tasklet);
1212
1213 cancel_work_sync(&trans_pcie->rx_replenish);
1214
1215 /* stop and reset the on-board processor */
1216 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1217
1218 /* clear all status bits */
1219 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1220 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1221 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1222 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1223 }
1224
1225 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1226 {
1227 /* let the ucode operate on its own */
1228 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1229 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1230
1231 iwl_disable_interrupts(trans);
1232 iwl_clear_bit(trans, CSR_GP_CNTRL,
1233 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1234 }
1235
1236 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1237 struct iwl_device_cmd *dev_cmd, int txq_id)
1238 {
1239 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1240 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1241 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1242 struct iwl_cmd_meta *out_meta;
1243 struct iwl_tx_queue *txq;
1244 struct iwl_queue *q;
1245 dma_addr_t phys_addr = 0;
1246 dma_addr_t txcmd_phys;
1247 dma_addr_t scratch_phys;
1248 u16 len, firstlen, secondlen;
1249 u8 wait_write_ptr = 0;
1250 __le16 fc = hdr->frame_control;
1251 u8 hdr_len = ieee80211_hdrlen(fc);
1252 u16 __maybe_unused wifi_seq;
1253
1254 txq = &trans_pcie->txq[txq_id];
1255 q = &txq->q;
1256
1257 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1258 WARN_ON_ONCE(1);
1259 return -EINVAL;
1260 }
1261
1262 spin_lock(&txq->lock);
1263
1264 /* Set up driver data for this TFD */
1265 txq->entries[q->write_ptr].skb = skb;
1266 txq->entries[q->write_ptr].cmd = dev_cmd;
1267
1268 dev_cmd->hdr.cmd = REPLY_TX;
1269 dev_cmd->hdr.sequence =
1270 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1271 INDEX_TO_SEQ(q->write_ptr)));
1272
1273 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1274 out_meta = &txq->entries[q->write_ptr].meta;
1275
1276 /*
1277 * Use the first empty entry in this queue's command buffer array
1278 * to contain the Tx command and MAC header concatenated together
1279 * (payload data will be in another buffer).
1280 * Size of this varies, due to varying MAC header length.
1281 * If end is not dword aligned, we'll have 2 extra bytes at the end
1282 * of the MAC header (device reads on dword boundaries).
1283 * We'll tell device about this padding later.
1284 */
1285 len = sizeof(struct iwl_tx_cmd) +
1286 sizeof(struct iwl_cmd_header) + hdr_len;
1287 firstlen = (len + 3) & ~3;
1288
1289 /* Tell NIC about any 2-byte padding after MAC header */
1290 if (firstlen != len)
1291 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1292
1293 /* Physical address of this Tx command's header (not MAC header!),
1294 * within command buffer array. */
1295 txcmd_phys = dma_map_single(trans->dev,
1296 &dev_cmd->hdr, firstlen,
1297 DMA_BIDIRECTIONAL);
1298 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1299 goto out_err;
1300 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1301 dma_unmap_len_set(out_meta, len, firstlen);
1302
1303 if (!ieee80211_has_morefrags(fc)) {
1304 txq->need_update = 1;
1305 } else {
1306 wait_write_ptr = 1;
1307 txq->need_update = 0;
1308 }
1309
1310 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1311 * if any (802.11 null frames have no payload). */
1312 secondlen = skb->len - hdr_len;
1313 if (secondlen > 0) {
1314 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1315 secondlen, DMA_TO_DEVICE);
1316 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1317 dma_unmap_single(trans->dev,
1318 dma_unmap_addr(out_meta, mapping),
1319 dma_unmap_len(out_meta, len),
1320 DMA_BIDIRECTIONAL);
1321 goto out_err;
1322 }
1323 }
1324
1325 /* Attach buffers to TFD */
1326 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1327 if (secondlen > 0)
1328 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1329 secondlen, 0);
1330
1331 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1332 offsetof(struct iwl_tx_cmd, scratch);
1333
1334 /* take back ownership of DMA buffer to enable update */
1335 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1336 DMA_BIDIRECTIONAL);
1337 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1338 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1339
1340 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1341 le16_to_cpu(dev_cmd->hdr.sequence));
1342 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1343
1344 /* Set up entry for this TFD in Tx byte-count array */
1345 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1346
1347 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1348 DMA_BIDIRECTIONAL);
1349
1350 trace_iwlwifi_dev_tx(trans->dev,
1351 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1352 sizeof(struct iwl_tfd),
1353 &dev_cmd->hdr, firstlen,
1354 skb->data + hdr_len, secondlen);
1355
1356 /* start timer if queue currently empty */
1357 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1358 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1359
1360 /* Tell device the write index *just past* this latest filled TFD */
1361 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1362 iwl_txq_update_write_ptr(trans, txq);
1363
1364 /*
1365 * At this point the frame is "transmitted" successfully
1366 * and we will get a TX status notification eventually,
1367 * regardless of the value of ret. "ret" only indicates
1368 * whether or not we should update the write pointer.
1369 */
1370 if (iwl_queue_space(q) < q->high_mark) {
1371 if (wait_write_ptr) {
1372 txq->need_update = 1;
1373 iwl_txq_update_write_ptr(trans, txq);
1374 } else {
1375 iwl_stop_queue(trans, txq);
1376 }
1377 }
1378 spin_unlock(&txq->lock);
1379 return 0;
1380 out_err:
1381 spin_unlock(&txq->lock);
1382 return -1;
1383 }
1384
1385 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1386 {
1387 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1388 int err;
1389 bool hw_rfkill;
1390
1391 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1392
1393 if (!trans_pcie->irq_requested) {
1394 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1395 iwl_irq_tasklet, (unsigned long)trans);
1396
1397 iwl_alloc_isr_ict(trans);
1398
1399 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1400 DRV_NAME, trans);
1401 if (err) {
1402 IWL_ERR(trans, "Error allocating IRQ %d\n",
1403 trans_pcie->irq);
1404 goto error;
1405 }
1406
1407 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1408 trans_pcie->irq_requested = true;
1409 }
1410
1411 err = iwl_prepare_card_hw(trans);
1412 if (err) {
1413 IWL_ERR(trans, "Error while preparing HW: %d", err);
1414 goto err_free_irq;
1415 }
1416
1417 iwl_apm_init(trans);
1418
1419 /* From now on, the op_mode will be kept updated about RF kill state */
1420 iwl_enable_rfkill_int(trans);
1421
1422 hw_rfkill = iwl_is_rfkill_set(trans);
1423 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1424
1425 return err;
1426
1427 err_free_irq:
1428 free_irq(trans_pcie->irq, trans);
1429 error:
1430 iwl_free_isr_ict(trans);
1431 tasklet_kill(&trans_pcie->irq_tasklet);
1432 return err;
1433 }
1434
1435 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1436 bool op_mode_leaving)
1437 {
1438 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1439 bool hw_rfkill;
1440 unsigned long flags;
1441
1442 iwl_apm_stop(trans);
1443
1444 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1445 iwl_disable_interrupts(trans);
1446 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1447
1448 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1449
1450 if (!op_mode_leaving) {
1451 /*
1452 * Even if we stop the HW, we still want the RF kill
1453 * interrupt
1454 */
1455 iwl_enable_rfkill_int(trans);
1456
1457 /*
1458 * Check again since the RF kill state may have changed while
1459 * all the interrupts were disabled, in this case we couldn't
1460 * receive the RF kill interrupt and update the state in the
1461 * op_mode.
1462 */
1463 hw_rfkill = iwl_is_rfkill_set(trans);
1464 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1465 }
1466 }
1467
1468 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1469 struct sk_buff_head *skbs)
1470 {
1471 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1473 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1474 int tfd_num = ssn & (txq->q.n_bd - 1);
1475 int freed = 0;
1476
1477 spin_lock(&txq->lock);
1478
1479 if (txq->q.read_ptr != tfd_num) {
1480 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1481 txq_id, txq->q.read_ptr, tfd_num, ssn);
1482 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1483 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1484 iwl_wake_queue(trans, txq);
1485 }
1486
1487 spin_unlock(&txq->lock);
1488 }
1489
1490 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1491 {
1492 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1493 }
1494
1495 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1496 {
1497 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1498 }
1499
1500 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1501 {
1502 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1503 }
1504
1505 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1506 const struct iwl_trans_config *trans_cfg)
1507 {
1508 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1509
1510 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1511 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1512 trans_pcie->n_no_reclaim_cmds = 0;
1513 else
1514 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1515 if (trans_pcie->n_no_reclaim_cmds)
1516 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1517 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1518
1519 trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1520
1521 if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1522 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1523
1524 /* at least the command queue must be mapped */
1525 WARN_ON(!trans_pcie->n_q_to_fifo);
1526
1527 memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1528 trans_pcie->n_q_to_fifo * sizeof(u8));
1529
1530 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1531 if (trans_pcie->rx_buf_size_8k)
1532 trans_pcie->rx_page_order = get_order(8 * 1024);
1533 else
1534 trans_pcie->rx_page_order = get_order(4 * 1024);
1535
1536 trans_pcie->wd_timeout =
1537 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1538
1539 trans_pcie->command_names = trans_cfg->command_names;
1540 }
1541
1542 void iwl_trans_pcie_free(struct iwl_trans *trans)
1543 {
1544 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1545
1546 iwl_trans_pcie_tx_free(trans);
1547 #ifndef CONFIG_IWLWIFI_IDI
1548 iwl_trans_pcie_rx_free(trans);
1549 #endif
1550 if (trans_pcie->irq_requested == true) {
1551 free_irq(trans_pcie->irq, trans);
1552 iwl_free_isr_ict(trans);
1553 }
1554
1555 pci_disable_msi(trans_pcie->pci_dev);
1556 iounmap(trans_pcie->hw_base);
1557 pci_release_regions(trans_pcie->pci_dev);
1558 pci_disable_device(trans_pcie->pci_dev);
1559
1560 kfree(trans);
1561 }
1562
1563 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1564 {
1565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1566
1567 if (state)
1568 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1569 else
1570 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1571 }
1572
1573 #ifdef CONFIG_PM_SLEEP
1574 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1575 {
1576 return 0;
1577 }
1578
1579 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1580 {
1581 bool hw_rfkill;
1582
1583 iwl_enable_rfkill_int(trans);
1584
1585 hw_rfkill = iwl_is_rfkill_set(trans);
1586 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1587
1588 if (!hw_rfkill)
1589 iwl_enable_interrupts(trans);
1590
1591 return 0;
1592 }
1593 #endif /* CONFIG_PM_SLEEP */
1594
1595 #define IWL_FLUSH_WAIT_MS 2000
1596
1597 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1598 {
1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1600 struct iwl_tx_queue *txq;
1601 struct iwl_queue *q;
1602 int cnt;
1603 unsigned long now = jiffies;
1604 int ret = 0;
1605
1606 /* waiting for all the tx frames complete might take a while */
1607 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1608 if (cnt == trans_pcie->cmd_queue)
1609 continue;
1610 txq = &trans_pcie->txq[cnt];
1611 q = &txq->q;
1612 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1613 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1614 msleep(1);
1615
1616 if (q->read_ptr != q->write_ptr) {
1617 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1618 ret = -ETIMEDOUT;
1619 break;
1620 }
1621 }
1622 return ret;
1623 }
1624
1625 static const char *get_fh_string(int cmd)
1626 {
1627 #define IWL_CMD(x) case x: return #x
1628 switch (cmd) {
1629 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1630 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1631 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1632 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1633 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1634 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1635 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1636 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1637 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1638 default:
1639 return "UNKNOWN";
1640 }
1641 #undef IWL_CMD
1642 }
1643
1644 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1645 {
1646 int i;
1647 #ifdef CONFIG_IWLWIFI_DEBUG
1648 int pos = 0;
1649 size_t bufsz = 0;
1650 #endif
1651 static const u32 fh_tbl[] = {
1652 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1653 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1654 FH_RSCSR_CHNL0_WPTR,
1655 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1656 FH_MEM_RSSR_SHARED_CTRL_REG,
1657 FH_MEM_RSSR_RX_STATUS_REG,
1658 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1659 FH_TSSR_TX_STATUS_REG,
1660 FH_TSSR_TX_ERROR_REG
1661 };
1662 #ifdef CONFIG_IWLWIFI_DEBUG
1663 if (display) {
1664 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1665 *buf = kmalloc(bufsz, GFP_KERNEL);
1666 if (!*buf)
1667 return -ENOMEM;
1668 pos += scnprintf(*buf + pos, bufsz - pos,
1669 "FH register values:\n");
1670 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1671 pos += scnprintf(*buf + pos, bufsz - pos,
1672 " %34s: 0X%08x\n",
1673 get_fh_string(fh_tbl[i]),
1674 iwl_read_direct32(trans, fh_tbl[i]));
1675 }
1676 return pos;
1677 }
1678 #endif
1679 IWL_ERR(trans, "FH register values:\n");
1680 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1681 IWL_ERR(trans, " %34s: 0X%08x\n",
1682 get_fh_string(fh_tbl[i]),
1683 iwl_read_direct32(trans, fh_tbl[i]));
1684 }
1685 return 0;
1686 }
1687
1688 static const char *get_csr_string(int cmd)
1689 {
1690 #define IWL_CMD(x) case x: return #x
1691 switch (cmd) {
1692 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1693 IWL_CMD(CSR_INT_COALESCING);
1694 IWL_CMD(CSR_INT);
1695 IWL_CMD(CSR_INT_MASK);
1696 IWL_CMD(CSR_FH_INT_STATUS);
1697 IWL_CMD(CSR_GPIO_IN);
1698 IWL_CMD(CSR_RESET);
1699 IWL_CMD(CSR_GP_CNTRL);
1700 IWL_CMD(CSR_HW_REV);
1701 IWL_CMD(CSR_EEPROM_REG);
1702 IWL_CMD(CSR_EEPROM_GP);
1703 IWL_CMD(CSR_OTP_GP_REG);
1704 IWL_CMD(CSR_GIO_REG);
1705 IWL_CMD(CSR_GP_UCODE_REG);
1706 IWL_CMD(CSR_GP_DRIVER_REG);
1707 IWL_CMD(CSR_UCODE_DRV_GP1);
1708 IWL_CMD(CSR_UCODE_DRV_GP2);
1709 IWL_CMD(CSR_LED_REG);
1710 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1711 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1712 IWL_CMD(CSR_ANA_PLL_CFG);
1713 IWL_CMD(CSR_HW_REV_WA_REG);
1714 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1715 default:
1716 return "UNKNOWN";
1717 }
1718 #undef IWL_CMD
1719 }
1720
1721 void iwl_dump_csr(struct iwl_trans *trans)
1722 {
1723 int i;
1724 static const u32 csr_tbl[] = {
1725 CSR_HW_IF_CONFIG_REG,
1726 CSR_INT_COALESCING,
1727 CSR_INT,
1728 CSR_INT_MASK,
1729 CSR_FH_INT_STATUS,
1730 CSR_GPIO_IN,
1731 CSR_RESET,
1732 CSR_GP_CNTRL,
1733 CSR_HW_REV,
1734 CSR_EEPROM_REG,
1735 CSR_EEPROM_GP,
1736 CSR_OTP_GP_REG,
1737 CSR_GIO_REG,
1738 CSR_GP_UCODE_REG,
1739 CSR_GP_DRIVER_REG,
1740 CSR_UCODE_DRV_GP1,
1741 CSR_UCODE_DRV_GP2,
1742 CSR_LED_REG,
1743 CSR_DRAM_INT_TBL_REG,
1744 CSR_GIO_CHICKEN_BITS,
1745 CSR_ANA_PLL_CFG,
1746 CSR_HW_REV_WA_REG,
1747 CSR_DBG_HPET_MEM_REG
1748 };
1749 IWL_ERR(trans, "CSR values:\n");
1750 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1751 "CSR_INT_PERIODIC_REG)\n");
1752 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1753 IWL_ERR(trans, " %25s: 0X%08x\n",
1754 get_csr_string(csr_tbl[i]),
1755 iwl_read32(trans, csr_tbl[i]));
1756 }
1757 }
1758
1759 #ifdef CONFIG_IWLWIFI_DEBUGFS
1760 /* create and remove of files */
1761 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1762 if (!debugfs_create_file(#name, mode, parent, trans, \
1763 &iwl_dbgfs_##name##_ops)) \
1764 return -ENOMEM; \
1765 } while (0)
1766
1767 /* file operation */
1768 #define DEBUGFS_READ_FUNC(name) \
1769 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1770 char __user *user_buf, \
1771 size_t count, loff_t *ppos);
1772
1773 #define DEBUGFS_WRITE_FUNC(name) \
1774 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1775 const char __user *user_buf, \
1776 size_t count, loff_t *ppos);
1777
1778
1779 #define DEBUGFS_READ_FILE_OPS(name) \
1780 DEBUGFS_READ_FUNC(name); \
1781 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1782 .read = iwl_dbgfs_##name##_read, \
1783 .open = simple_open, \
1784 .llseek = generic_file_llseek, \
1785 };
1786
1787 #define DEBUGFS_WRITE_FILE_OPS(name) \
1788 DEBUGFS_WRITE_FUNC(name); \
1789 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1790 .write = iwl_dbgfs_##name##_write, \
1791 .open = simple_open, \
1792 .llseek = generic_file_llseek, \
1793 };
1794
1795 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1796 DEBUGFS_READ_FUNC(name); \
1797 DEBUGFS_WRITE_FUNC(name); \
1798 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1799 .write = iwl_dbgfs_##name##_write, \
1800 .read = iwl_dbgfs_##name##_read, \
1801 .open = simple_open, \
1802 .llseek = generic_file_llseek, \
1803 };
1804
1805 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1806 char __user *user_buf,
1807 size_t count, loff_t *ppos)
1808 {
1809 struct iwl_trans *trans = file->private_data;
1810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1811 struct iwl_tx_queue *txq;
1812 struct iwl_queue *q;
1813 char *buf;
1814 int pos = 0;
1815 int cnt;
1816 int ret;
1817 size_t bufsz;
1818
1819 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1820
1821 if (!trans_pcie->txq)
1822 return -EAGAIN;
1823
1824 buf = kzalloc(bufsz, GFP_KERNEL);
1825 if (!buf)
1826 return -ENOMEM;
1827
1828 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1829 txq = &trans_pcie->txq[cnt];
1830 q = &txq->q;
1831 pos += scnprintf(buf + pos, bufsz - pos,
1832 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1833 cnt, q->read_ptr, q->write_ptr,
1834 !!test_bit(cnt, trans_pcie->queue_used),
1835 !!test_bit(cnt, trans_pcie->queue_stopped));
1836 }
1837 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1838 kfree(buf);
1839 return ret;
1840 }
1841
1842 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1843 char __user *user_buf,
1844 size_t count, loff_t *ppos)
1845 {
1846 struct iwl_trans *trans = file->private_data;
1847 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1849 char buf[256];
1850 int pos = 0;
1851 const size_t bufsz = sizeof(buf);
1852
1853 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1854 rxq->read);
1855 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1856 rxq->write);
1857 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1858 rxq->free_count);
1859 if (rxq->rb_stts) {
1860 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1861 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1862 } else {
1863 pos += scnprintf(buf + pos, bufsz - pos,
1864 "closed_rb_num: Not Allocated\n");
1865 }
1866 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1867 }
1868
1869 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1870 char __user *user_buf,
1871 size_t count, loff_t *ppos)
1872 {
1873 struct iwl_trans *trans = file->private_data;
1874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1875 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1876
1877 int pos = 0;
1878 char *buf;
1879 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1880 ssize_t ret;
1881
1882 buf = kzalloc(bufsz, GFP_KERNEL);
1883 if (!buf)
1884 return -ENOMEM;
1885
1886 pos += scnprintf(buf + pos, bufsz - pos,
1887 "Interrupt Statistics Report:\n");
1888
1889 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1890 isr_stats->hw);
1891 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1892 isr_stats->sw);
1893 if (isr_stats->sw || isr_stats->hw) {
1894 pos += scnprintf(buf + pos, bufsz - pos,
1895 "\tLast Restarting Code: 0x%X\n",
1896 isr_stats->err_code);
1897 }
1898 #ifdef CONFIG_IWLWIFI_DEBUG
1899 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1900 isr_stats->sch);
1901 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1902 isr_stats->alive);
1903 #endif
1904 pos += scnprintf(buf + pos, bufsz - pos,
1905 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1906
1907 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1908 isr_stats->ctkill);
1909
1910 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1911 isr_stats->wakeup);
1912
1913 pos += scnprintf(buf + pos, bufsz - pos,
1914 "Rx command responses:\t\t %u\n", isr_stats->rx);
1915
1916 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1917 isr_stats->tx);
1918
1919 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1920 isr_stats->unhandled);
1921
1922 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1923 kfree(buf);
1924 return ret;
1925 }
1926
1927 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1928 const char __user *user_buf,
1929 size_t count, loff_t *ppos)
1930 {
1931 struct iwl_trans *trans = file->private_data;
1932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1933 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1934
1935 char buf[8];
1936 int buf_size;
1937 u32 reset_flag;
1938
1939 memset(buf, 0, sizeof(buf));
1940 buf_size = min(count, sizeof(buf) - 1);
1941 if (copy_from_user(buf, user_buf, buf_size))
1942 return -EFAULT;
1943 if (sscanf(buf, "%x", &reset_flag) != 1)
1944 return -EFAULT;
1945 if (reset_flag == 0)
1946 memset(isr_stats, 0, sizeof(*isr_stats));
1947
1948 return count;
1949 }
1950
1951 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1952 const char __user *user_buf,
1953 size_t count, loff_t *ppos)
1954 {
1955 struct iwl_trans *trans = file->private_data;
1956 char buf[8];
1957 int buf_size;
1958 int csr;
1959
1960 memset(buf, 0, sizeof(buf));
1961 buf_size = min(count, sizeof(buf) - 1);
1962 if (copy_from_user(buf, user_buf, buf_size))
1963 return -EFAULT;
1964 if (sscanf(buf, "%d", &csr) != 1)
1965 return -EFAULT;
1966
1967 iwl_dump_csr(trans);
1968
1969 return count;
1970 }
1971
1972 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1973 char __user *user_buf,
1974 size_t count, loff_t *ppos)
1975 {
1976 struct iwl_trans *trans = file->private_data;
1977 char *buf;
1978 int pos = 0;
1979 ssize_t ret = -EFAULT;
1980
1981 ret = pos = iwl_dump_fh(trans, &buf, true);
1982 if (buf) {
1983 ret = simple_read_from_buffer(user_buf,
1984 count, ppos, buf, pos);
1985 kfree(buf);
1986 }
1987
1988 return ret;
1989 }
1990
1991 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1992 const char __user *user_buf,
1993 size_t count, loff_t *ppos)
1994 {
1995 struct iwl_trans *trans = file->private_data;
1996
1997 if (!trans->op_mode)
1998 return -EAGAIN;
1999
2000 iwl_op_mode_nic_error(trans->op_mode);
2001
2002 return count;
2003 }
2004
2005 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2006 DEBUGFS_READ_FILE_OPS(fh_reg);
2007 DEBUGFS_READ_FILE_OPS(rx_queue);
2008 DEBUGFS_READ_FILE_OPS(tx_queue);
2009 DEBUGFS_WRITE_FILE_OPS(csr);
2010 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2011
2012 /*
2013 * Create the debugfs files and directories
2014 *
2015 */
2016 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2017 struct dentry *dir)
2018 {
2019 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2020 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2021 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2022 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2023 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2024 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2025 return 0;
2026 }
2027 #else
2028 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2029 struct dentry *dir)
2030 {
2031 return 0;
2032 }
2033 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2034
2035 static const struct iwl_trans_ops trans_ops_pcie = {
2036 .start_hw = iwl_trans_pcie_start_hw,
2037 .stop_hw = iwl_trans_pcie_stop_hw,
2038 .fw_alive = iwl_trans_pcie_fw_alive,
2039 .start_fw = iwl_trans_pcie_start_fw,
2040 .stop_device = iwl_trans_pcie_stop_device,
2041
2042 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2043
2044 .send_cmd = iwl_trans_pcie_send_cmd,
2045
2046 .tx = iwl_trans_pcie_tx,
2047 .reclaim = iwl_trans_pcie_reclaim,
2048
2049 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2050 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2051
2052 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2053
2054 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2055
2056 #ifdef CONFIG_PM_SLEEP
2057 .suspend = iwl_trans_pcie_suspend,
2058 .resume = iwl_trans_pcie_resume,
2059 #endif
2060 .write8 = iwl_trans_pcie_write8,
2061 .write32 = iwl_trans_pcie_write32,
2062 .read32 = iwl_trans_pcie_read32,
2063 .configure = iwl_trans_pcie_configure,
2064 .set_pmi = iwl_trans_pcie_set_pmi,
2065 };
2066
2067 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2068 const struct pci_device_id *ent,
2069 const struct iwl_cfg *cfg)
2070 {
2071 struct iwl_trans_pcie *trans_pcie;
2072 struct iwl_trans *trans;
2073 u16 pci_cmd;
2074 int err;
2075
2076 trans = kzalloc(sizeof(struct iwl_trans) +
2077 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2078
2079 if (WARN_ON(!trans))
2080 return NULL;
2081
2082 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2083
2084 trans->ops = &trans_ops_pcie;
2085 trans->cfg = cfg;
2086 trans_pcie->trans = trans;
2087 spin_lock_init(&trans_pcie->irq_lock);
2088 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2089
2090 /* W/A - seems to solve weird behavior. We need to remove this if we
2091 * don't want to stay in L1 all the time. This wastes a lot of power */
2092 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2093 PCIE_LINK_STATE_CLKPM);
2094
2095 if (pci_enable_device(pdev)) {
2096 err = -ENODEV;
2097 goto out_no_pci;
2098 }
2099
2100 pci_set_master(pdev);
2101
2102 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2103 if (!err)
2104 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2105 if (err) {
2106 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2107 if (!err)
2108 err = pci_set_consistent_dma_mask(pdev,
2109 DMA_BIT_MASK(32));
2110 /* both attempts failed: */
2111 if (err) {
2112 dev_printk(KERN_ERR, &pdev->dev,
2113 "No suitable DMA available.\n");
2114 goto out_pci_disable_device;
2115 }
2116 }
2117
2118 err = pci_request_regions(pdev, DRV_NAME);
2119 if (err) {
2120 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2121 goto out_pci_disable_device;
2122 }
2123
2124 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2125 if (!trans_pcie->hw_base) {
2126 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2127 err = -ENODEV;
2128 goto out_pci_release_regions;
2129 }
2130
2131 dev_printk(KERN_INFO, &pdev->dev,
2132 "pci_resource_len = 0x%08llx\n",
2133 (unsigned long long) pci_resource_len(pdev, 0));
2134 dev_printk(KERN_INFO, &pdev->dev,
2135 "pci_resource_base = %p\n", trans_pcie->hw_base);
2136
2137 dev_printk(KERN_INFO, &pdev->dev,
2138 "HW Revision ID = 0x%X\n", pdev->revision);
2139
2140 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2141 * PCI Tx retries from interfering with C3 CPU state */
2142 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2143
2144 err = pci_enable_msi(pdev);
2145 if (err)
2146 dev_printk(KERN_ERR, &pdev->dev,
2147 "pci_enable_msi failed(0X%x)", err);
2148
2149 trans->dev = &pdev->dev;
2150 trans_pcie->irq = pdev->irq;
2151 trans_pcie->pci_dev = pdev;
2152 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2153 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2154 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2155 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2156
2157 /* TODO: Move this away, not needed if not MSI */
2158 /* enable rfkill interrupt: hw bug w/a */
2159 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2160 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2161 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2162 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2163 }
2164
2165 /* Initialize the wait queue for commands */
2166 init_waitqueue_head(&trans->wait_command_queue);
2167 spin_lock_init(&trans->reg_lock);
2168
2169 return trans;
2170
2171 out_pci_release_regions:
2172 pci_release_regions(pdev);
2173 out_pci_disable_device:
2174 pci_disable_device(pdev);
2175 out_no_pci:
2176 kfree(trans);
2177 return NULL;
2178 }
Linux kernel - Deliverables
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