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iwlwifi: clean up iwl-core.h inclusions
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
80
81 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
82 {
83 struct iwl_trans_pcie *trans_pcie =
84 IWL_TRANS_GET_PCIE_TRANS(trans);
85 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
86 struct device *dev = trans->dev;
87
88 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
89
90 spin_lock_init(&rxq->lock);
91
92 if (WARN_ON(rxq->bd || rxq->rb_stts))
93 return -EINVAL;
94
95 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
96 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
97 &rxq->bd_dma, GFP_KERNEL);
98 if (!rxq->bd)
99 goto err_bd;
100
101 /*Allocate the driver's pointer to receive buffer status */
102 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
103 &rxq->rb_stts_dma, GFP_KERNEL);
104 if (!rxq->rb_stts)
105 goto err_rb_stts;
106
107 return 0;
108
109 err_rb_stts:
110 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
111 rxq->bd, rxq->bd_dma);
112 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
113 rxq->bd = NULL;
114 err_bd:
115 return -ENOMEM;
116 }
117
118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
119 {
120 struct iwl_trans_pcie *trans_pcie =
121 IWL_TRANS_GET_PCIE_TRANS(trans);
122 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
123 int i;
124
125 /* Fill the rx_used queue with _all_ of the Rx buffers */
126 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
127 /* In the reset function, these buffers may have been allocated
128 * to an SKB, so we need to unmap and free potential storage */
129 if (rxq->pool[i].page != NULL) {
130 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
131 PAGE_SIZE << hw_params(trans).rx_page_order,
132 DMA_FROM_DEVICE);
133 __free_pages(rxq->pool[i].page,
134 hw_params(trans).rx_page_order);
135 rxq->pool[i].page = NULL;
136 }
137 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
138 }
139 }
140
141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
142 struct iwl_rx_queue *rxq)
143 {
144 u32 rb_size;
145 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
146 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
147
148 if (iwlagn_mod_params.amsdu_size_8K)
149 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
150 else
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
152
153 /* Stop Rx DMA */
154 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
155
156 /* Reset driver's Rx queue write index */
157 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
158
159 /* Tell device where to find RBD circular buffer in DRAM */
160 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
161 (u32)(rxq->bd_dma >> 8));
162
163 /* Tell device where in DRAM to update its Rx status */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
165 rxq->rb_stts_dma >> 4);
166
167 /* Enable Rx DMA
168 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
169 * the credit mechanism in 5000 HW RX FIFO
170 * Direct rx interrupts to hosts
171 * Rx buffer size 4 or 8k
172 * RB timeout 0x10
173 * 256 RBDs
174 */
175 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
176 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
177 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
178 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
179 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
180 rb_size|
181 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
182 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
183
184 /* Set interrupt coalescing timer to default (2048 usecs) */
185 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
186 }
187
188 static int iwl_rx_init(struct iwl_trans *trans)
189 {
190 struct iwl_trans_pcie *trans_pcie =
191 IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
193
194 int i, err;
195 unsigned long flags;
196
197 if (!rxq->bd) {
198 err = iwl_trans_rx_alloc(trans);
199 if (err)
200 return err;
201 }
202
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
206
207 iwl_trans_rxq_free_rx_bufs(trans);
208
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
211
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
216 rxq->free_count = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
218
219 iwlagn_rx_replenish(trans);
220
221 iwl_trans_rx_hw_init(trans, rxq);
222
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
227
228 return 0;
229 }
230
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie =
234 IWL_TRANS_GET_PCIE_TRANS(trans);
235 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
236
237 unsigned long flags;
238
239 /*if rxq->bd is NULL, it means that nothing has been allocated,
240 * exit now */
241 if (!rxq->bd) {
242 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
243 return;
244 }
245
246 spin_lock_irqsave(&rxq->lock, flags);
247 iwl_trans_rxq_free_rx_bufs(trans);
248 spin_unlock_irqrestore(&rxq->lock, flags);
249
250 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
251 rxq->bd, rxq->bd_dma);
252 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
253 rxq->bd = NULL;
254
255 if (rxq->rb_stts)
256 dma_free_coherent(trans->dev,
257 sizeof(struct iwl_rb_status),
258 rxq->rb_stts, rxq->rb_stts_dma);
259 else
260 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
261 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
262 rxq->rb_stts = NULL;
263 }
264
265 static int iwl_trans_rx_stop(struct iwl_trans *trans)
266 {
267
268 /* stop Rx DMA */
269 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
270 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
271 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
272 }
273
274 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
275 struct iwl_dma_ptr *ptr, size_t size)
276 {
277 if (WARN_ON(ptr->addr))
278 return -EINVAL;
279
280 ptr->addr = dma_alloc_coherent(trans->dev, size,
281 &ptr->dma, GFP_KERNEL);
282 if (!ptr->addr)
283 return -ENOMEM;
284 ptr->size = size;
285 return 0;
286 }
287
288 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
289 struct iwl_dma_ptr *ptr)
290 {
291 if (unlikely(!ptr->addr))
292 return;
293
294 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
295 memset(ptr, 0, sizeof(*ptr));
296 }
297
298 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
299 struct iwl_tx_queue *txq, int slots_num,
300 u32 txq_id)
301 {
302 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
303 int i;
304
305 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
306 return -EINVAL;
307
308 txq->q.n_window = slots_num;
309
310 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
311 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
312
313 if (!txq->meta || !txq->cmd)
314 goto error;
315
316 if (txq_id == trans->shrd->cmd_queue)
317 for (i = 0; i < slots_num; i++) {
318 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
319 GFP_KERNEL);
320 if (!txq->cmd[i])
321 goto error;
322 }
323
324 /* Alloc driver data array and TFD circular buffer */
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
327 if (txq_id != trans->shrd->cmd_queue) {
328 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
329 GFP_KERNEL);
330 if (!txq->skbs) {
331 IWL_ERR(trans, "kmalloc for auxiliary BD "
332 "structures failed\n");
333 goto error;
334 }
335 } else {
336 txq->skbs = NULL;
337 }
338
339 /* Circular buffer of transmit frame descriptors (TFDs),
340 * shared with device */
341 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
342 &txq->q.dma_addr, GFP_KERNEL);
343 if (!txq->tfds) {
344 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
345 goto error;
346 }
347 txq->q.id = txq_id;
348
349 return 0;
350 error:
351 kfree(txq->skbs);
352 txq->skbs = NULL;
353 /* since txq->cmd has been zeroed,
354 * all non allocated cmd[i] will be NULL */
355 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
356 for (i = 0; i < slots_num; i++)
357 kfree(txq->cmd[i]);
358 kfree(txq->meta);
359 kfree(txq->cmd);
360 txq->meta = NULL;
361 txq->cmd = NULL;
362
363 return -ENOMEM;
364
365 }
366
367 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
368 int slots_num, u32 txq_id)
369 {
370 int ret;
371
372 txq->need_update = 0;
373 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
374
375 /*
376 * For the default queues 0-3, set up the swq_id
377 * already -- all others need to get one later
378 * (if they need one at all).
379 */
380 if (txq_id < 4)
381 iwl_set_swq_id(txq, txq_id, txq_id);
382
383 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
384 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
385 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
386
387 /* Initialize queue's high/low-water marks, and head/tail indexes */
388 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
389 txq_id);
390 if (ret)
391 return ret;
392
393 spin_lock_init(&txq->lock);
394
395 /*
396 * Tell nic where to find circular buffer of Tx Frame Descriptors for
397 * given Tx queue, and enable the DMA channel used for that queue.
398 * Circular buffer (TFD queue in DRAM) physical base address */
399 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
400 txq->q.dma_addr >> 8);
401
402 return 0;
403 }
404
405 /**
406 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
407 */
408 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
409 {
410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
411 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
412 struct iwl_queue *q = &txq->q;
413 enum dma_data_direction dma_dir;
414
415 if (!q->n_bd)
416 return;
417
418 /* In the command queue, all the TBs are mapped as BIDI
419 * so unmap them as such.
420 */
421 if (txq_id == trans->shrd->cmd_queue)
422 dma_dir = DMA_BIDIRECTIONAL;
423 else
424 dma_dir = DMA_TO_DEVICE;
425
426 spin_lock_bh(&txq->lock);
427 while (q->write_ptr != q->read_ptr) {
428 /* The read_ptr needs to bound by q->n_window */
429 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
430 dma_dir);
431 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
432 }
433 spin_unlock_bh(&txq->lock);
434 }
435
436 /**
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
439 *
440 * Empty queue by removing and destroying all BD's.
441 * Free all buffers.
442 * 0-fill, but do not free "txq" descriptor structure.
443 */
444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
445 {
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
448 struct device *dev = trans->dev;
449 int i;
450 if (WARN_ON(!txq))
451 return;
452
453 iwl_tx_queue_unmap(trans, txq_id);
454
455 /* De-alloc array of command/tx buffers */
456
457 if (txq_id == trans->shrd->cmd_queue)
458 for (i = 0; i < txq->q.n_window; i++)
459 kfree(txq->cmd[i]);
460
461 /* De-alloc circular buffer of TFDs */
462 if (txq->q.n_bd) {
463 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
464 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
465 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
466 }
467
468 /* De-alloc array of per-TFD driver data */
469 kfree(txq->skbs);
470 txq->skbs = NULL;
471
472 /* deallocate arrays */
473 kfree(txq->cmd);
474 kfree(txq->meta);
475 txq->cmd = NULL;
476 txq->meta = NULL;
477
478 /* 0-fill queue descriptor structure */
479 memset(txq, 0, sizeof(*txq));
480 }
481
482 /**
483 * iwl_trans_tx_free - Free TXQ Context
484 *
485 * Destroy all TX DMA queues and structures
486 */
487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
488 {
489 int txq_id;
490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
491
492 /* Tx queues */
493 if (trans_pcie->txq) {
494 for (txq_id = 0;
495 txq_id < hw_params(trans).max_txq_num; txq_id++)
496 iwl_tx_queue_free(trans, txq_id);
497 }
498
499 kfree(trans_pcie->txq);
500 trans_pcie->txq = NULL;
501
502 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
503
504 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
505 }
506
507 /**
508 * iwl_trans_tx_alloc - allocate TX context
509 * Allocate all Tx DMA structures and initialize them
510 *
511 * @param priv
512 * @return error code
513 */
514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
515 {
516 int ret;
517 int txq_id, slots_num;
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
519
520 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
521 sizeof(struct iwlagn_scd_bc_tbl);
522
523 /*It is not allowed to alloc twice, so warn when this happens.
524 * We cannot rely on the previous allocation, so free and fail */
525 if (WARN_ON(trans_pcie->txq)) {
526 ret = -EINVAL;
527 goto error;
528 }
529
530 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
531 scd_bc_tbls_size);
532 if (ret) {
533 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
534 goto error;
535 }
536
537 /* Alloc keep-warm buffer */
538 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
539 if (ret) {
540 IWL_ERR(trans, "Keep Warm allocation failed\n");
541 goto error;
542 }
543
544 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
545 sizeof(struct iwl_tx_queue), GFP_KERNEL);
546 if (!trans_pcie->txq) {
547 IWL_ERR(trans, "Not enough memory for txq\n");
548 ret = ENOMEM;
549 goto error;
550 }
551
552 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
553 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
554 slots_num = (txq_id == trans->shrd->cmd_queue) ?
555 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
556 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
557 slots_num, txq_id);
558 if (ret) {
559 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
560 goto error;
561 }
562 }
563
564 return 0;
565
566 error:
567 iwl_trans_pcie_tx_free(trans);
568
569 return ret;
570 }
571 static int iwl_tx_init(struct iwl_trans *trans)
572 {
573 int ret;
574 int txq_id, slots_num;
575 unsigned long flags;
576 bool alloc = false;
577 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
578
579 if (!trans_pcie->txq) {
580 ret = iwl_trans_tx_alloc(trans);
581 if (ret)
582 goto error;
583 alloc = true;
584 }
585
586 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
587
588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(trans, SCD_TXFACT, 0);
590
591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
593 trans_pcie->kw.dma >> 4);
594
595 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
596
597 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
598 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
599 slots_num = (txq_id == trans->shrd->cmd_queue) ?
600 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
601 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
602 slots_num, txq_id);
603 if (ret) {
604 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
605 goto error;
606 }
607 }
608
609 return 0;
610 error:
611 /*Upon error, free only if we allocated something */
612 if (alloc)
613 iwl_trans_pcie_tx_free(trans);
614 return ret;
615 }
616
617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
618 {
619 /*
620 * (for documentation purposes)
621 * to set power to V_AUX, do:
622
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
627 */
628
629 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
631 ~APMG_PS_CTRL_MSK_PWR_SRC);
632 }
633
634 /* PCI registers */
635 #define PCI_CFG_RETRY_TIMEOUT 0x041
636 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
637 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
638
639 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
640 {
641 int pos;
642 u16 pci_lnk_ctl;
643 struct iwl_trans_pcie *trans_pcie =
644 IWL_TRANS_GET_PCIE_TRANS(trans);
645
646 struct pci_dev *pci_dev = trans_pcie->pci_dev;
647
648 pos = pci_pcie_cap(pci_dev);
649 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
650 return pci_lnk_ctl;
651 }
652
653 static void iwl_apm_config(struct iwl_trans *trans)
654 {
655 /*
656 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
657 * Check if BIOS (or OS) enabled L1-ASPM on this device.
658 * If so (likely), disable L0S, so device moves directly L0->L1;
659 * costs negligible amount of power savings.
660 * If not (unlikely), enable L0S, so there is at least some
661 * power savings, even without L1.
662 */
663 u16 lctl = iwl_pciexp_link_ctrl(trans);
664
665 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
666 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
667 /* L1-ASPM enabled; disable(!) L0S */
668 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
669 dev_printk(KERN_INFO, trans->dev,
670 "L1 Enabled; Disabling L0S\n");
671 } else {
672 /* L1-ASPM disabled; enable(!) L0S */
673 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
674 dev_printk(KERN_INFO, trans->dev,
675 "L1 Disabled; Enabling L0S\n");
676 }
677 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
678 }
679
680 /*
681 * Start up NIC's basic functionality after it has been reset
682 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
683 * NOTE: This does not load uCode nor start the embedded processor
684 */
685 static int iwl_apm_init(struct iwl_trans *trans)
686 {
687 int ret = 0;
688 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
689
690 /*
691 * Use "set_bit" below rather than "write", to preserve any hardware
692 * bits already set by default after reset.
693 */
694
695 /* Disable L0S exit timer (platform NMI Work/Around) */
696 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
697 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
698
699 /*
700 * Disable L0s without affecting L1;
701 * don't wait for ICH L0s (ICH bug W/A)
702 */
703 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
704 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
705
706 /* Set FH wait threshold to maximum (HW error during stress W/A) */
707 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
708
709 /*
710 * Enable HAP INTA (interrupt from management bus) to
711 * wake device's PCI Express link L1a -> L0s
712 */
713 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
714 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
715
716 iwl_apm_config(trans);
717
718 /* Configure analog phase-lock-loop before activating to D0A */
719 if (cfg(trans)->base_params->pll_cfg_val)
720 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
721 cfg(trans)->base_params->pll_cfg_val);
722
723 /*
724 * Set "initialization complete" bit to move adapter from
725 * D0U* --> D0A* (powered-up active) state.
726 */
727 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
728
729 /*
730 * Wait for clock stabilization; once stabilized, access to
731 * device-internal resources is supported, e.g. iwl_write_prph()
732 * and accesses to uCode SRAM.
733 */
734 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
735 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
736 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
737 if (ret < 0) {
738 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
739 goto out;
740 }
741
742 /*
743 * Enable DMA clock and wait for it to stabilize.
744 *
745 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
746 * do not disable clocks. This preserves any hardware bits already
747 * set by default in "CLK_CTRL_REG" after reset.
748 */
749 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
750 udelay(20);
751
752 /* Disable L1-Active */
753 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
754 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
755
756 set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
757
758 out:
759 return ret;
760 }
761
762 static int iwl_apm_stop_master(struct iwl_trans *trans)
763 {
764 int ret = 0;
765
766 /* stop device's busmaster DMA activity */
767 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
768
769 ret = iwl_poll_bit(trans, CSR_RESET,
770 CSR_RESET_REG_FLAG_MASTER_DISABLED,
771 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
772 if (ret)
773 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
774
775 IWL_DEBUG_INFO(trans, "stop master\n");
776
777 return ret;
778 }
779
780 static void iwl_apm_stop(struct iwl_trans *trans)
781 {
782 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
783
784 clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
785
786 /* Stop device's DMA activity */
787 iwl_apm_stop_master(trans);
788
789 /* Reset the entire device */
790 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
791
792 udelay(10);
793
794 /*
795 * Clear "initialization complete" bit to move adapter from
796 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
797 */
798 iwl_clear_bit(trans, CSR_GP_CNTRL,
799 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
800 }
801
802 static int iwl_nic_init(struct iwl_trans *trans)
803 {
804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
805 unsigned long flags;
806
807 /* nic_init */
808 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
809 iwl_apm_init(trans);
810
811 /* Set interrupt coalescing calibration timer to default (512 usecs) */
812 iwl_write8(trans, CSR_INT_COALESCING,
813 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
814
815 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
816
817 iwl_set_pwr_vmain(trans);
818
819 iwl_nic_config(priv(trans));
820
821 #ifndef CONFIG_IWLWIFI_IDI
822 /* Allocate the RX queue, or reset if it is already allocated */
823 iwl_rx_init(trans);
824 #endif
825
826 /* Allocate or reset and init all Tx and Command queues */
827 if (iwl_tx_init(trans))
828 return -ENOMEM;
829
830 if (cfg(trans)->base_params->shadow_reg_enable) {
831 /* enable shadow regs in HW */
832 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
833 0x800FFFFF);
834 }
835
836 set_bit(STATUS_INIT, &trans->shrd->status);
837
838 return 0;
839 }
840
841 #define HW_READY_TIMEOUT (50)
842
843 /* Note: returns poll_bit return value, which is >= 0 if success */
844 static int iwl_set_hw_ready(struct iwl_trans *trans)
845 {
846 int ret;
847
848 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
849 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
850
851 /* See if we got it */
852 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
853 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
855 HW_READY_TIMEOUT);
856
857 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
858 return ret;
859 }
860
861 /* Note: returns standard 0/-ERROR code */
862 static int iwl_prepare_card_hw(struct iwl_trans *trans)
863 {
864 int ret;
865
866 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
867
868 ret = iwl_set_hw_ready(trans);
869 /* If the card is ready, exit 0 */
870 if (ret >= 0)
871 return 0;
872
873 /* If HW is not ready, prepare the conditions to check again */
874 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
875 CSR_HW_IF_CONFIG_REG_PREPARE);
876
877 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
878 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
879 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
880
881 if (ret < 0)
882 return ret;
883
884 /* HW should be ready by now, check again. */
885 ret = iwl_set_hw_ready(trans);
886 if (ret >= 0)
887 return 0;
888 return ret;
889 }
890
891 #define IWL_AC_UNSET -1
892
893 struct queue_to_fifo_ac {
894 s8 fifo, ac;
895 };
896
897 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
898 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
899 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
900 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
901 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
902 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
903 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
904 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
905 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
906 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
907 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
908 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
909 };
910
911 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
912 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
913 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
914 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
915 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
916 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
917 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
918 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
919 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
920 { IWL_TX_FIFO_BE_IPAN, 2, },
921 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
922 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
923 };
924
925 static const u8 iwlagn_bss_ac_to_fifo[] = {
926 IWL_TX_FIFO_VO,
927 IWL_TX_FIFO_VI,
928 IWL_TX_FIFO_BE,
929 IWL_TX_FIFO_BK,
930 };
931 static const u8 iwlagn_bss_ac_to_queue[] = {
932 0, 1, 2, 3,
933 };
934 static const u8 iwlagn_pan_ac_to_fifo[] = {
935 IWL_TX_FIFO_VO_IPAN,
936 IWL_TX_FIFO_VI_IPAN,
937 IWL_TX_FIFO_BE_IPAN,
938 IWL_TX_FIFO_BK_IPAN,
939 };
940 static const u8 iwlagn_pan_ac_to_queue[] = {
941 7, 6, 5, 4,
942 };
943
944 /*
945 * ucode
946 */
947 static int iwl_load_section(struct iwl_trans *trans, const char *name,
948 const struct fw_desc *image, u32 dst_addr)
949 {
950 dma_addr_t phy_addr = image->p_addr;
951 u32 byte_cnt = image->len;
952 int ret;
953
954 trans->ucode_write_complete = 0;
955
956 iwl_write_direct32(trans,
957 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
958 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
959
960 iwl_write_direct32(trans,
961 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
962
963 iwl_write_direct32(trans,
964 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
965 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
966
967 iwl_write_direct32(trans,
968 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
969 (iwl_get_dma_hi_addr(phy_addr)
970 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
971
972 iwl_write_direct32(trans,
973 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
974 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
975 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
976 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
977
978 iwl_write_direct32(trans,
979 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
980 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
981 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
982 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
983
984 IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
985 ret = wait_event_timeout(trans->shrd->wait_command_queue,
986 trans->ucode_write_complete, 5 * HZ);
987 if (!ret) {
988 IWL_ERR(trans, "Could not load the %s uCode section\n",
989 name);
990 return -ETIMEDOUT;
991 }
992
993 return 0;
994 }
995
996 static int iwl_load_given_ucode(struct iwl_trans *trans,
997 const struct fw_img *image)
998 {
999 int ret = 0;
1000
1001 ret = iwl_load_section(trans, "INST", &image->code,
1002 IWLAGN_RTC_INST_LOWER_BOUND);
1003 if (ret)
1004 return ret;
1005
1006 ret = iwl_load_section(trans, "DATA", &image->data,
1007 IWLAGN_RTC_DATA_LOWER_BOUND);
1008 if (ret)
1009 return ret;
1010
1011 /* Remove all resets to allow NIC to operate */
1012 iwl_write32(trans, CSR_RESET, 0);
1013
1014 return 0;
1015 }
1016
1017 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1018 const struct fw_img *fw)
1019 {
1020 int ret;
1021 struct iwl_trans_pcie *trans_pcie =
1022 IWL_TRANS_GET_PCIE_TRANS(trans);
1023 bool hw_rfkill;
1024
1025 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1026 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1027 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1028
1029 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1030 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1031
1032 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1033 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1034
1035 /* This may fail if AMT took ownership of the device */
1036 if (iwl_prepare_card_hw(trans)) {
1037 IWL_WARN(trans, "Exit HW not ready\n");
1038 return -EIO;
1039 }
1040
1041 /* If platform's RF_KILL switch is NOT set to KILL */
1042 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1043 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1044 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1045
1046 if (hw_rfkill) {
1047 iwl_enable_interrupts(trans);
1048 return -ERFKILL;
1049 }
1050
1051 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1052
1053 ret = iwl_nic_init(trans);
1054 if (ret) {
1055 IWL_ERR(trans, "Unable to init nic\n");
1056 return ret;
1057 }
1058
1059 /* make sure rfkill handshake bits are cleared */
1060 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1061 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1062 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1063
1064 /* clear (again), then enable host interrupts */
1065 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1066 iwl_enable_interrupts(trans);
1067
1068 /* really make sure rfkill handshake bits are cleared */
1069 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1070 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1071
1072 /* Load the given image to the HW */
1073 iwl_load_given_ucode(trans, fw);
1074
1075 return 0;
1076 }
1077
1078 /*
1079 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1080 * must be called under the irq lock and with MAC access
1081 */
1082 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1083 {
1084 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1085 IWL_TRANS_GET_PCIE_TRANS(trans);
1086
1087 lockdep_assert_held(&trans_pcie->irq_lock);
1088
1089 iwl_write_prph(trans, SCD_TXFACT, mask);
1090 }
1091
1092 static void iwl_tx_start(struct iwl_trans *trans)
1093 {
1094 const struct queue_to_fifo_ac *queue_to_fifo;
1095 struct iwl_trans_pcie *trans_pcie =
1096 IWL_TRANS_GET_PCIE_TRANS(trans);
1097 u32 a;
1098 unsigned long flags;
1099 int i, chan;
1100 u32 reg_val;
1101
1102 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1103
1104 trans_pcie->scd_base_addr =
1105 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1106 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1107 /* reset conext data memory */
1108 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1109 a += 4)
1110 iwl_write_targ_mem(trans, a, 0);
1111 /* reset tx status memory */
1112 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1113 a += 4)
1114 iwl_write_targ_mem(trans, a, 0);
1115 for (; a < trans_pcie->scd_base_addr +
1116 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1117 a += 4)
1118 iwl_write_targ_mem(trans, a, 0);
1119
1120 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1121 trans_pcie->scd_bc_tbls.dma >> 10);
1122
1123 /* Enable DMA channel */
1124 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1125 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1126 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1127 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1128
1129 /* Update FH chicken bits */
1130 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1131 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1132 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1133
1134 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1135 SCD_QUEUECHAIN_SEL_ALL(trans));
1136 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1137
1138 /* initiate the queues */
1139 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1140 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1141 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1142 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1143 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1144 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1145 SCD_CONTEXT_QUEUE_OFFSET(i) +
1146 sizeof(u32),
1147 ((SCD_WIN_SIZE <<
1148 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1149 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1150 ((SCD_FRAME_LIMIT <<
1151 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1152 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1153 }
1154
1155 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1156 IWL_MASK(0, hw_params(trans).max_txq_num));
1157
1158 /* Activate all Tx DMA/FIFO channels */
1159 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1160
1161 /* map queues to FIFOs */
1162 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1163 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1164 else
1165 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1166
1167 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1168
1169 /* make sure all queue are not stopped */
1170 memset(&trans_pcie->queue_stopped[0], 0,
1171 sizeof(trans_pcie->queue_stopped));
1172 for (i = 0; i < 4; i++)
1173 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1174
1175 /* reset to 0 to enable all the queue first */
1176 trans_pcie->txq_ctx_active_msk = 0;
1177
1178 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1179 IWLAGN_FIRST_AMPDU_QUEUE);
1180 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1181 IWLAGN_FIRST_AMPDU_QUEUE);
1182
1183 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1184 int fifo = queue_to_fifo[i].fifo;
1185 int ac = queue_to_fifo[i].ac;
1186
1187 iwl_txq_ctx_activate(trans_pcie, i);
1188
1189 if (fifo == IWL_TX_FIFO_UNUSED)
1190 continue;
1191
1192 if (ac != IWL_AC_UNSET)
1193 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1194 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1195 fifo, 0);
1196 }
1197
1198 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1199
1200 /* Enable L1-Active */
1201 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1202 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1203 }
1204
1205 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1206 {
1207 iwl_reset_ict(trans);
1208 iwl_tx_start(trans);
1209 }
1210
1211 /**
1212 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1213 */
1214 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1215 {
1216 int ch, txq_id;
1217 unsigned long flags;
1218 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1219
1220 /* Turn off all Tx DMA fifos */
1221 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1222
1223 iwl_trans_txq_set_sched(trans, 0);
1224
1225 /* Stop each Tx DMA channel, and wait for it to be idle */
1226 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1227 iwl_write_direct32(trans,
1228 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1229 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1230 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1231 1000))
1232 IWL_ERR(trans, "Failing on timeout while stopping"
1233 " DMA channel %d [0x%08x]", ch,
1234 iwl_read_direct32(trans,
1235 FH_TSSR_TX_STATUS_REG));
1236 }
1237 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1238
1239 if (!trans_pcie->txq) {
1240 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1241 return 0;
1242 }
1243
1244 /* Unmap DMA from host system and free skb's */
1245 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1246 iwl_tx_queue_unmap(trans, txq_id);
1247
1248 return 0;
1249 }
1250
1251 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1252 {
1253 unsigned long flags;
1254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255
1256 /* tell the device to stop sending interrupts */
1257 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1258 iwl_disable_interrupts(trans);
1259 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1260
1261 /* device going down, Stop using ICT table */
1262 iwl_disable_ict(trans);
1263
1264 /*
1265 * If a HW restart happens during firmware loading,
1266 * then the firmware loading might call this function
1267 * and later it might be called again due to the
1268 * restart. So don't process again if the device is
1269 * already dead.
1270 */
1271 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1272 iwl_trans_tx_stop(trans);
1273 #ifndef CONFIG_IWLWIFI_IDI
1274 iwl_trans_rx_stop(trans);
1275 #endif
1276 /* Power-down device's busmaster DMA clocks */
1277 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1278 APMG_CLK_VAL_DMA_CLK_RQT);
1279 udelay(5);
1280 }
1281
1282 /* Make sure (redundant) we've released our request to stay awake */
1283 iwl_clear_bit(trans, CSR_GP_CNTRL,
1284 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1285
1286 /* Stop the device, and put it in low power state */
1287 iwl_apm_stop(trans);
1288
1289 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1290 * Clean again the interrupt here
1291 */
1292 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1293 iwl_disable_interrupts(trans);
1294 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1295
1296 /* wait to make sure we flush pending tasklet*/
1297 synchronize_irq(trans->irq);
1298 tasklet_kill(&trans_pcie->irq_tasklet);
1299
1300 cancel_work_sync(&trans_pcie->rx_replenish);
1301
1302 /* stop and reset the on-board processor */
1303 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1304 }
1305
1306 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1307 {
1308 /* let the ucode operate on its own */
1309 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1310 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1311
1312 iwl_disable_interrupts(trans);
1313 iwl_clear_bit(trans, CSR_GP_CNTRL,
1314 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1315 }
1316
1317 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1318 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1319 u8 sta_id, u8 tid)
1320 {
1321 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1322 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1323 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1324 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1325 struct iwl_cmd_meta *out_meta;
1326 struct iwl_tx_queue *txq;
1327 struct iwl_queue *q;
1328
1329 dma_addr_t phys_addr = 0;
1330 dma_addr_t txcmd_phys;
1331 dma_addr_t scratch_phys;
1332 u16 len, firstlen, secondlen;
1333 u8 wait_write_ptr = 0;
1334 u8 txq_id;
1335 bool is_agg = false;
1336 __le16 fc = hdr->frame_control;
1337 u8 hdr_len = ieee80211_hdrlen(fc);
1338 u16 __maybe_unused wifi_seq;
1339
1340 /*
1341 * Send this frame after DTIM -- there's a special queue
1342 * reserved for this for contexts that support AP mode.
1343 */
1344 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1345 txq_id = trans_pcie->mcast_queue[ctx];
1346
1347 /*
1348 * The microcode will clear the more data
1349 * bit in the last frame it transmits.
1350 */
1351 hdr->frame_control |=
1352 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1353 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1354 txq_id = IWL_AUX_QUEUE;
1355 else
1356 txq_id =
1357 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1358
1359 /* aggregation is on for this <sta,tid> */
1360 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1361 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1362 txq_id = trans_pcie->agg_txq[sta_id][tid];
1363 is_agg = true;
1364 }
1365
1366 txq = &trans_pcie->txq[txq_id];
1367 q = &txq->q;
1368
1369 spin_lock(&txq->lock);
1370
1371 /* In AGG mode, the index in the ring must correspond to the WiFi
1372 * sequence number. This is a HW requirements to help the SCD to parse
1373 * the BA.
1374 * Check here that the packets are in the right place on the ring.
1375 */
1376 #ifdef CONFIG_IWLWIFI_DEBUG
1377 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1378 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1379 "Q: %d WiFi Seq %d tfdNum %d",
1380 txq_id, wifi_seq, q->write_ptr);
1381 #endif
1382
1383 /* Set up driver data for this TFD */
1384 txq->skbs[q->write_ptr] = skb;
1385 txq->cmd[q->write_ptr] = dev_cmd;
1386
1387 dev_cmd->hdr.cmd = REPLY_TX;
1388 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1389 INDEX_TO_SEQ(q->write_ptr)));
1390
1391 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1392 out_meta = &txq->meta[q->write_ptr];
1393
1394 /*
1395 * Use the first empty entry in this queue's command buffer array
1396 * to contain the Tx command and MAC header concatenated together
1397 * (payload data will be in another buffer).
1398 * Size of this varies, due to varying MAC header length.
1399 * If end is not dword aligned, we'll have 2 extra bytes at the end
1400 * of the MAC header (device reads on dword boundaries).
1401 * We'll tell device about this padding later.
1402 */
1403 len = sizeof(struct iwl_tx_cmd) +
1404 sizeof(struct iwl_cmd_header) + hdr_len;
1405 firstlen = (len + 3) & ~3;
1406
1407 /* Tell NIC about any 2-byte padding after MAC header */
1408 if (firstlen != len)
1409 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1410
1411 /* Physical address of this Tx command's header (not MAC header!),
1412 * within command buffer array. */
1413 txcmd_phys = dma_map_single(trans->dev,
1414 &dev_cmd->hdr, firstlen,
1415 DMA_BIDIRECTIONAL);
1416 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1417 goto out_err;
1418 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1419 dma_unmap_len_set(out_meta, len, firstlen);
1420
1421 if (!ieee80211_has_morefrags(fc)) {
1422 txq->need_update = 1;
1423 } else {
1424 wait_write_ptr = 1;
1425 txq->need_update = 0;
1426 }
1427
1428 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1429 * if any (802.11 null frames have no payload). */
1430 secondlen = skb->len - hdr_len;
1431 if (secondlen > 0) {
1432 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1433 secondlen, DMA_TO_DEVICE);
1434 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1435 dma_unmap_single(trans->dev,
1436 dma_unmap_addr(out_meta, mapping),
1437 dma_unmap_len(out_meta, len),
1438 DMA_BIDIRECTIONAL);
1439 goto out_err;
1440 }
1441 }
1442
1443 /* Attach buffers to TFD */
1444 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1445 if (secondlen > 0)
1446 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1447 secondlen, 0);
1448
1449 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1450 offsetof(struct iwl_tx_cmd, scratch);
1451
1452 /* take back ownership of DMA buffer to enable update */
1453 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1454 DMA_BIDIRECTIONAL);
1455 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1456 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1457
1458 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1459 le16_to_cpu(dev_cmd->hdr.sequence));
1460 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1461 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1462 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1463
1464 /* Set up entry for this TFD in Tx byte-count array */
1465 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1466
1467 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1468 DMA_BIDIRECTIONAL);
1469
1470 trace_iwlwifi_dev_tx(trans->dev,
1471 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1472 sizeof(struct iwl_tfd),
1473 &dev_cmd->hdr, firstlen,
1474 skb->data + hdr_len, secondlen);
1475
1476 /* Tell device the write index *just past* this latest filled TFD */
1477 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1478 iwl_txq_update_write_ptr(trans, txq);
1479
1480 /*
1481 * At this point the frame is "transmitted" successfully
1482 * and we will get a TX status notification eventually,
1483 * regardless of the value of ret. "ret" only indicates
1484 * whether or not we should update the write pointer.
1485 */
1486 if (iwl_queue_space(q) < q->high_mark) {
1487 if (wait_write_ptr) {
1488 txq->need_update = 1;
1489 iwl_txq_update_write_ptr(trans, txq);
1490 } else {
1491 iwl_stop_queue(trans, txq, "Queue is full");
1492 }
1493 }
1494 spin_unlock(&txq->lock);
1495 return 0;
1496 out_err:
1497 spin_unlock(&txq->lock);
1498 return -1;
1499 }
1500
1501 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1502 {
1503 struct iwl_trans_pcie *trans_pcie =
1504 IWL_TRANS_GET_PCIE_TRANS(trans);
1505 int err;
1506 bool hw_rfkill;
1507
1508 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1509
1510 if (!trans_pcie->irq_requested) {
1511 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1512 iwl_irq_tasklet, (unsigned long)trans);
1513
1514 iwl_alloc_isr_ict(trans);
1515
1516 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1517 DRV_NAME, trans);
1518 if (err) {
1519 IWL_ERR(trans, "Error allocating IRQ %d\n",
1520 trans->irq);
1521 goto error;
1522 }
1523
1524 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1525 trans_pcie->irq_requested = true;
1526 }
1527
1528 err = iwl_prepare_card_hw(trans);
1529 if (err) {
1530 IWL_ERR(trans, "Error while preparing HW: %d", err);
1531 goto err_free_irq;
1532 }
1533
1534 iwl_apm_init(trans);
1535
1536 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1537 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1538 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1539
1540 return err;
1541
1542 err_free_irq:
1543 free_irq(trans->irq, trans);
1544 error:
1545 iwl_free_isr_ict(trans);
1546 tasklet_kill(&trans_pcie->irq_tasklet);
1547 return err;
1548 }
1549
1550 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1551 {
1552 iwl_apm_stop(trans);
1553
1554 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1555
1556 /* Even if we stop the HW, we still want the RF kill interrupt */
1557 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1558 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1559 }
1560
1561 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1562 int txq_id, int ssn, u32 status,
1563 struct sk_buff_head *skbs)
1564 {
1565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1566 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1567 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1568 int tfd_num = ssn & (txq->q.n_bd - 1);
1569 int freed = 0;
1570
1571 spin_lock(&txq->lock);
1572
1573 txq->time_stamp = jiffies;
1574
1575 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1576 tid != IWL_TID_NON_QOS &&
1577 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1578 /*
1579 * FIXME: this is a uCode bug which need to be addressed,
1580 * log the information and return for now.
1581 * Since it is can possibly happen very often and in order
1582 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1583 */
1584 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1585 "agg_txq[sta_id[tid] %d", txq_id,
1586 trans_pcie->agg_txq[sta_id][tid]);
1587 spin_unlock(&txq->lock);
1588 return 1;
1589 }
1590
1591 if (txq->q.read_ptr != tfd_num) {
1592 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1593 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1594 tfd_num, ssn);
1595 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1596 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1597 (!txq->sched_retry ||
1598 status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1599 iwl_wake_queue(trans, txq, "Packets reclaimed");
1600 }
1601
1602 spin_unlock(&txq->lock);
1603 return 0;
1604 }
1605
1606 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1607 {
1608 iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1609 }
1610
1611 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1612 {
1613 iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1614 }
1615
1616 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1617 {
1618 u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1619 return val;
1620 }
1621
1622 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1623 {
1624 struct iwl_trans_pcie *trans_pcie =
1625 IWL_TRANS_GET_PCIE_TRANS(trans);
1626
1627 iwl_trans_pcie_tx_free(trans);
1628 #ifndef CONFIG_IWLWIFI_IDI
1629 iwl_trans_pcie_rx_free(trans);
1630 #endif
1631 if (trans_pcie->irq_requested == true) {
1632 free_irq(trans->irq, trans);
1633 iwl_free_isr_ict(trans);
1634 }
1635
1636 pci_disable_msi(trans_pcie->pci_dev);
1637 pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1638 pci_release_regions(trans_pcie->pci_dev);
1639 pci_disable_device(trans_pcie->pci_dev);
1640
1641 trans->shrd->trans = NULL;
1642 kfree(trans);
1643 }
1644
1645 #ifdef CONFIG_PM_SLEEP
1646 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1647 {
1648 return 0;
1649 }
1650
1651 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1652 {
1653 bool hw_rfkill;
1654
1655 iwl_enable_interrupts(trans);
1656
1657 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1658 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1659 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1660
1661 return 0;
1662 }
1663 #endif /* CONFIG_PM_SLEEP */
1664
1665 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1666 enum iwl_rxon_context_id ctx,
1667 const char *msg)
1668 {
1669 u8 ac, txq_id;
1670 struct iwl_trans_pcie *trans_pcie =
1671 IWL_TRANS_GET_PCIE_TRANS(trans);
1672
1673 for (ac = 0; ac < AC_NUM; ac++) {
1674 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1675 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1676 ac,
1677 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1678 ? "stopped" : "awake");
1679 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1680 }
1681 }
1682
1683 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1684 const char *msg)
1685 {
1686 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1687
1688 iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1689 }
1690
1691 #define IWL_FLUSH_WAIT_MS 2000
1692
1693 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1694 {
1695 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1696 struct iwl_tx_queue *txq;
1697 struct iwl_queue *q;
1698 int cnt;
1699 unsigned long now = jiffies;
1700 int ret = 0;
1701
1702 /* waiting for all the tx frames complete might take a while */
1703 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1704 if (cnt == trans->shrd->cmd_queue)
1705 continue;
1706 txq = &trans_pcie->txq[cnt];
1707 q = &txq->q;
1708 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1709 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1710 msleep(1);
1711
1712 if (q->read_ptr != q->write_ptr) {
1713 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1714 ret = -ETIMEDOUT;
1715 break;
1716 }
1717 }
1718 return ret;
1719 }
1720
1721 /*
1722 * On every watchdog tick we check (latest) time stamp. If it does not
1723 * change during timeout period and queue is not empty we reset firmware.
1724 */
1725 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1726 {
1727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1729 struct iwl_queue *q = &txq->q;
1730 unsigned long timeout;
1731
1732 if (q->read_ptr == q->write_ptr) {
1733 txq->time_stamp = jiffies;
1734 return 0;
1735 }
1736
1737 timeout = txq->time_stamp +
1738 msecs_to_jiffies(hw_params(trans).wd_timeout);
1739
1740 if (time_after(jiffies, timeout)) {
1741 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1742 hw_params(trans).wd_timeout);
1743 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1744 q->read_ptr, q->write_ptr);
1745 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1746 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1747 & (TFD_QUEUE_SIZE_MAX - 1),
1748 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1749 return 1;
1750 }
1751
1752 return 0;
1753 }
1754
1755 static const char *get_fh_string(int cmd)
1756 {
1757 switch (cmd) {
1758 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1759 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1760 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1761 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1762 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1763 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1764 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1765 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1766 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1767 default:
1768 return "UNKNOWN";
1769 }
1770 }
1771
1772 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1773 {
1774 int i;
1775 #ifdef CONFIG_IWLWIFI_DEBUG
1776 int pos = 0;
1777 size_t bufsz = 0;
1778 #endif
1779 static const u32 fh_tbl[] = {
1780 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1781 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1782 FH_RSCSR_CHNL0_WPTR,
1783 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1784 FH_MEM_RSSR_SHARED_CTRL_REG,
1785 FH_MEM_RSSR_RX_STATUS_REG,
1786 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1787 FH_TSSR_TX_STATUS_REG,
1788 FH_TSSR_TX_ERROR_REG
1789 };
1790 #ifdef CONFIG_IWLWIFI_DEBUG
1791 if (display) {
1792 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1793 *buf = kmalloc(bufsz, GFP_KERNEL);
1794 if (!*buf)
1795 return -ENOMEM;
1796 pos += scnprintf(*buf + pos, bufsz - pos,
1797 "FH register values:\n");
1798 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1799 pos += scnprintf(*buf + pos, bufsz - pos,
1800 " %34s: 0X%08x\n",
1801 get_fh_string(fh_tbl[i]),
1802 iwl_read_direct32(trans, fh_tbl[i]));
1803 }
1804 return pos;
1805 }
1806 #endif
1807 IWL_ERR(trans, "FH register values:\n");
1808 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1809 IWL_ERR(trans, " %34s: 0X%08x\n",
1810 get_fh_string(fh_tbl[i]),
1811 iwl_read_direct32(trans, fh_tbl[i]));
1812 }
1813 return 0;
1814 }
1815
1816 static const char *get_csr_string(int cmd)
1817 {
1818 switch (cmd) {
1819 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1820 IWL_CMD(CSR_INT_COALESCING);
1821 IWL_CMD(CSR_INT);
1822 IWL_CMD(CSR_INT_MASK);
1823 IWL_CMD(CSR_FH_INT_STATUS);
1824 IWL_CMD(CSR_GPIO_IN);
1825 IWL_CMD(CSR_RESET);
1826 IWL_CMD(CSR_GP_CNTRL);
1827 IWL_CMD(CSR_HW_REV);
1828 IWL_CMD(CSR_EEPROM_REG);
1829 IWL_CMD(CSR_EEPROM_GP);
1830 IWL_CMD(CSR_OTP_GP_REG);
1831 IWL_CMD(CSR_GIO_REG);
1832 IWL_CMD(CSR_GP_UCODE_REG);
1833 IWL_CMD(CSR_GP_DRIVER_REG);
1834 IWL_CMD(CSR_UCODE_DRV_GP1);
1835 IWL_CMD(CSR_UCODE_DRV_GP2);
1836 IWL_CMD(CSR_LED_REG);
1837 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1838 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1839 IWL_CMD(CSR_ANA_PLL_CFG);
1840 IWL_CMD(CSR_HW_REV_WA_REG);
1841 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1842 default:
1843 return "UNKNOWN";
1844 }
1845 }
1846
1847 void iwl_dump_csr(struct iwl_trans *trans)
1848 {
1849 int i;
1850 static const u32 csr_tbl[] = {
1851 CSR_HW_IF_CONFIG_REG,
1852 CSR_INT_COALESCING,
1853 CSR_INT,
1854 CSR_INT_MASK,
1855 CSR_FH_INT_STATUS,
1856 CSR_GPIO_IN,
1857 CSR_RESET,
1858 CSR_GP_CNTRL,
1859 CSR_HW_REV,
1860 CSR_EEPROM_REG,
1861 CSR_EEPROM_GP,
1862 CSR_OTP_GP_REG,
1863 CSR_GIO_REG,
1864 CSR_GP_UCODE_REG,
1865 CSR_GP_DRIVER_REG,
1866 CSR_UCODE_DRV_GP1,
1867 CSR_UCODE_DRV_GP2,
1868 CSR_LED_REG,
1869 CSR_DRAM_INT_TBL_REG,
1870 CSR_GIO_CHICKEN_BITS,
1871 CSR_ANA_PLL_CFG,
1872 CSR_HW_REV_WA_REG,
1873 CSR_DBG_HPET_MEM_REG
1874 };
1875 IWL_ERR(trans, "CSR values:\n");
1876 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1877 "CSR_INT_PERIODIC_REG)\n");
1878 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1879 IWL_ERR(trans, " %25s: 0X%08x\n",
1880 get_csr_string(csr_tbl[i]),
1881 iwl_read32(trans, csr_tbl[i]));
1882 }
1883 }
1884
1885 #ifdef CONFIG_IWLWIFI_DEBUGFS
1886 /* create and remove of files */
1887 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1888 if (!debugfs_create_file(#name, mode, parent, trans, \
1889 &iwl_dbgfs_##name##_ops)) \
1890 return -ENOMEM; \
1891 } while (0)
1892
1893 /* file operation */
1894 #define DEBUGFS_READ_FUNC(name) \
1895 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1896 char __user *user_buf, \
1897 size_t count, loff_t *ppos);
1898
1899 #define DEBUGFS_WRITE_FUNC(name) \
1900 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1901 const char __user *user_buf, \
1902 size_t count, loff_t *ppos);
1903
1904
1905 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1906 {
1907 file->private_data = inode->i_private;
1908 return 0;
1909 }
1910
1911 #define DEBUGFS_READ_FILE_OPS(name) \
1912 DEBUGFS_READ_FUNC(name); \
1913 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1914 .read = iwl_dbgfs_##name##_read, \
1915 .open = iwl_dbgfs_open_file_generic, \
1916 .llseek = generic_file_llseek, \
1917 };
1918
1919 #define DEBUGFS_WRITE_FILE_OPS(name) \
1920 DEBUGFS_WRITE_FUNC(name); \
1921 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1922 .write = iwl_dbgfs_##name##_write, \
1923 .open = iwl_dbgfs_open_file_generic, \
1924 .llseek = generic_file_llseek, \
1925 };
1926
1927 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1928 DEBUGFS_READ_FUNC(name); \
1929 DEBUGFS_WRITE_FUNC(name); \
1930 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1931 .write = iwl_dbgfs_##name##_write, \
1932 .read = iwl_dbgfs_##name##_read, \
1933 .open = iwl_dbgfs_open_file_generic, \
1934 .llseek = generic_file_llseek, \
1935 };
1936
1937 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1938 char __user *user_buf,
1939 size_t count, loff_t *ppos)
1940 {
1941 struct iwl_trans *trans = file->private_data;
1942 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1943 struct iwl_tx_queue *txq;
1944 struct iwl_queue *q;
1945 char *buf;
1946 int pos = 0;
1947 int cnt;
1948 int ret;
1949 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1950
1951 if (!trans_pcie->txq) {
1952 IWL_ERR(trans, "txq not ready\n");
1953 return -EAGAIN;
1954 }
1955 buf = kzalloc(bufsz, GFP_KERNEL);
1956 if (!buf)
1957 return -ENOMEM;
1958
1959 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1960 txq = &trans_pcie->txq[cnt];
1961 q = &txq->q;
1962 pos += scnprintf(buf + pos, bufsz - pos,
1963 "hwq %.2d: read=%u write=%u stop=%d"
1964 " swq_id=%#.2x (ac %d/hwq %d)\n",
1965 cnt, q->read_ptr, q->write_ptr,
1966 !!test_bit(cnt, trans_pcie->queue_stopped),
1967 txq->swq_id, txq->swq_id & 3,
1968 (txq->swq_id >> 2) & 0x1f);
1969 if (cnt >= 4)
1970 continue;
1971 /* for the ACs, display the stop count too */
1972 pos += scnprintf(buf + pos, bufsz - pos,
1973 " stop-count: %d\n",
1974 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1975 }
1976 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1977 kfree(buf);
1978 return ret;
1979 }
1980
1981 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1982 char __user *user_buf,
1983 size_t count, loff_t *ppos) {
1984 struct iwl_trans *trans = file->private_data;
1985 struct iwl_trans_pcie *trans_pcie =
1986 IWL_TRANS_GET_PCIE_TRANS(trans);
1987 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1988 char buf[256];
1989 int pos = 0;
1990 const size_t bufsz = sizeof(buf);
1991
1992 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1993 rxq->read);
1994 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1995 rxq->write);
1996 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1997 rxq->free_count);
1998 if (rxq->rb_stts) {
1999 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2000 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
2001 } else {
2002 pos += scnprintf(buf + pos, bufsz - pos,
2003 "closed_rb_num: Not Allocated\n");
2004 }
2005 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2006 }
2007
2008 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2009 char __user *user_buf,
2010 size_t count, loff_t *ppos)
2011 {
2012 struct iwl_trans *trans = file->private_data;
2013 char *buf;
2014 int pos = 0;
2015 ssize_t ret = -ENOMEM;
2016
2017 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2018 if (buf) {
2019 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2020 kfree(buf);
2021 }
2022 return ret;
2023 }
2024
2025 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2026 const char __user *user_buf,
2027 size_t count, loff_t *ppos)
2028 {
2029 struct iwl_trans *trans = file->private_data;
2030 u32 event_log_flag;
2031 char buf[8];
2032 int buf_size;
2033
2034 memset(buf, 0, sizeof(buf));
2035 buf_size = min(count, sizeof(buf) - 1);
2036 if (copy_from_user(buf, user_buf, buf_size))
2037 return -EFAULT;
2038 if (sscanf(buf, "%d", &event_log_flag) != 1)
2039 return -EFAULT;
2040 if (event_log_flag == 1)
2041 iwl_dump_nic_event_log(trans, true, NULL, false);
2042
2043 return count;
2044 }
2045
2046 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2047 char __user *user_buf,
2048 size_t count, loff_t *ppos) {
2049
2050 struct iwl_trans *trans = file->private_data;
2051 struct iwl_trans_pcie *trans_pcie =
2052 IWL_TRANS_GET_PCIE_TRANS(trans);
2053 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2054
2055 int pos = 0;
2056 char *buf;
2057 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2058 ssize_t ret;
2059
2060 buf = kzalloc(bufsz, GFP_KERNEL);
2061 if (!buf) {
2062 IWL_ERR(trans, "Can not allocate Buffer\n");
2063 return -ENOMEM;
2064 }
2065
2066 pos += scnprintf(buf + pos, bufsz - pos,
2067 "Interrupt Statistics Report:\n");
2068
2069 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2070 isr_stats->hw);
2071 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2072 isr_stats->sw);
2073 if (isr_stats->sw || isr_stats->hw) {
2074 pos += scnprintf(buf + pos, bufsz - pos,
2075 "\tLast Restarting Code: 0x%X\n",
2076 isr_stats->err_code);
2077 }
2078 #ifdef CONFIG_IWLWIFI_DEBUG
2079 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2080 isr_stats->sch);
2081 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2082 isr_stats->alive);
2083 #endif
2084 pos += scnprintf(buf + pos, bufsz - pos,
2085 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2086
2087 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2088 isr_stats->ctkill);
2089
2090 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2091 isr_stats->wakeup);
2092
2093 pos += scnprintf(buf + pos, bufsz - pos,
2094 "Rx command responses:\t\t %u\n", isr_stats->rx);
2095
2096 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2097 isr_stats->tx);
2098
2099 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2100 isr_stats->unhandled);
2101
2102 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2103 kfree(buf);
2104 return ret;
2105 }
2106
2107 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2108 const char __user *user_buf,
2109 size_t count, loff_t *ppos)
2110 {
2111 struct iwl_trans *trans = file->private_data;
2112 struct iwl_trans_pcie *trans_pcie =
2113 IWL_TRANS_GET_PCIE_TRANS(trans);
2114 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2115
2116 char buf[8];
2117 int buf_size;
2118 u32 reset_flag;
2119
2120 memset(buf, 0, sizeof(buf));
2121 buf_size = min(count, sizeof(buf) - 1);
2122 if (copy_from_user(buf, user_buf, buf_size))
2123 return -EFAULT;
2124 if (sscanf(buf, "%x", &reset_flag) != 1)
2125 return -EFAULT;
2126 if (reset_flag == 0)
2127 memset(isr_stats, 0, sizeof(*isr_stats));
2128
2129 return count;
2130 }
2131
2132 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2133 const char __user *user_buf,
2134 size_t count, loff_t *ppos)
2135 {
2136 struct iwl_trans *trans = file->private_data;
2137 char buf[8];
2138 int buf_size;
2139 int csr;
2140
2141 memset(buf, 0, sizeof(buf));
2142 buf_size = min(count, sizeof(buf) - 1);
2143 if (copy_from_user(buf, user_buf, buf_size))
2144 return -EFAULT;
2145 if (sscanf(buf, "%d", &csr) != 1)
2146 return -EFAULT;
2147
2148 iwl_dump_csr(trans);
2149
2150 return count;
2151 }
2152
2153 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2154 char __user *user_buf,
2155 size_t count, loff_t *ppos)
2156 {
2157 struct iwl_trans *trans = file->private_data;
2158 char *buf;
2159 int pos = 0;
2160 ssize_t ret = -EFAULT;
2161
2162 ret = pos = iwl_dump_fh(trans, &buf, true);
2163 if (buf) {
2164 ret = simple_read_from_buffer(user_buf,
2165 count, ppos, buf, pos);
2166 kfree(buf);
2167 }
2168
2169 return ret;
2170 }
2171
2172 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2173 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2174 DEBUGFS_READ_FILE_OPS(fh_reg);
2175 DEBUGFS_READ_FILE_OPS(rx_queue);
2176 DEBUGFS_READ_FILE_OPS(tx_queue);
2177 DEBUGFS_WRITE_FILE_OPS(csr);
2178
2179 /*
2180 * Create the debugfs files and directories
2181 *
2182 */
2183 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2184 struct dentry *dir)
2185 {
2186 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2187 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2188 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2189 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2190 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2191 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2192 return 0;
2193 }
2194 #else
2195 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2196 struct dentry *dir)
2197 { return 0; }
2198
2199 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2200
2201 const struct iwl_trans_ops trans_ops_pcie = {
2202 .start_hw = iwl_trans_pcie_start_hw,
2203 .stop_hw = iwl_trans_pcie_stop_hw,
2204 .fw_alive = iwl_trans_pcie_fw_alive,
2205 .start_fw = iwl_trans_pcie_start_fw,
2206 .stop_device = iwl_trans_pcie_stop_device,
2207
2208 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2209
2210 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2211
2212 .send_cmd = iwl_trans_pcie_send_cmd,
2213
2214 .tx = iwl_trans_pcie_tx,
2215 .reclaim = iwl_trans_pcie_reclaim,
2216
2217 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2218 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2219 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2220
2221 .free = iwl_trans_pcie_free,
2222 .stop_queue = iwl_trans_pcie_stop_queue,
2223
2224 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2225
2226 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2227 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2228
2229 #ifdef CONFIG_PM_SLEEP
2230 .suspend = iwl_trans_pcie_suspend,
2231 .resume = iwl_trans_pcie_resume,
2232 #endif
2233 .write8 = iwl_trans_pcie_write8,
2234 .write32 = iwl_trans_pcie_write32,
2235 .read32 = iwl_trans_pcie_read32,
2236 };
2237
2238 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2239 struct pci_dev *pdev,
2240 const struct pci_device_id *ent)
2241 {
2242 struct iwl_trans_pcie *trans_pcie;
2243 struct iwl_trans *trans;
2244 u16 pci_cmd;
2245 int err;
2246
2247 trans = kzalloc(sizeof(struct iwl_trans) +
2248 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2249
2250 if (WARN_ON(!trans))
2251 return NULL;
2252
2253 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2254
2255 trans->ops = &trans_ops_pcie;
2256 trans->shrd = shrd;
2257 trans_pcie->trans = trans;
2258 spin_lock_init(&trans_pcie->irq_lock);
2259
2260 /* W/A - seems to solve weird behavior. We need to remove this if we
2261 * don't want to stay in L1 all the time. This wastes a lot of power */
2262 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2263 PCIE_LINK_STATE_CLKPM);
2264
2265 if (pci_enable_device(pdev)) {
2266 err = -ENODEV;
2267 goto out_no_pci;
2268 }
2269
2270 pci_set_master(pdev);
2271
2272 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2273 if (!err)
2274 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2275 if (err) {
2276 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2277 if (!err)
2278 err = pci_set_consistent_dma_mask(pdev,
2279 DMA_BIT_MASK(32));
2280 /* both attempts failed: */
2281 if (err) {
2282 dev_printk(KERN_ERR, &pdev->dev,
2283 "No suitable DMA available.\n");
2284 goto out_pci_disable_device;
2285 }
2286 }
2287
2288 err = pci_request_regions(pdev, DRV_NAME);
2289 if (err) {
2290 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2291 goto out_pci_disable_device;
2292 }
2293
2294 trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2295 if (!trans_pcie->hw_base) {
2296 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2297 err = -ENODEV;
2298 goto out_pci_release_regions;
2299 }
2300
2301 dev_printk(KERN_INFO, &pdev->dev,
2302 "pci_resource_len = 0x%08llx\n",
2303 (unsigned long long) pci_resource_len(pdev, 0));
2304 dev_printk(KERN_INFO, &pdev->dev,
2305 "pci_resource_base = %p\n", trans_pcie->hw_base);
2306
2307 dev_printk(KERN_INFO, &pdev->dev,
2308 "HW Revision ID = 0x%X\n", pdev->revision);
2309
2310 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2311 * PCI Tx retries from interfering with C3 CPU state */
2312 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2313
2314 err = pci_enable_msi(pdev);
2315 if (err)
2316 dev_printk(KERN_ERR, &pdev->dev,
2317 "pci_enable_msi failed(0X%x)", err);
2318
2319 trans->dev = &pdev->dev;
2320 trans->irq = pdev->irq;
2321 trans_pcie->pci_dev = pdev;
2322 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2323 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2324 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2325 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2326
2327 /* TODO: Move this away, not needed if not MSI */
2328 /* enable rfkill interrupt: hw bug w/a */
2329 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2330 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2331 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2332 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2333 }
2334
2335 return trans;
2336
2337 out_pci_release_regions:
2338 pci_release_regions(pdev);
2339 out_pci_disable_device:
2340 pci_disable_device(pdev);
2341 out_no_pci:
2342 kfree(trans);
2343 return NULL;
2344 }
2345
Linux kernel - Deliverables
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